drivers/ieee1394/init_ohci1394_dma.c

   1 /*
   2  * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2006-2007      Bernhard Kaindl <bk@suse.de>
   5  *
   6  * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
   7  * this file has functions to:
   8  * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
   9  * - reset and initialize them and make them join the IEEE1394 bus and
  10  * - enable physical DMA on them to allow remote debugging
  11  *
  12  * All code and data is marked as __init and __initdata, respective as
  13  * during boot, all OHCI1394 controllers may be claimed by the firewire
  14  * stack and at this point, this code should not touch them anymore.
  15  *
  16  * To use physical DMA after the initialization of the firewire stack,
  17  * be sure that the stack enables it and (re-)attach after the bus reset
  18  * which may be caused by the firewire stack initialization.
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2 of the License, or
  23  * (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software Foundation,
  32  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  33  */
  34
  35 #include <linux/interrupt.h>    /* for ohci1394.h */
  36 #include <linux/delay.h>
  37 #include <linux/pci.h>          /* for PCI defines */
  38 #include <linux/init_ohci1394_dma.h>
  39 #include <asm/pci-direct.h>     /* for direct PCI config space access */
  40 #include <asm/fixmap.h>
  41
  42 #include "ieee1394_types.h"
  43 #include "ohci1394.h"
  44
  45 int __initdata init_ohci1394_dma_early;
  46
  47 /* Reads a PHY register of an OHCI-1394 controller */
  48 static inline u8 __init get_phy_reg(struct ti_ohci *ohci, u8 addr)
  49 {
  50         int i;
  51         quadlet_t r;
  52
  53         reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
  54
  55         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  56                 if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
  57                         break;
  58                 mdelay(1);
  59         }
  60         r = reg_read(ohci, OHCI1394_PhyControl);
  61
  62         return (r & 0x00ff0000) >> 16;
  63 }
  64
  65 /* Writes to a PHY register of an OHCI-1394 controller */
  66 static inline void __init set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
  67 {
  68         int i;
  69
  70         reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
  71
  72         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  73                 u32 r = reg_read(ohci, OHCI1394_PhyControl);
  74                 if (!(r & 0x00004000))
  75                         break;
  76                 mdelay(1);
  77         }
  78 }
  79
  80 /* Resets an OHCI-1394 controller (for sane state before initialization) */
  81 static inline void __init init_ohci1394_soft_reset(struct ti_ohci *ohci) {
  82         int i;
  83
  84         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
  85
  86         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  87                 if (!(reg_read(ohci, OHCI1394_HCControlSet)
  88                                    & OHCI1394_HCControl_softReset))
  89                         break;
  90                 mdelay(1);
  91         }
  92 }
  93
  94 /* Basic OHCI-1394 register and port inititalization */
  95 static inline void __init init_ohci1394_initialize(struct ti_ohci *ohci)
  96 {
  97         quadlet_t bus_options;
  98         int num_ports, i;
  99
 100         /* Put some defaults to these undefined bus options */
 101         bus_options = reg_read(ohci, OHCI1394_BusOptions);
 102         bus_options |=  0x60000000; /* Enable CMC and ISC */
 103         bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
 104         bus_options &= ~0x18000000; /* Disable PMC and BMC */
 105         reg_write(ohci, OHCI1394_BusOptions, bus_options);
 106
 107         /* Set the bus number */
 108         reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
 109
 110         /* Enable posted writes */
 111         reg_write(ohci, OHCI1394_HCControlSet,
 112                         OHCI1394_HCControl_postedWriteEnable);
 113
 114         /* Clear link control register */
 115         reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
 116
 117         /* enable phys */
 118         reg_write(ohci, OHCI1394_LinkControlSet,
 119                         OHCI1394_LinkControl_RcvPhyPkt);
 120
 121         /* Don't accept phy packets into AR request context */
 122         reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
 123
 124         /* Clear the Isochonouys interrupt masks */
 125         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
 126         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
 127         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
 128         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
 129
 130         /* Accept asyncronous transfer requests from all nodes for now */
 131         reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
 132
 133         /* Specify asyncronous transfer retries */
 134         reg_write(ohci, OHCI1394_ATRetries,
 135                   OHCI1394_MAX_AT_REQ_RETRIES |
 136                   (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
 137                   (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
 138
 139         /* We don't want hardware swapping */
 140         reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
 141
 142         /* Enable link */
 143         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
 144
 145         /* If anything is connected to a port, make sure it is enabled */
 146         num_ports = get_phy_reg(ohci, 2) & 0xf;
 147         for (i = 0; i < num_ports; i++) {
 148                 unsigned int status;
 149
 150                 set_phy_reg(ohci, 7, i);
 151                 status = get_phy_reg(ohci, 8);
 152
 153                 if (status & 0x20)
 154                         set_phy_reg(ohci, 8, status & ~1);
 155         }
 156 }
 157
 158 /**
 159  * init_ohci1394_wait_for_busresets - wait until bus resets are completed
 160  *
 161  * OHCI1394 initialization itself and any device going on- or offline
 162  * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec
 163  * specifies that physical DMA is disabled on each bus reset and it
 164  * has to be enabled after each bus reset when needed. We resort
 165  * to polling here because on early boot, we have no interrupts.
 166  */
 167 static inline void __init init_ohci1394_wait_for_busresets(struct ti_ohci *ohci)
 168 {
 169         int i, events;
 170
 171         for (i=0; i < 9; i++) {
 172                 mdelay(200);
 173                 events = reg_read(ohci, OHCI1394_IntEventSet);
 174                 if (events & OHCI1394_busReset)
 175                         reg_write(ohci, OHCI1394_IntEventClear,
 176                                         OHCI1394_busReset);
 177         }
 178 }
 179
 180 /**
 181  * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging
 182  * This enables remote DMA access over IEEE1394 from every host for the low
 183  * 4GB of address space. DMA accesses above 4GB are not available currently.
 184  */
 185 static inline void __init init_ohci1394_enable_physical_dma(struct ti_ohci *hci)
 186 {
 187         reg_write(hci, OHCI1394_PhyReqFilterHiSet, 0xffffffff);
 188         reg_write(hci, OHCI1394_PhyReqFilterLoSet, 0xffffffff);
 189         reg_write(hci, OHCI1394_PhyUpperBound, 0xffff0000);
 190 }
 191
 192 /**
 193  * init_ohci1394_reset_and_init_dma - init controller and enable DMA
 194  * This initializes the given controller and enables physical DMA engine in it.
 195  */
 196 static inline void __init init_ohci1394_reset_and_init_dma(struct ti_ohci *ohci)
 197 {
 198         /* Start off with a soft reset, clears everything to a sane state. */
 199         init_ohci1394_soft_reset(ohci);
 200
 201         /* Accessing some registers without LPS enabled may cause lock up */
 202         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
 203
 204         /* Disable and clear interrupts */
 205         reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
 206         reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
 207
 208         mdelay(50); /* Wait 50msec to make sure we have full link enabled */
 209
 210         init_ohci1394_initialize(ohci);
 211         /*
 212          * The initialization causes at least one IEEE1394 bus reset. Enabling
 213          * physical DMA only works *after* *all* bus resets have calmed down:
 214          */
 215         init_ohci1394_wait_for_busresets(ohci);
 216
 217         /* We had to wait and do this now if we want to debug early problems */
 218         init_ohci1394_enable_physical_dma(ohci);
 219 }
 220
 221 /**
 222  * init_ohci1394_controller - Map the registers of the controller and init DMA
 223  * This maps the registers of the specified controller and initializes it
 224  */
 225 static inline void __init init_ohci1394_controller(int num, int slot, int func)
 226 {
 227         unsigned long ohci_base;
 228         struct ti_ohci ohci;
 229
 230         printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394"
 231                          " at %02x:%02x.%x\n", num, slot, func);
 232
 233         ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
 234                                                    & PCI_BASE_ADDRESS_MEM_MASK;
 235
 236         set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base);
 237
 238         ohci.registers = (void *)fix_to_virt(FIX_OHCI1394_BASE);
 239
 240         init_ohci1394_reset_and_init_dma(&ohci);
 241 }
 242
 243 /**
 244  * debug_init_ohci1394_dma - scan for OHCI1394 controllers and init DMA on them
 245  * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them
 246  */
 247 void __init init_ohci1394_dma_on_all_controllers(void)
 248 {
 249         int num, slot, func;
 250
 251         if (!early_pci_allowed())
 252                 return;
 253
 254         /* Poor man's PCI discovery, the only thing we can do at early boot */
 255         for (num = 0; num < 32; num++) {
 256                 for (slot = 0; slot < 32; slot++) {
 257                         for (func = 0; func < 8; func++) {
 258                                 u32 class = read_pci_config(num,slot,func,
 259                                                         PCI_CLASS_REVISION);
 260                                 if ((class == 0xffffffff))
 261                                         continue; /* No device at this func */
 262
 263                                 if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI)
 264                                         continue; /* Not an OHCI-1394 device */
 265
 266                                 init_ohci1394_controller(num, slot, func);
 267                                 break; /* Assume one controller per device */
 268                         }
 269                 }
 270         }
 271         printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n");
 272 }
 273
 274 /**
 275  * setup_init_ohci1394_early - enables early OHCI1394 DMA initialization
 276  */
 277 static int __init setup_ohci1394_dma(char *opt)
 278 {
 279         if (!strcmp(opt, "early"))
 280                 init_ohci1394_dma_early = 1;
 281         return 0;
 282 }
 283
 284 /* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */
 285 early_param("ohci1394_dma", setup_ohci1394_dma);