| blob | 0d701c1bf539e518035825a173e436da223d824d |
1 /*
2 * Lite5200 board Device Tree Source
3 *
4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
13 / {
14 model = "fsl,lite5200";
15 compatible = "fsl,lite5200";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
23 PowerPC,5200@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>;
27 i-cache-line-size = <20>;
28 d-cache-size = <4000>; // L1, 16K
29 i-cache-size = <4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
33 };
34 };
36 memory {
37 device_type = "memory";
38 reg = <00000000 04000000>; // 64MB
39 };
41 soc5200@f0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "fsl,mpc5200-immr";
45 ranges = <0 f0000000 0000c000>;
46 reg = <f0000000 00000100>;
47 bus-frequency = <0>; // from bootloader
48 system-frequency = <0>; // from bootloader
50 cdm@200 {
51 compatible = "fsl,mpc5200-cdm";
52 reg = <200 38>;
53 };
55 mpc5200_pic: interrupt-controller@500 {
56 // 5200 interrupts are encoded into two levels;
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 device_type = "interrupt-controller";
60 compatible = "fsl,mpc5200-pic";
61 reg = <500 80>;
62 };
64 timer@600 { // General Purpose Timer
65 compatible = "fsl,mpc5200-gpt";
66 cell-index = <0>;
67 reg = <600 10>;
68 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt;
71 };
73 timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200-gpt";
75 cell-index = <1>;
76 reg = <610 10>;
77 interrupts = <1 a 0>;
78 interrupt-parent = <&mpc5200_pic>;
79 };
81 timer@620 { // General Purpose Timer
82 compatible = "fsl,mpc5200-gpt";
83 cell-index = <2>;
84 reg = <620 10>;
85 interrupts = <1 b 0>;
86 interrupt-parent = <&mpc5200_pic>;
87 };
89 timer@630 { // General Purpose Timer
90 compatible = "fsl,mpc5200-gpt";
91 cell-index = <3>;
92 reg = <630 10>;
93 interrupts = <1 c 0>;
94 interrupt-parent = <&mpc5200_pic>;
95 };
97 timer@640 { // General Purpose Timer
98 compatible = "fsl,mpc5200-gpt";
99 cell-index = <4>;
100 reg = <640 10>;
101 interrupts = <1 d 0>;
102 interrupt-parent = <&mpc5200_pic>;
103 };
105 timer@650 { // General Purpose Timer
106 compatible = "fsl,mpc5200-gpt";
107 cell-index = <5>;
108 reg = <650 10>;
109 interrupts = <1 e 0>;
110 interrupt-parent = <&mpc5200_pic>;
111 };
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200-gpt";
115 cell-index = <6>;
116 reg = <660 10>;
117 interrupts = <1 f 0>;
118 interrupt-parent = <&mpc5200_pic>;
119 };
121 timer@670 { // General Purpose Timer
122 compatible = "fsl,mpc5200-gpt";
123 cell-index = <7>;
124 reg = <670 10>;
125 interrupts = <1 10 0>;
126 interrupt-parent = <&mpc5200_pic>;
127 };
129 rtc@800 { // Real time clock
130 compatible = "fsl,mpc5200-rtc";
131 device_type = "rtc";
132 reg = <800 100>;
133 interrupts = <1 5 0 1 6 0>;
134 interrupt-parent = <&mpc5200_pic>;
135 };
137 can@900 {
138 compatible = "fsl,mpc5200-mscan";
139 cell-index = <0>;
140 interrupts = <2 11 0>;
141 interrupt-parent = <&mpc5200_pic>;
142 reg = <900 80>;
143 };
145 can@980 {
146 compatible = "fsl,mpc5200-mscan";
147 cell-index = <1>;
148 interrupts = <2 12 0>;
149 interrupt-parent = <&mpc5200_pic>;
150 reg = <980 80>;
151 };
153 gpio@b00 {
154 compatible = "fsl,mpc5200-gpio";
155 reg = <b00 40>;
156 interrupts = <1 7 0>;
157 interrupt-parent = <&mpc5200_pic>;
158 };
160 gpio@c00 {
161 compatible = "fsl,mpc5200-gpio-wkup";
162 reg = <c00 40>;
163 interrupts = <1 8 0 0 3 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 };
167 spi@f00 {
168 compatible = "fsl,mpc5200-spi";
169 reg = <f00 20>;
170 interrupts = <2 d 0 2 e 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 };
174 usb@1000 {
175 compatible = "fsl,mpc5200-ohci","ohci-be";
176 reg = <1000 ff>;
177 interrupts = <2 6 0>;
178 interrupt-parent = <&mpc5200_pic>;
179 };
181 dma-controller@1200 {
182 device_type = "dma-controller";
183 compatible = "fsl,mpc5200-bestcomm";
184 reg = <1200 80>;
185 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
186 3 4 0 3 5 0 3 6 0 3 7 0
187 3 8 0 3 9 0 3 a 0 3 b 0
188 3 c 0 3 d 0 3 e 0 3 f 0>;
189 interrupt-parent = <&mpc5200_pic>;
190 };
192 xlb@1f00 {
193 compatible = "fsl,mpc5200-xlb";
194 reg = <1f00 100>;
195 };
197 serial@2000 { // PSC1
198 device_type = "serial";
199 compatible = "fsl,mpc5200-psc-uart";
200 port-number = <0>; // Logical port assignment
201 cell-index = <0>;
202 reg = <2000 100>;
203 interrupts = <2 1 0>;
204 interrupt-parent = <&mpc5200_pic>;
205 };
207 // PSC2 in ac97 mode example
208 //ac97@2200 { // PSC2
209 // compatible = "fsl,mpc5200-psc-ac97";
210 // cell-index = <1>;
211 // reg = <2200 100>;
212 // interrupts = <2 2 0>;
213 // interrupt-parent = <&mpc5200_pic>;
214 //};
216 // PSC3 in CODEC mode example
217 //i2s@2400 { // PSC3
218 // compatible = "fsl,mpc5200-psc-i2s";
219 // cell-index = <2>;
220 // reg = <2400 100>;
221 // interrupts = <2 3 0>;
222 // interrupt-parent = <&mpc5200_pic>;
223 //};
225 // PSC4 in uart mode example
226 //serial@2600 { // PSC4
227 // device_type = "serial";
228 // compatible = "fsl,mpc5200-psc-uart";
229 // cell-index = <3>;
230 // reg = <2600 100>;
231 // interrupts = <2 b 0>;
232 // interrupt-parent = <&mpc5200_pic>;
233 //};
235 // PSC5 in uart mode example
236 //serial@2800 { // PSC5
237 // device_type = "serial";
238 // compatible = "fsl,mpc5200-psc-uart";
239 // cell-index = <4>;
240 // reg = <2800 100>;
241 // interrupts = <2 c 0>;
242 // interrupt-parent = <&mpc5200_pic>;
243 //};
245 // PSC6 in spi mode example
246 //spi@2c00 { // PSC6
247 // compatible = "fsl,mpc5200-psc-spi";
248 // cell-index = <5>;
249 // reg = <2c00 100>;
250 // interrupts = <2 4 0>;
251 // interrupt-parent = <&mpc5200_pic>;
252 //};
254 ethernet@3000 {
255 device_type = "network";
256 compatible = "fsl,mpc5200-fec";
257 reg = <3000 800>;
258 local-mac-address = [ 00 00 00 00 00 00 ];
259 interrupts = <2 5 0>;
260 interrupt-parent = <&mpc5200_pic>;
261 };
263 ata@3a00 {
264 device_type = "ata";
265 compatible = "fsl,mpc5200-ata";
266 reg = <3a00 100>;
267 interrupts = <2 7 0>;
268 interrupt-parent = <&mpc5200_pic>;
269 };
271 i2c@3d00 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 compatible = "fsl,mpc5200-i2c","fsl-i2c";
275 cell-index = <0>;
276 reg = <3d00 40>;
277 interrupts = <2 f 0>;
278 interrupt-parent = <&mpc5200_pic>;
279 fsl5200-clocking;
280 };
282 i2c@3d40 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible = "fsl,mpc5200-i2c","fsl-i2c";
286 cell-index = <1>;
287 reg = <3d40 40>;
288 interrupts = <2 10 0>;
289 interrupt-parent = <&mpc5200_pic>;
290 fsl5200-clocking;
291 };
292 sram@8000 {
293 compatible = "fsl,mpc5200-sram","sram";
294 reg = <8000 4000>;
295 };
296 };
298 pci@f0000d00 {
299 #interrupt-cells = <1>;
300 #size-cells = <2>;
301 #address-cells = <3>;
302 device_type = "pci";
303 compatible = "fsl,mpc5200-pci";
304 reg = <f0000d00 100>;
305 interrupt-map-mask = <f800 0 0 7>;
306 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
307 c000 0 0 2 &mpc5200_pic 0 0 3
308 c000 0 0 3 &mpc5200_pic 0 0 3
309 c000 0 0 4 &mpc5200_pic 0 0 3>;
310 clock-frequency = <0>; // From boot loader
311 interrupts = <2 8 0 2 9 0 2 a 0>;
312 interrupt-parent = <&mpc5200_pic>;
313 bus-range = <0 0>;
314 ranges = <42000000 0 80000000 80000000 0 20000000
315 02000000 0 a0000000 a0000000 0 10000000
316 01000000 0 00000000 b0000000 0 01000000>;
317 };
318 };