debugfs: fix sparse warnings
[wrt350n-kernel.git] / include / linux / mmc / mmc.h
blob4236fbf0b6fbb831f4f617352e43ba3716d5188e
1 /*
2 * Header for MultiMediaCard (MMC)
4 * Copyright 2002 Hewlett-Packard Company
6 * Use consistent with the GNU GPL is permitted,
7 * provided that this copyright notice is
8 * preserved in its entirety in all copies and derived works.
10 * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
11 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
12 * FITNESS FOR ANY PARTICULAR PURPOSE.
14 * Many thanks to Alessandro Rubini and Jonathan Corbet!
16 * Based strongly on code by:
18 * Author: Yong-iL Joh <tolkien@mizi.com>
19 * Date : $Date: 2002/06/18 12:37:30 $
21 * Author: Andrew Christian
22 * 15 May 2002
25 #ifndef MMC_MMC_H
26 #define MMC_MMC_H
28 /* Standard MMC commands (4.1) type argument response */
29 /* class 1 */
30 #define MMC_GO_IDLE_STATE 0 /* bc */
31 #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
32 #define MMC_ALL_SEND_CID 2 /* bcr R2 */
33 #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
34 #define MMC_SET_DSR 4 /* bc [31:16] RCA */
35 #define MMC_SWITCH 6 /* ac [31:0] See below R1b */
36 #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
37 #define MMC_SEND_EXT_CSD 8 /* adtc R1 */
38 #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
39 #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
40 #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
41 #define MMC_STOP_TRANSMISSION 12 /* ac R1b */
42 #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
43 #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
44 #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
45 #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
47 /* class 2 */
48 #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
49 #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
50 #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
52 /* class 3 */
53 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
55 /* class 4 */
56 #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
57 #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
58 #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
59 #define MMC_PROGRAM_CID 26 /* adtc R1 */
60 #define MMC_PROGRAM_CSD 27 /* adtc R1 */
62 /* class 6 */
63 #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
64 #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
65 #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
67 /* class 5 */
68 #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
69 #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
70 #define MMC_ERASE 38 /* ac R1b */
72 /* class 9 */
73 #define MMC_FAST_IO 39 /* ac <Complex> R4 */
74 #define MMC_GO_IRQ_STATE 40 /* bcr R5 */
76 /* class 7 */
77 #define MMC_LOCK_UNLOCK 42 /* adtc R1b */
79 /* class 8 */
80 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
81 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
84 * MMC_SWITCH argument format:
86 * [31:26] Always 0
87 * [25:24] Access Mode
88 * [23:16] Location of target Byte in EXT_CSD
89 * [15:08] Value Byte
90 * [07:03] Always 0
91 * [02:00] Command Set
95 MMC status in R1, for native mode (SPI bits are different)
96 Type
97 e : error bit
98 s : status bit
99 r : detected and set for the actual command response
100 x : detected and set during command execution. the host must poll
101 the card by sending status command in order to read these bits.
102 Clear condition
103 a : according to the card state
104 b : always related to the previous command. Reception of
105 a valid command will clear it (with a delay of one command)
106 c : clear by read
109 #define R1_OUT_OF_RANGE (1 << 31) /* er, c */
110 #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
111 #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
112 #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
113 #define R1_ERASE_PARAM (1 << 27) /* ex, c */
114 #define R1_WP_VIOLATION (1 << 26) /* erx, c */
115 #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
116 #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
117 #define R1_COM_CRC_ERROR (1 << 23) /* er, b */
118 #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
119 #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
120 #define R1_CC_ERROR (1 << 20) /* erx, c */
121 #define R1_ERROR (1 << 19) /* erx, c */
122 #define R1_UNDERRUN (1 << 18) /* ex, c */
123 #define R1_OVERRUN (1 << 17) /* ex, c */
124 #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
125 #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
126 #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
127 #define R1_ERASE_RESET (1 << 13) /* sr, c */
128 #define R1_STATUS(x) (x & 0xFFFFE000)
129 #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
130 #define R1_READY_FOR_DATA (1 << 8) /* sx, a */
131 #define R1_APP_CMD (1 << 5) /* sr, c */
134 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
135 * R1 is the low order byte; R2 is the next highest byte, when present.
137 #define R1_SPI_IDLE (1 << 0)
138 #define R1_SPI_ERASE_RESET (1 << 1)
139 #define R1_SPI_ILLEGAL_COMMAND (1 << 2)
140 #define R1_SPI_COM_CRC (1 << 3)
141 #define R1_SPI_ERASE_SEQ (1 << 4)
142 #define R1_SPI_ADDRESS (1 << 5)
143 #define R1_SPI_PARAMETER (1 << 6)
144 /* R1 bit 7 is always zero */
145 #define R2_SPI_CARD_LOCKED (1 << 8)
146 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
147 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
148 #define R2_SPI_ERROR (1 << 10)
149 #define R2_SPI_CC_ERROR (1 << 11)
150 #define R2_SPI_CARD_ECC_ERROR (1 << 12)
151 #define R2_SPI_WP_VIOLATION (1 << 13)
152 #define R2_SPI_ERASE_PARAM (1 << 14)
153 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
154 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
156 /* These are unpacked versions of the actual responses */
158 struct _mmc_csd {
159 u8 csd_structure;
160 u8 spec_vers;
161 u8 taac;
162 u8 nsac;
163 u8 tran_speed;
164 u16 ccc;
165 u8 read_bl_len;
166 u8 read_bl_partial;
167 u8 write_blk_misalign;
168 u8 read_blk_misalign;
169 u8 dsr_imp;
170 u16 c_size;
171 u8 vdd_r_curr_min;
172 u8 vdd_r_curr_max;
173 u8 vdd_w_curr_min;
174 u8 vdd_w_curr_max;
175 u8 c_size_mult;
176 union {
177 struct { /* MMC system specification version 3.1 */
178 u8 erase_grp_size;
179 u8 erase_grp_mult;
180 } v31;
181 struct { /* MMC system specification version 2.2 */
182 u8 sector_size;
183 u8 erase_grp_size;
184 } v22;
185 } erase;
186 u8 wp_grp_size;
187 u8 wp_grp_enable;
188 u8 default_ecc;
189 u8 r2w_factor;
190 u8 write_bl_len;
191 u8 write_bl_partial;
192 u8 file_format_grp;
193 u8 copy;
194 u8 perm_write_protect;
195 u8 tmp_write_protect;
196 u8 file_format;
197 u8 ecc;
201 * OCR bits are mostly in host.h
203 #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
206 * Card Command Classes (CCC)
208 #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
209 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */
210 /* (and for SPI, CMD58,59) */
211 #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
212 /* (CMD11) */
213 #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
214 /* (CMD16,17,18) */
215 #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
216 /* (CMD20) */
217 #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
218 /* (CMD16,24,25,26,27) */
219 #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
220 /* (CMD32,33,34,35,36,37,38,39) */
221 #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
222 /* (CMD28,29,30) */
223 #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
224 /* (CMD16,CMD42) */
225 #define CCC_APP_SPEC (1<<8) /* (8) Application specific */
226 /* (CMD55,56,57,ACMD*) */
227 #define CCC_IO_MODE (1<<9) /* (9) I/O mode */
228 /* (CMD5,39,40,52,53) */
229 #define CCC_SWITCH (1<<10) /* (10) High speed switch */
230 /* (CMD6,34,35,36,37,50) */
231 /* (11) Reserved */
232 /* (CMD?) */
235 * CSD field definitions
238 #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
239 #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
240 #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
241 #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
243 #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
244 #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
245 #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
246 #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
247 #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
250 * EXT_CSD fields
253 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
254 #define EXT_CSD_HS_TIMING 185 /* R/W */
255 #define EXT_CSD_CARD_TYPE 196 /* RO */
256 #define EXT_CSD_REV 192 /* RO */
257 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
260 * EXT_CSD field definitions
263 #define EXT_CSD_CMD_SET_NORMAL (1<<0)
264 #define EXT_CSD_CMD_SET_SECURE (1<<1)
265 #define EXT_CSD_CMD_SET_CPSECURE (1<<2)
267 #define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
268 #define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
270 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
271 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
272 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
275 * MMC_SWITCH access modes
278 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
279 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
280 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
281 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
283 #endif /* MMC_MMC_PROTOCOL_H */