2 * ip22-mc.c: Routines for manipulating SGI Memory Controller.
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
5 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
6 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/kernel.h>
14 #include <asm/bootinfo.h>
15 #include <asm/sgialib.h>
16 #include <asm/sgi/mc.h>
17 #include <asm/sgi/hpc3.h>
18 #include <asm/sgi/ip22.h>
20 struct sgimc_regs
*sgimc
;
24 static inline unsigned long get_bank_addr(unsigned int memconfig
)
26 return ((memconfig
& SGIMC_MCONFIG_BASEADDR
) <<
27 ((sgimc
->systemid
& SGIMC_SYSID_MASKREV
) >= 5 ? 24 : 22));
30 static inline unsigned long get_bank_size(unsigned int memconfig
)
32 return ((memconfig
& SGIMC_MCONFIG_RMASK
) + 0x0100) <<
33 ((sgimc
->systemid
& SGIMC_SYSID_MASKREV
) >= 5 ? 16 : 14);
36 static inline unsigned int get_bank_config(int bank
)
38 unsigned int res
= bank
> 1 ? sgimc
->mconfig1
: sgimc
->mconfig0
;
39 return bank
% 2 ? res
& 0xffff : res
>> 16;
48 * Detect installed memory, do some sanity checks and notify kernel about it
50 static void __init
probe_memory(void)
52 int i
, j
, found
, cnt
= 0;
54 struct mem space
[2] = {{SGIMC_SEG0_BADDR
, 0}, {SGIMC_SEG1_BADDR
, 0}};
56 printk(KERN_INFO
"MC: Probing memory configuration:\n");
57 for (i
= 0; i
< ARRAY_SIZE(bank
); i
++) {
58 unsigned int tmp
= get_bank_config(i
);
59 if (!(tmp
& SGIMC_MCONFIG_BVALID
))
62 bank
[cnt
].size
= get_bank_size(tmp
);
63 bank
[cnt
].addr
= get_bank_addr(tmp
);
64 printk(KERN_INFO
" bank%d: %3ldM @ %08lx\n",
65 i
, bank
[cnt
].size
/ 1024 / 1024, bank
[cnt
].addr
);
69 /* And you thought bubble sort is dead algorithm... */
71 unsigned long addr
, size
;
74 for (i
= 1; i
< cnt
; i
++)
75 if (bank
[i
-1].addr
> bank
[i
].addr
) {
78 bank
[i
].addr
= bank
[i
-1].addr
;
79 bank
[i
].size
= bank
[i
-1].size
;
80 bank
[i
-1].addr
= addr
;
81 bank
[i
-1].size
= size
;
86 /* Figure out how are memory banks mapped into spaces */
87 for (i
= 0; i
< cnt
; i
++) {
89 for (j
= 0; j
< ARRAY_SIZE(space
) && !found
; j
++)
90 if (space
[j
].addr
+ space
[j
].size
== bank
[i
].addr
) {
91 space
[j
].size
+= bank
[i
].size
;
94 /* There is either hole or overlapping memory */
96 printk(KERN_CRIT
"MC: Memory configuration mismatch "
97 "(%08lx), expect Bus Error soon\n",
101 for (i
= 0; i
< ARRAY_SIZE(space
); i
++)
103 add_memory_region(space
[i
].addr
, space
[i
].size
,
107 void __init
sgimc_init(void)
111 /* ioremap can't fail */
112 sgimc
= (struct sgimc_regs
*)
113 ioremap(SGIMC_BASE
, sizeof(struct sgimc_regs
));
115 printk(KERN_INFO
"MC: SGI memory controller Revision %d\n",
116 (int) sgimc
->systemid
& SGIMC_SYSID_MASKREV
);
118 /* Place the MC into a known state. This must be done before
119 * interrupts are first enabled etc.
122 /* Step 0: Make sure we turn off the watchdog in case it's
123 * still running (which might be the case after a
126 tmp
= sgimc
->cpuctrl0
;
127 tmp
&= ~SGIMC_CCTRL0_WDOG
;
128 sgimc
->cpuctrl0
= tmp
;
130 /* Step 1: The CPU/GIO error status registers will not latch
131 * up a new error status until the register has been
132 * cleared by the cpu. These status registers are
133 * cleared by writing any value to them.
135 sgimc
->cstat
= sgimc
->gstat
= 0;
137 /* Step 2: Enable all parity checking in cpu control register
140 tmp
= sgimc
->cpuctrl0
;
141 tmp
|= (SGIMC_CCTRL0_EPERRGIO
| SGIMC_CCTRL0_EPERRMEM
|
142 SGIMC_CCTRL0_R4KNOCHKPARR
);
143 sgimc
->cpuctrl0
= tmp
;
145 /* Step 3: Setup the MC write buffer depth, this is controlled
146 * in cpu control register 1 in the lower 4 bits.
148 tmp
= sgimc
->cpuctrl1
;
151 sgimc
->cpuctrl1
= tmp
;
153 /* Step 4: Initialize the RPSS divider register to run as fast
154 * as it can correctly operate. The register is laid
157 * ----------------------------------------
158 * | RESERVED | INCREMENT | DIVIDER |
159 * ----------------------------------------
162 * DIVIDER determines how often a 'tick' happens,
163 * INCREMENT determines by how the RPSS increment
164 * registers value increases at each 'tick'. Thus,
165 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
167 sgimc
->divider
= 0x101;
169 /* Step 5: Initialize GIO64 arbitrator configuration register.
171 * NOTE: HPC init code in sgihpc_init() must run before us because
172 * we need to know Guiness vs. FullHouse and the board
173 * revision on this machine. You have been warned.
176 /* First the basic invariants across all GIO64 implementations. */
177 tmp
= SGIMC_GIOPAR_HPC64
; /* All 1st HPC's interface at 64bits */
178 tmp
|= SGIMC_GIOPAR_ONEBUS
; /* Only one physical GIO bus exists */
180 if (ip22_is_fullhouse()) {
181 /* Fullhouse specific settings. */
182 if (SGIOC_SYSID_BOARDREV(sgioc
->sysid
) < 2) {
183 tmp
|= SGIMC_GIOPAR_HPC264
; /* 2nd HPC at 64bits */
184 tmp
|= SGIMC_GIOPAR_PLINEEXP0
; /* exp0 pipelines */
185 tmp
|= SGIMC_GIOPAR_MASTEREXP1
; /* exp1 masters */
186 tmp
|= SGIMC_GIOPAR_RTIMEEXP0
; /* exp0 is realtime */
188 tmp
|= SGIMC_GIOPAR_HPC264
; /* 2nd HPC 64bits */
189 tmp
|= SGIMC_GIOPAR_PLINEEXP0
; /* exp[01] pipelined */
190 tmp
|= SGIMC_GIOPAR_PLINEEXP1
;
191 tmp
|= SGIMC_GIOPAR_MASTEREISA
; /* EISA masters */
192 tmp
|= SGIMC_GIOPAR_GFX64
; /* GFX at 64 bits */
195 /* Guiness specific settings. */
196 tmp
|= SGIMC_GIOPAR_EISA64
; /* MC talks to EISA at 64bits */
197 tmp
|= SGIMC_GIOPAR_MASTEREISA
; /* EISA bus can act as master */
199 sgimc
->giopar
= tmp
; /* poof */
204 void __init
prom_meminit(void) {}
205 void __init
prom_free_prom_memory(void)