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x86: restore correct module name for apm
[wrt350n-kernel.git] / drivers / rtc / rtc-sa1100.c
blob2eb38520f0c8cf267f57360ae16970623e316588
1 /*
2 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
3 *
4 * Copyright (c) 2000 Nils Faerber
5 *
6 * Based on rtc.c by Paul Gortmaker
7 *
8 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
9 *
10 * Modifications from:
11 * CIH <cih@coventive.com>
12 * Nicolas Pitre <nico@cam.org>
13 * Andrew Christian <andrew.christian@hp.com>
14 *
15 * Converted to the RTC subsystem and Driver Model
16 * by Richard Purdie <rpurdie@rpsys.net>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24 #include <linux/platform_device.h>
25 #include <linux/module.h>
26 #include <linux/rtc.h>
27 #include <linux/init.h>
28 #include <linux/fs.h>
29 #include <linux/interrupt.h>
30 #include <linux/string.h>
31 #include <linux/pm.h>
32 #include <linux/bitops.h>
33
34 #include <asm/hardware.h>
35 #include <asm/irq.h>
36 #include <asm/rtc.h>
37
38 #ifdef CONFIG_ARCH_PXA
39 #include <asm/arch/pxa-regs.h>
40 #endif
41
42 #define TIMER_FREQ CLOCK_TICK_RATE
43 #define RTC_DEF_DIVIDER 32768 - 1
44 #define RTC_DEF_TRIM 0
45
46 static unsigned long rtc_freq = 1024;
47 static struct rtc_time rtc_alarm;
48 static DEFINE_SPINLOCK(sa1100_rtc_lock);
49
50 static int rtc_update_alarm(struct rtc_time *alrm)
51 {
52 struct rtc_time alarm_tm, now_tm;
53 unsigned long now, time;
54 int ret;
55
56 do {
57 now = RCNR;
58 rtc_time_to_tm(now, &now_tm);
59 rtc_next_alarm_time(&alarm_tm, &now_tm, alrm);
60 ret = rtc_tm_to_time(&alarm_tm, &time);
61 if (ret != 0)
62 break;
63
64 RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
65 RTAR = time;
66 } while (now != RCNR);
67
68 return ret;
69 }
70
71 static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
72 {
73 struct platform_device *pdev = to_platform_device(dev_id);
74 struct rtc_device *rtc = platform_get_drvdata(pdev);
75 unsigned int rtsr;
76 unsigned long events = 0;
77
78 spin_lock(&sa1100_rtc_lock);
79
80 rtsr = RTSR;
81 /* clear interrupt sources */
82 RTSR = 0;
83 RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2);
84
85 /* clear alarm interrupt if it has occurred */
86 if (rtsr & RTSR_AL)
87 rtsr &= ~RTSR_ALE;
88 RTSR = rtsr & (RTSR_ALE | RTSR_HZE);
89
90 /* update irq data & counter */
91 if (rtsr & RTSR_AL)
92 events |= RTC_AF | RTC_IRQF;
93 if (rtsr & RTSR_HZ)
94 events |= RTC_UF | RTC_IRQF;
95
96 rtc_update_irq(rtc, 1, events);
97
98 if (rtsr & RTSR_AL && rtc_periodic_alarm(&rtc_alarm))
99 rtc_update_alarm(&rtc_alarm);
100
101 spin_unlock(&sa1100_rtc_lock);
102
103 return IRQ_HANDLED;
104 }
105
106 static int rtc_timer1_count;
107
108 static irqreturn_t timer1_interrupt(int irq, void *dev_id)
109 {
110 struct platform_device *pdev = to_platform_device(dev_id);
111 struct rtc_device *rtc = platform_get_drvdata(pdev);
112
113 /*
114 * If we match for the first time, rtc_timer1_count will be 1.
115 * Otherwise, we wrapped around (very unlikely but
116 * still possible) so compute the amount of missed periods.
117 * The match reg is updated only when the data is actually retrieved
118 * to avoid unnecessary interrupts.
119 */
120 OSSR = OSSR_M1; /* clear match on timer1 */
121
122 rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);
123
124 if (rtc_timer1_count == 1)
125 rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2)));
126
127 return IRQ_HANDLED;
128 }
129
130 static int sa1100_rtc_read_callback(struct device *dev, int data)
131 {
132 if (data & RTC_PF) {
133 /* interpolate missed periods and set match for the next */
134 unsigned long period = TIMER_FREQ/rtc_freq;
135 unsigned long oscr = OSCR;
136 unsigned long osmr1 = OSMR1;
137 unsigned long missed = (oscr - osmr1)/period;
138 data += missed << 8;
139 OSSR = OSSR_M1; /* clear match on timer 1 */
140 OSMR1 = osmr1 + (missed + 1)*period;
141 /* Ensure we didn't miss another match in the mean time.
142 * Here we compare (match - OSCR) 8 instead of 0 --
143 * see comment in pxa_timer_interrupt() for explanation.
144 */
145 while( (signed long)((osmr1 = OSMR1) - OSCR) <= 8 ) {
146 data += 0x100;
147 OSSR = OSSR_M1; /* clear match on timer 1 */
148 OSMR1 = osmr1 + period;
149 }
150 }
151 return data;
152 }
153
154 static int sa1100_rtc_open(struct device *dev)
155 {
156 int ret;
157
158 ret = request_irq(IRQ_RTC1Hz, sa1100_rtc_interrupt, IRQF_DISABLED,
159 "rtc 1Hz", dev);
160 if (ret) {
161 dev_err(dev, "IRQ %d already in use.\n", IRQ_RTC1Hz);
162 goto fail_ui;
163 }
164 ret = request_irq(IRQ_RTCAlrm, sa1100_rtc_interrupt, IRQF_DISABLED,
165 "rtc Alrm", dev);
166 if (ret) {
167 dev_err(dev, "IRQ %d already in use.\n", IRQ_RTCAlrm);
168 goto fail_ai;
169 }
170 ret = request_irq(IRQ_OST1, timer1_interrupt, IRQF_DISABLED,
171 "rtc timer", dev);
172 if (ret) {
173 dev_err(dev, "IRQ %d already in use.\n", IRQ_OST1);
174 goto fail_pi;
175 }
176 return 0;
177
178 fail_pi:
179 free_irq(IRQ_RTCAlrm, dev);
180 fail_ai:
181 free_irq(IRQ_RTC1Hz, dev);
182 fail_ui:
183 return ret;
184 }
185
186 static void sa1100_rtc_release(struct device *dev)
187 {
188 spin_lock_irq(&sa1100_rtc_lock);
189 RTSR = 0;
190 OIER &= ~OIER_E1;
191 OSSR = OSSR_M1;
192 spin_unlock_irq(&sa1100_rtc_lock);
193
194 free_irq(IRQ_OST1, dev);
195 free_irq(IRQ_RTCAlrm, dev);
196 free_irq(IRQ_RTC1Hz, dev);
197 }
198
199
200 static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
201 unsigned long arg)
202 {
203 switch(cmd) {
204 case RTC_AIE_OFF:
205 spin_lock_irq(&sa1100_rtc_lock);
206 RTSR &= ~RTSR_ALE;
207 spin_unlock_irq(&sa1100_rtc_lock);
208 return 0;
209 case RTC_AIE_ON:
210 spin_lock_irq(&sa1100_rtc_lock);
211 RTSR |= RTSR_ALE;
212 spin_unlock_irq(&sa1100_rtc_lock);
213 return 0;
214 case RTC_UIE_OFF:
215 spin_lock_irq(&sa1100_rtc_lock);
216 RTSR &= ~RTSR_HZE;
217 spin_unlock_irq(&sa1100_rtc_lock);
218 return 0;
219 case RTC_UIE_ON:
220 spin_lock_irq(&sa1100_rtc_lock);
221 RTSR |= RTSR_HZE;
222 spin_unlock_irq(&sa1100_rtc_lock);
223 return 0;
224 case RTC_PIE_OFF:
225 spin_lock_irq(&sa1100_rtc_lock);
226 OIER &= ~OIER_E1;
227 spin_unlock_irq(&sa1100_rtc_lock);
228 return 0;
229 case RTC_PIE_ON:
230 spin_lock_irq(&sa1100_rtc_lock);
231 OSMR1 = TIMER_FREQ/rtc_freq + OSCR;
232 OIER |= OIER_E1;
233 rtc_timer1_count = 1;
234 spin_unlock_irq(&sa1100_rtc_lock);
235 return 0;
236 case RTC_IRQP_READ:
237 return put_user(rtc_freq, (unsigned long *)arg);
238 case RTC_IRQP_SET:
239 if (arg < 1 || arg > TIMER_FREQ)
240 return -EINVAL;
241 rtc_freq = arg;
242 return 0;
243 }
244 return -ENOIOCTLCMD;
245 }
246
247 static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
248 {
249 rtc_time_to_tm(RCNR, tm);
250 return 0;
251 }
252
253 static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
254 {
255 unsigned long time;
256 int ret;
257
258 ret = rtc_tm_to_time(tm, &time);
259 if (ret == 0)
260 RCNR = time;
261 return ret;
262 }
263
264 static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
265 {
266 u32 rtsr;
267
268 memcpy(&alrm->time, &rtc_alarm, sizeof(struct rtc_time));
269 rtsr = RTSR;
270 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
271 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
272 return 0;
273 }
274
275 static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
276 {
277 int ret;
278
279 spin_lock_irq(&sa1100_rtc_lock);
280 ret = rtc_update_alarm(&alrm->time);
281 if (ret == 0) {
282 if (alrm->enabled)
283 RTSR |= RTSR_ALE;
284 else
285 RTSR &= ~RTSR_ALE;
286 }
287 spin_unlock_irq(&sa1100_rtc_lock);
288
289 return ret;
290 }
291
292 static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
293 {
294 seq_printf(seq, "trim/divider\t: 0x%08x\n", (u32) RTTR);
295 seq_printf(seq, "update_IRQ\t: %s\n",
296 (RTSR & RTSR_HZE) ? "yes" : "no");
297 seq_printf(seq, "periodic_IRQ\t: %s\n",
298 (OIER & OIER_E1) ? "yes" : "no");
299 seq_printf(seq, "periodic_freq\t: %ld\n", rtc_freq);
300
301 return 0;
302 }
303
304 static const struct rtc_class_ops sa1100_rtc_ops = {
305 .open = sa1100_rtc_open,
306 .read_callback = sa1100_rtc_read_callback,
307 .release = sa1100_rtc_release,
308 .ioctl = sa1100_rtc_ioctl,
309 .read_time = sa1100_rtc_read_time,
310 .set_time = sa1100_rtc_set_time,
311 .read_alarm = sa1100_rtc_read_alarm,
312 .set_alarm = sa1100_rtc_set_alarm,
313 .proc = sa1100_rtc_proc,
314 };
315
316 static int sa1100_rtc_probe(struct platform_device *pdev)
317 {
318 struct rtc_device *rtc;
319
320 /*
321 * According to the manual we should be able to let RTTR be zero
322 * and then a default diviser for a 32.768KHz clock is used.
323 * Apparently this doesn't work, at least for my SA1110 rev 5.
324 * If the clock divider is uninitialized then reset it to the
325 * default value to get the 1Hz clock.
326 */
327 if (RTTR == 0) {
328 RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
329 dev_warn(&pdev->dev, "warning: initializing default clock divider/trim value\n");
330 /* The current RTC value probably doesn't make sense either */
331 RCNR = 0;
332 }
333
334 rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
335 THIS_MODULE);
336
337 if (IS_ERR(rtc))
338 return PTR_ERR(rtc);
339
340 device_init_wakeup(&pdev->dev, 1);
341
342 platform_set_drvdata(pdev, rtc);
343
344 return 0;
345 }
346
347 static int sa1100_rtc_remove(struct platform_device *pdev)
348 {
349 struct rtc_device *rtc = platform_get_drvdata(pdev);
350
351 if (rtc)
352 rtc_device_unregister(rtc);
353
354 return 0;
355 }
356
357 #ifdef CONFIG_PM
358 static int sa1100_rtc_suspend(struct platform_device *pdev, pm_message_t state)
359 {
360 if (pdev->dev.power.power_state.event != state.event) {
361 if (state.event == PM_EVENT_SUSPEND &&
362 device_may_wakeup(&pdev->dev))
363 enable_irq_wake(IRQ_RTCAlrm);
364
365 pdev->dev.power.power_state = state;
366 }
367 return 0;
368 }
369
370 static int sa1100_rtc_resume(struct platform_device *pdev)
371 {
372 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
373 if (device_may_wakeup(&pdev->dev))
374 disable_irq_wake(IRQ_RTCAlrm);
375 pdev->dev.power.power_state = PMSG_ON;
376 }
377 return 0;
378 }
379 #else
380 #define sa1100_rtc_suspend NULL
381 #define sa1100_rtc_resume NULL
382 #endif
383
384 static struct platform_driver sa1100_rtc_driver = {
385 .probe = sa1100_rtc_probe,
386 .remove = sa1100_rtc_remove,
387 .suspend = sa1100_rtc_suspend,
388 .resume = sa1100_rtc_resume,
389 .driver = {
390 .name = "sa1100-rtc",
391 },
392 };
393
394 static int __init sa1100_rtc_init(void)
395 {
396 return platform_driver_register(&sa1100_rtc_driver);
397 }
398
399 static void __exit sa1100_rtc_exit(void)
400 {
401 platform_driver_unregister(&sa1100_rtc_driver);
402 }
403
404 module_init(sa1100_rtc_init);
405 module_exit(sa1100_rtc_exit);
406
407 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
408 MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
409 MODULE_LICENSE("GPL");
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