?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
au1550_spi: fix prototype of irq handler
[wrt350n-kernel.git] / arch / mips / jmr3927 / rbhma3100 / setup.c
blobc886d804d3037d964db8ae277b3c5da3ca2ebeda
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2001 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * ahennessy@mvista.com
25 *
26 * Copyright (C) 2000-2001 Toshiba Corporation
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
28 */
29
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/ioport.h>
35 #include <linux/delay.h>
36 #include <linux/pm.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #ifdef CONFIG_SERIAL_TXX9
40 #include <linux/serial_core.h>
41 #endif
42
43 #include <asm/txx9tmr.h>
44 #include <asm/reboot.h>
45 #include <asm/jmr3927/jmr3927.h>
46 #include <asm/mipsregs.h>
47
48 extern void puts(const char *cp);
49
50 /* don't enable - see errata */
51 static int jmr3927_ccfg_toeon;
52
53 static inline void do_reset(void)
54 {
55 #if 1 /* Resetting PCI bus */
56 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
57 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
58 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
59 mdelay(1);
60 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
61 #endif
62 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
63 }
64
65 static void jmr3927_machine_restart(char *command)
66 {
67 local_irq_disable();
68 puts("Rebooting...");
69 do_reset();
70 }
71
72 static void jmr3927_machine_halt(void)
73 {
74 puts("JMR-TX3927 halted.\n");
75 while (1);
76 }
77
78 static void jmr3927_machine_power_off(void)
79 {
80 puts("JMR-TX3927 halted. Please turn off the power.\n");
81 while (1);
82 }
83
84 void __init plat_time_init(void)
85 {
86 txx9_clockevent_init(TX3927_TMR_REG(0),
87 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
88 JMR3927_IMCLK);
89 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
90 }
91
92 #define DO_WRITE_THROUGH
93 #define DO_ENABLE_CACHE
94
95 extern char * __init prom_getcmdline(void);
96 static void jmr3927_board_init(void);
97 extern struct resource pci_io_resource;
98 extern struct resource pci_mem_resource;
99
100 void __init plat_mem_setup(void)
101 {
102 char *argptr;
103
104 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
105
106 _machine_restart = jmr3927_machine_restart;
107 _machine_halt = jmr3927_machine_halt;
108 pm_power_off = jmr3927_machine_power_off;
109
110 /*
111 * IO/MEM resources.
112 */
113 ioport_resource.start = pci_io_resource.start;
114 ioport_resource.end = pci_io_resource.end;
115 iomem_resource.start = 0;
116 iomem_resource.end = 0xffffffff;
117
118 /* Reboot on panic */
119 panic_timeout = 180;
120
121 /* cache setup */
122 {
123 unsigned int conf;
124 #ifdef DO_ENABLE_CACHE
125 int mips_ic_disable = 0, mips_dc_disable = 0;
126 #else
127 int mips_ic_disable = 1, mips_dc_disable = 1;
128 #endif
129 #ifdef DO_WRITE_THROUGH
130 int mips_config_cwfon = 0;
131 int mips_config_wbon = 0;
132 #else
133 int mips_config_cwfon = 1;
134 int mips_config_wbon = 1;
135 #endif
136
137 conf = read_c0_conf();
138 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
139 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
140 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
141 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
142 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
143
144 write_c0_conf(conf);
145 write_c0_cache(0);
146 }
147
148 /* initialize board */
149 jmr3927_board_init();
150
151 argptr = prom_getcmdline();
152
153 if ((argptr = strstr(argptr, "toeon")) != NULL)
154 jmr3927_ccfg_toeon = 1;
155 argptr = prom_getcmdline();
156 if ((argptr = strstr(argptr, "ip=")) == NULL) {
157 argptr = prom_getcmdline();
158 strcat(argptr, " ip=bootp");
159 }
160
161 #ifdef CONFIG_SERIAL_TXX9
162 {
163 extern int early_serial_txx9_setup(struct uart_port *port);
164 int i;
165 struct uart_port req;
166 for(i = 0; i < 2; i++) {
167 memset(&req, 0, sizeof(req));
168 req.line = i;
169 req.iotype = UPIO_MEM;
170 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
171 req.mapbase = TX3927_SIO_REG(i);
172 req.irq = i == 0 ?
173 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
174 if (i == 0)
175 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
176 req.uartclk = JMR3927_IMCLK;
177 early_serial_txx9_setup(&req);
178 }
179 }
180 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
181 argptr = prom_getcmdline();
182 if ((argptr = strstr(argptr, "console=")) == NULL) {
183 argptr = prom_getcmdline();
184 strcat(argptr, " console=ttyS1,115200");
185 }
186 #endif
187 #endif
188 }
189
190 static void tx3927_setup(void);
191
192 static void __init jmr3927_board_init(void)
193 {
194 tx3927_setup();
195
196 /* SIO0 DTR on */
197 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
198
199 jmr3927_led_set(0);
200
201 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
202 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
203 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
204 jmr3927_dipsw1(), jmr3927_dipsw2(),
205 jmr3927_dipsw3(), jmr3927_dipsw4());
206 }
207
208 static void __init tx3927_setup(void)
209 {
210 int i;
211 #ifdef CONFIG_PCI
212 unsigned long mips_pci_io_base = JMR3927_PCIIO;
213 unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
214 unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
215 unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
216 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
217 unsigned long mips_pci_io_pciaddr = 0;
218 #endif
219
220 /* SDRAMC are configured by PROM */
221
222 /* ROMC */
223 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
224 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
225 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
226 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
227
228 /* CCFG */
229 /* enable Timeout BusError */
230 if (jmr3927_ccfg_toeon)
231 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
232
233 /* clear BusErrorOnWrite flag */
234 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
235 /* Disable PCI snoop */
236 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
237 /* do reset on watchdog */
238 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
239
240 #ifdef DO_WRITE_THROUGH
241 /* Enable PCI SNOOP - with write through only */
242 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
243 #endif
244
245 /* Pin selection */
246 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
247 tx3927_ccfgptr->pcfg |=
248 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
249 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
250
251 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
252 tx3927_ccfgptr->crir,
253 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
254
255 /* TMR */
256 for (i = 0; i < TX3927_NR_TMR; i++)
257 txx9_tmr_init(TX3927_TMR_REG(i));
258
259 /* DMA */
260 tx3927_dmaptr->mcr = 0;
261 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
262 /* reset channel */
263 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
264 tx3927_dmaptr->ch[i].ccr = 0;
265 }
266 /* enable DMA */
267 #ifdef __BIG_ENDIAN
268 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
269 #else
270 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
271 #endif
272
273 #ifdef CONFIG_PCI
274 /* PCIC */
275 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
276 tx3927_pcicptr->did, tx3927_pcicptr->vid,
277 tx3927_pcicptr->rid);
278 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
279 printk("External\n");
280 /* XXX */
281 } else {
282 printk("Internal\n");
283
284 /* Reset PCI Bus */
285 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
286 udelay(100);
287 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
288 JMR3927_IOC_RESET_ADDR);
289 udelay(100);
290 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
291
292
293 /* Disable External PCI Config. Access */
294 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
295 #ifdef __BIG_ENDIAN
296 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
297 TX3927_PCIC_LBC_TIBSE |
298 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
299 #endif
300 /* LB->PCI mappings */
301 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
302 tx3927_pcicptr->ilbioma = mips_pci_io_base;
303 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
304 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
305 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
306 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
307 /* PCI->LB mappings */
308 tx3927_pcicptr->iobas = 0xffffffff;
309 tx3927_pcicptr->ioba = 0;
310 tx3927_pcicptr->tlbioma = 0;
311 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
312 tx3927_pcicptr->mba = 0;
313 tx3927_pcicptr->tlbmma = 0;
314 /* Enable Direct mapping Address Space Decoder */
315 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
316
317 /* Clear All Local Bus Status */
318 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
319 /* Enable All Local Bus Interrupts */
320 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
321 /* Clear All PCI Status Error */
322 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
323 /* Enable All PCI Status Error Interrupts */
324 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
325
326 /* PCIC Int => IRC IRQ10 */
327 tx3927_pcicptr->il = TX3927_IR_PCI;
328 /* Target Control (per errata) */
329 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
330
331 /* Enable Bus Arbiter */
332 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
333
334 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
335 PCI_COMMAND_MEMORY |
336 PCI_COMMAND_IO |
337 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
338 }
339 #endif /* CONFIG_PCI */
340
341 /* PIO */
342 /* PIO[15:12] connected to LEDs */
343 tx3927_pioptr->dir = 0x0000f000;
344 tx3927_pioptr->maskcpu = 0;
345 tx3927_pioptr->maskext = 0;
346 {
347 unsigned int conf;
348
349 conf = read_c0_conf();
350 if (!(conf & TX39_CONF_ICE))
351 printk("TX3927 I-Cache disabled.\n");
352 if (!(conf & TX39_CONF_DCE))
353 printk("TX3927 D-Cache disabled.\n");
354 else if (!(conf & TX39_CONF_WBON))
355 printk("TX3927 D-Cache WriteThrough.\n");
356 else if (!(conf & TX39_CONF_CWFON))
357 printk("TX3927 D-Cache WriteBack.\n");
358 else
359 printk("TX3927 D-Cache WriteBack (CWF) .\n");
360 }
361 }
362
363 /* This trick makes rtc-ds1742 driver usable as is. */
364 unsigned long __swizzle_addr_b(unsigned long port)
365 {
366 if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
367 return port;
368 port = (port & 0xffff0000) | (port & 0x7fff << 1);
369 #ifdef __BIG_ENDIAN
370 return port;
371 #else
372 return port | 1;
373 #endif
374 }
375 EXPORT_SYMBOL(__swizzle_addr_b);
376
377 static int __init jmr3927_rtc_init(void)
378 {
379 static struct resource __initdata res = {
380 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
381 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
382 .flags = IORESOURCE_MEM,
383 };
384 struct platform_device *dev;
385 dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
386 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
387 }
388 device_initcall(jmr3927_rtc_init);
389
390 /* Watchdog support */
391
392 static int __init txx9_wdt_init(unsigned long base)
393 {
394 struct resource res = {
395 .start = base,
396 .end = base + 0x100 - 1,
397 .flags = IORESOURCE_MEM,
398 };
399 struct platform_device *dev =
400 platform_device_register_simple("txx9wdt", -1, &res, 1);
401 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
402 }
403
404 static int __init jmr3927_wdt_init(void)
405 {
406 return txx9_wdt_init(TX3927_TMR_REG(2));
407 }
408 device_initcall(jmr3927_wdt_init);
409
410 /* Minimum CLK support */
411
412 struct clk *clk_get(struct device *dev, const char *id)
413 {
414 if (!strcmp(id, "imbus_clk"))
415 return (struct clk *)JMR3927_IMCLK;
416 return ERR_PTR(-ENOENT);
417 }
418 EXPORT_SYMBOL(clk_get);
419
420 int clk_enable(struct clk *clk)
421 {
422 return 0;
423 }
424 EXPORT_SYMBOL(clk_enable);
425
426 void clk_disable(struct clk *clk)
427 {
428 }
429 EXPORT_SYMBOL(clk_disable);
430
431 unsigned long clk_get_rate(struct clk *clk)
432 {
433 return (unsigned long)clk;
434 }
435 EXPORT_SYMBOL(clk_get_rate);
436
437 void clk_put(struct clk *clk)
438 {
439 }
440 EXPORT_SYMBOL(clk_put);
WRT350N Kernel Patches