2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
9 #include <linux/clockchips.h>
10 #include <linux/interrupt.h>
11 #include <linux/percpu.h>
13 #include <asm/smtc_ipi.h>
16 static int mips_next_event(unsigned long delta
,
17 struct clock_event_device
*evt
)
22 #ifdef CONFIG_MIPS_MT_SMTC
24 unsigned long flags
, vpflags
;
25 local_irq_save(flags
);
28 cnt
= read_c0_count();
30 write_c0_compare(cnt
);
31 res
= ((int)(read_c0_count() - cnt
) > 0) ? -ETIME
: 0;
32 #ifdef CONFIG_MIPS_MT_SMTC
34 local_irq_restore(flags
);
40 static void mips_set_mode(enum clock_event_mode mode
,
41 struct clock_event_device
*evt
)
43 /* Nothing to do ... */
46 static DEFINE_PER_CPU(struct clock_event_device
, mips_clockevent_device
);
47 static int cp0_timer_irq_installed
;
50 * Timer ack for an R4k-compatible timer of a known frequency.
52 static void c0_timer_ack(void)
54 write_c0_compare(read_c0_compare());
58 * Possibly handle a performance counter interrupt.
59 * Return true if the timer interrupt should not be checked
61 static inline int handle_perf_irq(int r2
)
64 * The performance counter overflow interrupt may be shared with the
65 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
66 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
67 * and we can't reliably determine if a counter interrupt has also
68 * happened (!r2) then don't check for a timer interrupt.
70 return (cp0_perfcount_irq
< 0) &&
71 perf_irq() == IRQ_HANDLED
&&
75 static irqreturn_t
c0_compare_interrupt(int irq
, void *dev_id
)
77 const int r2
= cpu_has_mips_r2
;
78 struct clock_event_device
*cd
;
79 int cpu
= smp_processor_id();
83 * Before R2 of the architecture there was no way to see if a
84 * performance counter interrupt was pending, so we have to run
85 * the performance counter interrupt handler anyway.
87 if (handle_perf_irq(r2
))
91 * The same applies to performance counter interrupts. But with the
92 * above we now know that the reason we got here must be a timer
93 * interrupt. Being the paranoiacs we are we check anyway.
95 if (!r2
|| (read_c0_cause() & (1 << 30))) {
97 #ifdef CONFIG_MIPS_MT_SMTC
98 if (cpu_data
[cpu
].vpe_id
)
102 cd
= &per_cpu(mips_clockevent_device
, cpu
);
103 cd
->event_handler(cd
);
110 static struct irqaction c0_compare_irqaction
= {
111 .handler
= c0_compare_interrupt
,
112 #ifdef CONFIG_MIPS_MT_SMTC
113 .flags
= IRQF_DISABLED
,
115 .flags
= IRQF_DISABLED
| IRQF_PERCPU
,
120 #ifdef CONFIG_MIPS_MT_SMTC
121 DEFINE_PER_CPU(struct clock_event_device
, smtc_dummy_clockevent_device
);
123 static void smtc_set_mode(enum clock_event_mode mode
,
124 struct clock_event_device
*evt
)
128 static void mips_broadcast(cpumask_t mask
)
132 for_each_cpu_mask(cpu
, mask
)
133 smtc_send_ipi(cpu
, SMTC_CLOCK_TICK
, 0);
136 static void setup_smtc_dummy_clockevent_device(void)
138 //uint64_t mips_freq = mips_hpt_^frequency;
139 unsigned int cpu
= smp_processor_id();
140 struct clock_event_device
*cd
;
142 cd
= &per_cpu(smtc_dummy_clockevent_device
, cpu
);
145 cd
->features
= CLOCK_EVT_FEAT_DUMMY
;
147 /* Calculate the min / max delta */
148 cd
->mult
= 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
150 cd
->max_delta_ns
= 0; //clockevent_delta2ns(0x7fffffff, cd);
151 cd
->min_delta_ns
= 0; //clockevent_delta2ns(0x30, cd);
156 // cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
158 cd
->cpumask
= cpumask_of_cpu(cpu
);
160 cd
->set_mode
= smtc_set_mode
;
162 cd
->broadcast
= mips_broadcast
;
164 clockevents_register_device(cd
);
168 static void mips_event_handler(struct clock_event_device
*dev
)
173 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
175 static int c0_compare_int_pending(void)
177 return (read_c0_cause() >> cp0_compare_irq
) & 0x100;
180 static int c0_compare_int_usable(void)
186 * IP7 already pending? Try to clear it by acking the timer.
188 if (c0_compare_int_pending()) {
189 write_c0_compare(read_c0_count());
190 irq_disable_hazard();
191 if (c0_compare_int_pending())
195 for (delta
= 0x10; delta
<= 0x400000; delta
<<= 1) {
196 cnt
= read_c0_count();
198 write_c0_compare(cnt
);
199 irq_disable_hazard();
200 if ((int)(read_c0_count() - cnt
) < 0)
202 /* increase delta if the timer was already expired */
205 while ((int)(read_c0_count() - cnt
) <= 0)
206 ; /* Wait for expiry */
208 if (!c0_compare_int_pending())
211 write_c0_compare(read_c0_count());
212 irq_disable_hazard();
213 if (c0_compare_int_pending())
217 * Feels like a real count / compare timer.
222 int __cpuinit
mips_clockevent_init(void)
224 uint64_t mips_freq
= mips_hpt_frequency
;
225 unsigned int cpu
= smp_processor_id();
226 struct clock_event_device
*cd
;
229 if (!cpu_has_counter
|| !mips_hpt_frequency
)
232 #ifdef CONFIG_MIPS_MT_SMTC
233 setup_smtc_dummy_clockevent_device();
236 * On SMTC we only register VPE0's compare interrupt as clockevent
243 if (!c0_compare_int_usable())
247 * With vectored interrupts things are getting platform specific.
248 * get_c0_compare_int is a hook to allow a platform to return the
249 * interrupt number of it's liking.
251 irq
= MIPS_CPU_IRQ_BASE
+ cp0_compare_irq
;
252 if (get_c0_compare_int
)
253 irq
= get_c0_compare_int();
255 cd
= &per_cpu(mips_clockevent_device
, cpu
);
258 cd
->features
= CLOCK_EVT_FEAT_ONESHOT
;
260 /* Calculate the min / max delta */
261 cd
->mult
= div_sc((unsigned long) mips_freq
, NSEC_PER_SEC
, 32);
263 cd
->max_delta_ns
= clockevent_delta2ns(0x7fffffff, cd
);
264 cd
->min_delta_ns
= clockevent_delta2ns(0x300, cd
);
268 #ifdef CONFIG_MIPS_MT_SMTC
269 cd
->cpumask
= CPU_MASK_ALL
;
271 cd
->cpumask
= cpumask_of_cpu(cpu
);
273 cd
->set_next_event
= mips_next_event
;
274 cd
->set_mode
= mips_set_mode
;
275 cd
->event_handler
= mips_event_handler
;
277 clockevents_register_device(cd
);
279 if (cp0_timer_irq_installed
)
282 cp0_timer_irq_installed
= 1;
284 #ifdef CONFIG_MIPS_MT_SMTC
285 #define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
286 setup_irq_smtc(irq
, &c0_compare_irqaction
, CPUCTR_IMASKBIT
);
288 setup_irq(irq
, &c0_compare_irqaction
);