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au1550_spi: fix prototype of irq handler
[wrt350n-kernel.git] / arch / mips / kernel / cpu-probe.c
blob89c3304cb93c391903f0178de2bd796a48e24c5d
1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
18
19 #include <asm/bugs.h>
20 #include <asm/cpu.h>
21 #include <asm/fpu.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24
25 /*
26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
27 * the implementation of the "wait" feature differs between CPU families. This
28 * points to the function that implements CPU specific wait.
29 * The wait instruction stops the pipeline and reduces the power consumption of
30 * the CPU very much.
31 */
32 void (*cpu_wait)(void) = NULL;
33
34 static void r3081_wait(void)
35 {
36 unsigned long cfg = read_c0_conf();
37 write_c0_conf(cfg | R30XX_CONF_HALT);
38 }
39
40 static void r39xx_wait(void)
41 {
42 local_irq_disable();
43 if (!need_resched())
44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
45 local_irq_enable();
46 }
47
48 /*
49 * There is a race when WAIT instruction executed with interrupt
50 * enabled.
51 * But it is implementation-dependent wheter the pipelie restarts when
52 * a non-enabled interrupt is requested.
53 */
54 static void r4k_wait(void)
55 {
56 __asm__(" .set mips3 \n"
57 " wait \n"
58 " .set mips0 \n");
59 }
60
61 /*
62 * This variant is preferable as it allows testing need_resched and going to
63 * sleep depending on the outcome atomically. Unfortunately the "It is
64 * implementation-dependent whether the pipeline restarts when a non-enabled
65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
66 * using this version a gamble.
67 */
68 static void r4k_wait_irqoff(void)
69 {
70 local_irq_disable();
71 if (!need_resched())
72 __asm__(" .set mips3 \n"
73 " wait \n"
74 " .set mips0 \n");
75 local_irq_enable();
76 }
77
78 /*
79 * The RM7000 variant has to handle erratum 38. The workaround is to not
80 * have any pending stores when the WAIT instruction is executed.
81 */
82 static void rm7k_wait_irqoff(void)
83 {
84 local_irq_disable();
85 if (!need_resched())
86 __asm__(
87 " .set push \n"
88 " .set mips3 \n"
89 " .set noat \n"
90 " mfc0 $1, $12 \n"
91 " sync \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " wait \n"
94 " mtc0 $1, $12 # stalls until W stage \n"
95 " .set pop \n");
96 local_irq_enable();
97 }
98
99 /* The Au1xxx wait is available only if using 32khz counter or
100 * external timer source, but specifically not CP0 Counter. */
101 int allow_au1k_wait;
102
103 static void au1k_wait(void)
104 {
105 /* using the wait instruction makes CP0 counter unusable */
106 __asm__(" .set mips3 \n"
107 " cache 0x14, 0(%0) \n"
108 " cache 0x14, 32(%0) \n"
109 " sync \n"
110 " nop \n"
111 " wait \n"
112 " nop \n"
113 " nop \n"
114 " nop \n"
115 " nop \n"
116 " .set mips0 \n"
117 : : "r" (au1k_wait));
118 }
119
120 static int __initdata nowait = 0;
121
122 static int __init wait_disable(char *s)
123 {
124 nowait = 1;
125
126 return 1;
127 }
128
129 __setup("nowait", wait_disable);
130
131 static inline void check_wait(void)
132 {
133 struct cpuinfo_mips *c = &current_cpu_data;
134
135 if (nowait) {
136 printk("Wait instruction disabled.\n");
137 return;
138 }
139
140 switch (c->cputype) {
141 case CPU_R3081:
142 case CPU_R3081E:
143 cpu_wait = r3081_wait;
144 break;
145 case CPU_TX3927:
146 cpu_wait = r39xx_wait;
147 break;
148 case CPU_R4200:
149 /* case CPU_R4300: */
150 case CPU_R4600:
151 case CPU_R4640:
152 case CPU_R4650:
153 case CPU_R4700:
154 case CPU_R5000:
155 case CPU_NEVADA:
156 case CPU_4KC:
157 case CPU_4KEC:
158 case CPU_4KSC:
159 case CPU_5KC:
160 case CPU_25KF:
161 case CPU_PR4450:
162 case CPU_BCM3302:
163 cpu_wait = r4k_wait;
164 break;
165
166 case CPU_RM7000:
167 cpu_wait = rm7k_wait_irqoff;
168 break;
169
170 case CPU_24K:
171 case CPU_34K:
172 cpu_wait = r4k_wait;
173 if (read_c0_config7() & MIPS_CONF7_WII)
174 cpu_wait = r4k_wait_irqoff;
175 break;
176
177 case CPU_74K:
178 cpu_wait = r4k_wait;
179 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
180 cpu_wait = r4k_wait_irqoff;
181 break;
182
183 case CPU_TX49XX:
184 cpu_wait = r4k_wait_irqoff;
185 break;
186 case CPU_AU1000:
187 case CPU_AU1100:
188 case CPU_AU1500:
189 case CPU_AU1550:
190 case CPU_AU1200:
191 case CPU_AU1210:
192 case CPU_AU1250:
193 if (allow_au1k_wait)
194 cpu_wait = au1k_wait;
195 break;
196 case CPU_20KC:
197 /*
198 * WAIT on Rev1.0 has E1, E2, E3 and E16.
199 * WAIT on Rev2.0 and Rev3.0 has E16.
200 * Rev3.1 WAIT is nop, why bother
201 */
202 if ((c->processor_id & 0xff) <= 0x64)
203 break;
204
205 /*
206 * Another rev is incremeting c0_count at a reduced clock
207 * rate while in WAIT mode. So we basically have the choice
208 * between using the cp0 timer as clocksource or avoiding
209 * the WAIT instruction. Until more details are known,
210 * disable the use of WAIT for 20Kc entirely.
211 cpu_wait = r4k_wait;
212 */
213 break;
214 case CPU_RM9000:
215 if ((c->processor_id & 0x00ff) >= 0x40)
216 cpu_wait = r4k_wait;
217 break;
218 default:
219 break;
220 }
221 }
222
223 static inline void check_errata(void)
224 {
225 struct cpuinfo_mips *c = &current_cpu_data;
226
227 switch (c->cputype) {
228 case CPU_34K:
229 /*
230 * Erratum "RPS May Cause Incorrect Instruction Execution"
231 * This code only handles VPE0, any SMP/SMTC/RTOS code
232 * making use of VPE1 will be responsable for that VPE.
233 */
234 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
235 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
236 break;
237 default:
238 break;
239 }
240 }
241
242 void __init check_bugs32(void)
243 {
244 check_wait();
245 check_errata();
246 }
247
248 /*
249 * Probe whether cpu has config register by trying to play with
250 * alternate cache bit and see whether it matters.
251 * It's used by cpu_probe to distinguish between R3000A and R3081.
252 */
253 static inline int cpu_has_confreg(void)
254 {
255 #ifdef CONFIG_CPU_R3000
256 extern unsigned long r3k_cache_size(unsigned long);
257 unsigned long size1, size2;
258 unsigned long cfg = read_c0_conf();
259
260 size1 = r3k_cache_size(ST0_ISC);
261 write_c0_conf(cfg ^ R30XX_CONF_AC);
262 size2 = r3k_cache_size(ST0_ISC);
263 write_c0_conf(cfg);
264 return size1 != size2;
265 #else
266 return 0;
267 #endif
268 }
269
270 /*
271 * Get the FPU Implementation/Revision.
272 */
273 static inline unsigned long cpu_get_fpu_id(void)
274 {
275 unsigned long tmp, fpu_id;
276
277 tmp = read_c0_status();
278 __enable_fpu();
279 fpu_id = read_32bit_cp1_register(CP1_REVISION);
280 write_c0_status(tmp);
281 return fpu_id;
282 }
283
284 /*
285 * Check the CPU has an FPU the official way.
286 */
287 static inline int __cpu_has_fpu(void)
288 {
289 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
290 }
291
292 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
293 | MIPS_CPU_COUNTER)
294
295 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
296 {
297 switch (c->processor_id & 0xff00) {
298 case PRID_IMP_R2000:
299 c->cputype = CPU_R2000;
300 c->isa_level = MIPS_CPU_ISA_I;
301 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
302 MIPS_CPU_NOFPUEX;
303 if (__cpu_has_fpu())
304 c->options |= MIPS_CPU_FPU;
305 c->tlbsize = 64;
306 break;
307 case PRID_IMP_R3000:
308 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
309 if (cpu_has_confreg())
310 c->cputype = CPU_R3081E;
311 else
312 c->cputype = CPU_R3000A;
313 else
314 c->cputype = CPU_R3000;
315 c->isa_level = MIPS_CPU_ISA_I;
316 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
317 MIPS_CPU_NOFPUEX;
318 if (__cpu_has_fpu())
319 c->options |= MIPS_CPU_FPU;
320 c->tlbsize = 64;
321 break;
322 case PRID_IMP_R4000:
323 if (read_c0_config() & CONF_SC) {
324 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
325 c->cputype = CPU_R4400PC;
326 else
327 c->cputype = CPU_R4000PC;
328 } else {
329 if ((c->processor_id & 0xff) >= PRID_REV_R4400)
330 c->cputype = CPU_R4400SC;
331 else
332 c->cputype = CPU_R4000SC;
333 }
334
335 c->isa_level = MIPS_CPU_ISA_III;
336 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
337 MIPS_CPU_WATCH | MIPS_CPU_VCE |
338 MIPS_CPU_LLSC;
339 c->tlbsize = 48;
340 break;
341 case PRID_IMP_VR41XX:
342 switch (c->processor_id & 0xf0) {
343 case PRID_REV_VR4111:
344 c->cputype = CPU_VR4111;
345 break;
346 case PRID_REV_VR4121:
347 c->cputype = CPU_VR4121;
348 break;
349 case PRID_REV_VR4122:
350 if ((c->processor_id & 0xf) < 0x3)
351 c->cputype = CPU_VR4122;
352 else
353 c->cputype = CPU_VR4181A;
354 break;
355 case PRID_REV_VR4130:
356 if ((c->processor_id & 0xf) < 0x4)
357 c->cputype = CPU_VR4131;
358 else
359 c->cputype = CPU_VR4133;
360 break;
361 default:
362 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
363 c->cputype = CPU_VR41XX;
364 break;
365 }
366 c->isa_level = MIPS_CPU_ISA_III;
367 c->options = R4K_OPTS;
368 c->tlbsize = 32;
369 break;
370 case PRID_IMP_R4300:
371 c->cputype = CPU_R4300;
372 c->isa_level = MIPS_CPU_ISA_III;
373 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
374 MIPS_CPU_LLSC;
375 c->tlbsize = 32;
376 break;
377 case PRID_IMP_R4600:
378 c->cputype = CPU_R4600;
379 c->isa_level = MIPS_CPU_ISA_III;
380 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
381 MIPS_CPU_LLSC;
382 c->tlbsize = 48;
383 break;
384 #if 0
385 case PRID_IMP_R4650:
386 /*
387 * This processor doesn't have an MMU, so it's not
388 * "real easy" to run Linux on it. It is left purely
389 * for documentation. Commented out because it shares
390 * it's c0_prid id number with the TX3900.
391 */
392 c->cputype = CPU_R4650;
393 c->isa_level = MIPS_CPU_ISA_III;
394 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
395 c->tlbsize = 48;
396 break;
397 #endif
398 case PRID_IMP_TX39:
399 c->isa_level = MIPS_CPU_ISA_I;
400 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
401
402 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
403 c->cputype = CPU_TX3927;
404 c->tlbsize = 64;
405 } else {
406 switch (c->processor_id & 0xff) {
407 case PRID_REV_TX3912:
408 c->cputype = CPU_TX3912;
409 c->tlbsize = 32;
410 break;
411 case PRID_REV_TX3922:
412 c->cputype = CPU_TX3922;
413 c->tlbsize = 64;
414 break;
415 default:
416 c->cputype = CPU_UNKNOWN;
417 break;
418 }
419 }
420 break;
421 case PRID_IMP_R4700:
422 c->cputype = CPU_R4700;
423 c->isa_level = MIPS_CPU_ISA_III;
424 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
425 MIPS_CPU_LLSC;
426 c->tlbsize = 48;
427 break;
428 case PRID_IMP_TX49:
429 c->cputype = CPU_TX49XX;
430 c->isa_level = MIPS_CPU_ISA_III;
431 c->options = R4K_OPTS | MIPS_CPU_LLSC;
432 if (!(c->processor_id & 0x08))
433 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
434 c->tlbsize = 48;
435 break;
436 case PRID_IMP_R5000:
437 c->cputype = CPU_R5000;
438 c->isa_level = MIPS_CPU_ISA_IV;
439 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
440 MIPS_CPU_LLSC;
441 c->tlbsize = 48;
442 break;
443 case PRID_IMP_R5432:
444 c->cputype = CPU_R5432;
445 c->isa_level = MIPS_CPU_ISA_IV;
446 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
447 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
448 c->tlbsize = 48;
449 break;
450 case PRID_IMP_R5500:
451 c->cputype = CPU_R5500;
452 c->isa_level = MIPS_CPU_ISA_IV;
453 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
454 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
455 c->tlbsize = 48;
456 break;
457 case PRID_IMP_NEVADA:
458 c->cputype = CPU_NEVADA;
459 c->isa_level = MIPS_CPU_ISA_IV;
460 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
461 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
462 c->tlbsize = 48;
463 break;
464 case PRID_IMP_R6000:
465 c->cputype = CPU_R6000;
466 c->isa_level = MIPS_CPU_ISA_II;
467 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
468 MIPS_CPU_LLSC;
469 c->tlbsize = 32;
470 break;
471 case PRID_IMP_R6000A:
472 c->cputype = CPU_R6000A;
473 c->isa_level = MIPS_CPU_ISA_II;
474 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
475 MIPS_CPU_LLSC;
476 c->tlbsize = 32;
477 break;
478 case PRID_IMP_RM7000:
479 c->cputype = CPU_RM7000;
480 c->isa_level = MIPS_CPU_ISA_IV;
481 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
482 MIPS_CPU_LLSC;
483 /*
484 * Undocumented RM7000: Bit 29 in the info register of
485 * the RM7000 v2.0 indicates if the TLB has 48 or 64
486 * entries.
487 *
488 * 29 1 => 64 entry JTLB
489 * 0 => 48 entry JTLB
490 */
491 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
492 break;
493 case PRID_IMP_RM9000:
494 c->cputype = CPU_RM9000;
495 c->isa_level = MIPS_CPU_ISA_IV;
496 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
497 MIPS_CPU_LLSC;
498 /*
499 * Bit 29 in the info register of the RM9000
500 * indicates if the TLB has 48 or 64 entries.
501 *
502 * 29 1 => 64 entry JTLB
503 * 0 => 48 entry JTLB
504 */
505 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
506 break;
507 case PRID_IMP_R8000:
508 c->cputype = CPU_R8000;
509 c->isa_level = MIPS_CPU_ISA_IV;
510 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
511 MIPS_CPU_FPU | MIPS_CPU_32FPR |
512 MIPS_CPU_LLSC;
513 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
514 break;
515 case PRID_IMP_R10000:
516 c->cputype = CPU_R10000;
517 c->isa_level = MIPS_CPU_ISA_IV;
518 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
519 MIPS_CPU_FPU | MIPS_CPU_32FPR |
520 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
521 MIPS_CPU_LLSC;
522 c->tlbsize = 64;
523 break;
524 case PRID_IMP_R12000:
525 c->cputype = CPU_R12000;
526 c->isa_level = MIPS_CPU_ISA_IV;
527 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
528 MIPS_CPU_FPU | MIPS_CPU_32FPR |
529 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
530 MIPS_CPU_LLSC;
531 c->tlbsize = 64;
532 break;
533 case PRID_IMP_R14000:
534 c->cputype = CPU_R14000;
535 c->isa_level = MIPS_CPU_ISA_IV;
536 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
537 MIPS_CPU_FPU | MIPS_CPU_32FPR |
538 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
539 MIPS_CPU_LLSC;
540 c->tlbsize = 64;
541 break;
542 case PRID_IMP_LOONGSON2:
543 c->cputype = CPU_LOONGSON2;
544 c->isa_level = MIPS_CPU_ISA_III;
545 c->options = R4K_OPTS |
546 MIPS_CPU_FPU | MIPS_CPU_LLSC |
547 MIPS_CPU_32FPR;
548 c->tlbsize = 64;
549 break;
550 }
551 }
552
553 static char unknown_isa[] __cpuinitdata = KERN_ERR \
554 "Unsupported ISA type, c0.config0: %d.";
555
556 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
557 {
558 unsigned int config0;
559 int isa;
560
561 config0 = read_c0_config();
562
563 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
564 c->options |= MIPS_CPU_TLB;
565 isa = (config0 & MIPS_CONF_AT) >> 13;
566 switch (isa) {
567 case 0:
568 switch ((config0 & MIPS_CONF_AR) >> 10) {
569 case 0:
570 c->isa_level = MIPS_CPU_ISA_M32R1;
571 break;
572 case 1:
573 c->isa_level = MIPS_CPU_ISA_M32R2;
574 break;
575 default:
576 goto unknown;
577 }
578 break;
579 case 2:
580 switch ((config0 & MIPS_CONF_AR) >> 10) {
581 case 0:
582 c->isa_level = MIPS_CPU_ISA_M64R1;
583 break;
584 case 1:
585 c->isa_level = MIPS_CPU_ISA_M64R2;
586 break;
587 default:
588 goto unknown;
589 }
590 break;
591 default:
592 goto unknown;
593 }
594
595 return config0 & MIPS_CONF_M;
596
597 unknown:
598 panic(unknown_isa, config0);
599 }
600
601 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
602 {
603 unsigned int config1;
604
605 config1 = read_c0_config1();
606
607 if (config1 & MIPS_CONF1_MD)
608 c->ases |= MIPS_ASE_MDMX;
609 if (config1 & MIPS_CONF1_WR)
610 c->options |= MIPS_CPU_WATCH;
611 if (config1 & MIPS_CONF1_CA)
612 c->ases |= MIPS_ASE_MIPS16;
613 if (config1 & MIPS_CONF1_EP)
614 c->options |= MIPS_CPU_EJTAG;
615 if (config1 & MIPS_CONF1_FP) {
616 c->options |= MIPS_CPU_FPU;
617 c->options |= MIPS_CPU_32FPR;
618 }
619 if (cpu_has_tlb)
620 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
621
622 return config1 & MIPS_CONF_M;
623 }
624
625 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
626 {
627 unsigned int config2;
628
629 config2 = read_c0_config2();
630
631 if (config2 & MIPS_CONF2_SL)
632 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
633
634 return config2 & MIPS_CONF_M;
635 }
636
637 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
638 {
639 unsigned int config3;
640
641 config3 = read_c0_config3();
642
643 if (config3 & MIPS_CONF3_SM)
644 c->ases |= MIPS_ASE_SMARTMIPS;
645 if (config3 & MIPS_CONF3_DSP)
646 c->ases |= MIPS_ASE_DSP;
647 if (config3 & MIPS_CONF3_VINT)
648 c->options |= MIPS_CPU_VINT;
649 if (config3 & MIPS_CONF3_VEIC)
650 c->options |= MIPS_CPU_VEIC;
651 if (config3 & MIPS_CONF3_MT)
652 c->ases |= MIPS_ASE_MIPSMT;
653 if (config3 & MIPS_CONF3_ULRI)
654 c->options |= MIPS_CPU_ULRI;
655
656 return config3 & MIPS_CONF_M;
657 }
658
659 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
660 {
661 /* MIPS32 or MIPS64 compliant CPU. */
662 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
663 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
664
665 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
666
667 /* Read Config registers. */
668 if (!decode_config0(c))
669 return; /* actually worth a panic() */
670 if (!decode_config1(c))
671 return;
672 if (!decode_config2(c))
673 return;
674 if (!decode_config3(c))
675 return;
676 }
677
678 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
679 {
680 decode_configs(c);
681 switch (c->processor_id & 0xff00) {
682 case PRID_IMP_4KC:
683 c->cputype = CPU_4KC;
684 break;
685 case PRID_IMP_4KEC:
686 c->cputype = CPU_4KEC;
687 break;
688 case PRID_IMP_4KECR2:
689 c->cputype = CPU_4KEC;
690 break;
691 case PRID_IMP_4KSC:
692 case PRID_IMP_4KSD:
693 c->cputype = CPU_4KSC;
694 break;
695 case PRID_IMP_5KC:
696 c->cputype = CPU_5KC;
697 break;
698 case PRID_IMP_20KC:
699 c->cputype = CPU_20KC;
700 break;
701 case PRID_IMP_24K:
702 case PRID_IMP_24KE:
703 c->cputype = CPU_24K;
704 break;
705 case PRID_IMP_25KF:
706 c->cputype = CPU_25KF;
707 break;
708 case PRID_IMP_34K:
709 c->cputype = CPU_34K;
710 break;
711 case PRID_IMP_74K:
712 c->cputype = CPU_74K;
713 break;
714 }
715 }
716
717 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
718 {
719 decode_configs(c);
720 switch (c->processor_id & 0xff00) {
721 case PRID_IMP_AU1_REV1:
722 case PRID_IMP_AU1_REV2:
723 switch ((c->processor_id >> 24) & 0xff) {
724 case 0:
725 c->cputype = CPU_AU1000;
726 break;
727 case 1:
728 c->cputype = CPU_AU1500;
729 break;
730 case 2:
731 c->cputype = CPU_AU1100;
732 break;
733 case 3:
734 c->cputype = CPU_AU1550;
735 break;
736 case 4:
737 c->cputype = CPU_AU1200;
738 if (2 == (c->processor_id & 0xff))
739 c->cputype = CPU_AU1250;
740 break;
741 case 5:
742 c->cputype = CPU_AU1210;
743 break;
744 default:
745 panic("Unknown Au Core!");
746 break;
747 }
748 break;
749 }
750 }
751
752 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
753 {
754 decode_configs(c);
755
756 switch (c->processor_id & 0xff00) {
757 case PRID_IMP_SB1:
758 c->cputype = CPU_SB1;
759 /* FPU in pass1 is known to have issues. */
760 if ((c->processor_id & 0xff) < 0x02)
761 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
762 break;
763 case PRID_IMP_SB1A:
764 c->cputype = CPU_SB1A;
765 break;
766 }
767 }
768
769 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
770 {
771 decode_configs(c);
772 switch (c->processor_id & 0xff00) {
773 case PRID_IMP_SR71000:
774 c->cputype = CPU_SR71000;
775 c->scache.ways = 8;
776 c->tlbsize = 64;
777 break;
778 }
779 }
780
781 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
782 {
783 decode_configs(c);
784 switch (c->processor_id & 0xff00) {
785 case PRID_IMP_PR4450:
786 c->cputype = CPU_PR4450;
787 c->isa_level = MIPS_CPU_ISA_M32R1;
788 break;
789 default:
790 panic("Unknown Philips Core!"); /* REVISIT: die? */
791 break;
792 }
793 }
794
795
796 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
797 {
798 decode_configs(c);
799 switch (c->processor_id & 0xff00) {
800 case PRID_IMP_BCM3302:
801 c->cputype = CPU_BCM3302;
802 break;
803 case PRID_IMP_BCM4710:
804 c->cputype = CPU_BCM4710;
805 break;
806 default:
807 c->cputype = CPU_UNKNOWN;
808 break;
809 }
810 }
811
812 const char *__cpu_name[NR_CPUS];
813
814 /*
815 * Name a CPU
816 */
817 static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
818 {
819 const char *name = NULL;
820
821 switch (c->cputype) {
822 case CPU_UNKNOWN: name = "unknown"; break;
823 case CPU_R2000: name = "R2000"; break;
824 case CPU_R3000: name = "R3000"; break;
825 case CPU_R3000A: name = "R3000A"; break;
826 case CPU_R3041: name = "R3041"; break;
827 case CPU_R3051: name = "R3051"; break;
828 case CPU_R3052: name = "R3052"; break;
829 case CPU_R3081: name = "R3081"; break;
830 case CPU_R3081E: name = "R3081E"; break;
831 case CPU_R4000PC: name = "R4000PC"; break;
832 case CPU_R4000SC: name = "R4000SC"; break;
833 case CPU_R4000MC: name = "R4000MC"; break;
834 case CPU_R4200: name = "R4200"; break;
835 case CPU_R4400PC: name = "R4400PC"; break;
836 case CPU_R4400SC: name = "R4400SC"; break;
837 case CPU_R4400MC: name = "R4400MC"; break;
838 case CPU_R4600: name = "R4600"; break;
839 case CPU_R6000: name = "R6000"; break;
840 case CPU_R6000A: name = "R6000A"; break;
841 case CPU_R8000: name = "R8000"; break;
842 case CPU_R10000: name = "R10000"; break;
843 case CPU_R12000: name = "R12000"; break;
844 case CPU_R14000: name = "R14000"; break;
845 case CPU_R4300: name = "R4300"; break;
846 case CPU_R4650: name = "R4650"; break;
847 case CPU_R4700: name = "R4700"; break;
848 case CPU_R5000: name = "R5000"; break;
849 case CPU_R5000A: name = "R5000A"; break;
850 case CPU_R4640: name = "R4640"; break;
851 case CPU_NEVADA: name = "Nevada"; break;
852 case CPU_RM7000: name = "RM7000"; break;
853 case CPU_RM9000: name = "RM9000"; break;
854 case CPU_R5432: name = "R5432"; break;
855 case CPU_4KC: name = "MIPS 4Kc"; break;
856 case CPU_5KC: name = "MIPS 5Kc"; break;
857 case CPU_R4310: name = "R4310"; break;
858 case CPU_SB1: name = "SiByte SB1"; break;
859 case CPU_SB1A: name = "SiByte SB1A"; break;
860 case CPU_TX3912: name = "TX3912"; break;
861 case CPU_TX3922: name = "TX3922"; break;
862 case CPU_TX3927: name = "TX3927"; break;
863 case CPU_AU1000: name = "Au1000"; break;
864 case CPU_AU1500: name = "Au1500"; break;
865 case CPU_AU1100: name = "Au1100"; break;
866 case CPU_AU1550: name = "Au1550"; break;
867 case CPU_AU1200: name = "Au1200"; break;
868 case CPU_AU1210: name = "Au1210"; break;
869 case CPU_AU1250: name = "Au1250"; break;
870 case CPU_4KEC: name = "MIPS 4KEc"; break;
871 case CPU_4KSC: name = "MIPS 4KSc"; break;
872 case CPU_VR41XX: name = "NEC Vr41xx"; break;
873 case CPU_R5500: name = "R5500"; break;
874 case CPU_TX49XX: name = "TX49xx"; break;
875 case CPU_20KC: name = "MIPS 20Kc"; break;
876 case CPU_24K: name = "MIPS 24K"; break;
877 case CPU_25KF: name = "MIPS 25Kf"; break;
878 case CPU_34K: name = "MIPS 34K"; break;
879 case CPU_74K: name = "MIPS 74K"; break;
880 case CPU_VR4111: name = "NEC VR4111"; break;
881 case CPU_VR4121: name = "NEC VR4121"; break;
882 case CPU_VR4122: name = "NEC VR4122"; break;
883 case CPU_VR4131: name = "NEC VR4131"; break;
884 case CPU_VR4133: name = "NEC VR4133"; break;
885 case CPU_VR4181: name = "NEC VR4181"; break;
886 case CPU_VR4181A: name = "NEC VR4181A"; break;
887 case CPU_SR71000: name = "Sandcraft SR71000"; break;
888 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
889 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
890 case CPU_PR4450: name = "Philips PR4450"; break;
891 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
892 default:
893 BUG();
894 }
895
896 return name;
897 }
898
899 __cpuinit void cpu_probe(void)
900 {
901 struct cpuinfo_mips *c = &current_cpu_data;
902 unsigned int cpu = smp_processor_id();
903
904 c->processor_id = PRID_IMP_UNKNOWN;
905 c->fpu_id = FPIR_IMP_NONE;
906 c->cputype = CPU_UNKNOWN;
907
908 c->processor_id = read_c0_prid();
909 switch (c->processor_id & 0xff0000) {
910 case PRID_COMP_LEGACY:
911 cpu_probe_legacy(c);
912 break;
913 case PRID_COMP_MIPS:
914 cpu_probe_mips(c);
915 break;
916 case PRID_COMP_ALCHEMY:
917 cpu_probe_alchemy(c);
918 break;
919 case PRID_COMP_SIBYTE:
920 cpu_probe_sibyte(c);
921 break;
922 case PRID_COMP_BROADCOM:
923 cpu_probe_broadcom(c);
924 break;
925 case PRID_COMP_SANDCRAFT:
926 cpu_probe_sandcraft(c);
927 break;
928 case PRID_COMP_PHILIPS:
929 cpu_probe_philips(c);
930 break;
931 default:
932 c->cputype = CPU_UNKNOWN;
933 }
934
935 /*
936 * Platform code can force the cpu type to optimize code
937 * generation. In that case be sure the cpu type is correctly
938 * manually setup otherwise it could trigger some nasty bugs.
939 */
940 BUG_ON(current_cpu_type() != c->cputype);
941
942 if (c->options & MIPS_CPU_FPU) {
943 c->fpu_id = cpu_get_fpu_id();
944
945 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
946 c->isa_level == MIPS_CPU_ISA_M32R2 ||
947 c->isa_level == MIPS_CPU_ISA_M64R1 ||
948 c->isa_level == MIPS_CPU_ISA_M64R2) {
949 if (c->fpu_id & MIPS_FPIR_3D)
950 c->ases |= MIPS_ASE_MIPS3D;
951 }
952 }
953
954 __cpu_name[cpu] = cpu_to_name(c);
955
956 if (cpu_has_mips_r2)
957 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
958 else
959 c->srsets = 1;
960 }
961
962 __cpuinit void cpu_report(void)
963 {
964 struct cpuinfo_mips *c = &current_cpu_data;
965
966 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
967 c->processor_id, cpu_name_string());
968 if (c->options & MIPS_CPU_FPU)
969 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
970 }
WRT350N Kernel Patches