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au1550_spi: fix prototype of irq handler
[wrt350n-kernel.git] / arch / mips / tx4927 / toshiba_rbtx4927 / toshiba_rbtx4927_setup.c
blobe466e5e711d8919c69b49f2033b60e9407a202f4
1 /*
2 * Toshiba rbtx4927 specific setup
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2001-2002 MontaVista Software Inc.
8 *
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * Copyright (C) 2000 RidgeRun, Inc.
11 * Author: RidgeRun, Inc.
12 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
13 *
14 * Copyright 2001 MontaVista Software Inc.
15 * Author: jsun@mvista.com or jsun@junsun.net
16 *
17 * Copyright 2002 MontaVista Software Inc.
18 * Author: Michael Pruznick, michael_pruznick@mvista.com
19 *
20 * Copyright (C) 2000-2001 Toshiba Corporation
21 *
22 * Copyright (C) 2004 MontaVista Software Inc.
23 * Author: Manish Lachwani, mlachwani@mvista.com
24 *
25 * This program is free software; you can redistribute it and/or modify it
26 * under the terms of the GNU General Public License as published by the
27 * Free Software Foundation; either version 2 of the License, or (at your
28 * option) any later version.
29 *
30 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
31 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
36 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
38 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
39 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * You should have received a copy of the GNU General Public License along
42 * with this program; if not, write to the Free Software Foundation, Inc.,
43 * 675 Mass Ave, Cambridge, MA 02139, USA.
44 */
45 #include <linux/init.h>
46 #include <linux/kernel.h>
47 #include <linux/types.h>
48 #include <linux/ioport.h>
49 #include <linux/interrupt.h>
50 #include <linux/pci.h>
51 #include <linux/pm.h>
52 #include <linux/platform_device.h>
53 #include <linux/clk.h>
54
55 #include <asm/bootinfo.h>
56 #include <asm/io.h>
57 #include <asm/processor.h>
58 #include <asm/reboot.h>
59 #include <asm/time.h>
60 #include <asm/txx9tmr.h>
61 #ifdef CONFIG_TOSHIBA_FPCIB0
62 #include <asm/tx4927/smsc_fdc37m81x.h>
63 #endif
64 #include <asm/tx4927/toshiba_rbtx4927.h>
65 #ifdef CONFIG_PCI
66 #include <asm/tx4927/tx4927_pci.h>
67 #endif
68 #ifdef CONFIG_SERIAL_TXX9
69 #include <linux/serial_core.h>
70 #endif
71
72 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
73
74 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
75 #define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
76 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
77 #define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
78 #define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
79
80 #define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
81 #endif
82
83 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
84 static const u32 toshiba_rbtx4927_setup_debug_flag =
85 (TOSHIBA_RBTX4927_SETUP_SETUP |
86 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
87 TOSHIBA_RBTX4927_SETUP_PCI2);
88 #endif
89
90 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
91 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
92 if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
93 { \
94 char tmp[100]; \
95 sprintf( tmp, str ); \
96 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
97 }
98 #else
99 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
100 #endif
101
102 /* These functions are used for rebooting or halting the machine*/
103 extern void toshiba_rbtx4927_restart(char *command);
104 extern void toshiba_rbtx4927_halt(void);
105 extern void toshiba_rbtx4927_power_off(void);
106
107 int tx4927_using_backplane = 0;
108
109 extern void toshiba_rbtx4927_irq_setup(void);
110
111 char *prom_getcmdline(void);
112
113 #ifdef CONFIG_PCI
114 #undef TX4927_SUPPORT_COMMAND_IO
115 #undef TX4927_SUPPORT_PCI_66
116 int tx4927_cpu_clock = 100000000; /* 100MHz */
117 unsigned long mips_pci_io_base;
118 unsigned long mips_pci_io_size;
119 unsigned long mips_pci_mem_base;
120 unsigned long mips_pci_mem_size;
121 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
122 unsigned long mips_pci_io_pciaddr = 0;
123 unsigned long mips_memory_upper;
124 static int tx4927_ccfg_toeon = 1;
125 static int tx4927_pcic_trdyto = 0; /* default: disabled */
126 unsigned long tx4927_ce_base[8];
127 void tx4927_reset_pci_pcic(void);
128 int tx4927_pci66 = 0; /* 0:auto */
129 #endif
130
131 char *toshiba_name = "";
132
133 #ifdef CONFIG_PCI
134 extern struct pci_controller tx4927_controller;
135
136 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
137 int top_bus, int busnr, int devfn)
138 {
139 static struct pci_dev dev;
140 static struct pci_bus bus;
141
142 dev.sysdata = (void *)hose;
143 dev.devfn = devfn;
144 bus.number = busnr;
145 bus.ops = hose->pci_ops;
146 bus.parent = NULL;
147 dev.bus = &bus;
148
149 return &dev;
150 }
151
152 #define EARLY_PCI_OP(rw, size, type) \
153 static int early_##rw##_config_##size(struct pci_controller *hose, \
154 int top_bus, int bus, int devfn, int offset, type value) \
155 { \
156 return pci_##rw##_config_##size( \
157 fake_pci_dev(hose, top_bus, bus, devfn), \
158 offset, value); \
159 }
160
161 EARLY_PCI_OP(read, byte, u8 *)
162 EARLY_PCI_OP(read, dword, u32 *)
163 EARLY_PCI_OP(write, byte, u8)
164 EARLY_PCI_OP(write, dword, u32)
165
166 static int __init tx4927_pcibios_init(void)
167 {
168 unsigned int id;
169 u32 pci_devfn;
170 int devfn_start = 0;
171 int devfn_stop = 0xff;
172 int busno = 0; /* One bus on the Toshiba */
173 struct pci_controller *hose = &tx4927_controller;
174
175 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
176 "-\n");
177
178 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
179 early_read_config_dword(hose, busno, busno, pci_devfn,
180 PCI_VENDOR_ID, &id);
181
182 if (id == 0xffffffff) {
183 continue;
184 }
185
186 if (id == 0x94601055) {
187 u8 v08_64;
188 u32 v32_b0;
189 u8 v08_e1;
190 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
191 char *s = " sb/isa --";
192 #endif
193
194 TOSHIBA_RBTX4927_SETUP_DPRINTK
195 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
196 s);
197
198 early_read_config_byte(hose, busno, busno,
199 pci_devfn, 0x64, &v08_64);
200 early_read_config_dword(hose, busno, busno,
201 pci_devfn, 0xb0, &v32_b0);
202 early_read_config_byte(hose, busno, busno,
203 pci_devfn, 0xe1, &v08_e1);
204
205 TOSHIBA_RBTX4927_SETUP_DPRINTK
206 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
207 ":%s beg 0x64 = 0x%02x\n", s, v08_64);
208 TOSHIBA_RBTX4927_SETUP_DPRINTK
209 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
210 ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
211 TOSHIBA_RBTX4927_SETUP_DPRINTK
212 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
213 ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
214
215 /* serial irq control */
216 v08_64 = 0xd0;
217
218 /* serial irq pin */
219 v32_b0 |= 0x00010000;
220
221 /* ide irq on isa14 */
222 v08_e1 &= 0xf0;
223 v08_e1 |= 0x0d;
224
225 TOSHIBA_RBTX4927_SETUP_DPRINTK
226 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
227 ":%s mid 0x64 = 0x%02x\n", s, v08_64);
228 TOSHIBA_RBTX4927_SETUP_DPRINTK
229 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
230 ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
231 TOSHIBA_RBTX4927_SETUP_DPRINTK
232 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
233 ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
234
235 early_write_config_byte(hose, busno, busno,
236 pci_devfn, 0x64, v08_64);
237 early_write_config_dword(hose, busno, busno,
238 pci_devfn, 0xb0, v32_b0);
239 early_write_config_byte(hose, busno, busno,
240 pci_devfn, 0xe1, v08_e1);
241
242 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
243 {
244 early_read_config_byte(hose, busno, busno,
245 pci_devfn, 0x64,
246 &v08_64);
247 early_read_config_dword(hose, busno, busno,
248 pci_devfn, 0xb0,
249 &v32_b0);
250 early_read_config_byte(hose, busno, busno,
251 pci_devfn, 0xe1,
252 &v08_e1);
253
254 TOSHIBA_RBTX4927_SETUP_DPRINTK
255 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
256 ":%s end 0x64 = 0x%02x\n", s, v08_64);
257 TOSHIBA_RBTX4927_SETUP_DPRINTK
258 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
259 ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
260 TOSHIBA_RBTX4927_SETUP_DPRINTK
261 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
262 ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
263 }
264 #endif
265
266 TOSHIBA_RBTX4927_SETUP_DPRINTK
267 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
268 s);
269 }
270
271 if (id == 0x91301055) {
272 u8 v08_04;
273 u8 v08_09;
274 u8 v08_41;
275 u8 v08_43;
276 u8 v08_5c;
277 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
278 char *s = " sb/ide --";
279 #endif
280
281 TOSHIBA_RBTX4927_SETUP_DPRINTK
282 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
283 s);
284
285 early_read_config_byte(hose, busno, busno,
286 pci_devfn, 0x04, &v08_04);
287 early_read_config_byte(hose, busno, busno,
288 pci_devfn, 0x09, &v08_09);
289 early_read_config_byte(hose, busno, busno,
290 pci_devfn, 0x41, &v08_41);
291 early_read_config_byte(hose, busno, busno,
292 pci_devfn, 0x43, &v08_43);
293 early_read_config_byte(hose, busno, busno,
294 pci_devfn, 0x5c, &v08_5c);
295
296 TOSHIBA_RBTX4927_SETUP_DPRINTK
297 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
298 ":%s beg 0x04 = 0x%02x\n", s, v08_04);
299 TOSHIBA_RBTX4927_SETUP_DPRINTK
300 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
301 ":%s beg 0x09 = 0x%02x\n", s, v08_09);
302 TOSHIBA_RBTX4927_SETUP_DPRINTK
303 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
304 ":%s beg 0x41 = 0x%02x\n", s, v08_41);
305 TOSHIBA_RBTX4927_SETUP_DPRINTK
306 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
307 ":%s beg 0x43 = 0x%02x\n", s, v08_43);
308 TOSHIBA_RBTX4927_SETUP_DPRINTK
309 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
310 ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
311
312 /* enable ide master/io */
313 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
314
315 /* enable ide native mode */
316 v08_09 |= 0x05;
317
318 /* enable primary ide */
319 v08_41 |= 0x80;
320
321 /* enable secondary ide */
322 v08_43 |= 0x80;
323
324 /*
325 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
326 *
327 * This line of code is intended to provide the user with a work
328 * around solution to the anomalies cited in SMSC's anomaly sheet
329 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
330 *
331 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
332 */
333 v08_5c |= 0x01;
334
335 TOSHIBA_RBTX4927_SETUP_DPRINTK
336 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
337 ":%s mid 0x04 = 0x%02x\n", s, v08_04);
338 TOSHIBA_RBTX4927_SETUP_DPRINTK
339 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
340 ":%s mid 0x09 = 0x%02x\n", s, v08_09);
341 TOSHIBA_RBTX4927_SETUP_DPRINTK
342 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
343 ":%s mid 0x41 = 0x%02x\n", s, v08_41);
344 TOSHIBA_RBTX4927_SETUP_DPRINTK
345 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
346 ":%s mid 0x43 = 0x%02x\n", s, v08_43);
347 TOSHIBA_RBTX4927_SETUP_DPRINTK
348 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
349 ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
350
351 early_write_config_byte(hose, busno, busno,
352 pci_devfn, 0x5c, v08_5c);
353 early_write_config_byte(hose, busno, busno,
354 pci_devfn, 0x04, v08_04);
355 early_write_config_byte(hose, busno, busno,
356 pci_devfn, 0x09, v08_09);
357 early_write_config_byte(hose, busno, busno,
358 pci_devfn, 0x41, v08_41);
359 early_write_config_byte(hose, busno, busno,
360 pci_devfn, 0x43, v08_43);
361
362 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
363 {
364 early_read_config_byte(hose, busno, busno,
365 pci_devfn, 0x04,
366 &v08_04);
367 early_read_config_byte(hose, busno, busno,
368 pci_devfn, 0x09,
369 &v08_09);
370 early_read_config_byte(hose, busno, busno,
371 pci_devfn, 0x41,
372 &v08_41);
373 early_read_config_byte(hose, busno, busno,
374 pci_devfn, 0x43,
375 &v08_43);
376 early_read_config_byte(hose, busno, busno,
377 pci_devfn, 0x5c,
378 &v08_5c);
379
380 TOSHIBA_RBTX4927_SETUP_DPRINTK
381 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
382 ":%s end 0x04 = 0x%02x\n", s, v08_04);
383 TOSHIBA_RBTX4927_SETUP_DPRINTK
384 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
385 ":%s end 0x09 = 0x%02x\n", s, v08_09);
386 TOSHIBA_RBTX4927_SETUP_DPRINTK
387 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
388 ":%s end 0x41 = 0x%02x\n", s, v08_41);
389 TOSHIBA_RBTX4927_SETUP_DPRINTK
390 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
391 ":%s end 0x43 = 0x%02x\n", s, v08_43);
392 TOSHIBA_RBTX4927_SETUP_DPRINTK
393 (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
394 ":%s end 0x5c = 0x%02x\n", s, v08_5c);
395 }
396 #endif
397
398 TOSHIBA_RBTX4927_SETUP_DPRINTK
399 (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
400 s);
401 }
402
403 }
404
405 register_pci_controller(&tx4927_controller);
406 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
407 "+\n");
408
409 return 0;
410 }
411
412 arch_initcall(tx4927_pcibios_init);
413
414 extern struct resource pci_io_resource;
415 extern struct resource pci_mem_resource;
416
417 void __init tx4927_pci_setup(void)
418 {
419 static int called = 0;
420 extern unsigned int tx4927_get_mem_size(void);
421
422 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
423
424 mips_memory_upper = tx4927_get_mem_size() << 20;
425 mips_memory_upper += KSEG0;
426 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
427 "0x%08lx=mips_memory_upper\n",
428 mips_memory_upper);
429 mips_pci_io_base = TX4927_PCIIO;
430 mips_pci_io_size = TX4927_PCIIO_SIZE;
431 mips_pci_mem_base = TX4927_PCIMEM;
432 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
433
434 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
435 "0x%08lx=mips_pci_io_base\n",
436 mips_pci_io_base);
437 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
438 "0x%08lx=mips_pci_io_size\n",
439 mips_pci_io_size);
440 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
441 "0x%08lx=mips_pci_mem_base\n",
442 mips_pci_mem_base);
443 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
444 "0x%08lx=mips_pci_mem_size\n",
445 mips_pci_mem_size);
446 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
447 "0x%08lx=pci_io_resource.start\n",
448 pci_io_resource.start);
449 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
450 "0x%08lx=pci_io_resource.end\n",
451 pci_io_resource.end);
452 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
453 "0x%08lx=pci_mem_resource.start\n",
454 pci_mem_resource.start);
455 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
456 "0x%08lx=pci_mem_resource.end\n",
457 pci_mem_resource.end);
458 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
459 "0x%08lx=mips_io_port_base",
460 mips_io_port_base);
461 if (!called) {
462 printk
463 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
464 toshiba_name,
465 (unsigned short) (tx4927_pcicptr->pciid >> 16),
466 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
467 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
468 (!(tx4927_ccfgptr->
469 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
470 "Internal");
471 called = 1;
472 }
473 printk("%s PCIC --%s PCICLK:", toshiba_name,
474 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
475 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
476 int pciclk = 0;
477 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
478 switch ((unsigned long) tx4927_ccfgptr->
479 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
480 case TX4937_CCFG_PCIDIVMODE_4:
481 pciclk = tx4927_cpu_clock / 4;
482 break;
483 case TX4937_CCFG_PCIDIVMODE_4_5:
484 pciclk = tx4927_cpu_clock * 2 / 9;
485 break;
486 case TX4937_CCFG_PCIDIVMODE_5:
487 pciclk = tx4927_cpu_clock / 5;
488 break;
489 case TX4937_CCFG_PCIDIVMODE_5_5:
490 pciclk = tx4927_cpu_clock * 2 / 11;
491 break;
492 case TX4937_CCFG_PCIDIVMODE_8:
493 pciclk = tx4927_cpu_clock / 8;
494 break;
495 case TX4937_CCFG_PCIDIVMODE_9:
496 pciclk = tx4927_cpu_clock / 9;
497 break;
498 case TX4937_CCFG_PCIDIVMODE_10:
499 pciclk = tx4927_cpu_clock / 10;
500 break;
501 case TX4937_CCFG_PCIDIVMODE_11:
502 pciclk = tx4927_cpu_clock / 11;
503 break;
504 }
505
506 else
507 switch ((unsigned long) tx4927_ccfgptr->
508 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
509 case TX4927_CCFG_PCIDIVMODE_2_5:
510 pciclk = tx4927_cpu_clock * 2 / 5;
511 break;
512 case TX4927_CCFG_PCIDIVMODE_3:
513 pciclk = tx4927_cpu_clock / 3;
514 break;
515 case TX4927_CCFG_PCIDIVMODE_5:
516 pciclk = tx4927_cpu_clock / 5;
517 break;
518 case TX4927_CCFG_PCIDIVMODE_6:
519 pciclk = tx4927_cpu_clock / 6;
520 break;
521 }
522
523 printk("Internal(%dMHz)", pciclk / 1000000);
524 } else {
525 int pciclk = 0;
526 int pciclk_setting = *tx4927_pci_clk_ptr;
527 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
528 case TX4927_PCI_CLK_33:
529 pciclk = 33333333;
530 break;
531 case TX4927_PCI_CLK_25:
532 pciclk = 25000000;
533 break;
534 case TX4927_PCI_CLK_66:
535 pciclk = 66666666;
536 break;
537 case TX4927_PCI_CLK_50:
538 pciclk = 50000000;
539 break;
540 }
541 printk("External(%dMHz)", pciclk / 1000000);
542 }
543 printk("\n");
544
545
546
547 /* GB->PCI mappings */
548 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
549 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
550 #ifdef __BIG_ENDIAN
551 TX4927_PCIC_G2PIOGBASE_ECHG
552 #else
553 TX4927_PCIC_G2PIOGBASE_BSDIS
554 #endif
555 ;
556
557 tx4927_pcicptr->g2piopbase = 0;
558
559 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
560 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
561 #ifdef __BIG_ENDIAN
562 TX4927_PCIC_G2PMnGBASE_ECHG
563 #else
564 TX4927_PCIC_G2PMnGBASE_BSDIS
565 #endif
566 ;
567 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
568
569 tx4927_pcicptr->g2pmmask[1] = 0;
570 tx4927_pcicptr->g2pmgbase[1] = 0;
571 tx4927_pcicptr->g2pmpbase[1] = 0;
572 tx4927_pcicptr->g2pmmask[2] = 0;
573 tx4927_pcicptr->g2pmgbase[2] = 0;
574 tx4927_pcicptr->g2pmpbase[2] = 0;
575
576
577 /* PCI->GB mappings (I/O 256B) */
578 tx4927_pcicptr->p2giopbase = 0; /* 256B */
579
580 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
581 tx4927_pcicptr->p2gm0plbase = 0;
582 tx4927_pcicptr->p2gm0pubase = 0;
583 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
584 #ifdef __BIG_ENDIAN
585 TX4927_PCIC_P2GMnGBASE_TECHG
586 #else
587 TX4927_PCIC_P2GMnGBASE_TBSDIS
588 #endif
589 ;
590
591 /* PCI->GB mappings (MEM 16MB) -not used */
592 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
593 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
594 tx4927_pcicptr->p2gmgbase[1] = 0;
595
596 /* PCI->GB mappings (MEM 1MB) -not used */
597 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
598 tx4927_pcicptr->p2gmgbase[2] = 0;
599
600
601 /* Enable Initiator Memory 0 Space, I/O Space, Config */
602 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
603 tx4927_pcicptr->pciccfg |=
604 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
605 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
606
607
608 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
609 tx4927_pcicptr->pcicfg1 = 0;
610
611 if (tx4927_pcic_trdyto >= 0) {
612 tx4927_pcicptr->g2ptocnt &= ~0xff;
613 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
614 }
615
616 /* Clear All Local Bus Status */
617 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
618 /* Enable All Local Bus Interrupts */
619 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
620 /* Clear All Initiator Status */
621 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
622 /* Enable All Initiator Interrupts */
623 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
624 /* Clear All PCI Status Error */
625 tx4927_pcicptr->pcistatus =
626 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
627 (TX4927_PCIC_PCISTATUS_ALL << 16);
628 /* Enable All PCI Status Error Interrupts */
629 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
630
631 /* PCIC Int => IRC IRQ16 */
632 tx4927_pcicptr->pcicfg2 =
633 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
634
635 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
636 /* XXX */
637 } else {
638 /* Reset Bus Arbiter */
639 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
640 /* Enable Bus Arbiter */
641 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
642 }
643
644 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
645 PCI_COMMAND_MEMORY |
646 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
647
648 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
649 ":pci setup complete:\n");
650 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
651 }
652
653 #endif /* CONFIG_PCI */
654
655 static void __noreturn wait_forever(void)
656 {
657 while (1)
658 if (cpu_wait)
659 (*cpu_wait)();
660 }
661
662 void toshiba_rbtx4927_restart(char *command)
663 {
664 printk(KERN_NOTICE "System Rebooting...\n");
665
666 /* enable the s/w reset register */
667 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
668
669 /* wait for enable to be seen */
670 while ((readb(RBTX4927_SW_RESET_ENABLE) &
671 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
672
673 /* do a s/w reset */
674 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
675
676 /* do something passive while waiting for reset */
677 local_irq_disable();
678 wait_forever();
679 /* no return */
680 }
681
682
683 void toshiba_rbtx4927_halt(void)
684 {
685 printk(KERN_NOTICE "System Halted\n");
686 local_irq_disable();
687 wait_forever();
688 /* no return */
689 }
690
691 void toshiba_rbtx4927_power_off(void)
692 {
693 toshiba_rbtx4927_halt();
694 /* no return */
695 }
696
697 void __init plat_mem_setup(void)
698 {
699 int i;
700 u32 cp0_config;
701 char *argptr;
702
703 printk("CPU is %s\n", toshiba_name);
704
705 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
706 "-\n");
707
708 /* f/w leaves this on at startup */
709 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
710 ":Clearing STO_ERL.\n");
711 clear_c0_status(ST0_ERL);
712
713 /* enable caches -- HCP5 does this, pmon does not */
714 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
715 ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
716 cp0_config = read_c0_config();
717 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
718 write_c0_config(cp0_config);
719
720 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
721 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
722 ":mips_io_port_base=0x%08lx\n",
723 mips_io_port_base);
724
725 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
726 ":Resource\n");
727 ioport_resource.end = 0xffffffff;
728 iomem_resource.end = 0xffffffff;
729
730 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
731 ":ResetRoutines\n");
732 _machine_restart = toshiba_rbtx4927_restart;
733 _machine_halt = toshiba_rbtx4927_halt;
734 pm_power_off = toshiba_rbtx4927_power_off;
735
736 for (i = 0; i < TX4927_NR_TMR; i++)
737 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
738
739 #ifdef CONFIG_PCI
740
741 /* PCIC */
742 /*
743 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
744 *
745 * For TX4927:
746 * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
747 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
748 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
749 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
750 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
751 * i.e. S9[3]: ON (83MHz), OFF (100MHz)
752 *
753 * For TX4937:
754 * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
755 * PCIDIVMODE[10] is 0.
756 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
757 * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
758 * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
759 * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
760 * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
761 * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
762 *
763 */
764 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
765 "ccfg is %lx, PCIDIVMODE is %x\n",
766 (unsigned long) tx4927_ccfgptr->ccfg,
767 (unsigned long) tx4927_ccfgptr->ccfg &
768 (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
769 TX4937_CCFG_PCIDIVMODE_MASK :
770 TX4927_CCFG_PCIDIVMODE_MASK));
771
772 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
773 "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
774 (unsigned long) tx4927_ccfgptr->
775 ccfg & TX4927_CCFG_PCI66,
776 (unsigned long) tx4927_ccfgptr->
777 ccfg & TX4927_CCFG_PCIMIDE,
778 (unsigned long) tx4927_ccfgptr->
779 ccfg & TX4927_CCFG_PCIXARB);
780
781 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
782 switch ((unsigned long)tx4927_ccfgptr->
783 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
784 case TX4937_CCFG_PCIDIVMODE_8:
785 case TX4937_CCFG_PCIDIVMODE_4:
786 tx4927_cpu_clock = 266666666; /* 266MHz */
787 break;
788 case TX4937_CCFG_PCIDIVMODE_9:
789 case TX4937_CCFG_PCIDIVMODE_4_5:
790 tx4927_cpu_clock = 300000000; /* 300MHz */
791 break;
792 default:
793 tx4927_cpu_clock = 333333333; /* 333MHz */
794 }
795 else
796 switch ((unsigned long)tx4927_ccfgptr->
797 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
798 case TX4927_CCFG_PCIDIVMODE_2_5:
799 case TX4927_CCFG_PCIDIVMODE_5:
800 tx4927_cpu_clock = 166666666; /* 166MHz */
801 break;
802 default:
803 tx4927_cpu_clock = 200000000; /* 200MHz */
804 }
805
806 /* CCFG */
807 /* do reset on watchdog */
808 tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR;
809 /* enable Timeout BusError */
810 if (tx4927_ccfg_toeon)
811 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
812
813 tx4927_pci_setup();
814 if (tx4927_using_backplane == 1)
815 printk("backplane board IS installed\n");
816 else
817 printk("No Backplane \n");
818
819 /* this is on ISA bus behind PCI bus, so need PCI up first */
820 #ifdef CONFIG_TOSHIBA_FPCIB0
821 {
822 if (tx4927_using_backplane) {
823 TOSHIBA_RBTX4927_SETUP_DPRINTK
824 (TOSHIBA_RBTX4927_SETUP_SETUP,
825 ":fpcibo=yes\n");
826
827 TOSHIBA_RBTX4927_SETUP_DPRINTK
828 (TOSHIBA_RBTX4927_SETUP_SETUP,
829 ":smsc_fdc37m81x_init()\n");
830 smsc_fdc37m81x_init(0x3f0);
831
832 TOSHIBA_RBTX4927_SETUP_DPRINTK
833 (TOSHIBA_RBTX4927_SETUP_SETUP,
834 ":smsc_fdc37m81x_config_beg()\n");
835 smsc_fdc37m81x_config_beg();
836
837 TOSHIBA_RBTX4927_SETUP_DPRINTK
838 (TOSHIBA_RBTX4927_SETUP_SETUP,
839 ":smsc_fdc37m81x_config_set(KBD)\n");
840 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
841 SMSC_FDC37M81X_KBD);
842 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
843 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
844 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
845 1);
846
847 smsc_fdc37m81x_config_end();
848 TOSHIBA_RBTX4927_SETUP_DPRINTK
849 (TOSHIBA_RBTX4927_SETUP_SETUP,
850 ":smsc_fdc37m81x_config_end()\n");
851 } else {
852 TOSHIBA_RBTX4927_SETUP_DPRINTK
853 (TOSHIBA_RBTX4927_SETUP_SETUP,
854 ":fpcibo=not_found\n");
855 }
856 }
857 #else
858 {
859 TOSHIBA_RBTX4927_SETUP_DPRINTK
860 (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
861 }
862 #endif
863
864 #endif /* CONFIG_PCI */
865
866 #ifdef CONFIG_SERIAL_TXX9
867 {
868 extern int early_serial_txx9_setup(struct uart_port *port);
869 struct uart_port req;
870 for(i = 0; i < 2; i++) {
871 memset(&req, 0, sizeof(req));
872 req.line = i;
873 req.iotype = UPIO_MEM;
874 req.membase = (char *)(0xff1ff300 + i * 0x100);
875 req.mapbase = 0xff1ff300 + i * 0x100;
876 req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
877 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
878 req.uartclk = 50000000;
879 early_serial_txx9_setup(&req);
880 }
881 }
882 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
883 argptr = prom_getcmdline();
884 if (strstr(argptr, "console=") == NULL) {
885 strcat(argptr, " console=ttyS0,38400");
886 }
887 #endif
888 #endif
889
890 #ifdef CONFIG_ROOT_NFS
891 argptr = prom_getcmdline();
892 if (strstr(argptr, "root=") == NULL) {
893 strcat(argptr, " root=/dev/nfs rw");
894 }
895 #endif
896
897
898 #ifdef CONFIG_IP_PNP
899 argptr = prom_getcmdline();
900 if (strstr(argptr, "ip=") == NULL) {
901 strcat(argptr, " ip=any");
902 }
903 #endif
904
905
906 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
907 "+\n");
908 }
909
910 void __init plat_time_init(void)
911 {
912 mips_hpt_frequency = tx4927_cpu_clock / 2;
913 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
914 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
915 TXX9_IRQ_BASE + 17,
916 50000000);
917 }
918
919 static int __init toshiba_rbtx4927_rtc_init(void)
920 {
921 static struct resource __initdata res = {
922 .start = 0x1c010000,
923 .end = 0x1c010000 + 0x800 - 1,
924 .flags = IORESOURCE_MEM,
925 };
926 struct platform_device *dev =
927 platform_device_register_simple("rtc-ds1742", -1, &res, 1);
928 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
929 }
930 device_initcall(toshiba_rbtx4927_rtc_init);
931
932 static int __init rbtx4927_ne_init(void)
933 {
934 static struct resource __initdata res[] = {
935 {
936 .start = RBTX4927_RTL_8019_BASE,
937 .end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
938 .flags = IORESOURCE_IO,
939 }, {
940 .start = RBTX4927_RTL_8019_IRQ,
941 .flags = IORESOURCE_IRQ,
942 }
943 };
944 struct platform_device *dev =
945 platform_device_register_simple("ne", -1,
946 res, ARRAY_SIZE(res));
947 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
948 }
949 device_initcall(rbtx4927_ne_init);
950
951 /* Watchdog support */
952
953 static int __init txx9_wdt_init(unsigned long base)
954 {
955 struct resource res = {
956 .start = base,
957 .end = base + 0x100 - 1,
958 .flags = IORESOURCE_MEM,
959 };
960 struct platform_device *dev =
961 platform_device_register_simple("txx9wdt", -1, &res, 1);
962 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
963 }
964
965 static int __init rbtx4927_wdt_init(void)
966 {
967 return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
968 }
969 device_initcall(rbtx4927_wdt_init);
970
971 /* Minimum CLK support */
972
973 struct clk *clk_get(struct device *dev, const char *id)
974 {
975 if (!strcmp(id, "imbus_clk"))
976 return (struct clk *)50000000;
977 return ERR_PTR(-ENOENT);
978 }
979 EXPORT_SYMBOL(clk_get);
980
981 int clk_enable(struct clk *clk)
982 {
983 return 0;
984 }
985 EXPORT_SYMBOL(clk_enable);
986
987 void clk_disable(struct clk *clk)
988 {
989 }
990 EXPORT_SYMBOL(clk_disable);
991
992 unsigned long clk_get_rate(struct clk *clk)
993 {
994 return (unsigned long)clk;
995 }
996 EXPORT_SYMBOL(clk_get_rate);
997
998 void clk_put(struct clk *clk)
999 {
1000 }
1001 EXPORT_SYMBOL(clk_put);
WRT350N Kernel Patches