arch/ppc/platforms/4xx/ibm405gp.h

   1 /*
   2  * Author: Armin Kuster akuster@mvista.com
   3  *
   4  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
   5  * the terms of the GNU General Public License version 2.  This program
   6  * is licensed "as is" without any warranty of any kind, whether express
   7  * or implied.
   8  */
   9
  10 #ifdef __KERNEL__
  11 #ifndef __ASM_IBM405GP_H__
  12 #define __ASM_IBM405GP_H__
  13
  14
  15 /* ibm405.h at bottom of this file */
  16
  17 /* PCI
  18  * PCI Bridge config reg definitions
  19  * see 17-19 of manual
  20  */
  21
  22 #define PPC405_PCI_CONFIG_ADDR  0xeec00000
  23 #define PPC405_PCI_CONFIG_DATA  0xeec00004
  24
  25 #define PPC405_PCI_PHY_MEM_BASE 0x80000000      /* hose_a->pci_mem_offset */
  26                                                 /* setbat */
  27 #define PPC405_PCI_MEM_BASE     PPC405_PCI_PHY_MEM_BASE /* setbat */
  28 #define PPC405_PCI_PHY_IO_BASE  0xe8000000      /* setbat */
  29 #define PPC405_PCI_IO_BASE      PPC405_PCI_PHY_IO_BASE  /* setbat */
  30
  31 #define PPC405_PCI_LOWER_MEM    0x80000000      /* hose_a->mem_space.start */
  32 #define PPC405_PCI_UPPER_MEM    0xBfffffff      /* hose_a->mem_space.end */
  33 #define PPC405_PCI_LOWER_IO     0x00000000      /* hose_a->io_space.start */
  34 #define PPC405_PCI_UPPER_IO     0x0000ffff      /* hose_a->io_space.end */
  35
  36 #define PPC405_ISA_IO_BASE      PPC405_PCI_IO_BASE
  37
  38 #define PPC4xx_PCI_IO_PADDR     ((uint)PPC405_PCI_PHY_IO_BASE)
  39 #define PPC4xx_PCI_IO_VADDR     PPC4xx_PCI_IO_PADDR
  40 #define PPC4xx_PCI_IO_SIZE      ((uint)64*1024)
  41 #define PPC4xx_PCI_CFG_PADDR    ((uint)PPC405_PCI_CONFIG_ADDR)
  42 #define PPC4xx_PCI_CFG_VADDR    PPC4xx_PCI_CFG_PADDR
  43 #define PPC4xx_PCI_CFG_SIZE     ((uint)4*1024)
  44 #define PPC4xx_PCI_LCFG_PADDR   ((uint)0xef400000)
  45 #define PPC4xx_PCI_LCFG_VADDR   PPC4xx_PCI_LCFG_PADDR
  46 #define PPC4xx_PCI_LCFG_SIZE    ((uint)4*1024)
  47 #define PPC4xx_ONB_IO_PADDR     ((uint)0xef600000)
  48 #define PPC4xx_ONB_IO_VADDR     PPC4xx_ONB_IO_PADDR
  49 #define PPC4xx_ONB_IO_SIZE      ((uint)4*1024)
  50
  51 /* serial port defines */
  52 #define RS_TABLE_SIZE   2
  53
  54 #define UART0_INT       0
  55 #define UART1_INT       1
  56
  57 #define PCIL0_BASE      0xEF400000
  58 #define UART0_IO_BASE   0xEF600300
  59 #define UART1_IO_BASE   0xEF600400
  60 #define EMAC0_BASE      0xEF600800
  61
  62 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
  63
  64 #define STD_UART_OP(num)                                        \
  65         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
  66                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
  67                 iomem_base: (u8 *)UART##num##_IO_BASE,          \
  68                 io_type: SERIAL_IO_MEM},
  69
  70 #if defined(CONFIG_UART0_TTYS0)
  71 #define SERIAL_DEBUG_IO_BASE    UART0_IO_BASE
  72 #define SERIAL_PORT_DFNS        \
  73         STD_UART_OP(0)          \
  74         STD_UART_OP(1)
  75 #endif
  76
  77 #if defined(CONFIG_UART0_TTYS1)
  78 #define SERIAL_DEBUG_IO_BASE    UART1_IO_BASE
  79 #define SERIAL_PORT_DFNS        \
  80         STD_UART_OP(1)          \
  81         STD_UART_OP(0)
  82 #endif
  83
  84 /* DCR defines */
  85 #define DCRN_CHCR_BASE          0x0B1
  86 #define DCRN_CHPSR_BASE         0x0B4
  87 #define DCRN_CPMSR_BASE         0x0B8
  88 #define DCRN_CPMFR_BASE         0x0BA
  89
  90 #define CHR0_U0EC       0x00000080      /* Select external clock for UART0 */
  91 #define CHR0_U1EC       0x00000040      /* Select external clock for UART1 */
  92 #define CHR0_UDIV       0x0000003E      /* UART internal clock divisor */
  93 #define CHR1_CETE       0x00800000      /* CPU external timer enable */
  94
  95 #define DCRN_CHPSR_BASE         0x0B4
  96 #define  PSR_PLL_FWD_MASK        0xC0000000
  97 #define  PSR_PLL_FDBACK_MASK     0x30000000
  98 #define  PSR_PLL_TUNING_MASK     0x0E000000
  99 #define  PSR_PLB_CPU_MASK        0x01800000
 100 #define  PSR_OPB_PLB_MASK        0x00600000
 101 #define  PSR_PCI_PLB_MASK        0x00180000
 102 #define  PSR_EB_PLB_MASK         0x00060000
 103 #define  PSR_ROM_WIDTH_MASK      0x00018000
 104 #define  PSR_ROM_LOC             0x00004000
 105 #define  PSR_PCI_ASYNC_EN        0x00001000
 106 #define  PSR_PCI_ARBIT_EN        0x00000400
 107
 108 #define IBM_CPM_IIC0            0x80000000      /* IIC interface */
 109 #define IBM_CPM_PCI             0x40000000      /* PCI bridge */
 110 #define IBM_CPM_CPU             0x20000000      /* processor core */
 111 #define IBM_CPM_DMA             0x10000000      /* DMA controller */
 112 #define IBM_CPM_OPB             0x08000000      /* PLB to OPB bridge */
 113 #define IBM_CPM_DCP             0x04000000      /* CodePack */
 114 #define IBM_CPM_EBC             0x02000000      /* ROM/SRAM peripheral controller */
 115 #define IBM_CPM_SDRAM0          0x01000000      /* SDRAM memory controller */
 116 #define IBM_CPM_PLB             0x00800000      /* PLB bus arbiter */
 117 #define IBM_CPM_GPIO0           0x00400000      /* General Purpose IO (??) */
 118 #define IBM_CPM_UART0           0x00200000      /* serial port 0 */
 119 #define IBM_CPM_UART1           0x00100000      /* serial port 1 */
 120 #define IBM_CPM_UIC             0x00080000      /* Universal Interrupt Controller */
 121 #define IBM_CPM_TMRCLK          0x00040000      /* CPU timers */
 122 #define IBM_CPM_EMAC0           0x00020000      /* on-chip ethernet MM unit */
 123 #define DFLT_IBM4xx_PM          ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
 124                                         | IBM_CPM_OPB | IBM_CPM_EBC \
 125                                         | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
 126                                         | IBM_CPM_UIC | IBM_CPM_TMRCLK)
 127
 128 #define DCRN_DMA0_BASE          0x100
 129 #define DCRN_DMA1_BASE          0x108
 130 #define DCRN_DMA2_BASE          0x110
 131 #define DCRN_DMA3_BASE          0x118
 132 #define DCRNCAP_DMA_SG          1       /* have DMA scatter/gather capability */
 133 #define DCRN_DMASR_BASE         0x120
 134 #define DCRN_EBC_BASE           0x012
 135 #define DCRN_DCP0_BASE          0x014
 136 #define DCRN_MAL_BASE           0x180
 137 #define DCRN_OCM0_BASE          0x018
 138 #define DCRN_PLB0_BASE          0x084
 139 #define DCRN_PLLMR_BASE         0x0B0
 140 #define DCRN_POB0_BASE          0x0A0
 141 #define DCRN_SDRAM0_BASE        0x010
 142 #define DCRN_UIC0_BASE          0x0C0
 143 #define UIC0 DCRN_UIC0_BASE
 144
 145 #include <asm/ibm405.h>
 146
 147 #endif                          /* __ASM_IBM405GP_H__ */
 148 #endif                          /* __KERNEL__ */