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au1550_spi: fix prototype of irq handler
[wrt350n-kernel.git] / arch / ppc / platforms / katana.c
blobfe6e88cdb1cd0de4f11b3f8d0db6811a42c7a470
1 /*
2 * Board setup routines for the Artesyn Katana cPCI boards.
3 *
4 * Author: Tim Montgomery <timm@artesyncp.com>
5 * Maintained by: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
8 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15 /*
16 * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical
17 * to the 750i except that it has an mv64460 bridge.
18 */
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/kdev_t.h>
22 #include <linux/console.h>
23 #include <linux/initrd.h>
24 #include <linux/root_dev.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/mtd/physmap.h>
28 #include <linux/mv643xx.h>
29 #include <linux/platform_device.h>
30 #include <asm/io.h>
31 #include <asm/unistd.h>
32 #include <asm/page.h>
33 #include <asm/time.h>
34 #include <asm/smp.h>
35 #include <asm/todc.h>
36 #include <asm/bootinfo.h>
37 #include <asm/ppcboot.h>
38 #include <asm/mv64x60.h>
39 #include <platforms/katana.h>
40 #include <asm/machdep.h>
41
42 static struct mv64x60_handle bh;
43 static katana_id_t katana_id;
44 static void __iomem *cpld_base;
45 static void __iomem *sram_base;
46 static u32 katana_flash_size_0;
47 static u32 katana_flash_size_1;
48 static u32 katana_bus_frequency;
49 static struct pci_controller katana_hose_a;
50
51 unsigned char __res[sizeof(bd_t)];
52
53 /* PCI Interrupt routing */
54 static int __init
55 katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
56 {
57 static char pci_irq_table[][4] = {
58 /*
59 * PCI IDSEL/INTPIN->INTLINE
60 * A B C D
61 */
62 /* IDSEL 4 (PMC 1) */
63 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
64 KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
65 /* IDSEL 5 (PMC 2) */
66 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
67 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
68 /* IDSEL 6 (T8110) */
69 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
70 /* IDSEL 7 (unused) */
71 {0, 0, 0, 0 },
72 /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
73 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
74 };
75 const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
76
77 return PCI_IRQ_TABLE_LOOKUP;
78 }
79
80 static int __init
81 katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
82 {
83 static char pci_irq_table[][4] = {
84 /*
85 * PCI IDSEL/INTPIN->INTLINE
86 * A B C D
87 */
88 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
89 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
90 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
91 };
92 const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
93
94 return PCI_IRQ_TABLE_LOOKUP;
95 }
96
97 static int __init
98 katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
99 {
100 switch (katana_id) {
101 case KATANA_ID_750I:
102 case KATANA_ID_752I:
103 return katana_irq_lookup_750i(idsel, pin);
104
105 case KATANA_ID_3750:
106 return katana_irq_lookup_3750(idsel, pin);
107
108 default:
109 printk(KERN_ERR "Bogus board ID\n");
110 return 0;
111 }
112 }
113
114 /* Board info retrieval routines */
115 void __init
116 katana_get_board_id(void)
117 {
118 switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
119 case KATANA_PRODUCT_ID_3750:
120 katana_id = KATANA_ID_3750;
121 break;
122
123 case KATANA_PRODUCT_ID_750i:
124 katana_id = KATANA_ID_750I;
125 break;
126
127 case KATANA_PRODUCT_ID_752i:
128 katana_id = KATANA_ID_752I;
129 break;
130
131 default:
132 printk(KERN_ERR "Unsupported board\n");
133 }
134 }
135
136 int __init
137 katana_get_proc_num(void)
138 {
139 u16 val;
140 u8 save_exclude;
141 static int proc = -1;
142 static u8 first_time = 1;
143
144 if (first_time) {
145 if (katana_id != KATANA_ID_3750)
146 proc = 0;
147 else {
148 save_exclude = mv64x60_pci_exclude_bridge;
149 mv64x60_pci_exclude_bridge = 0;
150
151 early_read_config_word(bh.hose_b, 0,
152 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
153
154 mv64x60_pci_exclude_bridge = save_exclude;
155
156 switch(val) {
157 case PCI_DEVICE_ID_KATANA_3750_PROC0:
158 proc = 0;
159 break;
160
161 case PCI_DEVICE_ID_KATANA_3750_PROC1:
162 proc = 1;
163 break;
164
165 case PCI_DEVICE_ID_KATANA_3750_PROC2:
166 proc = 2;
167 break;
168
169 default:
170 printk(KERN_ERR "Bogus Device ID\n");
171 }
172 }
173
174 first_time = 0;
175 }
176
177 return proc;
178 }
179
180 static inline int
181 katana_is_monarch(void)
182 {
183 return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
184 KATANA_CPLD_BD_CFG_3_MONARCH;
185 }
186
187 static void __init
188 katana_setup_bridge(void)
189 {
190 struct pci_controller hose;
191 struct mv64x60_setup_info si;
192 void __iomem *vaddr;
193 int i;
194 u32 v;
195 u16 val, type;
196 u8 save_exclude;
197
198 /*
199 * Some versions of the Katana firmware mistakenly change the vendor
200 * & device id fields in the bridge's pci device (visible via pci
201 * config accesses). This breaks mv64x60_init() because those values
202 * are used to identify the type of bridge that's there. Artesyn
203 * claims that the subsystem vendor/device id's will have the correct
204 * Marvell values so this code puts back the correct values from there.
205 */
206 memset(&hose, 0, sizeof(hose));
207 vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
208 setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
209 vaddr + MV64x60_PCI0_CONFIG_DATA);
210 save_exclude = mv64x60_pci_exclude_bridge;
211 mv64x60_pci_exclude_bridge = 0;
212
213 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
214
215 if (val != PCI_VENDOR_ID_MARVELL) {
216 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
217 PCI_SUBSYSTEM_VENDOR_ID, &val);
218 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
219 PCI_VENDOR_ID, val);
220 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
221 PCI_SUBSYSTEM_ID, &val);
222 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
223 PCI_DEVICE_ID, val);
224 }
225
226 /*
227 * While we're in here, set the hotswap register correctly.
228 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
229 */
230 early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
231 MV64360_PCICFG_CPCI_HOTSWAP, &v);
232 v &= ~(1<<19);
233 v |= ((1<<17) | (1<<22) | (1<<23));
234 early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
235 MV64360_PCICFG_CPCI_HOTSWAP, v);
236
237 /* While we're at it, grab the bridge type for later */
238 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
239
240 mv64x60_pci_exclude_bridge = save_exclude;
241 iounmap(vaddr);
242
243 memset(&si, 0, sizeof(si));
244
245 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
246
247 si.pci_1.enable_bus = 1;
248 si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
249 si.pci_1.pci_io.pci_base_hi = 0;
250 si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
251 si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
252 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
253 si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
254 si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
255 si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
256 si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
257 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
258 si.pci_1.pci_cmd_bits = 0;
259 si.pci_1.latency_timer = 0x80;
260
261 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
262 #if defined(CONFIG_NOT_COHERENT_CACHE)
263 si.cpu_prot_options[i] = 0;
264 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
265 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
266 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
267
268 si.pci_1.acc_cntl_options[i] =
269 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
270 MV64360_PCI_ACC_CNTL_SWAP_NONE |
271 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
272 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
273 #else
274 si.cpu_prot_options[i] = 0;
275 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
276 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
277 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
278
279 si.pci_1.acc_cntl_options[i] =
280 MV64360_PCI_ACC_CNTL_SNOOP_WB |
281 MV64360_PCI_ACC_CNTL_SWAP_NONE |
282 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
283 ((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
284 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
285 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
286 #endif
287 }
288
289 /* Lookup PCI host bridges */
290 if (mv64x60_init(&bh, &si))
291 printk(KERN_WARNING "Bridge initialization failed.\n");
292
293 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
294 ppc_md.pci_swizzle = common_swizzle;
295 ppc_md.pci_map_irq = katana_map_irq;
296 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
297
298 mv64x60_set_bus(&bh, 1, 0);
299 bh.hose_b->first_busno = 0;
300 bh.hose_b->last_busno = 0xff;
301
302 /*
303 * Need to access hotswap reg which is in the pci config area of the
304 * bridge's hose 0. Note that pcibios_alloc_controller() can't be used
305 * to alloc hose_a b/c that would make hose 0 known to the generic
306 * pci code which we don't want.
307 */
308 bh.hose_a = &katana_hose_a;
309 setup_indirect_pci_nomap(bh.hose_a,
310 bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
311 bh.v_base + MV64x60_PCI0_CONFIG_DATA);
312 }
313
314 /* Bridge & platform setup routines */
315 void __init
316 katana_intr_setup(void)
317 {
318 if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
319 mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
320
321 /* MPP 8, 9, and 10 */
322 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
323
324 /* MPP 14 */
325 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
326 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
327
328 /*
329 * Define GPP 8,9,and 10 interrupt polarity as active low
330 * input signal and level triggered
331 */
332 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
333 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
334
335 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
336 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
337 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
338 }
339
340 /* Config GPP intr ctlr to respond to level trigger */
341 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
342
343 if (bh.type == MV64x60_TYPE_MV64360) {
344 /* Erratum FEr PCI-#9 */
345 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
346 (1<<4) | (1<<5) | (1<<6) | (1<<7));
347 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
348 } else {
349 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
350 mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
351 (1<<4) | (1<<5) | (1<<8) | (1<<9));
352 }
353
354 /*
355 * Dismiss and then enable interrupt on GPP interrupt cause
356 * for CPU #0
357 */
358 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
359 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
360
361 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
362 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
363 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
364 }
365
366 /*
367 * Dismiss and then enable interrupt on CPU #0 high cause reg
368 * BIT25 summarizes GPP interrupts 8-15
369 */
370 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
371 }
372
373 void __init
374 katana_setup_peripherals(void)
375 {
376 u32 base;
377
378 /* Set up windows for boot CS, soldered & socketed flash, and CPLD */
379 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
380 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
381 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
382
383 /* Assume firmware set up window sizes correctly for dev 0 & 1 */
384 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
385 &katana_flash_size_0);
386
387 if (katana_flash_size_0 > 0) {
388 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
389 KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
390 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
391 }
392
393 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
394 &katana_flash_size_1);
395
396 if (katana_flash_size_1 > 0) {
397 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
398 (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
399 katana_flash_size_1, 0);
400 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
401 }
402
403 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
404 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
405 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
406
407 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
408 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
409 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
410 cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
411
412 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
413 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
414 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
415 sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
416
417 /* Set up Enet->SRAM window */
418 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
419 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
420 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
421
422 /* Give enet r/w access to memory region */
423 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
424 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
425 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
426
427 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
428 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
429 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
430
431 /* Must wait until window set up before retrieving board id */
432 katana_get_board_id();
433
434 /* Enumerate pci bus (must know board id before getting proc number) */
435 if (katana_get_proc_num() == 0)
436 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
437
438 #if defined(CONFIG_NOT_COHERENT_CACHE)
439 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
440 #else
441 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
442 #endif
443
444 /*
445 * Setting the SRAM to 0. Note that this generates parity errors on
446 * internal data path in SRAM since it's first time accessing it
447 * while after reset it's not configured.
448 */
449 memset(sram_base, 0, MV64360_SRAM_SIZE);
450
451 /* Only processor zero [on 3750] is an PCI interrupt controller */
452 if (katana_get_proc_num() == 0)
453 katana_intr_setup();
454 }
455
456 static void __init
457 katana_enable_ipmi(void)
458 {
459 u8 reset_out;
460
461 /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
462 reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
463 reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
464 out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
465 }
466
467 static void __init
468 katana_setup_arch(void)
469 {
470 if (ppc_md.progress)
471 ppc_md.progress("katana_setup_arch: enter", 0);
472
473 set_tb(0, 0);
474
475 #ifdef CONFIG_BLK_DEV_INITRD
476 if (initrd_start)
477 ROOT_DEV = Root_RAM0;
478 else
479 #endif
480 #ifdef CONFIG_ROOT_NFS
481 ROOT_DEV = Root_NFS;
482 #else
483 ROOT_DEV = Root_SDA2;
484 #endif
485
486 /*
487 * Set up the L2CR register.
488 *
489 * 750FX has only L2E, L2PE (bits 2-8 are reserved)
490 * DD2.0 has bug that requires the L2 to be in WRT mode
491 * avoid dirty data in cache
492 */
493 if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
494 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
495 "to Writethrough mode\n");
496 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
497 } else
498 _set_L2CR(L2CR_L2E | L2CR_L2PE);
499
500 if (ppc_md.progress)
501 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
502
503 katana_setup_bridge();
504 katana_setup_peripherals();
505 katana_enable_ipmi();
506
507 katana_bus_frequency = katana_bus_freq(cpld_base);
508
509 printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
510 if (ppc_md.progress)
511 ppc_md.progress("katana_setup_arch: exit", 0);
512 }
513
514 void
515 katana_fixup_resources(struct pci_dev *dev)
516 {
517 u16 v16;
518
519 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2);
520
521 pci_read_config_word(dev, PCI_COMMAND, &v16);
522 v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
523 pci_write_config_word(dev, PCI_COMMAND, v16);
524 }
525
526 static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
527 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/
528 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/
529 };
530
531 static int
532 katana_get_cpu_freq(void)
533 {
534 unsigned long pll_cfg;
535
536 pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
537 return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
538 }
539
540 /* Platform device data fixup routines. */
541 #if defined(CONFIG_SERIAL_MPSC)
542 static void __init
543 katana_fixup_mpsc_pdata(struct platform_device *pdev)
544 {
545 struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
546 bd_t *bdp = (bd_t *)__res;
547
548 if (bdp->bi_baudrate)
549 pdata->default_baud = bdp->bi_baudrate;
550 else
551 pdata->default_baud = KATANA_DEFAULT_BAUD;
552
553 pdata->max_idle = 40;
554 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
555 /*
556 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
557 * TCLK == SysCLK but on 64460, they are separate pins.
558 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
559 */
560 pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
561 }
562 #endif
563
564 #if defined(CONFIG_MV643XX_ETH)
565 static void __init
566 katana_fixup_eth_pdata(struct platform_device *pdev)
567 {
568 struct mv643xx_eth_platform_data *eth_pd;
569 static u16 phy_addr[] = {
570 KATANA_ETH0_PHY_ADDR,
571 KATANA_ETH1_PHY_ADDR,
572 KATANA_ETH2_PHY_ADDR,
573 };
574
575 eth_pd = pdev->dev.platform_data;
576 eth_pd->force_phy_addr = 1;
577 eth_pd->phy_addr = phy_addr[pdev->id];
578 eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
579 eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
580 }
581 #endif
582
583 #if defined(CONFIG_SYSFS)
584 static void __init
585 katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
586 {
587 struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
588 pdev->dev.platform_data;
589
590 /* Katana supports the mv64xxx hotswap register */
591 pdata->hs_reg_valid = 1;
592 }
593 #endif
594
595 static int
596 katana_platform_notify(struct device *dev)
597 {
598 static struct {
599 char *bus_id;
600 void ((*rtn)(struct platform_device *pdev));
601 } dev_map[] = {
602 #if defined(CONFIG_SERIAL_MPSC)
603 { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
604 { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
605 #endif
606 #if defined(CONFIG_MV643XX_ETH)
607 { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
608 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
609 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
610 #endif
611 #if defined(CONFIG_SYSFS)
612 { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
613 #endif
614 };
615 struct platform_device *pdev;
616 int i;
617
618 if (dev && dev->bus_id)
619 for (i=0; i<ARRAY_SIZE(dev_map); i++)
620 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
621 BUS_ID_SIZE)) {
622 pdev = container_of(dev,
623 struct platform_device, dev);
624 dev_map[i].rtn(pdev);
625 }
626
627 return 0;
628 }
629
630 #ifdef CONFIG_MTD_PHYSMAP
631
632 #ifndef MB
633 #define MB (1 << 20)
634 #endif
635
636 /*
637 * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
638 *
639 * FLASH Amount: 128 64 32 16
640 * ------------- --- -- -- --
641 * Monitor: 1 1 1 1
642 * Primary Kernel: 1.5 1.5 1.5 1.5
643 * Primary fs: 30 30 <end> <end>
644 * Secondary Kernel: 1.5 1.5 N/A N/A
645 * Secondary fs: <end> <end> N/A N/A
646 * User: <overlays entire FLASH except for "Monitor" section>
647 */
648 static int __init
649 katana_setup_mtd(void)
650 {
651 u32 size;
652 int ptbl_entries;
653 static struct mtd_partition *ptbl;
654
655 size = katana_flash_size_0 + katana_flash_size_1;
656 if (!size)
657 return -ENOMEM;
658
659 ptbl_entries = (size >= (64*MB)) ? 6 : 4;
660
661 if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition),
662 GFP_KERNEL)) == NULL) {
663 printk(KERN_WARNING "Can't alloc MTD partition table\n");
664 return -ENOMEM;
665 }
666
667 ptbl[0].name = "Monitor";
668 ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
669 ptbl[1].name = "Primary Kernel";
670 ptbl[1].offset = MTDPART_OFS_NXTBLK;
671 ptbl[1].size = 0x00180000; /* 1.5 MB */
672 ptbl[2].name = "Primary Filesystem";
673 ptbl[2].offset = MTDPART_OFS_APPEND;
674 ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
675 ptbl[ptbl_entries-1].name = "User FLASH";
676 ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
677 ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
678
679 if (size >= (64*MB)) {
680 ptbl[2].size = 30*MB;
681 ptbl[3].name = "Secondary Kernel";
682 ptbl[3].offset = MTDPART_OFS_NXTBLK;
683 ptbl[3].size = 0x00180000; /* 1.5 MB */
684 ptbl[4].name = "Secondary Filesystem";
685 ptbl[4].offset = MTDPART_OFS_APPEND;
686 ptbl[4].size = MTDPART_SIZ_FULL;
687 }
688
689 physmap_map.size = size;
690 physmap_set_partitions(ptbl, ptbl_entries);
691 return 0;
692 }
693 arch_initcall(katana_setup_mtd);
694 #endif
695
696 static void
697 katana_restart(char *cmd)
698 {
699 ulong i = 10000000;
700
701 /* issue hard reset to the reset command register */
702 out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
703
704 while (i-- > 0) ;
705 panic("restart failed\n");
706 }
707
708 static void
709 katana_halt(void)
710 {
711 u8 v;
712
713 /* Turn on blue LED to indicate its okay to remove */
714 if (katana_id == KATANA_ID_750I) {
715 u32 v;
716 u8 save_exclude;
717
718 /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
719 save_exclude = mv64x60_pci_exclude_bridge;
720 mv64x60_pci_exclude_bridge = 0;
721 early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
722 MV64360_PCICFG_CPCI_HOTSWAP, &v);
723 v &= 0xff;
724 v |= (1 << 19);
725 early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
726 MV64360_PCICFG_CPCI_HOTSWAP, v);
727 mv64x60_pci_exclude_bridge = save_exclude;
728 } else if (katana_id == KATANA_ID_752I) {
729 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
730 v |= HSL_PLD_HOT_SWAP_LED_BIT;
731 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
732 }
733
734 while (1) ;
735 /* NOTREACHED */
736 }
737
738 static void
739 katana_power_off(void)
740 {
741 katana_halt();
742 /* NOTREACHED */
743 }
744
745 static int
746 katana_show_cpuinfo(struct seq_file *m)
747 {
748 char *s;
749
750 seq_printf(m, "cpu freq\t: %dMHz\n",
751 (katana_get_cpu_freq() + 500000) / 1000000);
752 seq_printf(m, "bus freq\t: %ldMHz\n",
753 ((long)katana_bus_frequency + 500000) / 1000000);
754 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
755
756 seq_printf(m, "board\t\t: ");
757 switch (katana_id) {
758 case KATANA_ID_3750:
759 seq_printf(m, "Katana 3750");
760 break;
761
762 case KATANA_ID_750I:
763 seq_printf(m, "Katana 750i");
764 break;
765
766 case KATANA_ID_752I:
767 seq_printf(m, "Katana 752i");
768 break;
769
770 default:
771 seq_printf(m, "Unknown");
772 break;
773 }
774 seq_printf(m, " (product id: 0x%x)\n",
775 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
776
777 seq_printf(m, "pci mode\t: %sMonarch\n",
778 katana_is_monarch()? "" : "Non-");
779 seq_printf(m, "hardware rev\t: 0x%x\n",
780 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
781 seq_printf(m, "pld rev\t\t: 0x%x\n",
782 in_8(cpld_base + KATANA_CPLD_PLD_VER));
783
784 switch(bh.type) {
785 case MV64x60_TYPE_GT64260A:
786 s = "gt64260a";
787 break;
788 case MV64x60_TYPE_GT64260B:
789 s = "gt64260b";
790 break;
791 case MV64x60_TYPE_MV64360:
792 s = "mv64360";
793 break;
794 case MV64x60_TYPE_MV64460:
795 s = "mv64460";
796 break;
797 default:
798 s = "Unknown";
799 }
800 seq_printf(m, "bridge type\t: %s\n", s);
801 seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
802 #if defined(CONFIG_NOT_COHERENT_CACHE)
803 seq_printf(m, "coherency\t: %s\n", "off");
804 #else
805 seq_printf(m, "coherency\t: %s\n", "on");
806 #endif
807
808 return 0;
809 }
810
811 static void __init
812 katana_calibrate_decr(void)
813 {
814 u32 freq;
815
816 freq = katana_bus_frequency / 4;
817
818 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
819 (long)freq / 1000000, (long)freq % 1000000);
820
821 tb_ticks_per_jiffy = freq / HZ;
822 tb_to_us = mulhwu_scale_factor(freq, 1000000);
823 }
824
825 /*
826 * The katana supports both uImage and zImage. If uImage, get the mem size
827 * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in
828 * the bi_rec data which is sucked out and put into boot_mem_size by
829 * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem
830 * size and not call this routine. The only way this will fail is when a uImage
831 * is used but the fw doesn't pass in a valid bi_memsize. This should never
832 * happen, though.
833 */
834 unsigned long __init
835 katana_find_end_of_memory(void)
836 {
837 bd_t *bdp = (bd_t *)__res;
838 return bdp->bi_memsize;
839 }
840
841 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
842 static void __init
843 katana_map_io(void)
844 {
845 io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
846 }
847 #endif
848
849 void __init
850 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
851 unsigned long r6, unsigned long r7)
852 {
853 parse_bootinfo(find_bootinfo());
854
855 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
856 * are non-zero, then we should use the board info from the bd_t
857 * structure and the cmdline pointed to by r6 instead of the
858 * information from birecs, if any. Otherwise, use the information
859 * from birecs as discovered by the preceding call to
860 * parse_bootinfo(). This rule should work with both PPCBoot, which
861 * uses a bd_t board info structure, and the kernel boot wrapper,
862 * which uses birecs.
863 */
864 if (r3 && r6) {
865 /* copy board info structure */
866 memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
867 /* copy command line */
868 *(char *)(r7+KERNELBASE) = 0;
869 strcpy(cmd_line, (char *)(r6+KERNELBASE));
870 }
871
872 #ifdef CONFIG_BLK_DEV_INITRD
873 /* take care of initrd if we have one */
874 if (r4) {
875 initrd_start = r4 + KERNELBASE;
876 initrd_end = r5 + KERNELBASE;
877 }
878 #endif /* CONFIG_BLK_DEV_INITRD */
879
880 isa_mem_base = 0;
881
882 ppc_md.setup_arch = katana_setup_arch;
883 ppc_md.pcibios_fixup_resources = katana_fixup_resources;
884 ppc_md.show_cpuinfo = katana_show_cpuinfo;
885 ppc_md.init_IRQ = mv64360_init_irq;
886 ppc_md.get_irq = mv64360_get_irq;
887 ppc_md.restart = katana_restart;
888 ppc_md.power_off = katana_power_off;
889 ppc_md.halt = katana_halt;
890 ppc_md.find_end_of_memory = katana_find_end_of_memory;
891 ppc_md.calibrate_decr = katana_calibrate_decr;
892
893 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
894 ppc_md.setup_io_mappings = katana_map_io;
895 ppc_md.progress = mv64x60_mpsc_progress;
896 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
897 #endif
898
899 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
900 platform_notify = katana_platform_notify;
901 #endif
902 }
WRT350N Kernel Patches