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au1550_spi: fix prototype of irq handler
[wrt350n-kernel.git] / drivers / mtd / nand / s3c2410.c
blob9260ad947524f4f4a28959a3b843f48a8069c7f8
1 /* linux/drivers/mtd/nand/s3c2410.c
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Samsung S3C2410/S3C240 NAND driver
8 *
9 * Changelog:
10 * 21-Sep-2004 BJD Initial version
11 * 23-Sep-2004 BJD Multiple device support
12 * 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
13 * 12-Oct-2004 BJD Fixed errors in use of platform data
14 * 18-Feb-2005 BJD Fix sparse errors
15 * 14-Mar-2005 BJD Applied tglx's code reduction patch
16 * 02-May-2005 BJD Fixed s3c2440 support
17 * 02-May-2005 BJD Reduced hwcontrol decode
18 * 20-Jun-2005 BJD Updated s3c2440 support, fixed timing bug
19 * 08-Jul-2005 BJD Fix OOPS when no platform data supplied
20 * 20-Oct-2005 BJD Fix timing calculation bug
21 * 14-Jan-2006 BJD Allow clock to be stopped when idle
22 *
23 * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
24 *
25 * This program is free software; you can redistribute it and/or modify
26 * it under the terms of the GNU General Public License as published by
27 * the Free Software Foundation; either version 2 of the License, or
28 * (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
38 */
39
40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
41 #define DEBUG
42 #endif
43
44 #include <linux/module.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/kernel.h>
48 #include <linux/string.h>
49 #include <linux/ioport.h>
50 #include <linux/platform_device.h>
51 #include <linux/delay.h>
52 #include <linux/err.h>
53 #include <linux/slab.h>
54 #include <linux/clk.h>
55
56 #include <linux/mtd/mtd.h>
57 #include <linux/mtd/nand.h>
58 #include <linux/mtd/nand_ecc.h>
59 #include <linux/mtd/partitions.h>
60
61 #include <asm/io.h>
62
63 #include <asm/plat-s3c/regs-nand.h>
64 #include <asm/plat-s3c/nand.h>
65
66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
67 static int hardware_ecc = 1;
68 #else
69 static int hardware_ecc = 0;
70 #endif
71
72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
73 static int clock_stop = 1;
74 #else
75 static const int clock_stop = 0;
76 #endif
77
78
79 /* new oob placement block for use with hardware ecc generation
80 */
81
82 static struct nand_ecclayout nand_hw_eccoob = {
83 .eccbytes = 3,
84 .eccpos = {0, 1, 2},
85 .oobfree = {{8, 8}}
86 };
87
88 /* controller and mtd information */
89
90 struct s3c2410_nand_info;
91
92 struct s3c2410_nand_mtd {
93 struct mtd_info mtd;
94 struct nand_chip chip;
95 struct s3c2410_nand_set *set;
96 struct s3c2410_nand_info *info;
97 int scan_res;
98 };
99
100 enum s3c_cpu_type {
101 TYPE_S3C2410,
102 TYPE_S3C2412,
103 TYPE_S3C2440,
104 };
105
106 /* overview of the s3c2410 nand state */
107
108 struct s3c2410_nand_info {
109 /* mtd info */
110 struct nand_hw_control controller;
111 struct s3c2410_nand_mtd *mtds;
112 struct s3c2410_platform_nand *platform;
113
114 /* device info */
115 struct device *device;
116 struct resource *area;
117 struct clk *clk;
118 void __iomem *regs;
119 void __iomem *sel_reg;
120 int sel_bit;
121 int mtd_count;
122
123 unsigned long save_nfconf;
124
125 enum s3c_cpu_type cpu_type;
126 };
127
128 /* conversion functions */
129
130 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
131 {
132 return container_of(mtd, struct s3c2410_nand_mtd, mtd);
133 }
134
135 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
136 {
137 return s3c2410_nand_mtd_toours(mtd)->info;
138 }
139
140 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
141 {
142 return platform_get_drvdata(dev);
143 }
144
145 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
146 {
147 return dev->dev.platform_data;
148 }
149
150 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
151 {
152 return clock_stop;
153 }
154
155 /* timing calculations */
156
157 #define NS_IN_KHZ 1000000
158
159 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
160 {
161 int result;
162
163 result = (wanted * clk) / NS_IN_KHZ;
164 result++;
165
166 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
167
168 if (result > max) {
169 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
170 return -1;
171 }
172
173 if (result < 1)
174 result = 1;
175
176 return result;
177 }
178
179 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
180
181 /* controller setup */
182
183 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
184 struct platform_device *pdev)
185 {
186 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
187 unsigned long clkrate = clk_get_rate(info->clk);
188 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
189 int tacls, twrph0, twrph1;
190 unsigned long cfg = 0;
191
192 /* calculate the timing information for the controller */
193
194 clkrate /= 1000; /* turn clock into kHz for ease of use */
195
196 if (plat != NULL) {
197 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
198 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
199 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
200 } else {
201 /* default timings */
202 tacls = tacls_max;
203 twrph0 = 8;
204 twrph1 = 8;
205 }
206
207 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
208 dev_err(info->device, "cannot get suitable timings\n");
209 return -EINVAL;
210 }
211
212 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
213 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
214
215 switch (info->cpu_type) {
216 case TYPE_S3C2410:
217 cfg = S3C2410_NFCONF_EN;
218 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
219 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
220 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
221 break;
222
223 case TYPE_S3C2440:
224 case TYPE_S3C2412:
225 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
226 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
227 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
228
229 /* enable the controller and de-assert nFCE */
230
231 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
232 }
233
234 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
235
236 writel(cfg, info->regs + S3C2410_NFCONF);
237 return 0;
238 }
239
240 /* select chip */
241
242 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
243 {
244 struct s3c2410_nand_info *info;
245 struct s3c2410_nand_mtd *nmtd;
246 struct nand_chip *this = mtd->priv;
247 unsigned long cur;
248
249 nmtd = this->priv;
250 info = nmtd->info;
251
252 if (chip != -1 && allow_clk_stop(info))
253 clk_enable(info->clk);
254
255 cur = readl(info->sel_reg);
256
257 if (chip == -1) {
258 cur |= info->sel_bit;
259 } else {
260 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
261 dev_err(info->device, "invalid chip %d\n", chip);
262 return;
263 }
264
265 if (info->platform != NULL) {
266 if (info->platform->select_chip != NULL)
267 (info->platform->select_chip) (nmtd->set, chip);
268 }
269
270 cur &= ~info->sel_bit;
271 }
272
273 writel(cur, info->sel_reg);
274
275 if (chip == -1 && allow_clk_stop(info))
276 clk_disable(info->clk);
277 }
278
279 /* s3c2410_nand_hwcontrol
280 *
281 * Issue command and address cycles to the chip
282 */
283
284 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
285 unsigned int ctrl)
286 {
287 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
288
289 if (cmd == NAND_CMD_NONE)
290 return;
291
292 if (ctrl & NAND_CLE)
293 writeb(cmd, info->regs + S3C2410_NFCMD);
294 else
295 writeb(cmd, info->regs + S3C2410_NFADDR);
296 }
297
298 /* command and control functions */
299
300 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
301 unsigned int ctrl)
302 {
303 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
304
305 if (cmd == NAND_CMD_NONE)
306 return;
307
308 if (ctrl & NAND_CLE)
309 writeb(cmd, info->regs + S3C2440_NFCMD);
310 else
311 writeb(cmd, info->regs + S3C2440_NFADDR);
312 }
313
314 /* s3c2410_nand_devready()
315 *
316 * returns 0 if the nand is busy, 1 if it is ready
317 */
318
319 static int s3c2410_nand_devready(struct mtd_info *mtd)
320 {
321 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
322 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
323 }
324
325 static int s3c2440_nand_devready(struct mtd_info *mtd)
326 {
327 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
328 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
329 }
330
331 static int s3c2412_nand_devready(struct mtd_info *mtd)
332 {
333 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
334 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
335 }
336
337 /* ECC handling functions */
338
339 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
340 u_char *read_ecc, u_char *calc_ecc)
341 {
342 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
343 unsigned int diff0, diff1, diff2;
344 unsigned int bit, byte;
345
346 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
347
348 diff0 = read_ecc[0] ^ calc_ecc[0];
349 diff1 = read_ecc[1] ^ calc_ecc[1];
350 diff2 = read_ecc[2] ^ calc_ecc[2];
351
352 pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
353 __func__,
354 read_ecc[0], read_ecc[1], read_ecc[2],
355 calc_ecc[0], calc_ecc[1], calc_ecc[2],
356 diff0, diff1, diff2);
357
358 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
359 return 0; /* ECC is ok */
360
361 /* Can we correct this ECC (ie, one row and column change).
362 * Note, this is similar to the 256 error code on smartmedia */
363
364 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
365 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
366 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
367 /* calculate the bit position of the error */
368
369 bit = ((diff2 >> 3) & 1) |
370 ((diff2 >> 4) & 2) |
371 ((diff2 >> 5) & 4);
372
373 /* calculate the byte position of the error */
374
375 byte = ((diff2 << 7) & 0x100) |
376 ((diff1 << 0) & 0x80) |
377 ((diff1 << 1) & 0x40) |
378 ((diff1 << 2) & 0x20) |
379 ((diff1 << 3) & 0x10) |
380 ((diff0 >> 4) & 0x08) |
381 ((diff0 >> 3) & 0x04) |
382 ((diff0 >> 2) & 0x02) |
383 ((diff0 >> 1) & 0x01);
384
385 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
386 bit, byte);
387
388 dat[byte] ^= (1 << bit);
389 return 1;
390 }
391
392 /* if there is only one bit difference in the ECC, then
393 * one of only a row or column parity has changed, which
394 * means the error is most probably in the ECC itself */
395
396 diff0 |= (diff1 << 8);
397 diff0 |= (diff2 << 16);
398
399 if ((diff0 & ~(1<<fls(diff0))) == 0)
400 return 1;
401
402 return -1;
403 }
404
405 /* ECC functions
406 *
407 * These allow the s3c2410 and s3c2440 to use the controller's ECC
408 * generator block to ECC the data as it passes through]
409 */
410
411 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
412 {
413 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
414 unsigned long ctrl;
415
416 ctrl = readl(info->regs + S3C2410_NFCONF);
417 ctrl |= S3C2410_NFCONF_INITECC;
418 writel(ctrl, info->regs + S3C2410_NFCONF);
419 }
420
421 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
422 {
423 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
424 unsigned long ctrl;
425
426 ctrl = readl(info->regs + S3C2440_NFCONT);
427 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
428 }
429
430 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
431 {
432 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
433 unsigned long ctrl;
434
435 ctrl = readl(info->regs + S3C2440_NFCONT);
436 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
437 }
438
439 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
440 {
441 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
442
443 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
444 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
445 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
446
447 pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
448 ecc_code[0], ecc_code[1], ecc_code[2]);
449
450 return 0;
451 }
452
453 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
454 {
455 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
456 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
457
458 ecc_code[0] = ecc;
459 ecc_code[1] = ecc >> 8;
460 ecc_code[2] = ecc >> 16;
461
462 pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
463
464 return 0;
465 }
466
467 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
468 {
469 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
470 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
471
472 ecc_code[0] = ecc;
473 ecc_code[1] = ecc >> 8;
474 ecc_code[2] = ecc >> 16;
475
476 pr_debug("%s: returning ecc %06lx\n", __func__, ecc);
477
478 return 0;
479 }
480
481 /* over-ride the standard functions for a little more speed. We can
482 * use read/write block to move the data buffers to/from the controller
483 */
484
485 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
486 {
487 struct nand_chip *this = mtd->priv;
488 readsb(this->IO_ADDR_R, buf, len);
489 }
490
491 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
492 {
493 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
494 readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
495 }
496
497 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
498 {
499 struct nand_chip *this = mtd->priv;
500 writesb(this->IO_ADDR_W, buf, len);
501 }
502
503 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
504 {
505 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
506 writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
507 }
508
509 /* device management functions */
510
511 static int s3c2410_nand_remove(struct platform_device *pdev)
512 {
513 struct s3c2410_nand_info *info = to_nand_info(pdev);
514
515 platform_set_drvdata(pdev, NULL);
516
517 if (info == NULL)
518 return 0;
519
520 /* first thing we need to do is release all our mtds
521 * and their partitions, then go through freeing the
522 * resources used
523 */
524
525 if (info->mtds != NULL) {
526 struct s3c2410_nand_mtd *ptr = info->mtds;
527 int mtdno;
528
529 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
530 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
531 nand_release(&ptr->mtd);
532 }
533
534 kfree(info->mtds);
535 }
536
537 /* free the common resources */
538
539 if (info->clk != NULL && !IS_ERR(info->clk)) {
540 if (!allow_clk_stop(info))
541 clk_disable(info->clk);
542 clk_put(info->clk);
543 }
544
545 if (info->regs != NULL) {
546 iounmap(info->regs);
547 info->regs = NULL;
548 }
549
550 if (info->area != NULL) {
551 release_resource(info->area);
552 kfree(info->area);
553 info->area = NULL;
554 }
555
556 kfree(info);
557
558 return 0;
559 }
560
561 #ifdef CONFIG_MTD_PARTITIONS
562 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
563 struct s3c2410_nand_mtd *mtd,
564 struct s3c2410_nand_set *set)
565 {
566 if (set == NULL)
567 return add_mtd_device(&mtd->mtd);
568
569 if (set->nr_partitions > 0 && set->partitions != NULL) {
570 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
571 }
572
573 return add_mtd_device(&mtd->mtd);
574 }
575 #else
576 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
577 struct s3c2410_nand_mtd *mtd,
578 struct s3c2410_nand_set *set)
579 {
580 return add_mtd_device(&mtd->mtd);
581 }
582 #endif
583
584 /* s3c2410_nand_init_chip
585 *
586 * init a single instance of an chip
587 */
588
589 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
590 struct s3c2410_nand_mtd *nmtd,
591 struct s3c2410_nand_set *set)
592 {
593 struct nand_chip *chip = &nmtd->chip;
594 void __iomem *regs = info->regs;
595
596 chip->write_buf = s3c2410_nand_write_buf;
597 chip->read_buf = s3c2410_nand_read_buf;
598 chip->select_chip = s3c2410_nand_select_chip;
599 chip->chip_delay = 50;
600 chip->priv = nmtd;
601 chip->options = 0;
602 chip->controller = &info->controller;
603
604 switch (info->cpu_type) {
605 case TYPE_S3C2410:
606 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
607 info->sel_reg = regs + S3C2410_NFCONF;
608 info->sel_bit = S3C2410_NFCONF_nFCE;
609 chip->cmd_ctrl = s3c2410_nand_hwcontrol;
610 chip->dev_ready = s3c2410_nand_devready;
611 break;
612
613 case TYPE_S3C2440:
614 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
615 info->sel_reg = regs + S3C2440_NFCONT;
616 info->sel_bit = S3C2440_NFCONT_nFCE;
617 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
618 chip->dev_ready = s3c2440_nand_devready;
619 chip->read_buf = s3c2440_nand_read_buf;
620 chip->write_buf = s3c2440_nand_write_buf;
621 break;
622
623 case TYPE_S3C2412:
624 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
625 info->sel_reg = regs + S3C2440_NFCONT;
626 info->sel_bit = S3C2412_NFCONT_nFCE0;
627 chip->cmd_ctrl = s3c2440_nand_hwcontrol;
628 chip->dev_ready = s3c2412_nand_devready;
629
630 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
631 dev_info(info->device, "System booted from NAND\n");
632
633 break;
634 }
635
636 chip->IO_ADDR_R = chip->IO_ADDR_W;
637
638 nmtd->info = info;
639 nmtd->mtd.priv = chip;
640 nmtd->mtd.owner = THIS_MODULE;
641 nmtd->set = set;
642
643 if (hardware_ecc) {
644 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
645 chip->ecc.correct = s3c2410_nand_correct_data;
646 chip->ecc.mode = NAND_ECC_HW;
647 chip->ecc.size = 512;
648 chip->ecc.bytes = 3;
649 chip->ecc.layout = &nand_hw_eccoob;
650
651 switch (info->cpu_type) {
652 case TYPE_S3C2410:
653 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
654 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
655 break;
656
657 case TYPE_S3C2412:
658 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
659 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
660 break;
661
662 case TYPE_S3C2440:
663 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
664 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
665 break;
666
667 }
668 } else {
669 chip->ecc.mode = NAND_ECC_SOFT;
670 }
671 }
672
673 /* s3c2410_nand_probe
674 *
675 * called by device layer when it finds a device matching
676 * one our driver can handled. This code checks to see if
677 * it can allocate all necessary resources then calls the
678 * nand layer to look for devices
679 */
680
681 static int s3c24xx_nand_probe(struct platform_device *pdev,
682 enum s3c_cpu_type cpu_type)
683 {
684 struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
685 struct s3c2410_nand_info *info;
686 struct s3c2410_nand_mtd *nmtd;
687 struct s3c2410_nand_set *sets;
688 struct resource *res;
689 int err = 0;
690 int size;
691 int nr_sets;
692 int setno;
693
694 pr_debug("s3c2410_nand_probe(%p)\n", pdev);
695
696 info = kmalloc(sizeof(*info), GFP_KERNEL);
697 if (info == NULL) {
698 dev_err(&pdev->dev, "no memory for flash info\n");
699 err = -ENOMEM;
700 goto exit_error;
701 }
702
703 memzero(info, sizeof(*info));
704 platform_set_drvdata(pdev, info);
705
706 spin_lock_init(&info->controller.lock);
707 init_waitqueue_head(&info->controller.wq);
708
709 /* get the clock source and enable it */
710
711 info->clk = clk_get(&pdev->dev, "nand");
712 if (IS_ERR(info->clk)) {
713 dev_err(&pdev->dev, "failed to get clock\n");
714 err = -ENOENT;
715 goto exit_error;
716 }
717
718 clk_enable(info->clk);
719
720 /* allocate and map the resource */
721
722 /* currently we assume we have the one resource */
723 res = pdev->resource;
724 size = res->end - res->start + 1;
725
726 info->area = request_mem_region(res->start, size, pdev->name);
727
728 if (info->area == NULL) {
729 dev_err(&pdev->dev, "cannot reserve register region\n");
730 err = -ENOENT;
731 goto exit_error;
732 }
733
734 info->device = &pdev->dev;
735 info->platform = plat;
736 info->regs = ioremap(res->start, size);
737 info->cpu_type = cpu_type;
738
739 if (info->regs == NULL) {
740 dev_err(&pdev->dev, "cannot reserve register region\n");
741 err = -EIO;
742 goto exit_error;
743 }
744
745 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
746
747 /* initialise the hardware */
748
749 err = s3c2410_nand_inithw(info, pdev);
750 if (err != 0)
751 goto exit_error;
752
753 sets = (plat != NULL) ? plat->sets : NULL;
754 nr_sets = (plat != NULL) ? plat->nr_sets : 1;
755
756 info->mtd_count = nr_sets;
757
758 /* allocate our information */
759
760 size = nr_sets * sizeof(*info->mtds);
761 info->mtds = kmalloc(size, GFP_KERNEL);
762 if (info->mtds == NULL) {
763 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
764 err = -ENOMEM;
765 goto exit_error;
766 }
767
768 memzero(info->mtds, size);
769
770 /* initialise all possible chips */
771
772 nmtd = info->mtds;
773
774 for (setno = 0; setno < nr_sets; setno++, nmtd++) {
775 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
776
777 s3c2410_nand_init_chip(info, nmtd, sets);
778
779 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
780
781 if (nmtd->scan_res == 0) {
782 s3c2410_nand_add_partition(info, nmtd, sets);
783 }
784
785 if (sets != NULL)
786 sets++;
787 }
788
789 if (allow_clk_stop(info)) {
790 dev_info(&pdev->dev, "clock idle support enabled\n");
791 clk_disable(info->clk);
792 }
793
794 pr_debug("initialised ok\n");
795 return 0;
796
797 exit_error:
798 s3c2410_nand_remove(pdev);
799
800 if (err == 0)
801 err = -EINVAL;
802 return err;
803 }
804
805 /* PM Support */
806 #ifdef CONFIG_PM
807
808 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
809 {
810 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
811
812 if (info) {
813 info->save_nfconf = readl(info->regs + S3C2410_NFCONF);
814
815 /* For the moment, we must ensure nFCE is high during
816 * the time we are suspended. This really should be
817 * handled by suspending the MTDs we are using, but
818 * that is currently not the case. */
819
820 writel(info->save_nfconf | info->sel_bit,
821 info->regs + S3C2410_NFCONF);
822
823 if (!allow_clk_stop(info))
824 clk_disable(info->clk);
825 }
826
827 return 0;
828 }
829
830 static int s3c24xx_nand_resume(struct platform_device *dev)
831 {
832 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
833 unsigned long nfconf;
834
835 if (info) {
836 clk_enable(info->clk);
837 s3c2410_nand_inithw(info, dev);
838
839 /* Restore the state of the nFCE line. */
840
841 nfconf = readl(info->regs + S3C2410_NFCONF);
842 nfconf &= ~info->sel_bit;
843 nfconf |= info->save_nfconf & info->sel_bit;
844 writel(nfconf, info->regs + S3C2410_NFCONF);
845
846 if (allow_clk_stop(info))
847 clk_disable(info->clk);
848 }
849
850 return 0;
851 }
852
853 #else
854 #define s3c24xx_nand_suspend NULL
855 #define s3c24xx_nand_resume NULL
856 #endif
857
858 /* driver device registration */
859
860 static int s3c2410_nand_probe(struct platform_device *dev)
861 {
862 return s3c24xx_nand_probe(dev, TYPE_S3C2410);
863 }
864
865 static int s3c2440_nand_probe(struct platform_device *dev)
866 {
867 return s3c24xx_nand_probe(dev, TYPE_S3C2440);
868 }
869
870 static int s3c2412_nand_probe(struct platform_device *dev)
871 {
872 return s3c24xx_nand_probe(dev, TYPE_S3C2412);
873 }
874
875 static struct platform_driver s3c2410_nand_driver = {
876 .probe = s3c2410_nand_probe,
877 .remove = s3c2410_nand_remove,
878 .suspend = s3c24xx_nand_suspend,
879 .resume = s3c24xx_nand_resume,
880 .driver = {
881 .name = "s3c2410-nand",
882 .owner = THIS_MODULE,
883 },
884 };
885
886 static struct platform_driver s3c2440_nand_driver = {
887 .probe = s3c2440_nand_probe,
888 .remove = s3c2410_nand_remove,
889 .suspend = s3c24xx_nand_suspend,
890 .resume = s3c24xx_nand_resume,
891 .driver = {
892 .name = "s3c2440-nand",
893 .owner = THIS_MODULE,
894 },
895 };
896
897 static struct platform_driver s3c2412_nand_driver = {
898 .probe = s3c2412_nand_probe,
899 .remove = s3c2410_nand_remove,
900 .suspend = s3c24xx_nand_suspend,
901 .resume = s3c24xx_nand_resume,
902 .driver = {
903 .name = "s3c2412-nand",
904 .owner = THIS_MODULE,
905 },
906 };
907
908 static int __init s3c2410_nand_init(void)
909 {
910 printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
911
912 platform_driver_register(&s3c2412_nand_driver);
913 platform_driver_register(&s3c2440_nand_driver);
914 return platform_driver_register(&s3c2410_nand_driver);
915 }
916
917 static void __exit s3c2410_nand_exit(void)
918 {
919 platform_driver_unregister(&s3c2412_nand_driver);
920 platform_driver_unregister(&s3c2440_nand_driver);
921 platform_driver_unregister(&s3c2410_nand_driver);
922 }
923
924 module_init(s3c2410_nand_init);
925 module_exit(s3c2410_nand_exit);
926
927 MODULE_LICENSE("GPL");
928 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
929 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
WRT350N Kernel Patches