| blob | ade0fb8fbdb23fa9264174e9b6b2c08a972e42f2 |
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $
41 */
43 #ifdef __linux__
47 #else
48 #include <dev/aic7xxx/aic79xx_osm.h>
49 #include <dev/aic7xxx/aic79xx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
51 #endif
54 /***************************** Lookup Tables **********************************/
56 {
60 "aic7901A"
61 };
64 /*
65 * Hardware error codes.
66 */
70 };
79 };
83 {
94 };
96 /*
97 * In most cases we only wish to itterate over real phases, so
98 * exclude the last element from the count.
99 */
102 /* Our Sequencer Program */
105 /**************************** Function Declarations ***************************/
108 u_int lqistat1);
110 u_int busfreetime);
119 #ifdef AHD_TARGET_MODE
122 #endif
127 role_t role);
147 u_int bus_width);
155 AHDMSG_1B,
156 AHDMSG_2B,
157 AHDMSG_EXT
172 #ifdef AHD_TARGET_MODE
176 #endif
180 static bus_dmamap_callback_t
181 ahd_dmamap_cb;
199 ahd_search_action action,
201 u_int tid);
204 u_int tid_next);
206 u_int scbid);
211 #ifdef AHD_DUMP_SEQ
213 #endif
219 u_int address);
228 #ifdef AHD_TARGET_MODE
231 u_int initiator_id,
232 u_int event_type,
233 u_int event_arg);
235 u_int targid_mask);
238 #endif
245 u_int scbid);
260 u_int timer,
261 u_int maxcmds,
262 u_int mincmds);
269 /******************************** Private Inlines *****************************/
273 {
275 }
277 /*
278 * Determine if the current connection has a packetized
279 * agreement. This does not necessarily mean that we
280 * are currently in a packetized transfer. We could
281 * just as easily be sending or receiving a message.
282 */
285 {
286 ahd_mode_state saved_modes;
291 /*
292 * The packetized bit refers to the last
293 * connection, not the current one. Check
294 * for non-zero LQISTATE instead.
295 */
301 }
304 }
308 {
309 u_int active_fifo;
320 }
321 }
325 {
327 }
329 /*
330 * Determine whether the sequencer reported a residual
331 * for this SCB/transaction.
332 */
335 {
341 }
345 {
351 else
353 }
356 /************************* Sequencer Execution Control ************************/
357 /*
358 * Restart the sequencer program from address zero
359 */
360 static void
362 {
368 /* No more pending messages */
379 /*
380 * Ensure that the sequencer's idea of TQINPOS
381 * matches our own. The sequencer increments TQINPOS
382 * only after it sees a DMA complete and a reset could
383 * occur before the increment leaving the kernel to believe
384 * the command arrived but the sequencer to not.
385 */
388 /* Always allow reselection */
393 /*
394 * Clear any pending sequencer interrupt. It is no
395 * longer relevant since we're resetting the Program
396 * Counter.
397 */
402 }
404 static void
406 {
407 ahd_mode_state saved_modes;
409 #ifdef AHD_DEBUG
412 #endif
421 }
423 /************************* Input/Output Queues ********************************/
424 /*
425 * Flush and completed commands that are sitting in the command
426 * complete queues down on the chip but have yet to be dma'ed back up.
427 */
428 static void
430 {
432 ahd_mode_state saved_modes;
433 u_int saved_scbptr;
434 u_int ccscbctl;
435 u_int scbid;
436 u_int next_scbid;
440 /*
441 * Flush the good status FIFO for completed packetized commands.
442 */
446 u_int fifo_mode;
447 u_int i;
455 }
456 /*
457 * Determine if this transaction is still active in
458 * any FIFO. If it is, we must flush that FIFO to
459 * the host before completing the command.
460 */
462 rescan_fifos:
464 /* Toggle to the other mode. */
473 /*
474 * Running this FIFO may cause a CFG4DATA for
475 * this same transaction to assert in the other
476 * FIFO or a new snapshot SAVEPTRS interrupt
477 * in this FIFO. Even running a FIFO may not
478 * clear the transaction if we are still waiting
479 * for data to drain to the host. We must loop
480 * until the transaction is not active in either
481 * FIFO just to be sure. Reset our loop counter
482 * so we will visit both FIFOs again before
483 * declaring this transaction finished. We
484 * also delay a bit so that status has a chance
485 * to change before we look at this FIFO again.
486 */
489 }
496 u_int comp_head;
498 /*
499 * The transfer completed with a residual.
500 * Place this SCB on the complete DMA list
501 * so that we update our in-core copy of the
502 * SCB before completing the command.
503 */
515 u_int tail;
522 }
525 }
528 /*
529 * Setup for command channel portion of flush.
530 */
533 /*
534 * Wait for any inprogress DMA to complete and clear DMA state
535 * if this if for an SCB in the qinfifo.
536 */
545 }
546 /*
547 * We leave the sequencer to cleanup in the case of DMA's to
548 * update the qoutfifo. In all other cases (DMA's to the
549 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
550 * we disable the DMA engine so that the sequencer will not
551 * attempt to handle the DMA completion.
552 */
556 /*
557 * Complete any SCBs that just finished
558 * being DMA'ed into the qoutfifo.
559 */
563 /*
564 * Manually update/complete any completed SCBs that are waiting to be
565 * DMA'ed back up to the host.
566 */
570 u_int i;
579 }
586 }
600 }
604 }
617 }
621 }
624 /*
625 * Restore state.
626 */
630 }
632 /*
633 * Determine if an SCB for a packetized transaction
634 * is active in a FIFO.
635 */
636 static int
638 {
640 /*
641 * The FIFO is only active for our transaction if
642 * the SCBPTR matches the SCB's ID and the firmware
643 * has installed a handler for the FIFO or we have
644 * a pending SAVEPTRS or CFG4DATA interrupt.
645 */
652 }
654 /*
655 * Run a data fifo to completion for a transaction we know
656 * has completed across the SCSI bus (good status has been
657 * received). We are already set to the correct FIFO mode
658 * on entry to this routine.
659 *
660 * This function attempts to operate exactly as the firmware
661 * would when running this FIFO. Care must be taken to update
662 * this routine any time the firmware's FIFO algorithm is
663 * changed.
664 */
665 static void
667 {
668 u_int seqintsrc;
675 /*
676 * Clear full residual flag.
677 */
681 /*
682 * Load datacnt and address.
683 */
695 /*
696 * Initialize Residual Fields.
697 */
701 /*
702 * Mark the SCB as having a FIFO in use.
703 */
707 /*
708 * Install a "fake" handler for this FIFO.
709 */
712 /*
713 * Notify the hardware that we have satisfied
714 * this sequencer interrupt.
715 */
722 /*
723 * Snapshot Save Pointers. All that
724 * is necessary to clear the snapshot
725 * is a CLRCHN.
726 */
728 }
730 /*
731 * Disable S/G fetch so the DMA engine
732 * is available to future users.
733 */
738 /*
739 * Flush the data FIFO. Strickly only
740 * necessary for Rev A parts.
741 */
744 /*
745 * Calculate residual.
746 */
752 /*
753 * Must back up to the correct S/G element.
754 * Typically this just means resetting our
755 * low byte to the offset in the SG_CACHE,
756 * but if we wrapped, we have to correct
757 * the other bytes of the sgptr too.
758 */
770 }
771 /*
772 * Save Pointers.
773 */
780 /*
781 * If the data is to the SCSI bus, we are
782 * done, otherwise wait for FIFOEMP.
783 */
790 u_int dfcntrl;
792 /*
793 * Disable S/G fetch so the DMA engine
794 * is available to future users. We won't
795 * be using the DMA engine to load segments.
796 */
800 }
802 /*
803 * Wait for the DMA engine to notice that the
804 * host transfer is enabled and that there is
805 * space in the S/G FIFO for new segments before
806 * loading more segments.
807 */
811 /*
812 * Determine the offset of the next S/G
813 * element to load.
814 */
833 }
835 /*
836 * Update residual information.
837 */
841 /*
842 * Load the S/G.
843 */
847 }
852 /*
853 * Advertise the segment to the hardware.
854 */
857 /*
858 * Use SCSIENWRDIS so that SCSIEN
859 * is never modified by this
860 * operation.
861 */
863 }
865 }
868 /*
869 * Transfer completed to the end of SG list
870 * and has flushed to the host.
871 */
876 clrchn:
877 /*
878 * Clear any handler for this FIFO, decrement
879 * the FIFO use count for the SCB, and release
880 * the FIFO.
881 */
886 }
887 }
889 /*
890 * Look for entries in the QoutFIFO that have completed.
891 * The valid_tag completion field indicates the validity
892 * of the entry - the valid value toggles each time through
893 * the queue. We use the sg_status field in the completion
894 * entry to avoid referencing the hscb if the completion
895 * occurred with no errors and no residual. sg_status is
896 * a copy of the first byte (little endian) of the sgptr
897 * hscb field.
898 */
899 void
901 {
904 u_int scb_index;
928 }
933 }
935 }
937 /************************* Interrupt Handling *********************************/
938 void
940 {
941 /*
942 * Some catastrophic hardware error has occurred.
943 * Print it for the user and disable the controller.
944 */
953 }
958 /* Tell everyone that this HBA is no longer available */
961 CAM_NO_HBA);
963 /* Tell the system that this controller has gone away. */
965 }
967 #ifdef AHD_DEBUG
968 static void
970 {
985 i,
991 }
1001 i,
1006 }
1007 }
1008 }
1009 }
1012 void
1014 {
1015 u_int seqintcode;
1017 /*
1018 * Save the sequencer interrupt code and clear the SEQINT
1019 * bit. We will unpause the sequencer, if appropriate,
1020 * after servicing the request.
1021 */
1025 /*
1026 * Unpause the sequencer and let it clear
1027 * SEQINT by writing NO_SEQINT to it. This
1028 * will cause the sequencer to be paused again,
1029 * which is the expected state of this routine.
1030 */
1033 ;
1035 }
1037 #ifdef AHD_DEBUG
1041 #endif
1044 {
1046 u_int scbid;
1053 /*
1054 * Somehow need to know if this
1055 * is from a selection or reselection.
1056 * From that, we can determine target
1057 * ID so we at least have an I_T nexus.
1058 */
1063 }
1066 /*
1067 * Phase change after read stream with
1068 * CRC error with P0 asserted on last
1069 * packet.
1070 */
1071 #ifdef AHD_DEBUG
1075 #endif
1076 }
1077 #ifdef AHD_DEBUG
1080 #endif
1082 }
1087 #ifdef AHD_DEBUG
1090 #endif
1094 {
1096 u_int scbid;
1102 else
1108 }
1110 {
1112 u_int scbid;
1120 }
1127 }
1129 {
1130 u_int bus_phase;
1148 {
1154 u_int scbid;
1156 /*
1157 * If a target takes us into the command phase
1158 * assume that it has been externally reset and
1159 * has thus lost our previous packetized negotiation
1160 * agreement. Since we have not sent an identify
1161 * message and may not have fully qualified the
1162 * connection, we change our command to TUR, assert
1163 * ATN and ABORT the task when we go to message in
1164 * phase. The OSM will see the REQUEUE_REQUEST
1165 * status and retry the command.
1166 */
1175 }
1180 ROLE_INITIATOR);
1192 /* Hand-craft TUR command */
1205 /*
1206 * The lun is 0, regardless of the SCB's lun
1207 * as we have not sent an identify message.
1208 */
1218 /* Notify XPT */
1222 /*
1223 * Allow the sequencer to continue with
1224 * non-pack processing.
1225 */
1230 }
1231 #ifdef AHD_DEBUG
1236 }
1237 #endif
1239 }
1240 }
1242 }
1244 {
1246 u_int scb_index;
1248 #ifdef AHD_DEBUG
1252 }
1253 #endif
1257 /*
1258 * Attempt to transfer to an SCB that is
1259 * not outstanding.
1260 */
1267 /*
1268 * Clear status received flag to prevent any
1269 * attempt to complete this bogus SCB.
1270 */
1274 }
1276 }
1278 {
1281 }
1283 {
1284 #ifdef AHD_DEBUG
1290 }
1291 #endif
1294 }
1296 {
1299 /*
1300 * The sequencer has encountered a message phase
1301 * that requires host assistance for completion.
1302 * While handling the message phase(s), we will be
1303 * notified by the sequencer after each byte is
1304 * transfered so we can track bus phase changes.
1305 *
1306 * If this is the first time we've seen a HOST_MSG_LOOP
1307 * interrupt, initialize the state of the host message
1308 * loop.
1309 */
1313 u_int scb_index;
1314 u_int bus_phase;
1321 /*
1322 * Probably transitioned to bus free before
1323 * we got here. Just punt the message.
1324 */
1329 }
1337 scb);
1340 MSG_TYPE_INITIATOR_MSGIN;
1342 }
1343 }
1344 #ifdef AHD_TARGET_MODE
1348 MSG_TYPE_TARGET_MSGOUT;
1350 }
1351 else
1354 scb);
1355 }
1356 #endif
1357 }
1361 }
1363 {
1364 /* Ensure we don't leave the selection hardware on */
1399 }
1401 {
1404 }
1406 {
1412 }
1414 {
1415 u_int lastphase;
1424 }
1426 {
1427 u_int lastphase;
1437 }
1439 {
1440 /*
1441 * When the sequencer detects an overrun, it
1442 * places the controller in "BITBUCKET" mode
1443 * and allows the target to complete its transfer.
1444 * Unfortunately, none of the counters get updated
1445 * when the controller is in this mode, so we have
1446 * no way of knowing how large the overrun was.
1447 */
1449 u_int scbindex;
1450 #ifdef AHD_DEBUG
1451 u_int lastphase;
1452 #endif
1456 #ifdef AHD_DEBUG
1470 }
1471 #endif
1473 /*
1474 * Set this and it will take effect when the
1475 * target does a command complete.
1476 */
1481 }
1483 {
1486 u_int scbid;
1496 /*
1497 * Ensure that we didn't put a second instance of this
1498 * SCB into the QINFIFO.
1499 */
1504 SEARCH_REMOVE);
1508 }
1510 {
1511 u_int scbid;
1517 u_int lun;
1518 u_int tag;
1519 cam_status error;
1536 error);
1541 {
1547 CAM_BDR_SENT,
1548 lun != CAM_LUN_WILDCARD
1553 }
1557 }
1558 }
1560 }
1562 {
1563 u_int scbid;
1566 /*
1567 * An ABORT TASK TMF failed to be delivered before
1568 * the targeted command completed normally.
1569 */
1573 /*
1574 * Remove the second instance of this SCB from
1575 * the QINFIFO if it is still there.
1576 */
1579 /*
1580 * Handle losing the race. Wait until any
1581 * current selection completes. We will then
1582 * set the TMF back to zero in this SCB so that
1583 * the sequencer doesn't bother to issue another
1584 * sequencer interrupt for its completion.
1585 */
1589 ;
1595 SEARCH_REMOVE);
1596 }
1598 }
1613 seqintcode);
1615 }
1616 /*
1617 * The sequencer is paused immediately on
1618 * a SEQINT, so we should restart it when
1619 * we're done.
1620 */
1622 }
1624 void
1626 {
1628 u_int status0;
1629 u_int status3;
1630 u_int status;
1631 u_int lqistat1;
1632 u_int lqostat0;
1633 u_int scbid;
1634 u_int busfreetime;
1646 /*
1647 * Ignore external resets after a bus reset.
1648 */
1652 }
1654 /*
1655 * Clear bus reset flag
1656 */
1660 u_int simode0;
1666 }
1674 u_int now_lvd;
1680 /*
1681 * A change in I/O mode is equivalent to a bus reset.
1682 */
1698 /* Make sure the sequencer is in a safe location. */
1709 u_int scbid;
1711 /* Stop the selection */
1714 /* Make sure the sequencer is in a safe location. */
1717 /* No more pending messages */
1720 /* Clear interrupt state */
1723 /*
1724 * Although the driver does not care about the
1725 * 'Selection in Progress' status bit, the busy
1726 * LED does. SELINGO is only cleared by a sucessfull
1727 * selection, so we must manually clear it to insure
1728 * the LED turns off just incase no future successful
1729 * selections occur (e.g. no devices on the bus).
1730 */
1742 #ifdef AHD_DEBUG
1746 scbid);
1747 }
1748 #endif
1753 /*
1754 * Cancel any pending transactions on the device
1755 * now that it seems to be missing. This will
1756 * also revert us to async/narrow transfers until
1757 * we can renegotiate with the device.
1758 */
1760 CAM_LUN_WILDCARD,
1761 CAM_SEL_TIMEOUT,
1764 }
1778 /* Make sure the sequencer is in a safe location. */
1783 /*
1784 * This status can be delayed during some
1785 * streaming operations. The SCSIPHASE
1786 * handler has already dealt with this case
1787 * so just clear the error.
1788 */
1792 u_int lqostat1;
1796 u_int mode;
1798 /*
1799 * Clear our selection hardware as soon as possible.
1800 * We may have an entry in the waiting Q for this target,
1801 * that is affected by this busfree and we don't want to
1802 * go about selecting the target while we handle the event.
1803 */
1806 /* Make sure the sequencer is in a safe location. */
1809 /*
1810 * Determine what we were up to at the time of
1811 * the busfree.
1812 */
1819 {
1820 u_int scbid;
1837 }
1850 /*
1851 * Assume packetized if we are not
1852 * on the bus in a non-packetized
1853 * capacity and any pending selection
1854 * was a packetized selection.
1855 */
1858 }
1860 #ifdef AHD_DEBUG
1863 busfreetime);
1864 #endif
1865 /*
1866 * Busfrees that occur in non-packetized phases are
1867 * handled by the nonpkt_busfree handler.
1868 */
1874 }
1875 /*
1876 * Clear the busfree interrupt status. The setting of
1877 * the interrupt is a pulse, so in a perfect world, we
1878 * would not need to muck with the ENBUSFREE logic. This
1879 * would ensure that if the bus moves on to another
1880 * connection, busfree protection is still in force. If
1881 * BUSFREEREV is broken, however, we must manually clear
1882 * the ENBUSFREE if the busfree occurred during a non-pack
1883 * connection so that we don't get false positives during
1884 * future, packetized, connections.
1885 */
1901 }
1908 }
1909 }
1911 static void
1913 {
1915 u_int scbid;
1916 u_int lqistat1;
1917 u_int lqistat2;
1918 u_int msg_out;
1919 u_int curphase;
1920 u_int lastphase;
1921 u_int perrdiag;
1922 u_int cur_col;
1931 u_int lqistate;
1937 #ifdef AHD_DEBUG
1941 }
1942 #endif
1944 }
1946 }
1955 /*
1956 * Try to find the SCB associated with this error.
1957 */
1967 }
1978 }
1985 }
1989 /*
1990 * A CRC error has been detected on an incoming LQ.
1991 * The bus is currently hung on the last ACK.
1992 * Hit LQIRETRY to release the last ack, and
1993 * wait for the sequencer to determine that ATNO
1994 * is asserted while in message out to take us
1995 * to our host message loop. No NONPACKREQ or
1996 * LQIPHASE type errors will occur in this
1997 * scenario. After this first LQIRETRY, the LQI
1998 * manager will be in ISELO where it will
1999 * happily sit until another packet phase begins.
2000 * Unexpected bus free detection is enabled
2001 * through any phases that occur after we release
2002 * this last ack until the LQI manager sees a
2003 * packet phase. This implies we may have to
2004 * ignore a perfectly valid "unexected busfree"
2005 * after our "initiator detected error" message is
2006 * sent. A busfree is the expected response after
2007 * we tell the target that it's L_Q was corrupted.
2008 * (SPI4R09 10.7.3.3.3)
2009 */
2013 /*
2014 * We detected a CRC error in a NON-LQ packet.
2015 * The hardware has varying behavior in this situation
2016 * depending on whether this packet was part of a
2017 * stream or not.
2018 *
2019 * PKT by PKT mode:
2020 * The hardware has already acked the complete packet.
2021 * If the target honors our outstanding ATN condition,
2022 * we should be (or soon will be) in MSGOUT phase.
2023 * This will trigger the LQIPHASE_LQ status bit as the
2024 * hardware was expecting another LQ. Unexpected
2025 * busfree detection is enabled. Once LQIPHASE_LQ is
2026 * true (first entry into host message loop is much
2027 * the same), we must clear LQIPHASE_LQ and hit
2028 * LQIRETRY so the hardware is ready to handle
2029 * a future LQ. NONPACKREQ will not be asserted again
2030 * once we hit LQIRETRY until another packet is
2031 * processed. The target may either go busfree
2032 * or start another packet in response to our message.
2033 *
2034 * Read Streaming P0 asserted:
2035 * If we raise ATN and the target completes the entire
2036 * stream (P0 asserted during the last packet), the
2037 * hardware will ack all data and return to the ISTART
2038 * state. When the target reponds to our ATN condition,
2039 * LQIPHASE_LQ will be asserted. We should respond to
2040 * this with an LQIRETRY to prepare for any future
2041 * packets. NONPACKREQ will not be asserted again
2042 * once we hit LQIRETRY until another packet is
2043 * processed. The target may either go busfree or
2044 * start another packet in response to our message.
2045 * Busfree detection is enabled.
2046 *
2047 * Read Streaming P0 not asserted:
2048 * If we raise ATN and the target transitions to
2049 * MSGOUT in or after a packet where P0 is not
2050 * asserted, the hardware will assert LQIPHASE_NLQ.
2051 * We should respond to the LQIPHASE_NLQ with an
2052 * LQIRETRY. Should the target stay in a non-pkt
2053 * phase after we send our message, the hardware
2054 * will assert LQIPHASE_LQ. Recovery is then just as
2055 * listed above for the read streaming with P0 asserted.
2056 * Busfree detection is enabled.
2057 */
2065 }
2072 /* Ack the byte. So we can continue. */
2077 }
2081 }
2083 /*
2084 * We've set the hardware to assert ATN if we
2085 * get a parity error on "in" phases, so all we
2086 * need to do is stuff the message buffer with
2087 * the appropriate message. "In" phases have set
2088 * mesg_out to something other than MSG_NOP.
2089 */
2096 }
2098 static void
2100 {
2101 /*
2102 * Clear the sources of the interrupts.
2103 */
2107 /*
2108 * If the "illegal" phase changes were in response
2109 * to our ATN to flag a CRC error, AND we ended up
2110 * on packet boundaries, clear the error, restart the
2111 * LQI manager as appropriate, and go on our merry
2112 * way toward sending the message. Otherwise, reset
2113 * the bus to clear the error.
2114 */
2133 }
2134 }
2136 /*
2137 * Packetized unexpected or expected busfree.
2138 * Entered in mode based on busfreetime.
2139 */
2140 static int
2142 {
2143 u_int lqostat1;
2150 u_int scbid;
2151 u_int saved_scbptr;
2152 u_int waiting_h;
2153 u_int waiting_t;
2154 u_int next;
2156 /*
2157 * The LQO manager detected an unexpected busfree
2158 * either:
2159 *
2160 * 1) During an outgoing LQ.
2161 * 2) After an outgoing LQ but before the first
2162 * REQ of the command packet.
2163 * 3) During an outgoing command packet.
2164 *
2165 * In all cases, CURRSCB is pointing to the
2166 * SCB that encountered the failure. Clean
2167 * up the queue, clear SELDO and LQOBUSFREE,
2168 * and allow the sequencer to restart the select
2169 * out at its lesure.
2170 */
2176 /*
2177 * Clear the status.
2178 */
2186 /*
2187 * Return the LQO manager to its idle loop. It will
2188 * not do this automatically if the busfree occurs
2189 * after the first REQ of either the LQ or command
2190 * packet or between the LQ and command packet.
2191 */
2194 /*
2195 * Update the waiting for selection queue so
2196 * we restart on the correct SCB.
2197 */
2210 }
2213 }
2220 }
2226 }
2227 /* Return unpausing the sequencer. */
2230 /*
2231 * Ignore what are really parity errors that
2232 * occur on the last REQ of a free running
2233 * clock prior to going busfree. Some drives
2234 * do not properly active negate just before
2235 * going busfree resulting in a parity glitch.
2236 */
2238 #ifdef AHD_DEBUG
2243 #endif
2244 /* Return unpausing the sequencer. */
2246 }
2248 u_int scbid;
2260 /* Return restarting the sequencer. */
2262 }
2265 /* Restart the sequencer. */
2267 }
2269 /*
2270 * Non-packetized unexpected or expected busfree.
2271 */
2272 static int
2274 {
2277 u_int lastphase;
2278 u_int saved_scsiid;
2279 u_int saved_lun;
2280 u_int target;
2281 u_int initiator_role_id;
2282 u_int scbid;
2283 u_int ppr_busfree;
2286 /*
2287 * Look at what phase we were last in. If its message out,
2288 * chances are pretty good that the busfree was in response
2289 * to one of our abort requests.
2290 */
2308 u_int tag;
2320 /* restart the sequencer. */
2322 }
2333 /*
2334 * This abort is in response to an
2335 * unexpected switch to command phase
2336 * for a packetized connection. Since
2337 * the identify message was never sent,
2338 * "saved lun" is 0. We really want to
2339 * abort only the SCB that encountered
2340 * this error, which could have a different
2341 * lun. The SCB will be retried so the OS
2342 * will see the UA after renegotiating to
2343 * packetized.
2344 */
2347 }
2350 CAM_REQ_ABORTED);
2355 #ifdef __FreeBSD__
2356 /*
2357 * Don't mark the user's request for this BDR
2358 * as completing with CAM_BDR_SENT. CAM3
2359 * specifies CAM_REQ_CMP.
2360 */
2365 ROLE_INITIATOR))
2367 #endif
2377 /*
2378 * PPR Rejected.
2379 *
2380 * If the previous negotiation was packetized,
2381 * this could be because the device has been
2382 * reset without our knowledge. Force our
2383 * current negotiation to async and retry the
2384 * negotiation. Otherwise retry the command
2385 * with non-ppr negotiation.
2386 */
2387 #ifdef AHD_DEBUG
2390 #endif
2396 MSG_EXT_WDTR_BUS_8_BIT,
2397 AHD_TRANS_CUR,
2402 AHD_TRANS_CUR,
2404 /*
2405 * The expect PPR busfree handler below
2406 * will effect the retry and necessary
2407 * abort.
2408 */
2413 /*
2414 * Remove any SCBs in the waiting for selection
2415 * queue that may also be for this target so
2416 * that command ordering is preserved.
2417 */
2421 }
2424 /*
2425 * Negotiation Rejected. Go-narrow and
2426 * retry command.
2427 */
2428 #ifdef AHD_DEBUG
2431 #endif
2433 MSG_EXT_WDTR_BUS_8_BIT,
2436 /*
2437 * Remove any SCBs in the waiting for selection
2438 * queue that may also be for this target so that
2439 * command ordering is preserved.
2440 */
2446 /*
2447 * Negotiation Rejected. Go-async and
2448 * retry command.
2449 */
2450 #ifdef AHD_DEBUG
2453 #endif
2459 /*
2460 * Remove any SCBs in the waiting for selection
2461 * queue that may also be for this target so that
2462 * command ordering is preserved.
2463 */
2471 #ifdef AHD_DEBUG
2474 #endif
2480 #ifdef AHD_DEBUG
2483 #endif
2485 }
2486 }
2488 /*
2489 * The busfree required flag is honored at the end of
2490 * the message phases. We check it last in case we
2491 * had to send some other message that caused a busfree.
2492 */
2506 #ifdef AHD_DEBUG
2509 #endif
2511 }
2513 }
2519 u_int tag;
2523 else
2528 ROLE_INITIATOR,
2529 CAM_UNEXP_BUSFREE);
2531 /*
2532 * We had not fully identified this connection,
2533 * so we cannot abort anything.
2534 */
2536 }
2540 aborted,
2545 }
2546 /* Always restart the sequencer. */
2548 }
2550 static void
2552 {
2555 u_int scbid;
2556 u_int seq_flags;
2557 u_int curphase;
2558 u_int lastphase;
2569 /*
2570 * The reconnecting target either did not send an
2571 * identify message, or did, but we didn't find an SCB
2572 * to match.
2573 */
2579 /*
2580 * We don't seem to have an SCB active for this
2581 * transaction. Print an error and reset the bus.
2582 */
2593 /*
2594 * The target never bothered to provide status to
2595 * us prior to completing the command. Since we don't
2596 * know the disposition of this command, we must attempt
2597 * to abort it. Assert ATN and prepare to send an abort
2598 * message.
2599 */
2606 }
2607 }
2610 proto_violation_reset:
2611 /*
2612 * Target either went directly to data
2613 * phase or didn't respond to our ATN.
2614 * The only safe thing to do is to blow
2615 * it away with a bus reset.
2616 */
2621 /*
2622 * Leave the selection hardware off in case
2623 * this abort attempt will affect yet to
2624 * be sent commands.
2625 */
2639 }
2642 }
2643 }
2645 /*
2646 * Force renegotiation to occur the next time we initiate
2647 * a command to the current device.
2648 */
2649 static void
2651 {
2655 #ifdef AHD_DEBUG
2659 }
2660 #endif
2668 }
2670 #define AHD_MAX_STEPS 2000
2671 static void
2673 {
2674 ahd_mode_state saved_modes;
2678 u_int simode0;
2679 u_int simode1;
2680 u_int simode3;
2681 u_int lqimode0;
2682 u_int lqimode1;
2683 u_int lqomode0;
2684 u_int lqomode1;
2702 u_int seqaddr;
2703 u_int i;
2713 }
2722 seqaddr);
2725 }
2727 steps++;
2728 #ifdef AHD_DEBUG
2731 seqaddr);
2732 #endif
2751 /*
2752 * We don't clear ENBUSFREE. Unfortunately
2753 * we cannot re-enable busfree detection within
2754 * the current connection, so we must leave it
2755 * on while single stepping.
2756 */
2760 }
2768 }
2780 /*
2781 * SCSIINT seems to glitch occassionally when
2782 * the interrupt masks are restored. Clear SCSIINT
2783 * one more time so that only persistent errors
2784 * are seen as a real interrupt.
2785 */
2787 }
2789 }
2791 /*
2792 * Clear any pending interrupt status.
2793 */
2794 static void
2796 {
2799 /* Clear any interrupt conditions this may have caused */
2812 }
2819 }
2821 /**************************** Debugging Routines ******************************/
2822 #ifdef AHD_DEBUG
2824 #endif
2826 #if 0
2827 void
2829 {
2850 }
2853 /************************* Transfer Negotiation *******************************/
2854 /*
2855 * Allocate per target mode instance (ID we respond to as a target)
2856 * transfer negotiation data structures.
2857 */
2860 {
2874 /*
2875 * If we have allocated a master tstate, copy user settings from
2876 * the master tstate (taken from SRAM or the EEPROM) for this
2877 * channel, but reset our current and goal settings to async/narrow
2878 * until an initiator talks to us.
2879 */
2888 }
2893 }
2895 #ifdef AHD_TARGET_MODE
2896 /*
2897 * Free per target mode instance (ID we respond to as a target)
2898 * transfer negotiation data structures.
2899 */
2900 static void
2902 {
2905 /*
2906 * Don't clean up our "master" tstate.
2907 * It has our default user settings.
2908 */
2917 }
2918 #endif
2920 /*
2921 * Called when we have an active connection to a target on the bus,
2922 * this function finds the nearest period to the input period limited
2923 * by the capabilities of the bus connectivity of and sync settings for
2924 * the target.
2925 */
2926 void
2930 {
2932 u_int maxsync;
2939 /* Can't do DT related options on an SE bus */
2941 }
2942 /*
2943 * Never allow a value higher than our current goal
2944 * period otherwise we may allow a target initiated
2945 * negotiation to go above the limit as set by the
2946 * user. In the case of an initiator initiated
2947 * sync negotiation, we limit based on the user
2948 * setting. This allows the system to still accept
2949 * incoming negotiations even if target initiated
2950 * negotiation is not performed.
2951 */
2954 else
2960 }
2967 }
2968 }
2970 /*
2971 * Look up the valid period to SCSIRATE conversion in our table.
2972 * Return the period and offset that should be sent to the target
2973 * if this was the beginning of an SDTR.
2974 */
2975 void
2978 {
2989 /* Honor PPR option conformance rules. */
2999 /* Skip all PACED only entries if IU is not available */
3004 /* Skip all DT only entries if DT is not available */
3008 }
3010 /*
3011 * Truncate the given synchronous offset to a value the
3012 * current adapter type and syncrate are capable of.
3013 */
3014 static void
3018 role_t role)
3019 {
3020 u_int maxoffset;
3022 /* Limit offset to what we can do */
3028 else
3036 else
3038 }
3039 }
3041 /*
3042 * Truncate the given transfer width parameter to a value the
3043 * current adapter type is capable of.
3044 */
3045 static void
3048 {
3052 /* Respond Wide */
3055 }
3056 /* FALLTHROUGH */
3060 }
3064 else
3066 }
3067 }
3069 /*
3070 * Update the bitmask of targets for which the controller should
3071 * negotiate with at the next convenient oportunity. This currently
3072 * means the next time we send the initial identify messages for
3073 * a new transaction.
3074 */
3075 int
3079 {
3080 u_int auto_negotiate_orig;
3084 /*
3085 * Force our "current" settings to be
3086 * unknown so that unless a bus reset
3087 * occurs the need to renegotiate is
3088 * recorded persistently.
3089 */
3094 }
3104 else
3108 }
3110 /*
3111 * Update the user/goal/curr tables of synchronous negotiation
3112 * parameters as well as, in the case of a current or active update,
3113 * any data structures on the host controller. In the case of an
3114 * active update, the specified target is currently talking to us on
3115 * the bus, so the transfer parameter update must take effect
3116 * immediately.
3117 */
3118 void
3122 {
3125 u_int old_period;
3126 u_int old_offset;
3127 u_int old_ppr;
3137 }
3146 }
3152 }
3163 update_needed++;
3182 options++;
3183 }
3186 options++;
3187 }
3190 options++;
3191 }
3194 options++;
3195 }
3198 options++;
3199 }
3202 else
3210 }
3211 }
3212 }
3213 /*
3214 * Always refresh the neg-table to handle the case of the
3215 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3216 * We will always renegotiate in that case if this is a
3217 * packetized request. Also manage the busfree expected flag
3218 * from this common routine so that we catch changes due to
3219 * WDTR or SDTR messages.
3220 */
3230 #ifdef AHD_DEBUG
3234 }
3235 #endif
3238 }
3240 #ifdef AHD_DEBUG
3243 #endif
3245 }
3246 }
3247 }
3254 }
3256 /*
3257 * Update the user/goal/curr tables of wide negotiation
3258 * parameters as well as, in the case of a current or active update,
3259 * any data structures on the host controller. In the case of an
3260 * active update, the specified target is currently talking to us on
3261 * the bus, so the transfer parameter update must take effect
3262 * immediately.
3263 */
3264 void
3267 {
3270 u_int oldwidth;
3288 update_needed++;
3297 }
3298 }
3306 }
3313 }
3315 /*
3316 * Update the current state of tagged queuing for a given target.
3317 */
3318 static void
3321 {
3327 }
3329 static void
3332 {
3333 ahd_mode_state saved_modes;
3334 u_int period;
3335 u_int ppr_opts;
3336 u_int con_opts;
3337 u_int offset;
3338 u_int saved_negoaddr;
3357 /*
3358 * When the SPI4 spec was finalized, PACE transfers
3359 * was not made a configurable option in the PPR
3360 * message. Instead it is assumed to be enabled for
3361 * any syncrate faster than 80MHz. Nevertheless,
3362 * Harpoon2A4 allows this to be configurable.
3363 *
3364 * Harpoon2A4 also assumes at most 2 data bytes per
3365 * negotiated REQ/ACK offset. Paced transfers take
3366 * 4, so we must adjust our offset.
3367 */
3371 /*
3372 * Harpoon2A assumed that there would be a
3373 * fallback rate between 160MHz and 80Mhz,
3374 * so 7 is used as the period factor rather
3375 * than 8 for 160MHz.
3376 */
3378 }
3383 /*
3384 * Precomp should be disabled for non-paced transfers.
3385 */
3391 /*
3392 * Slow down our CRC interval to be
3393 * compatible with non-packetized
3394 * U160 devices that can't handle a
3395 * CRC at full speed.
3396 */
3398 }
3401 /*
3402 * On H2A4, revert to a slower slewrate
3403 * on non-paced transfers.
3404 */
3407 }
3408 }
3422 /*
3423 * Slow down our CRC interval to be
3424 * compatible with packetized U320 devices
3425 * that can't handle a CRC at full speed
3426 */
3429 }
3431 /*
3432 * During packetized transfers, the target will
3433 * give us the oportunity to send command packets
3434 * without us asserting attention.
3435 */
3441 }
3443 /*
3444 * When the transfer settings for a connection change, setup for
3445 * negotiation in pending SCBs to effect the change as quickly as
3446 * possible. We also cancel any negotiations that are scheduled
3447 * for inflight SCBs that have not been started yet.
3448 */
3449 static void
3451 {
3455 u_int saved_scbptr;
3456 ahd_mode_state saved_modes;
3458 /*
3459 * Traverse the pending SCB list and ensure that all of the
3460 * SCBs there have the proper settings. We can only safely
3461 * clear the negotiation required flag (setting requires the
3462 * execution queue to be modified) and this is only possible
3463 * if we are not already attempting to select out for this
3464 * SCB. For this reason, all callers only call this routine
3465 * if we are changing the negotiation settings for the currently
3466 * active transaction on the bus.
3467 */
3482 }
3485 pending_scb_count++;
3486 }
3496 }
3498 /*
3499 * Force the sequencer to reinitialize the selection for
3500 * the command at the head of the execution queue if it
3501 * has already been setup. The negotiation changes may
3502 * effect whether we select-out with ATN. It is only
3503 * safe to clear ENSELO when the bus is not free and no
3504 * selection is in progres or completed.
3505 */
3512 /* Ensure that the hscbs down on the card match the new information */
3514 u_int scb_tag;
3515 u_int control;
3523 }
3529 }
3531 /**************************** Pathing Information *****************************/
3532 static void
3534 {
3535 ahd_mode_state saved_modes;
3536 u_int saved_scsiid;
3537 role_t role;
3545 else
3550 /* We were selected, so pull our id from TARGIDIN */
3554 else
3559 our_id,
3563 role);
3565 }
3567 void
3569 {
3572 }
3576 {
3580 /*
3581 * num_phases doesn't include the default entry which
3582 * will be returned if the phase doesn't match.
3583 */
3588 }
3590 }
3592 void
3595 {
3605 }
3607 static void
3610 {
3611 role_t role;
3620 }
3623 /************************ Message Phase Processing ****************************/
3624 /*
3625 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3626 * or enters the initial message out phase, we are interrupted. Fill our
3627 * outgoing message buffer with the appropriate message and beging handing
3628 * the message phase(s) manually.
3629 */
3630 static void
3633 {
3634 /*
3635 * To facilitate adding multiple messages together,
3636 * each routine should increment the index and len
3637 * variables instead of setting them explicitly.
3638 */
3650 #ifdef AHD_DEBUG
3653 #endif
3662 }
3667 u_int identify_msg;
3680 }
3681 }
3688 /*
3689 * Clear our selection hardware in advance of
3690 * the busfree. We may have an entry in the waiting
3691 * Q for this target, and we don't want to go about
3692 * selecting while we handle the busfree and blow it
3693 * away.
3694 */
3702 }
3707 /*
3708 * Clear our selection hardware in advance of
3709 * the busfree. We may have an entry in the waiting
3710 * Q for this target, and we don't want to go about
3711 * selecting while we handle the busfree and blow it
3712 * away.
3713 */
3717 /*
3718 * Clear our selection hardware in advance of potential
3719 * PPR IU status change busfree. We may have an entry in
3720 * the waiting Q for this target, and we don't want to go
3721 * about selecting while we handle the busfree and blow
3722 * it away.
3723 */
3734 }
3736 /*
3737 * Clear the MK_MESSAGE flag from the SCB so we aren't
3738 * asked to send this message again.
3739 */
3745 }
3747 /*
3748 * Build an appropriate transfer negotiation message for the
3749 * currently active target.
3750 */
3751 static void
3753 {
3754 /*
3755 * We need to initiate transfer negotiations.
3756 * If our current and goal settings are identical,
3757 * we want to renegotiate due to a check condition.
3758 */
3764 u_int period;
3765 u_int ppr_options;
3766 u_int offset;
3770 /*
3771 * Filter our period based on the current connection.
3772 * If we can't perform DT transfers on this segment (not in LVD
3773 * mode for instance), then our decision to issue a PPR message
3774 * may change.
3775 */
3779 /* Target initiated PPR is not allowed in the SCSI spec */
3786 /*
3787 * Only use PPR if we have options that need it, even if the device
3788 * claims to support it. There might be an expander in the way
3789 * that doesn't.
3790 */
3796 }
3799 /*
3800 * Force async with a WDTR message if we have a wide bus,
3801 * or just issue an SDTR with a 0 offset.
3802 */
3805 else
3811 }
3812 }
3813 /* Target initiated PPR is not allowed in the SCSI spec */
3817 /*
3818 * Both the PPR message and SDTR message require the
3819 * goal syncrate to be limited to what the target device
3820 * is capable of handling (based on whether an LVD->SE
3821 * expander is on the bus), so combine these two cases.
3822 * Regardless, guarantee that if we are using WDTR and SDTR
3823 * messages that WDTR comes first.
3824 */
3837 }
3840 }
3841 }
3843 /*
3844 * Build a synchronous negotiation message in our message
3845 * buffer based on the input parameters.
3846 */
3847 static void
3850 {
3860 }
3861 }
3863 /*
3864 * Build a wide negotiateion message in our message
3865 * buffer based on the input parameters.
3866 */
3867 static void
3869 u_int bus_width)
3870 {
3878 }
3879 }
3881 /*
3882 * Build a parallel protocol request message in our message
3883 * buffer based on the input parameters.
3884 */
3885 static void
3888 u_int ppr_options)
3889 {
3890 /*
3891 * Always request precompensation from
3892 * the other target if we are running
3893 * at paced syncrates.
3894 */
3908 }
3909 }
3911 /*
3912 * Clear any active message state.
3913 */
3914 static void
3916 {
3917 ahd_mode_state saved_modes;
3927 /*
3928 * The target didn't care to respond to our
3929 * message request, so clear ATN.
3930 */
3932 }
3937 }
3939 /*
3940 * Manual message loop handler.
3941 */
3942 static void
3944 {
3946 u_int bus_phase;
3956 }
3957 reswitch:
3960 {
3968 #ifdef AHD_DEBUG
3972 }
3973 #endif
3976 #ifdef AHD_DEBUG
3981 }
3982 #endif
3984 /*
3985 * Change gears and see if
3986 * this messages is of interest to
3987 * us or should be passed back to
3988 * the sequencer.
3989 */
3995 }
3998 }
4003 #ifdef AHD_DEBUG
4006 #endif
4007 /*
4008 * If we are notifying the target of a CRC error
4009 * during packetized operations, the target is
4010 * within its rights to acknowledge our message
4011 * with a busfree.
4012 */
4020 }
4024 /*
4025 * The target has requested a retry.
4026 * Re-assert ATN, reset our message index to
4027 * 0, and try again.
4028 */
4031 }
4035 /* Last byte is signified by dropping ATN */
4037 }
4039 /*
4040 * Clear our interrupt status and present
4041 * the next byte on the bus.
4042 */
4044 #ifdef AHD_DEBUG
4048 #endif
4052 }
4054 {
4058 #ifdef AHD_DEBUG
4062 }
4063 #endif
4066 #ifdef AHD_DEBUG
4071 }
4072 #endif
4080 }
4083 }
4085 /* Pull the byte in without acking it */
4087 #ifdef AHD_DEBUG
4091 #endif
4096 /*
4097 * Clear our incoming message buffer in case there
4098 * is another message following this one.
4099 */
4102 /*
4103 * If this message illicited a response,
4104 * assert ATN so the target takes us to the
4105 * message out phase.
4106 */
4108 #ifdef AHD_DEBUG
4112 }
4113 #endif
4115 }
4122 /* Ack the byte */
4125 }
4127 }
4129 {
4133 /*
4134 * By default, the message loop will continue.
4135 */
4141 /*
4142 * If we interrupted a mesgout session, the initiator
4143 * will not know this until our first REQ. So, we
4144 * only honor mesgout requests after we've sent our
4145 * first byte.
4146 */
4150 else
4155 /*
4156 * Change gears and see if
4157 * this messages is of interest to
4158 * us or should be passed back to
4159 * the sequencer.
4160 */
4164 /* Dummy read to REQ for first byte */
4169 }
4177 }
4179 /*
4180 * Present the next byte on the bus.
4181 */
4185 }
4187 {
4191 /*
4192 * By default, the message loop will continue.
4193 */
4196 /*
4197 * The initiator signals that this is
4198 * the last byte by dropping ATN.
4199 */
4202 /*
4203 * Read the latched byte, but turn off SPIOEN first
4204 * so that we don't inadvertently cause a REQ for the
4205 * next byte.
4206 */
4211 /*
4212 * The message is *really* done in that it caused
4213 * us to go to bus free. The sequencer has already
4214 * been reset at this point, so pull the ejection
4215 * handle.
4216 */
4218 }
4222 /*
4223 * XXX Read spec about initiator dropping ATN too soon
4224 * and use msgdone to detect it.
4225 */
4229 /*
4230 * If this message illicited a response, transition
4231 * to the Message in phase and send it.
4232 */
4240 }
4241 }
4246 /* Ask for the next byte. */
4249 }
4252 }
4255 }
4263 /*
4264 * Perform the equivalent of a clear_target_state.
4265 */
4272 }
4273 }
4274 }
4276 /*
4277 * See if we sent a particular extended message to the target.
4278 * If "full" is true, return true only if the target saw the full
4279 * message. If "full" is false, return true if the target saw at
4280 * least the first byte of the message.
4281 */
4282 static int
4284 {
4286 u_int index;
4293 u_int end_index;
4304 }
4309 /* Skip tag type and tag id or residue param*/
4312 /* Single byte message */
4319 index++;
4320 }
4324 }
4326 }
4328 /*
4329 * Wait for a complete incoming message, parse it, and respond accordingly.
4330 */
4331 static int
4333 {
4346 /*
4347 * Parse as much of the message as is available,
4348 * rejecting it if we don't support it. When
4349 * the entire message is available and has been
4350 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4351 * that we have parsed an entire message.
4352 *
4353 * In the case of extended messages, we accept the length
4354 * byte outright and perform more checking once we know the
4355 * extended message type.
4356 */
4363 /*
4364 * End our message loop as these are messages
4365 * the sequencer handles on its own.
4366 */
4371 /* FALLTHROUGH */
4376 {
4377 /* Wait for enough of the message to begin validation */
4382 {
4383 u_int period;
4384 u_int ppr_options;
4385 u_int offset;
4386 u_int saved_offset;
4391 }
4393 /*
4394 * Wait until we have both args before validating
4395 * and acting on this message.
4396 *
4397 * Add one to MSG_EXT_SDTR_LEN to account for
4398 * the extended message preamble.
4399 */
4418 }
4424 /*
4425 * See if we initiated Sync Negotiation
4426 * and didn't have to fall down to async
4427 * transfers.
4428 */
4430 /* We started it */
4432 /* Went too low - force async */
4434 }
4436 /*
4437 * Send our own SDTR in reply
4438 */
4445 }
4452 }
4455 }
4457 {
4458 u_int bus_width;
4459 u_int saved_width;
4460 u_int sending_reply;
4466 }
4468 /*
4469 * Wait until we have our arg before validating
4470 * and acting on this message.
4471 *
4472 * Add one to MSG_EXT_WDTR_LEN to account for
4473 * the extended message preamble.
4474 */
4488 }
4491 /*
4492 * Don't send a WDTR back to the
4493 * target, since we asked first.
4494 * If the width went higher than our
4495 * request, reject it.
4496 */
4505 }
4507 /*
4508 * Send our own WDTR in reply
4509 */
4516 }
4523 }
4524 /*
4525 * After a wide message, we are async, but
4526 * some devices don't seem to honor this portion
4527 * of the spec. Force a renegotiation of the
4528 * sync component of our transfer agreement even
4529 * if our goal is async. By updating our width
4530 * after forcing the negotiation, we avoid
4531 * renegotiating for width.
4532 */
4540 /*
4541 * We will always have an SDTR to send.
4542 */
4548 }
4551 }
4553 {
4554 u_int period;
4555 u_int offset;
4556 u_int bus_width;
4557 u_int ppr_options;
4558 u_int saved_width;
4559 u_int saved_offset;
4560 u_int saved_ppr_options;
4565 }
4567 /*
4568 * Wait until we have all args before validating
4569 * and acting on this message.
4570 *
4571 * Add one to MSG_EXT_PPR_LEN to account for
4572 * the extended message preamble.
4573 */
4582 /*
4583 * According to the spec, a DT only
4584 * period factor with no DT option
4585 * set implies async.
4586 */
4593 /*
4594 * Transfer options are only available if we
4595 * are negotiating wide.
4596 */
4608 /*
4609 * If we are unable to do any of the
4610 * requested options (we went too low),
4611 * then we'll have to reject the message.
4612 */
4621 }
4628 else
4639 }
4650 }
4661 }
4663 /* Unknown extended message. Reject it. */
4666 }
4668 }
4669 #ifdef AHD_TARGET_MODE
4672 CAM_BDR_SENT,
4681 {
4684 /* Target mode messages */
4688 }
4694 CAM_REQ_ABORTED);
4707 }
4708 }
4712 }
4713 #endif
4715 #ifdef AHD_DEBUG
4719 #endif
4721 /* FALLTHROUGH */
4726 }
4729 /*
4730 * Setup to reject the message.
4731 */
4737 }
4740 /* Clear the outgoing message buffer */
4744 }
4746 /*
4747 * Process a message reject message.
4748 */
4749 static int
4751 {
4752 /*
4753 * What we care about here is if we had an
4754 * outstanding SDTR or WDTR message for this
4755 * target. If we did, this is a signal that
4756 * the target is refusing negotiation.
4757 */
4761 u_int scb_index;
4762 u_int last_msg;
4770 /* Might be necessary */
4776 /*
4777 * Target may not like our SPI-4 PPR Options.
4778 * Attempt to negotiate 80MHz which will turn
4779 * off these options.
4780 */
4786 }
4789 | MSG_EXT_PPR_QAS_REQ
4792 /*
4793 * Target does not support the PPR message.
4794 * Attempt to negotiate SPI-2 style.
4795 */
4801 }
4805 }
4813 /* note 8bit xfers */
4820 /*
4821 * No need to clear the sync rate. If the target
4822 * did not accept the command, our syncrate is
4823 * unaffected. If the target started the negotiation,
4824 * but rejected our response, we already cleared the
4825 * sync rate before sending our WDTR.
4826 */
4829 /* Start the sync negotiation */
4835 }
4837 /* note asynch xfers and clear flag */
4866 }
4868 /*
4869 * Resend the identify for this CCB as the target
4870 * may believe that the selection is invalid otherwise.
4871 */
4882 /*
4883 * Requeue all tagged commands for this target
4884 * currently in our posession so they can be
4885 * converted to untagged commands.
4886 */
4891 SEARCH_COMPLETE);
4893 /*
4894 * Most likely the device believes that we had
4895 * previously negotiated packetized.
4896 */
4907 /*
4908 * Otherwise, we ignore it.
4909 */
4912 last_msg);
4913 }
4915 }
4917 /*
4918 * Process an ingnore wide residue message.
4919 */
4920 static void
4922 {
4923 u_int scb_index;
4928 /*
4929 * XXX Actually check data direction in the sequencer?
4930 * Perhaps add datadir to some spare bits in the hscb?
4931 */
4934 /*
4935 * Ignore the message if we haven't
4936 * seen an appropriate data phase yet.
4937 */
4939 /*
4940 * If the residual occurred on the last
4941 * transfer and the transfer request was
4942 * expected to end on an odd count, do
4943 * nothing. Otherwise, subtract a byte
4944 * and update the residual count accordingly.
4945 */
4952 /*
4953 * If the residual occurred on the last
4954 * transfer and the transfer request was
4955 * expected to end on an odd count, do
4956 * nothing.
4957 */
4963 /* Pull in the rest of the sgptr */
4967 /*
4968 * The residual data count is not updated
4969 * for the command run to completion case.
4970 * Explicitly zero the count.
4971 */
4973 }
4983 /*
4984 * The residual sg ptr points to the next S/G
4985 * to load so we must go back one.
4986 */
4987 sg--;
4992 sg--;
4994 /*
4995 * Preserve High Address and SG_LIST
4996 * bits while setting the count to 1.
4997 */
5003 /*
5004 * Increment sg so it points to the
5005 * "next" sg.
5006 */
5007 sg++;
5009 sg);
5010 }
5016 /*
5017 * The residual sg ptr points to the next S/G
5018 * to load so we must go back one.
5019 */
5020 sg--;
5025 sg--;
5027 /*
5028 * Preserve High Address and SG_LIST
5029 * bits while setting the count to 1.
5030 */
5036 /*
5037 * Increment sg so it points to the
5038 * "next" sg.
5039 */
5040 sg++;
5042 sg);
5043 }
5044 }
5045 /*
5046 * Toggle the "oddness" of the transfer length
5047 * to handle this mid-transfer ignore wide
5048 * residue. This ensures that the oddness is
5049 * correct for subsequent data transfers.
5050 */
5057 /*
5058 * The FIFO's pointers will be updated if/when the
5059 * sequencer re-enters a data phase.
5060 */
5061 }
5062 }
5063 }
5066 /*
5067 * Reinitialize the data pointers for the active transfer
5068 * based on its current residual.
5069 */
5070 static void
5072 {
5074 ahd_mode_state saved_modes;
5075 u_int scb_index;
5076 u_int wait;
5087 /*
5088 * Release and reacquire the FIFO so we
5089 * have a clean slate.
5090 */
5099 }
5106 /*
5107 * Determine initial values for data_addr and data_cnt
5108 * for resuming the data phase.
5109 */
5122 /* The residual sg_ptr always points to the next sg */
5123 sg--;
5134 /* The residual sg_ptr always points to the next sg */
5135 sg--;
5142 }
5147 }
5149 /*
5150 * Handle the effects of issuing a bus device reset message.
5151 */
5152 static void
5156 {
5157 #ifdef AHD_TARGET_MODE
5159 #endif
5164 status);
5166 #ifdef AHD_TARGET_MODE
5167 /*
5168 * Send an immediate notify ccb to all target mord peripheral
5169 * drivers affected by this action.
5170 */
5173 u_int cur_lun;
5174 u_int max_lun;
5182 }
5193 }
5194 }
5195 #endif
5197 /*
5198 * Go back to async/narrow transfers and renegotiate.
5199 */
5213 }
5215 #ifdef AHD_TARGET_MODE
5216 static void
5219 {
5221 /*
5222 * To facilitate adding multiple messages together,
5223 * each routine should increment the index and len
5224 * variables instead of setting them explicitly.
5225 */
5231 else
5236 }
5237 #endif
5238 /**************************** Initialization **********************************/
5239 static u_int
5241 {
5242 bus_size_t list_size;
5248 }
5250 /*
5251 * Calculate the optimum S/G List allocation size. S/G elements used
5252 * for a given transaction must be physically contiguous. Assume the
5253 * OS will allocate full pages to us, so it doesn't make sense to request
5254 * less than a page.
5255 */
5256 static u_int
5258 {
5259 bus_size_t sg_list_increment;
5260 bus_size_t sg_list_size;
5261 bus_size_t max_list_size;
5262 bus_size_t best_list_size;
5264 /* Start out with the minimum required for AHD_NSEG. */
5268 /* Get us as close as possible to a page in size. */
5272 /*
5273 * Try to reduce the amount of wastage by allocating
5274 * multiple pages.
5275 */
5284 bus_size_t new_mod;
5285 bus_size_t best_mod;
5292 }
5293 }
5295 }
5297 /*
5298 * Allocate a controller structure for a new device
5299 * and perform initial initializion.
5300 */
5303 {
5306 #ifndef __FreeBSD__
5312 }
5313 #else
5315 #endif
5320 #ifndef __FreeBSD__
5322 #endif
5325 }
5327 /* We don't know our unit number until the OSM sets it */
5345 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5350 }
5351 #ifdef AHD_DEBUG
5356 }
5357 #endif
5359 }
5361 int
5363 {
5368 }
5370 void
5372 {
5374 }
5376 void
5378 {
5382 }
5384 void
5386 {
5393 /* FALLTHROUGH */
5397 /* FALLTHROUGH */
5403 /* FALLTHROUGH */
5407 #ifndef __linux__
5409 #endif
5413 }
5415 #ifndef __linux__
5417 #endif
5425 #ifdef AHD_TARGET_MODE
5435 }
5436 }
5437 #endif
5439 }
5440 }
5441 #ifdef AHD_TARGET_MODE
5445 }
5446 #endif
5453 #ifndef __FreeBSD__
5455 #endif
5457 }
5459 static void
5461 {
5466 /*
5467 * Stop periodic timer callbacks.
5468 */
5472 /* This will reset most registers to 0, but not all */
5474 }
5476 /*
5477 * Reset the controller and record some information about it
5478 * that is only available just after a reset. If "reinit" is
5479 * non-zero, this reset occured after initial configuration
5480 * and the caller requests that the chip be fully reinitialized
5481 * to a runable state. Chip interrupts are *not* enabled after
5482 * a reinitialization. The caller must enable interrupts via
5483 * ahd_intr_enable().
5484 */
5485 int
5487 {
5488 u_int sxfrctl1;
5492 /*
5493 * Preserve the value of the SXFRCTL1 register for all channels.
5494 * It contains settings that affect termination and we don't want
5495 * to disturb the integrity of the bus.
5496 */
5506 /*
5507 * A4 Razor #632
5508 * During the assertion of CHIPRST, the chip
5509 * does not disable its parity logic prior to
5510 * the start of the reset. This may cause a
5511 * parity error to be detected and thus a
5512 * spurious SERR or PERR assertion. Disble
5513 * PERR and SERR responses during the CHIPRST.
5514 */
5518 }
5521 /*
5522 * Ensure that the reset has finished. We delay 1000us
5523 * prior to reading the register to make sure the chip
5524 * has sufficiently completed its reset to handle register
5525 * accesses.
5526 */
5535 }
5539 /*
5540 * Clear any latched PCI error status and restore
5541 * previous SERR and PERR response enables.
5542 */
5547 }
5549 /*
5550 * Mode should be SCSI after a chip reset, but lets
5551 * set it just to be safe. We touch the MODE_PTR
5552 * register directly so as to bypass the lazy update
5553 * code in ahd_set_modes().
5554 */
5559 /*
5560 * Restore SXFRCTL1.
5561 *
5562 * We must always initialize STPWEN to 1 before we
5563 * restore the saved values. STPWEN is initialized
5564 * to a tri-state condition which can only be cleared
5565 * by turning it on.
5566 */
5570 /* Determine chip configuration */
5575 /*
5576 * If a recovery action has forced a chip reset,
5577 * re-initialize the chip to our liking.
5578 */
5583 }
5585 /*
5586 * Determine the number of SCBs available on the controller
5587 */
5588 static int
5601 /* Start out life as unallocated (needing an abort) */
5608 }
5610 }
5612 static void
5614 {
5619 }
5621 static void
5623 {
5629 /* Clear the control byte. */
5632 /* Set the next pointer */
5634 }
5635 }
5637 static int
5639 {
5652 /* Determine the number of hardware SCBs and initialize them */
5657 }
5661 /*
5662 * Create our DMA tags. These tags define the kinds of device
5663 * accessible memory allocations and memory mappings we will
5664 * need to perform during normal operation.
5665 *
5666 * Unless we need to further restrict the allocation, we rely
5667 * on the restrictions of the parent dmat, hence the common
5668 * use of MAXADDR and MAXSIZE.
5669 */
5671 /* DMA tag for our hardware scb structures */
5681 }
5685 /* DMA tag for our S/G structures. */
5695 }
5696 #ifdef AHD_DEBUG
5700 #endif
5704 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5714 }
5718 /* Perform initial CCB allocation */
5726 }
5728 /*
5729 * Note that we were successfull
5730 */
5733 error_exit:
5736 }
5740 {
5743 /*
5744 * Look on the pending list.
5745 */
5749 }
5751 /*
5752 * Then on all of the collision free lists.
5753 */
5763 }
5765 /*
5766 * And finally on the generic free list.
5767 */
5771 }
5774 }
5776 static void
5778 {
5788 {
5798 }
5800 /* FALLTHROUGH */
5801 }
5803 {
5813 }
5815 /* FALLTHROUGH */
5816 }
5818 {
5828 }
5830 /* FALLTHROUGH */
5831 }
5838 }
5839 }
5841 /*
5842 * DSP filter Bypass must be enabled until the first selection
5843 * after a change in bus mode (Razor #491 and #493).
5844 */
5845 static void
5847 {
5848 ahd_mode_state saved_modes;
5855 #ifdef AHD_DEBUG
5858 #endif
5861 }
5863 static void
5865 {
5866 ahd_mode_state saved_modes;
5867 u_int sblkctl;
5875 #ifdef AHD_DEBUG
5878 #endif
5882 #ifdef AHD_DEBUG
5885 #endif
5886 }
5891 }
5893 /*************************** SCB Management ***********************************/
5894 static void
5896 {
5911 }
5912 }
5914 static void
5916 {
5920 u_int col_idx;
5930 /*
5931 * Maintain order in the collision free
5932 * lists for fairness if this device has
5933 * other colliding tags active.
5934 */
5939 }
5941 }
5943 }
5945 /*
5946 * Get a free scb. If there are none, see if we can allocate a new SCB.
5947 */
5950 {
5955 look_again:
5960 }
5961 }
5968 }
5975 }
5976 found:
5979 }
5981 /*
5982 * Return an SCB resource to the free list.
5983 */
5984 void
5986 {
5988 /* Clean up for the next user */
5995 /*
5996 * No collision possible. Just free normally.
5997 */
6002 /*
6003 * The SCB we might have collided with is on
6004 * a free collision list. Put both SCBs on
6005 * the generic list.
6006 */
6016 /*
6017 * The SCB we might collide with on the next allocation
6018 * is still active in a non-packetized, tagged, context.
6019 * Put us on the SCB collision list.
6020 */
6024 /*
6025 * The SCB we might collide with on the next allocation
6026 * is either active in a packetized context, or free.
6027 * Since we can't collide, put this SCB on the generic
6028 * free list.
6029 */
6032 }
6035 }
6037 static void
6039 {
6048 dma_addr_t hscb_busaddr;
6049 dma_addr_t sg_busaddr;
6050 dma_addr_t sense_busaddr;
6056 /* Can't allocate any more */
6072 /* Allocate the next batch of hardware SCBs */
6078 }
6089 }
6105 /* Allocate the next batch of S/G lists */
6111 }
6123 #ifdef AHD_DEBUG
6126 #endif
6127 }
6142 /* Allocate the next batch of sense buffers */
6148 }
6159 #ifdef AHD_DEBUG
6162 #endif
6163 }
6170 u_int col_tag;
6171 #ifndef __linux__
6173 #endif
6185 }
6197 /*
6198 * The sequencer always starts with the second entry.
6199 * The first entry is embedded in the scb.
6200 */
6203 next_scb->sg_list_busaddr
6205 else
6209 #ifndef __linux__
6216 }
6217 #endif
6224 hscb++;
6234 }
6235 }
6237 void
6239 {
6252 }
6259 }
6265 "Secondary High"
6266 };
6272 "Not Configured"
6273 };
6275 /*
6276 * Start the board, ready for normal operation
6277 */
6278 int
6280 {
6282 dma_addr_t next_baddr;
6286 u_int warn_user;
6298 /*
6299 * Verify that the compiler hasn't over-agressively
6300 * padded important structures.
6301 */
6305 #ifdef AHD_DEBUG
6308 #endif
6310 /*
6311 * Default to allowing initiator operations.
6312 */
6315 /*
6316 * Only allow target mode features if this unit has them enabled.
6317 */
6321 #ifndef __linux__
6322 /* DMA tag for mapping buffers into device visible space. */
6336 }
6337 #endif
6341 /*
6342 * DMA tag for our command fifos and other data in system memory
6343 * the card's sequencer must be able to access. For initiator
6344 * roles, we need to allocate space for the qoutfifo. When providing
6345 * for the target mode role, we must additionally provide space for
6346 * the incoming target command fifo.
6347 */
6359 driver_data_size,
6364 }
6368 /* Allocation of driver data */
6371 BUS_DMA_NOWAIT,
6374 }
6378 /* And permanently map it in */
6391 }
6397 }
6399 /*
6400 * We need one SCB to serve as the "next SCB". Since the
6401 * tag identifier in this SCB will never be used, there is
6402 * no point in using a valid HSCB tag from an SCB pulled from
6403 * the standard free pool. So, we allocate this "sentinel"
6404 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6405 */
6412 /* Allocate SCB data now that buffer_dmat is initialized */
6419 /*
6420 * Before committing these settings to the chip, give
6421 * the OSM one last chance to modify our configuration.
6422 */
6425 /* Bring up the chip. */
6433 /*
6434 * Verify termination based on current draw and
6435 * warn user if the bus is over/under terminated.
6436 */
6438 CURSENSE_ENB);
6442 }
6450 }
6451 }
6456 }
6458 /* Latch Current Sensing status. */
6463 }
6465 /* Diable current sensing. */
6468 #ifdef AHD_DEBUG
6472 }
6473 #endif
6476 u_int term_stat;
6482 warn_user++;
6490 }
6491 }
6496 }
6497 init_done:
6502 }
6504 /*
6505 * (Re)initialize chip state after a chip reset.
6506 */
6507 static void
6509 {
6511 u_int sxfrctl1;
6512 u_int scsiseq_template;
6513 u_int wait;
6514 u_int i;
6515 u_int target;
6518 /*
6519 * Take the LED out of diagnostic mode
6520 */
6523 /*
6524 * Return HS_MAILBOX to its default value.
6525 */
6529 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6536 /*
6537 * The selection timer duration is twice as long
6538 * as it should be. Halve it by adding "1" to
6539 * the user specified setting.
6540 */
6544 }
6550 /*
6551 * Now that termination is set, wait for up
6552 * to 500ms for our transceivers to settle. If
6553 * the adapter does not have a cable attached,
6554 * the transceivers may never settle, so don't
6555 * complain if we fail here.
6556 */
6559 wait--)
6562 /* Clear any false bus resets due to the transceivers settling */
6566 /* Initialize mode specific S/G state. */
6575 }
6586 }
6589 /*
6590 * Do not issue a target abort when a split completion
6591 * error occurs. Let our PCIX interrupt handler deal
6592 * with it instead. H2A4 Razor #625
6593 */
6599 /*
6600 * Tweak IOCELL settings.
6601 */
6606 }
6607 #ifdef AHD_DEBUG
6610 WRTBIASCTL_HP_DEFAULT);
6611 #endif
6612 }
6615 /*
6616 * Enable LQI Manager interrupts.
6617 */
6622 /*
6623 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6624 * manually for the command phase at the start of a packetized
6625 * selection case. ENLQOBUSFREE should be made redundant by
6626 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6627 * events fail to assert the BUSFREE interrupt so we must
6628 * also enable LQOBUSFREE interrupts.
6629 */
6632 /*
6633 * Setup sequencer interrupt handlers.
6634 */
6638 /*
6639 * Setup SCB Offset registers.
6640 */
6643 pkt_long_lun));
6646 }
6661 }
6667 /* We haven't been enabled for target mode yet. */
6672 /* Initialize the negotiation table. */
6674 /*
6675 * Clear the spare bytes in the neg table to avoid
6676 * spurious parity errors.
6677 */
6683 }
6684 }
6696 }
6701 #ifdef NEEDS_MORE_TESTING
6702 /*
6703 * Always enable abort on incoming L_Qs if this feature is
6704 * supported. We use this to catch invalid SCB references.
6705 */
6708 else
6709 #endif
6712 /* All of our queues are empty */
6725 /* All target command blocks start out invalid. */
6732 }
6734 /* Initialize Scratch Ram. */
6738 /* We don't have any waiting selections */
6746 /*
6747 * Nobody is waiting to be DMAed into the QOUTFIFO.
6748 */
6755 /*
6756 * The Freeze Count is 0.
6757 */
6762 /*
6763 * Tell the sequencer where it can find our arrays in memory.
6764 */
6769 /*
6770 * Setup the allowed SCSI Sequences based on operational mode.
6771 * If we are a target, we'll enable select in operations once
6772 * we've had a lun enabled.
6773 */
6779 /* There are no busy SCBs yet. */
6785 }
6787 /*
6788 * Initialize the group code to command length table.
6789 * Vendor Unique codes are set to 0 so we only capture
6790 * the first byte of the cdb. These can be overridden
6791 * when target mode is enabled.
6792 */
6802 /* Tell the sequencer of our initial queue positions */
6812 /*
6813 * Tell the sequencer which SCB will be the next one it receives.
6814 */
6818 /*
6819 * Default to coalescing disabled.
6820 */
6839 else
6841 }
6842 }
6844 /*
6845 * Setup default device and controller settings.
6846 * This should only be called if our probe has
6847 * determined that no configuration data is available.
6848 */
6849 int
6851 {
6856 /*
6857 * Allocate a tstate to house information for our
6858 * initiator presence on the bus as well as the user
6859 * data for any target mode initiator.
6860 */
6865 }
6875 /*
6876 * We support SPC2 and SPI4.
6877 */
6885 #ifdef AHD_FORCE_160
6887 #else
6889 #endif
6892 | MSG_EXT_PPR_WR_FLOW
6893 | MSG_EXT_PPR_HOLD_MCS
6894 | MSG_EXT_PPR_IU_REQ
6895 | MSG_EXT_PPR_QAS_REQ
6902 /*
6903 * Start out Async/Narrow/Untagged and with
6904 * conservative protocol support.
6905 */
6919 }
6921 }
6923 /*
6924 * Parse device configuration information.
6925 */
6926 int
6928 {
6935 /*
6936 * Allocate a tstate to house information for our
6937 * initiator presence on the bus as well as the user
6938 * data for any target mode initiator.
6939 */
6944 }
6957 /*
6958 * We support SPC2 and SPI4.
6959 */
6972 /*
6973 * Cannot be packetized without disconnection.
6974 */
6976 }
6987 }
6988 #ifdef AHD_FORCE_160
6991 #endif
6995 | MSG_EXT_PPR_WR_FLOW
6996 | MSG_EXT_PPR_HOLD_MCS
7000 }
7007 else
7009 #ifdef AHD_DEBUG
7014 #endif
7015 /*
7016 * Start out Async/Narrow/Untagged and with
7017 * conservative protocol support.
7018 */
7032 }
7055 }
7057 /*
7058 * Parse device configuration information.
7059 */
7060 int
7062 {
7071 }
7073 void
7075 {
7076 u_int hcntrl;
7086 }
7088 }
7090 static void
7092 u_int mincmds)
7093 {
7106 }
7108 static void
7110 {
7118 }
7120 /*
7121 * Ensure that the card is paused in a location
7122 * outside of all critical sections and that all
7123 * pending work is completed prior to returning.
7124 * This routine should only be called from outside
7125 * an interrupt context.
7126 */
7127 void
7129 {
7130 u_int intstat;
7131 u_int maxloops;
7136 /*
7137 * Freeze the outgoing selections. We do this only
7138 * until we are safely paused without further selections
7139 * pending.
7140 */
7147 /*
7148 * Give the sequencer some time to service
7149 * any active selections.
7150 */
7159 }
7169 }
7176 }
7178 #ifdef CONFIG_PM
7179 int
7181 {
7188 }
7191 }
7193 void
7195 {
7200 }
7201 #endif
7203 /************************** Busy Target Table *********************************/
7204 /*
7205 * Set SCBPTR to the SCB that contains the busy
7206 * table entry for TCL. Return the offset into
7207 * the SCB that contains the entry for TCL.
7208 * saved_scbid is dereferenced and set to the
7209 * scbid that should be restored once manipualtion
7210 * of the TCL entry is complete.
7211 */
7212 static __inline u_int
7214 {
7215 /*
7216 * Index to the SCB that contains the busy entry.
7217 */
7223 /*
7224 * And now calculate the SCB offset to the entry.
7225 * Each entry is 2 bytes wide, hence the
7226 * multiplication by 2.
7227 */
7229 }
7231 /*
7232 * Return the untagged transaction id for a given target/channel lun.
7233 */
7234 static u_int
7236 {
7237 u_int scbid;
7238 u_int scb_offset;
7239 u_int saved_scbptr;
7245 }
7247 static void
7249 {
7250 u_int scb_offset;
7251 u_int saved_scbptr;
7256 }
7258 /************************** SCB and SCB queue management **********************/
7259 static int
7262 {
7274 #ifdef AHD_TARGET_MODE
7286 }
7290 }
7293 }
7295 static void
7297 {
7311 }
7313 void
7315 {
7317 ahd_mode_state saved_modes;
7323 u_int prev_tag;
7324 u_int prev_pos;
7329 }
7333 }
7335 static void
7338 {
7348 }
7353 }
7355 static int
7357 {
7358 u_int qinpos;
7359 u_int wrap_qinpos;
7360 u_int wrap_qinfifonext;
7368 else
7371 }
7373 void
7375 {
7377 ahd_mode_state saved_modes;
7378 u_int pending_cmds;
7383 /*
7384 * Don't count any commands as outstanding that the
7385 * sequencer has already marked for completion.
7386 */
7391 pending_cmds++;
7392 }
7396 }
7398 static void
7400 {
7401 cam_status ostat;
7402 cam_status cstat;
7411 }
7413 int
7416 ahd_search_action action)
7417 {
7421 ahd_mode_state saved_modes;
7422 u_int qinstart;
7423 u_int qinpos;
7424 u_int qintail;
7425 u_int tid_next;
7426 u_int tid_prev;
7427 u_int scbid;
7428 u_int seq_flags2;
7429 u_int savedscbptr;
7434 /* Must be in CCHAN mode */
7438 /*
7439 * Halt any pending SCB DMA. The sequencer will reinitiate
7440 * this dma if the qinfifo is not empty once we unpause.
7441 */
7447 ;
7448 }
7449 /* Determine sequencer's position in the qinfifo. */
7459 }
7461 /*
7462 * Start with an empty queue. Entries that are not chosen
7463 * for removal will be re-added to the queue as we go.
7464 */
7475 }
7478 /*
7479 * We found an scb that needs to be acted on.
7480 */
7481 found++;
7487 /* FALLTHROUGH */
7492 /* FALLTHROUGH */
7497 }
7501 }
7503 }
7510 /*
7511 * Search waiting for selection lists. We traverse the
7512 * list of "their ids" waiting for selection and, if
7513 * appropriate, traverse the SCBs of each "their id"
7514 * looking for matches.
7515 */
7528 u_int tid_head;
7529 u_int tid_tail;
7531 targets++;
7541 }
7547 }
7554 }
7556 /*
7557 * We found a list of scbs that needs to be searched.
7558 */
7566 /*
7567 * Check any MK_MESSAGE SCB that is still waiting to
7568 * enter this target's waiting for selection queue.
7569 */
7574 /*
7575 * We found an scb that needs to be acted on.
7576 */
7577 found++;
7583 /* FALLTHROUGH */
7585 {
7586 u_int tail_offset;
7590 /*
7591 * Reset our tail to the tail of the
7592 * main per-target list.
7593 */
7594 tail_offset = WAITING_SCB_TAILS
7604 }
7607 /* FALLTHROUGH */
7610 }
7611 }
7618 /*
7619 * When removing the last SCB for a target
7620 * queue with a pending MK_MESSAGE scb, we
7621 * must queue the MK_MESSAGE scb.
7622 */
7628 }
7635 }
7637 /* Restore saved state. */
7641 }
7643 static int
7648 {
7650 u_int scbid;
7651 u_int next;
7652 u_int prev;
7667 }
7673 }
7681 }
7682 found++;
7688 /* FALLTHROUGH */
7700 }
7703 }
7708 }
7710 static void
7713 {
7718 /* Bypass current TID list */
7724 }
7729 /* Stitch through tid_cur */
7735 }
7741 }
7742 }
7744 /*
7745 * Manipulate the waiting for selection list and return the
7746 * scb that follows the one that we remove.
7747 */
7748 static u_int
7751 {
7752 u_int tail_offset;
7758 }
7760 /*
7761 * SCBs that have MK_MESSAGE set in them may
7762 * cause the tail pointer to be updated without
7763 * setting the next pointer of the previous tail.
7764 * Only clear the tail if the removed SCB was
7765 * the tail.
7766 */
7774 }
7776 /*
7777 * Add the SCB as selected by SCBPTR onto the on chip list of
7778 * free hardware SCBs. This list is empty/unused if we are not
7779 * performing SCB paging.
7780 */
7781 static void
7783 {
7784 /* XXX Need some other mechanism to designate "free". */
7785 /*
7786 * Invalidate the tag so that our abort
7787 * routines don't think it's active.
7788 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7789 */
7790 }
7792 /******************************** Error Handling ******************************/
7793 /*
7794 * Abort all SCBs that match the given description (target/channel/lun/tag),
7795 * setting their status to the passed in status if the status has not already
7796 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7797 * is paused before it is called.
7798 */
7799 static int
7802 {
7806 u_int maxtarget;
7807 u_int minlun;
7808 u_int maxlun;
7810 ahd_mode_state saved_modes;
7812 /* restore this when we're done */
7819 /*
7820 * Clean out the busy target table for any untagged commands.
7821 */
7829 }
7839 }
7844 u_int scbid;
7845 u_int tcl;
7855 }
7856 }
7857 }
7859 /*
7860 * Don't abort commands that have already completed,
7861 * but haven't quite made it up to the host yet.
7862 */
7865 /*
7866 * Go through the pending CCB list and look for
7867 * commands for this target that are still active.
7868 * These are other tagged commands that were
7869 * disconnected when the reset occurred.
7870 */
7876 cam_status ostat;
7886 found++;
7887 }
7888 }
7893 }
7895 static void
7897 {
7906 /* Turn off the bus reset */
7911 /*
7912 * 2A Razor #474
7913 * Certain chip state is not cleared for
7914 * SCSI bus resets that we initiate, so
7915 * we must reset the chip.
7916 */
7920 }
7923 }
7925 int
7927 {
7929 u_int initiator;
7930 u_int target;
7931 u_int max_scsiid;
7933 u_int fifo;
7934 u_int next_fifo;
7937 /*
7938 * Check if the last bus reset is cleared
7939 */
7944 }
7950 CAM_TARGET_WILDCARD,
7951 CAM_TARGET_WILDCARD,
7952 CAM_LUN_WILDCARD,
7956 /* Make sure the sequencer is in a safe location. */
7959 /*
7960 * Run our command complete fifos to ensure that we perform
7961 * completion processing on any commands that 'completed'
7962 * before the reset occurred.
7963 */
7965 #ifdef AHD_TARGET_MODE
7968 }
7969 #endif
7972 /*
7973 * Disable selections so no automatic hardware
7974 * functions will modify chip state.
7975 */
7979 /*
7980 * Safely shut down our DMA engines. Always start with
7981 * the FIFO that is not currently active (if any are
7982 * actively connected).
7983 */
7986 /* If disconneced, arbitrarily start with FIFO1. */
7995 /*
7996 * Set CURRFIFO to the now inactive channel.
7997 */
8002 /*
8003 * Reset the bus if we are initiating this reset
8004 */
8014 /*
8015 * Clean up all the state information for the
8016 * pending transactions on this bus.
8017 */
8022 /*
8023 * Cleanup anything left in the FIFOs.
8024 */
8028 /*
8029 * Clear SCSI interrupt status
8030 */
8033 /*
8034 * Reenable selections
8035 */
8041 #ifdef AHD_TARGET_MODE
8042 /*
8043 * Send an immediate notify ccb to all target more peripheral
8044 * drivers affected by this action.
8045 */
8048 u_int lun;
8063 }
8064 }
8065 #endif
8066 /*
8067 * Revert to async/narrow transfers until we renegotiate.
8068 */
8077 CAM_LUN_WILDCARD,
8084 }
8085 }
8087 /* Notify the XPT that a bus reset occurred */
8094 }
8096 /**************************** Statistics Processing ***************************/
8097 static void
8099 {
8101 u_long s;
8114 #ifdef AHD_DEBUG
8121 #endif
8122 }
8130 }
8132 /****************************** Status Processing *****************************/
8134 static void
8136 {
8140 /*
8141 * The sequencer freezes its select-out queue
8142 * anytime a SCSI status error occurs. We must
8143 * handle the error and increment our qfreeze count
8144 * to allow the sequencer to continue. We don't
8145 * bother clearing critical sections here since all
8146 * operations are on data structures that the sequencer
8147 * is not touching once the queue is frozen.
8148 */
8156 }
8158 /* Freeze the queue until the client sees the error. */
8167 /* Don't want to clobber the original sense code */
8169 /*
8170 * Clear the SCB_SENSE Flag and perform
8171 * a normal command completion.
8172 */
8177 }
8182 {
8188 #ifdef AHD_DEBUG
8197 }
8198 #endif
8225 }
8226 }
8229 CAM_REQ_CMP_ERR);
8230 }
8233 #ifdef AHD_DEBUG
8236 #endif
8237 }
8240 }
8243 {
8250 #ifdef AHD_DEBUG
8255 }
8256 #endif
8265 ROLE_INITIATOR);
8274 /*
8275 * Save off the residual if there is one.
8276 */
8278 #ifdef AHD_DEBUG
8282 }
8283 #endif
8298 /*
8299 * We can't allow the target to disconnect.
8300 * This will be an untagged transaction and
8301 * having the target disconnect will make this
8302 * transaction indestinguishable from outstanding
8303 * tagged transactions.
8304 */
8307 /*
8308 * This request sense could be because the
8309 * the device lost power or in some other
8310 * way has lost our transfer negotiations.
8311 * Renegotiate if appropriate. Unit attention
8312 * errors will be reported before any data
8313 * phases occur.
8314 */
8318 AHD_NEG_IF_NON_ASYNC);
8319 }
8325 }
8331 }
8335 /* FALLTHROUGH */
8339 }
8340 }
8342 static void
8344 {
8350 }
8351 }
8353 /*
8354 * Calculate the residual for a just completed SCB.
8355 */
8356 static void
8358 {
8365 /*
8366 * 5 cases.
8367 * 1) No residual.
8368 * SG_STATUS_VALID clear in sgptr.
8369 * 2) Transferless command
8370 * 3) Never performed any transfers.
8371 * sgptr has SG_FULL_RESID set.
8372 * 4) No residual but target did not
8373 * save data pointers after the
8374 * last transfer, so sgptr was
8375 * never updated.
8376 * 5) We have a partial residual.
8377 * Use residual_sgptr to determine
8378 * where we are.
8379 */
8384 /* Case 1 */
8389 /* Case 2 */
8392 /*
8393 * Residual fields are the same in both
8394 * target and initiator status packets,
8395 * so we can always use the initiator fields
8396 * regardless of the role for this SCB.
8397 */
8401 /* Case 3 */
8404 /* Case 4 */
8416 /* NOTREACHED */
8420 /*
8421 * Remainder of the SG where the transfer
8422 * stopped.
8423 */
8427 /* The residual sg_ptr always points to the next sg */
8428 sg--;
8430 /*
8431 * Add up the contents of all residual
8432 * SG segments that are after the SG where
8433 * the transfer stopped.
8434 */
8436 sg++;
8438 }
8439 }
8442 else
8445 #ifdef AHD_DEBUG
8450 }
8451 #endif
8452 }
8454 /******************************* Target Mode **********************************/
8455 #ifdef AHD_TARGET_MODE
8456 /*
8457 * Add a target mode event to this lun's queue
8458 */
8459 static void
8462 {
8469 else
8475 /*
8476 * Any earlier events are irrelevant, so reset our buffer.
8477 * This has the effect of allowing us to deal with reset
8478 * floods (an external device holding down the reset line)
8479 * without losing the event that is really interesting.
8480 */
8484 }
8495 }
8504 }
8506 /*
8507 * Send any target mode events queued up waiting
8508 * for immediate notify resources.
8509 */
8510 void
8512 {
8532 }
8539 }
8540 }
8541 #endif
8543 /******************** Sequencer Program Patching/Download *********************/
8545 #ifdef AHD_DUMP_SEQ
8546 void
8548 {
8564 }
8565 }
8566 #endif
8568 static void
8570 {
8575 u_int cs_count;
8576 u_int cur_cs;
8577 u_int i;
8579 u_int skip_addr;
8580 u_int sg_prefetch_cnt;
8581 u_int sg_prefetch_cnt_limit;
8582 u_int sg_prefetch_align;
8583 u_int sg_size;
8584 u_int cacheline_mask;
8591 #if DOWNLOAD_CONST_COUNT != 8
8593 #endif
8594 /*
8595 * Start out with 0 critical sections
8596 * that apply to this firmware load.
8597 */
8603 /*
8604 * Setup downloadable constant table.
8605 *
8606 * The computation for the S/G prefetch variables is
8607 * a bit complicated. We would like to always fetch
8608 * in terms of cachelined sized increments. However,
8609 * if the cacheline is not an even multiple of the
8610 * SG element size or is larger than our SG RAM, using
8611 * just the cache size might leave us with only a portion
8612 * of an SG element at the tail of a prefetch. If the
8613 * cacheline is larger than our S/G prefetch buffer less
8614 * the size of an SG element, we may round down to a cacheline
8615 * that doesn't contain any or all of the S/G of interest
8616 * within the bounds of our S/G ram. Provide variables to
8617 * the sequencer that will allow it to handle these edge
8618 * cases.
8619 */
8620 /* Start by aligning to the nearest cacheline. */
8624 /* Round down to the nearest power of 2. */
8626 sg_prefetch_align--;
8630 /*
8631 * If the cacheline boundary is greater than half our prefetch RAM
8632 * we risk not being able to fetch even a single complete S/G
8633 * segment if we align to that boundary.
8634 */
8637 /* Start by fetching a single cacheline. */
8639 /*
8640 * Increment the prefetch count by cachelines until
8641 * at least one S/G element will fit.
8642 */
8648 /*
8649 * If the cacheline is not an even multiple of
8650 * the S/G size, we may only get a partial S/G when
8651 * we align. Add a cacheline if this is the case.
8652 */
8656 /*
8657 * Lastly, compute a value that the sequencer can use
8658 * to determine if the remainder of the CCSGRAM buffer
8659 * has a full S/G element in it.
8660 */
8679 /*
8680 * Don't download this instruction as it
8681 * is in a patch that was removed.
8682 */
8684 }
8685 /*
8686 * Move through the CS table until we find a CS
8687 * that might apply to this instruction.
8688 */
8695 cs_count++;
8696 }
8698 }
8703 }
8705 }
8707 downloaded++;
8708 }
8718 }
8725 }
8726 }
8728 static int
8731 {
8734 u_int num_patches;
8744 /* Start rejecting code */
8748 /* Accepted this patch. Advance to the next
8749 * one and wait for our intruction pointer to
8750 * hit this point.
8751 */
8752 cur_patch++;
8753 }
8754 }
8758 /* Still skipping */
8762 }
8764 static u_int
8766 {
8769 u_int skip_addr;
8770 u_int i;
8787 i++;
8788 }
8789 }
8791 }
8793 static void
8795 {
8799 u_int opcode;
8801 /*
8802 * The firmware is always compiled into a little endian format.
8803 */
8809 /* Pull the opcode */
8820 {
8823 /* FALLTHROUGH */
8824 }
8833 }
8835 /* FALLTHROUGH */
8837 {
8840 /* Calculate odd parity for the instruction */
8846 count++;
8847 }
8851 /* The sequencer is a little endian cpu */
8855 }
8859 }
8860 }
8862 static int
8864 {
8871 /*
8872 * We avoid using 0 as a pattern to avoid
8873 * confusion if the stack implementation
8874 * "back-fills" with zeros when "poping'
8875 * entries.
8876 */
8880 }
8882 /* Verify */
8884 u_int stack_entry;
8890 }
8891 last_probe++;
8892 }
8893 sized:
8895 }
8897 int
8901 {
8903 u_int printed_mask;
8908 }
8914 }
8932 }
8935 }
8938 else
8943 }
8945 void
8947 {
8949 ahd_mode_state saved_modes;
8950 u_int dffstat;
8952 u_int scb_index;
8953 u_int saved_scb_index;
8954 u_int cur_col;
8962 }
8977 /*
8978 * Mode independent registers.
8979 */
9024 /* QINFIFO */
9041 }
9054 }
9060 }
9070 }
9080 }
9091 }
9100 }
9105 #ifdef AHD_DEBUG
9107 #endif
9108 u_int fifo_scbptr;
9130 }
9140 }
9148 #ifdef AHD_DEBUG
9153 }
9154 #endif
9155 }
9196 }
9200 }
9205 }
9207 #if 0
9208 void
9210 {
9211 ahd_mode_state saved_modes;
9212 u_int saved_scb_index;
9228 }
9232 }
9235 /**************************** Flexport Logic **********************************/
9236 /*
9237 * Read count 16bit words from 16bit word address start_addr from the
9238 * SEEPROM attached to the controller, into buf, using the controller's
9239 * SEEPROM reading state machine. Optionally treat the data as a byte
9240 * stream in terms of byte order.
9241 */
9242 int
9245 {
9246 u_int cur_addr;
9247 u_int end_addr;
9250 /*
9251 * If we never make it through the loop even once,
9252 * we were passed invalid arguments.
9253 */
9272 /*
9273 * ahd_inw() already handles machine byte order.
9274 */
9276 }
9277 buf++;
9278 }
9280 }
9282 /*
9283 * Write count 16bit words from buf, into SEEPROM attache to the
9284 * controller starting at 16bit word address start_addr, using the
9285 * controller's SEEPROM writing state machine.
9286 */
9287 int
9290 {
9291 u_int cur_addr;
9292 u_int end_addr;
9299 /* Place the chip into write-enable mode */
9306 /*
9307 * Write the data. If we don't get throught the loop at
9308 * least once, the arguments were invalid.
9309 */
9320 }
9322 /*
9323 * Disable writes.
9324 */
9331 }
9333 /*
9334 * Wait ~100us for the serial eeprom to satisfy our request.
9335 */
9336 static int
9338 {
9348 }
9350 /*
9351 * Validate the two checksums in the per_channel
9352 * vital product data struct.
9353 */
9354 static int
9356 {
9380 }
9382 int
9384 {
9401 }
9402 }
9404 int
9406 {
9407 /*
9408 * We should be able to determine the SEEPROM type
9409 * from the flexport logic, but unfortunately not
9410 * all implementations have this logic and there is
9411 * no programatic method for determining if the logic
9412 * is present.
9413 */
9415 #if 0
9424 #endif
9425 }
9427 void
9429 {
9430 /* Currently a no-op */
9431 }
9433 /*
9434 * Wait at most 2 seconds for flexport arbitration to succeed.
9435 */
9436 static int
9438 {
9449 }
9451 int
9453 {
9472 }
9474 int
9476 {
9490 }
9492 /************************* Target Mode ****************************************/
9493 #ifdef AHD_TARGET_MODE
9494 cam_status
9499 {
9504 /*
9505 * Handle the 'black hole' device that sucks up
9506 * requests to unattached luns on enabled targets.
9507 */
9513 u_int max_id;
9527 }
9533 }
9535 void
9537 {
9538 #if NOT_YET
9542 cam_status status;
9543 u_int target;
9544 u_int lun;
9545 u_int target_mask;
9546 u_long s;
9555 }
9558 u_int our_id;
9564 /*
9565 * Only allow additional targets if
9566 * the initiator role is disabled.
9567 * The hardware cannot handle a re-select-in
9568 * on the initiator id during a re-select-out
9569 * on a different target id.
9570 */
9574 /*
9575 * Only allow our target id to change
9576 * if the initiator role is not configured
9577 * and there are no enabled luns which
9578 * are attached to the currently registered
9579 * scsi id.
9580 */
9582 }
9583 }
9584 }
9589 }
9591 /*
9592 * We now have an id that is valid.
9593 * If we aren't in target mode, switch modes.
9594 */
9597 u_long s;
9605 }
9613 }
9623 u_int scsiseq1;
9625 /* Are we already enabled?? */
9631 }
9635 /*
9636 * Don't (yet?) support vendor
9637 * specific commands.
9638 */
9642 }
9644 /*
9645 * Seems to be okay.
9646 * Setup our data structures.
9647 */
9655 }
9656 }
9663 }
9675 }
9685 u_int targid_mask;
9692 u_int our_id;
9698 /*
9699 * This can only happen if selections
9700 * are not enabled
9701 */
9703 u_int sblkctl;
9723 }
9724 }
9727 /* Allow select-in operations */
9735 }
9748 }
9763 }
9764 }
9769 }
9774 }
9779 }
9787 /* Can we clean up the target too? */
9795 }
9801 u_int targid_mask;
9807 }
9808 }
9813 /*
9814 * We can't allow selections without
9815 * our black hole device.
9816 */
9818 }
9820 /* Disallow select-in */
9821 u_int scsiseq1;
9837 /*
9838 * Unpaused. The extra unpause
9839 * that follows is harmless.
9840 */
9841 }
9842 }
9845 }
9846 #endif
9847 }
9849 static void
9851 {
9852 #if NOT_YET
9853 u_int scsiid_mask;
9854 u_int scsiid;
9859 /*
9860 * Since we will rely on the TARGID mask
9861 * for selection enables, ensure that OID
9862 * in SCSIID is not set to some other ID
9863 * that we don't want to allow selections on.
9864 */
9867 else
9871 u_int our_id;
9873 /* ffs counts from 1 */
9877 else
9878 our_id--;
9881 }
9884 else
9886 #endif
9887 }
9889 void
9891 {
9897 /*
9898 * Only advance through the queue if we
9899 * have the resources to process the command.
9900 */
9909 BUS_DMASYNC_PREREAD);
9912 /*
9913 * Lazily update our position in the target mode incoming
9914 * command queue as seen by the sequencer.
9915 */
9917 u_int hs_mailbox;
9923 }
9924 }
9925 }
9927 static int
9929 {
9948 /*
9949 * Commands for disabled luns go to the black hole driver.
9950 */
9957 /*
9958 * Wait for more ATIOs from the peripheral driver for this lun.
9959 */
9963 #ifdef AHD_DEBUG
9968 #endif
9972 /* Fill in the wildcards */
9975 }
9977 /*
9978 * Package it up and send it off to
9979 * whomever has this lun enabled.
9980 */
9984 /* Tag was included */
9990 }
9991 byte++;
9993 /* Okay. Now determine the cdb size based on the command code */
10010 /* Only copy the opcode. */
10014 }
10021 /*
10022 * We weren't allowed to disconnect.
10023 * We're hanging on the bus until a
10024 * continue target I/O comes in response
10025 * to this accept tio.
10026 */
10027 #ifdef AHD_DEBUG
10031 #endif
10035 }
10038 }
10040 #endif