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au1550_spi: fix prototype of irq handler
[wrt350n-kernel.git] / drivers / scsi / nsp32.c
blob7fed35372150afe68d619d61d4faa4a2a4588437
1 /*
2 * NinjaSCSI-32Bi Cardbus, NinjaSCSI-32UDE PCI/CardBus SCSI driver
3 * Copyright (C) 2001, 2002, 2003
4 * YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>
5 * GOTO Masanori <gotom@debian.or.jp>, <gotom@debian.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 *
18 * Revision History:
19 * 1.0: Initial Release.
20 * 1.1: Add /proc SDTR status.
21 * Remove obsolete error handler nsp32_reset.
22 * Some clean up.
23 * 1.2: PowerPC (big endian) support.
24 */
25
26 #include <linux/version.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/timer.h>
33 #include <linux/ioport.h>
34 #include <linux/major.h>
35 #include <linux/blkdev.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/ctype.h>
40 #include <linux/dma-mapping.h>
41
42 #include <asm/dma.h>
43 #include <asm/system.h>
44 #include <asm/io.h>
45
46 #include <scsi/scsi.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <scsi/scsi_device.h>
49 #include <scsi/scsi_host.h>
50 #include <scsi/scsi_ioctl.h>
51
52 #include "nsp32.h"
53
54
55 /***********************************************************************
56 * Module parameters
57 */
58 static int trans_mode = 0; /* default: BIOS */
59 module_param (trans_mode, int, 0);
60 MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
61 #define ASYNC_MODE 1
62 #define ULTRA20M_MODE 2
63
64 static int auto_param = 0; /* default: ON */
65 module_param (auto_param, bool, 0);
66 MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
67
68 static int disc_priv = 1; /* default: OFF */
69 module_param (disc_priv, bool, 0);
70 MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
71
72 MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
73 MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
74 MODULE_LICENSE("GPL");
75
76 static const char *nsp32_release_version = "1.2";
77
78
79 /****************************************************************************
80 * Supported hardware
81 */
82 static struct pci_device_id nsp32_pci_table[] __devinitdata = {
83 {
84 .vendor = PCI_VENDOR_ID_IODATA,
85 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
86 .subvendor = PCI_ANY_ID,
87 .subdevice = PCI_ANY_ID,
88 .driver_data = MODEL_IODATA,
89 },
90 {
91 .vendor = PCI_VENDOR_ID_WORKBIT,
92 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
93 .subvendor = PCI_ANY_ID,
94 .subdevice = PCI_ANY_ID,
95 .driver_data = MODEL_KME,
96 },
97 {
98 .vendor = PCI_VENDOR_ID_WORKBIT,
99 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
100 .subvendor = PCI_ANY_ID,
101 .subdevice = PCI_ANY_ID,
102 .driver_data = MODEL_WORKBIT,
103 },
104 {
105 .vendor = PCI_VENDOR_ID_WORKBIT,
106 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
107 .subvendor = PCI_ANY_ID,
108 .subdevice = PCI_ANY_ID,
109 .driver_data = MODEL_PCI_WORKBIT,
110 },
111 {
112 .vendor = PCI_VENDOR_ID_WORKBIT,
113 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
114 .subvendor = PCI_ANY_ID,
115 .subdevice = PCI_ANY_ID,
116 .driver_data = MODEL_LOGITEC,
117 },
118 {
119 .vendor = PCI_VENDOR_ID_WORKBIT,
120 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
121 .subvendor = PCI_ANY_ID,
122 .subdevice = PCI_ANY_ID,
123 .driver_data = MODEL_PCI_LOGITEC,
124 },
125 {
126 .vendor = PCI_VENDOR_ID_WORKBIT,
127 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
128 .subvendor = PCI_ANY_ID,
129 .subdevice = PCI_ANY_ID,
130 .driver_data = MODEL_PCI_MELCO,
131 },
132 {
133 .vendor = PCI_VENDOR_ID_WORKBIT,
134 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
135 .subvendor = PCI_ANY_ID,
136 .subdevice = PCI_ANY_ID,
137 .driver_data = MODEL_PCI_MELCO,
138 },
139 {0,0,},
140 };
141 MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
142
143 static nsp32_hw_data nsp32_data_base; /* probe <-> detect glue */
144
145
146 /*
147 * Period/AckWidth speed conversion table
148 *
149 * Note: This period/ackwidth speed table must be in descending order.
150 */
151 static nsp32_sync_table nsp32_sync_table_40M[] = {
152 /* {PNo, AW, SP, EP, SREQ smpl} Speed(MB/s) Period AckWidth */
153 {0x1, 0, 0x0c, 0x0c, SMPL_40M}, /* 20.0 : 50ns, 25ns */
154 {0x2, 0, 0x0d, 0x18, SMPL_40M}, /* 13.3 : 75ns, 25ns */
155 {0x3, 1, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
156 {0x4, 1, 0x1a, 0x1f, SMPL_20M}, /* 8.0 : 125ns, 50ns */
157 {0x5, 2, 0x20, 0x25, SMPL_20M}, /* 6.7 : 150ns, 75ns */
158 {0x6, 2, 0x26, 0x31, SMPL_20M}, /* 5.7 : 175ns, 75ns */
159 {0x7, 3, 0x32, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
160 {0x8, 3, 0x33, 0x38, SMPL_10M}, /* 4.4 : 225ns, 100ns */
161 {0x9, 3, 0x39, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
162 };
163
164 static nsp32_sync_table nsp32_sync_table_20M[] = {
165 {0x1, 0, 0x19, 0x19, SMPL_40M}, /* 10.0 : 100ns, 50ns */
166 {0x2, 0, 0x1a, 0x25, SMPL_20M}, /* 6.7 : 150ns, 50ns */
167 {0x3, 1, 0x26, 0x32, SMPL_20M}, /* 5.0 : 200ns, 100ns */
168 {0x4, 1, 0x33, 0x3e, SMPL_10M}, /* 4.0 : 250ns, 100ns */
169 {0x5, 2, 0x3f, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 150ns */
170 {0x6, 2, 0x4c, 0x57, SMPL_10M}, /* 2.8 : 350ns, 150ns */
171 {0x7, 3, 0x58, 0x64, SMPL_10M}, /* 2.5 : 400ns, 200ns */
172 {0x8, 3, 0x65, 0x70, SMPL_10M}, /* 2.2 : 450ns, 200ns */
173 {0x9, 3, 0x71, 0x7d, SMPL_10M}, /* 2.0 : 500ns, 200ns */
174 };
175
176 static nsp32_sync_table nsp32_sync_table_pci[] = {
177 {0x1, 0, 0x0c, 0x0f, SMPL_40M}, /* 16.6 : 60ns, 30ns */
178 {0x2, 0, 0x10, 0x16, SMPL_40M}, /* 11.1 : 90ns, 30ns */
179 {0x3, 1, 0x17, 0x1e, SMPL_20M}, /* 8.3 : 120ns, 60ns */
180 {0x4, 1, 0x1f, 0x25, SMPL_20M}, /* 6.7 : 150ns, 60ns */
181 {0x5, 2, 0x26, 0x2d, SMPL_20M}, /* 5.6 : 180ns, 90ns */
182 {0x6, 2, 0x2e, 0x34, SMPL_10M}, /* 4.8 : 210ns, 90ns */
183 {0x7, 3, 0x35, 0x3c, SMPL_10M}, /* 4.2 : 240ns, 120ns */
184 {0x8, 3, 0x3d, 0x43, SMPL_10M}, /* 3.7 : 270ns, 120ns */
185 {0x9, 3, 0x44, 0x4b, SMPL_10M}, /* 3.3 : 300ns, 120ns */
186 };
187
188 /*
189 * function declaration
190 */
191 /* module entry point */
192 static int __devinit nsp32_probe (struct pci_dev *, const struct pci_device_id *);
193 static void __devexit nsp32_remove(struct pci_dev *);
194 static int __init init_nsp32 (void);
195 static void __exit exit_nsp32 (void);
196
197 /* struct struct scsi_host_template */
198 static int nsp32_proc_info (struct Scsi_Host *, char *, char **, off_t, int, int);
199
200 static int nsp32_detect (struct pci_dev *pdev);
201 static int nsp32_queuecommand(struct scsi_cmnd *,
202 void (*done)(struct scsi_cmnd *));
203 static const char *nsp32_info (struct Scsi_Host *);
204 static int nsp32_release (struct Scsi_Host *);
205
206 /* SCSI error handler */
207 static int nsp32_eh_abort (struct scsi_cmnd *);
208 static int nsp32_eh_bus_reset (struct scsi_cmnd *);
209 static int nsp32_eh_host_reset(struct scsi_cmnd *);
210
211 /* generate SCSI message */
212 static void nsp32_build_identify(struct scsi_cmnd *);
213 static void nsp32_build_nop (struct scsi_cmnd *);
214 static void nsp32_build_reject (struct scsi_cmnd *);
215 static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, unsigned char);
216
217 /* SCSI message handler */
218 static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
219 static void nsp32_msgout_occur (struct scsi_cmnd *);
220 static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, unsigned short);
221
222 static int nsp32_setup_sg_table (struct scsi_cmnd *);
223 static int nsp32_selection_autopara(struct scsi_cmnd *);
224 static int nsp32_selection_autoscsi(struct scsi_cmnd *);
225 static void nsp32_scsi_done (struct scsi_cmnd *);
226 static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
227 static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
228 static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
229 static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
230
231 /* SCSI SDTR */
232 static void nsp32_analyze_sdtr (struct scsi_cmnd *);
233 static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, unsigned char);
234 static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
235 static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, unsigned char *, unsigned char *);
236 static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, int, unsigned char);
237
238 /* SCSI bus status handler */
239 static void nsp32_wait_req (nsp32_hw_data *, int);
240 static void nsp32_wait_sack (nsp32_hw_data *, int);
241 static void nsp32_sack_assert (nsp32_hw_data *);
242 static void nsp32_sack_negate (nsp32_hw_data *);
243 static void nsp32_do_bus_reset(nsp32_hw_data *);
244
245 /* hardware interrupt handler */
246 static irqreturn_t do_nsp32_isr(int, void *);
247
248 /* initialize hardware */
249 static int nsp32hw_init(nsp32_hw_data *);
250
251 /* EEPROM handler */
252 static int nsp32_getprom_param (nsp32_hw_data *);
253 static int nsp32_getprom_at24 (nsp32_hw_data *);
254 static int nsp32_getprom_c16 (nsp32_hw_data *);
255 static void nsp32_prom_start (nsp32_hw_data *);
256 static void nsp32_prom_stop (nsp32_hw_data *);
257 static int nsp32_prom_read (nsp32_hw_data *, int);
258 static int nsp32_prom_read_bit (nsp32_hw_data *);
259 static void nsp32_prom_write_bit(nsp32_hw_data *, int);
260 static void nsp32_prom_set (nsp32_hw_data *, int, int);
261 static int nsp32_prom_get (nsp32_hw_data *, int);
262
263 /* debug/warning/info message */
264 static void nsp32_message (const char *, int, char *, char *, ...);
265 #ifdef NSP32_DEBUG
266 static void nsp32_dmessage(const char *, int, int, char *, ...);
267 #endif
268
269 /*
270 * max_sectors is currently limited up to 128.
271 */
272 static struct scsi_host_template nsp32_template = {
273 .proc_name = "nsp32",
274 .name = "Workbit NinjaSCSI-32Bi/UDE",
275 .proc_info = nsp32_proc_info,
276 .info = nsp32_info,
277 .queuecommand = nsp32_queuecommand,
278 .can_queue = 1,
279 .sg_tablesize = NSP32_SG_SIZE,
280 .max_sectors = 128,
281 .cmd_per_lun = 1,
282 .this_id = NSP32_HOST_SCSIID,
283 .use_clustering = DISABLE_CLUSTERING,
284 .eh_abort_handler = nsp32_eh_abort,
285 .eh_bus_reset_handler = nsp32_eh_bus_reset,
286 .eh_host_reset_handler = nsp32_eh_host_reset,
287 /* .highmem_io = 1, */
288 };
289
290 #include "nsp32_io.h"
291
292 /***********************************************************************
293 * debug, error print
294 */
295 #ifndef NSP32_DEBUG
296 # define NSP32_DEBUG_MASK 0x000000
297 # define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
298 # define nsp32_dbg(mask, args...) /* */
299 #else
300 # define NSP32_DEBUG_MASK 0xffffff
301 # define nsp32_msg(type, args...) \
302 nsp32_message (__FUNCTION__, __LINE__, (type), args)
303 # define nsp32_dbg(mask, args...) \
304 nsp32_dmessage(__FUNCTION__, __LINE__, (mask), args)
305 #endif
306
307 #define NSP32_DEBUG_QUEUECOMMAND BIT(0)
308 #define NSP32_DEBUG_REGISTER BIT(1)
309 #define NSP32_DEBUG_AUTOSCSI BIT(2)
310 #define NSP32_DEBUG_INTR BIT(3)
311 #define NSP32_DEBUG_SGLIST BIT(4)
312 #define NSP32_DEBUG_BUSFREE BIT(5)
313 #define NSP32_DEBUG_CDB_CONTENTS BIT(6)
314 #define NSP32_DEBUG_RESELECTION BIT(7)
315 #define NSP32_DEBUG_MSGINOCCUR BIT(8)
316 #define NSP32_DEBUG_EEPROM BIT(9)
317 #define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
318 #define NSP32_DEBUG_BUSRESET BIT(11)
319 #define NSP32_DEBUG_RESTART BIT(12)
320 #define NSP32_DEBUG_SYNC BIT(13)
321 #define NSP32_DEBUG_WAIT BIT(14)
322 #define NSP32_DEBUG_TARGETFLAG BIT(15)
323 #define NSP32_DEBUG_PROC BIT(16)
324 #define NSP32_DEBUG_INIT BIT(17)
325 #define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
326
327 #define NSP32_DEBUG_BUF_LEN 100
328
329 static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
330 {
331 va_list args;
332 char buf[NSP32_DEBUG_BUF_LEN];
333
334 va_start(args, fmt);
335 vsnprintf(buf, sizeof(buf), fmt, args);
336 va_end(args);
337
338 #ifndef NSP32_DEBUG
339 printk("%snsp32: %s\n", type, buf);
340 #else
341 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
342 #endif
343 }
344
345 #ifdef NSP32_DEBUG
346 static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
347 {
348 va_list args;
349 char buf[NSP32_DEBUG_BUF_LEN];
350
351 va_start(args, fmt);
352 vsnprintf(buf, sizeof(buf), fmt, args);
353 va_end(args);
354
355 if (mask & NSP32_DEBUG_MASK) {
356 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
357 }
358 }
359 #endif
360
361 #ifdef NSP32_DEBUG
362 # include "nsp32_debug.c"
363 #else
364 # define show_command(arg) /* */
365 # define show_busphase(arg) /* */
366 # define show_autophase(arg) /* */
367 #endif
368
369 /*
370 * IDENTIFY Message
371 */
372 static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
373 {
374 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
375 int pos = data->msgout_len;
376 int mode = FALSE;
377
378 /* XXX: Auto DiscPriv detection is progressing... */
379 if (disc_priv == 0) {
380 /* mode = TRUE; */
381 }
382
383 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
384
385 data->msgout_len = pos;
386 }
387
388 /*
389 * SDTR Message Routine
390 */
391 static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
392 unsigned char period,
393 unsigned char offset)
394 {
395 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
396 int pos = data->msgout_len;
397
398 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
399 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
400 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
401 data->msgoutbuf[pos] = period; pos++;
402 data->msgoutbuf[pos] = offset; pos++;
403
404 data->msgout_len = pos;
405 }
406
407 /*
408 * No Operation Message
409 */
410 static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
411 {
412 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
413 int pos = data->msgout_len;
414
415 if (pos != 0) {
416 nsp32_msg(KERN_WARNING,
417 "Some messages are already contained!");
418 return;
419 }
420
421 data->msgoutbuf[pos] = NOP; pos++;
422 data->msgout_len = pos;
423 }
424
425 /*
426 * Reject Message
427 */
428 static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
429 {
430 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
431 int pos = data->msgout_len;
432
433 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
434 data->msgout_len = pos;
435 }
436
437 /*
438 * timer
439 */
440 #if 0
441 static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
442 {
443 unsigned int base = SCpnt->host->io_port;
444
445 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
446
447 if (time & (~TIMER_CNT_MASK)) {
448 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
449 }
450
451 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
452 }
453 #endif
454
455
456 /*
457 * set SCSI command and other parameter to asic, and start selection phase
458 */
459 static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
460 {
461 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
462 unsigned int base = SCpnt->device->host->io_port;
463 unsigned int host_id = SCpnt->device->host->this_id;
464 unsigned char target = scmd_id(SCpnt);
465 nsp32_autoparam *param = data->autoparam;
466 unsigned char phase;
467 int i, ret;
468 unsigned int msgout;
469 u16_le s;
470
471 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
472
473 /*
474 * check bus free
475 */
476 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
477 if (phase != BUSMON_BUS_FREE) {
478 nsp32_msg(KERN_WARNING, "bus busy");
479 show_busphase(phase & BUSMON_PHASE_MASK);
480 SCpnt->result = DID_BUS_BUSY << 16;
481 return FALSE;
482 }
483
484 /*
485 * message out
486 *
487 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
488 * over 3 messages needs another routine.
489 */
490 if (data->msgout_len == 0) {
491 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
492 SCpnt->result = DID_ERROR << 16;
493 return FALSE;
494 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
495 msgout = 0;
496 for (i = 0; i < data->msgout_len; i++) {
497 /*
498 * the sending order of the message is:
499 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
500 * MCNT 2: MSG#1 -> MSG#2
501 * MCNT 1: MSG#2
502 */
503 msgout >>= 8;
504 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
505 }
506 msgout |= MV_VALID; /* MV valid */
507 msgout |= (unsigned int)data->msgout_len; /* len */
508 } else {
509 /* data->msgout_len > 3 */
510 msgout = 0;
511 }
512
513 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n", nsp32_read2(base, SEL_TIME_OUT));
514 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
515
516 /*
517 * setup asic parameter
518 */
519 memset(param, 0, sizeof(nsp32_autoparam));
520
521 /* cdb */
522 for (i = 0; i < SCpnt->cmd_len; i++) {
523 param->cdb[4 * i] = SCpnt->cmnd[i];
524 }
525
526 /* outgoing messages */
527 param->msgout = cpu_to_le32(msgout);
528
529 /* syncreg, ackwidth, target id, SREQ sampling rate */
530 param->syncreg = data->cur_target->syncreg;
531 param->ackwidth = data->cur_target->ackwidth;
532 param->target_id = BIT(host_id) | BIT(target);
533 param->sample_reg = data->cur_target->sample_reg;
534
535 // nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "sample rate=0x%x\n", data->cur_target->sample_reg);
536
537 /* command control */
538 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
539 AUTOSCSI_START |
540 AUTO_MSGIN_00_OR_04 |
541 AUTO_MSGIN_02 |
542 AUTO_ATN );
543
544
545 /* transfer control */
546 s = 0;
547 switch (data->trans_method) {
548 case NSP32_TRANSFER_BUSMASTER:
549 s |= BM_START;
550 break;
551 case NSP32_TRANSFER_MMIO:
552 s |= CB_MMIO_MODE;
553 break;
554 case NSP32_TRANSFER_PIO:
555 s |= CB_IO_MODE;
556 break;
557 default:
558 nsp32_msg(KERN_ERR, "unknown trans_method");
559 break;
560 }
561 /*
562 * OR-ed BLIEND_MODE, FIFO intr is decreased, instead of PCI bus waits.
563 * For bus master transfer, it's taken off.
564 */
565 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
566 param->transfer_control = cpu_to_le16(s);
567
568 /* sg table addr */
569 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
570
571 /*
572 * transfer parameter to ASIC
573 */
574 nsp32_write4(base, SGT_ADR, data->auto_paddr);
575 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER |
576 AUTO_PARAMETER );
577
578 /*
579 * Check arbitration
580 */
581 ret = nsp32_arbitration(SCpnt, base);
582
583 return ret;
584 }
585
586
587 /*
588 * Selection with AUTO SCSI (without AUTO PARAMETER)
589 */
590 static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
591 {
592 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
593 unsigned int base = SCpnt->device->host->io_port;
594 unsigned int host_id = SCpnt->device->host->this_id;
595 unsigned char target = scmd_id(SCpnt);
596 unsigned char phase;
597 int status;
598 unsigned short command = 0;
599 unsigned int msgout = 0;
600 unsigned short execph;
601 int i;
602
603 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
604
605 /*
606 * IRQ disable
607 */
608 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
609
610 /*
611 * check bus line
612 */
613 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
614 if(((phase & BUSMON_BSY) == 1) || (phase & BUSMON_SEL) == 1) {
615 nsp32_msg(KERN_WARNING, "bus busy");
616 SCpnt->result = DID_BUS_BUSY << 16;
617 status = 1;
618 goto out;
619 }
620
621 /*
622 * clear execph
623 */
624 execph = nsp32_read2(base, SCSI_EXECUTE_PHASE);
625
626 /*
627 * clear FIFO counter to set CDBs
628 */
629 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
630
631 /*
632 * set CDB0 - CDB15
633 */
634 for (i = 0; i < SCpnt->cmd_len; i++) {
635 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
636 }
637 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
638
639 /*
640 * set SCSIOUT LATCH(initiator)/TARGET(target) (OR-ed) ID
641 */
642 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target));
643
644 /*
645 * set SCSI MSGOUT REG
646 *
647 * Note: If the range of msgout_len is 1 - 3, fill scsi_msgout.
648 * over 3 messages needs another routine.
649 */
650 if (data->msgout_len == 0) {
651 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
652 SCpnt->result = DID_ERROR << 16;
653 status = 1;
654 goto out;
655 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
656 msgout = 0;
657 for (i = 0; i < data->msgout_len; i++) {
658 /*
659 * the sending order of the message is:
660 * MCNT 3: MSG#0 -> MSG#1 -> MSG#2
661 * MCNT 2: MSG#1 -> MSG#2
662 * MCNT 1: MSG#2
663 */
664 msgout >>= 8;
665 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
666 }
667 msgout |= MV_VALID; /* MV valid */
668 msgout |= (unsigned int)data->msgout_len; /* len */
669 nsp32_write4(base, SCSI_MSG_OUT, msgout);
670 } else {
671 /* data->msgout_len > 3 */
672 nsp32_write4(base, SCSI_MSG_OUT, 0);
673 }
674
675 /*
676 * set selection timeout(= 250ms)
677 */
678 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
679
680 /*
681 * set SREQ hazard killer sampling rate
682 *
683 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz.
684 * check other internal clock!
685 */
686 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
687
688 /*
689 * clear Arbit
690 */
691 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
692
693 /*
694 * set SYNCREG
695 * Don't set BM_START_ADR before setting this register.
696 */
697 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
698
699 /*
700 * set ACKWIDTH
701 */
702 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
703
704 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
705 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
706 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
707 nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
708 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
709 data->msgout_len, msgout);
710
711 /*
712 * set SGT ADDR (physical address)
713 */
714 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
715
716 /*
717 * set TRANSFER CONTROL REG
718 */
719 command = 0;
720 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
721 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
722 if (scsi_bufflen(SCpnt) > 0) {
723 command |= BM_START;
724 }
725 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
726 command |= CB_MMIO_MODE;
727 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
728 command |= CB_IO_MODE;
729 }
730 nsp32_write2(base, TRANSFER_CONTROL, command);
731
732 /*
733 * start AUTO SCSI, kick off arbitration
734 */
735 command = (CLEAR_CDB_FIFO_POINTER |
736 AUTOSCSI_START |
737 AUTO_MSGIN_00_OR_04 |
738 AUTO_MSGIN_02 |
739 AUTO_ATN );
740 nsp32_write2(base, COMMAND_CONTROL, command);
741
742 /*
743 * Check arbitration
744 */
745 status = nsp32_arbitration(SCpnt, base);
746
747 out:
748 /*
749 * IRQ enable
750 */
751 nsp32_write2(base, IRQ_CONTROL, 0);
752
753 return status;
754 }
755
756
757 /*
758 * Arbitration Status Check
759 *
760 * Note: Arbitration counter is waited during ARBIT_GO is not lifting.
761 * Using udelay(1) consumes CPU time and system time, but
762 * arbitration delay time is defined minimal 2.4us in SCSI
763 * specification, thus udelay works as coarse grained wait timer.
764 */
765 static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
766 {
767 unsigned char arbit;
768 int status = TRUE;
769 int time = 0;
770
771 do {
772 arbit = nsp32_read1(base, ARBIT_STATUS);
773 time++;
774 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
775 (time <= ARBIT_TIMEOUT_TIME));
776
777 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
778 "arbit: 0x%x, delay time: %d", arbit, time);
779
780 if (arbit & ARBIT_WIN) {
781 /* Arbitration succeeded */
782 SCpnt->result = DID_OK << 16;
783 nsp32_index_write1(base, EXT_PORT, LED_ON); /* PCI LED on */
784 } else if (arbit & ARBIT_FAIL) {
785 /* Arbitration failed */
786 SCpnt->result = DID_BUS_BUSY << 16;
787 status = FALSE;
788 } else {
789 /*
790 * unknown error or ARBIT_GO timeout,
791 * something lock up! guess no connection.
792 */
793 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
794 SCpnt->result = DID_NO_CONNECT << 16;
795 status = FALSE;
796 }
797
798 /*
799 * clear Arbit
800 */
801 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
802
803 return status;
804 }
805
806
807 /*
808 * reselection
809 *
810 * Note: This reselection routine is called from msgin_occur,
811 * reselection target id&lun must be already set.
812 * SCSI-2 says IDENTIFY implies RESTORE_POINTER operation.
813 */
814 static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
815 {
816 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
817 unsigned int host_id = SCpnt->device->host->this_id;
818 unsigned int base = SCpnt->device->host->io_port;
819 unsigned char tmpid, newid;
820
821 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
822
823 /*
824 * calculate reselected SCSI ID
825 */
826 tmpid = nsp32_read1(base, RESELECT_ID);
827 tmpid &= (~BIT(host_id));
828 newid = 0;
829 while (tmpid) {
830 if (tmpid & 1) {
831 break;
832 }
833 tmpid >>= 1;
834 newid++;
835 }
836
837 /*
838 * If reselected New ID:LUN is not existed
839 * or current nexus is not existed, unexpected
840 * reselection is occurred. Send reject message.
841 */
842 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) {
843 nsp32_msg(KERN_WARNING, "unknown id/lun");
844 return FALSE;
845 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
846 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
847 return FALSE;
848 }
849
850 data->cur_id = newid;
851 data->cur_lun = newlun;
852 data->cur_target = &(data->target[newid]);
853 data->cur_lunt = &(data->lunt[newid][newlun]);
854
855 /* reset SACK/SavedACK counter (or ALL clear?) */
856 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
857
858 return TRUE;
859 }
860
861
862 /*
863 * nsp32_setup_sg_table - build scatter gather list for transfer data
864 * with bus master.
865 *
866 * Note: NinjaSCSI-32Bi/UDE bus master can not transfer over 64KB at a time.
867 */
868 static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
869 {
870 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
871 struct scatterlist *sg;
872 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
873 int num, i;
874 u32_le l;
875
876 if (sgt == NULL) {
877 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
878 return FALSE;
879 }
880
881 num = scsi_dma_map(SCpnt);
882 if (!num)
883 return TRUE;
884 else if (num < 0)
885 return FALSE;
886 else {
887 scsi_for_each_sg(SCpnt, sg, num, i) {
888 /*
889 * Build nsp32_sglist, substitute sg dma addresses.
890 */
891 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
892 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
893
894 if (le32_to_cpu(sgt[i].len) > 0x10000) {
895 nsp32_msg(KERN_ERR,
896 "can't transfer over 64KB at a time, size=0x%lx", le32_to_cpu(sgt[i].len));
897 return FALSE;
898 }
899 nsp32_dbg(NSP32_DEBUG_SGLIST,
900 "num 0x%x : addr 0x%lx len 0x%lx",
901 i,
902 le32_to_cpu(sgt[i].addr),
903 le32_to_cpu(sgt[i].len ));
904 }
905
906 /* set end mark */
907 l = le32_to_cpu(sgt[num-1].len);
908 sgt[num-1].len = cpu_to_le32(l | SGTEND);
909 }
910
911 return TRUE;
912 }
913
914 static int nsp32_queuecommand(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
915 {
916 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
917 nsp32_target *target;
918 nsp32_lunt *cur_lunt;
919 int ret;
920
921 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
922 "enter. target: 0x%x LUN: 0x%x cmnd: 0x%x cmndlen: 0x%x "
923 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
924 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], SCpnt->cmd_len,
925 scsi_sg_count(SCpnt), scsi_sglist(SCpnt), scsi_bufflen(SCpnt));
926
927 if (data->CurrentSC != NULL) {
928 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
929 data->CurrentSC = NULL;
930 SCpnt->result = DID_NO_CONNECT << 16;
931 done(SCpnt);
932 return 0;
933 }
934
935 /* check target ID is not same as this initiator ID */
936 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
937 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "terget==host???");
938 SCpnt->result = DID_BAD_TARGET << 16;
939 done(SCpnt);
940 return 0;
941 }
942
943 /* check target LUN is allowable value */
944 if (SCpnt->device->lun >= MAX_LUN) {
945 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
946 SCpnt->result = DID_BAD_TARGET << 16;
947 done(SCpnt);
948 return 0;
949 }
950
951 show_command(SCpnt);
952
953 SCpnt->scsi_done = done;
954 data->CurrentSC = SCpnt;
955 SCpnt->SCp.Status = CHECK_CONDITION;
956 SCpnt->SCp.Message = 0;
957 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
958
959 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt);
960 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt);
961 SCpnt->SCp.buffer = NULL;
962 SCpnt->SCp.buffers_residual = 0;
963
964 /* initialize data */
965 data->msgout_len = 0;
966 data->msgin_len = 0;
967 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
968 cur_lunt->SCpnt = SCpnt;
969 cur_lunt->save_datp = 0;
970 cur_lunt->msgin03 = FALSE;
971 data->cur_lunt = cur_lunt;
972 data->cur_id = SCpnt->device->id;
973 data->cur_lun = SCpnt->device->lun;
974
975 ret = nsp32_setup_sg_table(SCpnt);
976 if (ret == FALSE) {
977 nsp32_msg(KERN_ERR, "SGT fail");
978 SCpnt->result = DID_ERROR << 16;
979 nsp32_scsi_done(SCpnt);
980 return 0;
981 }
982
983 /* Build IDENTIFY */
984 nsp32_build_identify(SCpnt);
985
986 /*
987 * If target is the first time to transfer after the reset
988 * (target don't have SDTR_DONE and SDTR_INITIATOR), sync
989 * message SDTR is needed to do synchronous transfer.
990 */
991 target = &data->target[scmd_id(SCpnt)];
992 data->cur_target = target;
993
994 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
995 unsigned char period, offset;
996
997 if (trans_mode != ASYNC_MODE) {
998 nsp32_set_max_sync(data, target, &period, &offset);
999 nsp32_build_sdtr(SCpnt, period, offset);
1000 target->sync_flag |= SDTR_INITIATOR;
1001 } else {
1002 nsp32_set_async(data, target);
1003 target->sync_flag |= SDTR_DONE;
1004 }
1005
1006 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1007 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
1008 target->limit_entry, period, offset);
1009 } else if (target->sync_flag & SDTR_INITIATOR) {
1010 /*
1011 * It was negotiating SDTR with target, sending from the
1012 * initiator, but there are no chance to remove this flag.
1013 * Set async because we don't get proper negotiation.
1014 */
1015 nsp32_set_async(data, target);
1016 target->sync_flag &= ~SDTR_INITIATOR;
1017 target->sync_flag |= SDTR_DONE;
1018
1019 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1020 "SDTR_INITIATOR: fall back to async");
1021 } else if (target->sync_flag & SDTR_TARGET) {
1022 /*
1023 * It was negotiating SDTR with target, sending from target,
1024 * but there are no chance to remove this flag. Set async
1025 * because we don't get proper negotiation.
1026 */
1027 nsp32_set_async(data, target);
1028 target->sync_flag &= ~SDTR_TARGET;
1029 target->sync_flag |= SDTR_DONE;
1030
1031 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1032 "Unknown SDTR from target is reached, fall back to async.");
1033 }
1034
1035 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1036 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1037 SCpnt->device->id, target->sync_flag, target->syncreg,
1038 target->ackwidth);
1039
1040 /* Selection */
1041 if (auto_param == 0) {
1042 ret = nsp32_selection_autopara(SCpnt);
1043 } else {
1044 ret = nsp32_selection_autoscsi(SCpnt);
1045 }
1046
1047 if (ret != TRUE) {
1048 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1049 nsp32_scsi_done(SCpnt);
1050 }
1051
1052 return 0;
1053 }
1054
1055 /* initialize asic */
1056 static int nsp32hw_init(nsp32_hw_data *data)
1057 {
1058 unsigned int base = data->BaseAddress;
1059 unsigned short irq_stat;
1060 unsigned long lc_reg;
1061 unsigned char power;
1062
1063 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1064 if ((lc_reg & 0xff00) == 0) {
1065 lc_reg |= (0x20 << 8);
1066 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1067 }
1068
1069 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1070 nsp32_write2(base, TRANSFER_CONTROL, 0);
1071 nsp32_write4(base, BM_CNT, 0);
1072 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1073
1074 do {
1075 irq_stat = nsp32_read2(base, IRQ_STATUS);
1076 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1077 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1078
1079 /*
1080 * Fill FIFO_FULL_SHLD, FIFO_EMPTY_SHLD. Below parameter is
1081 * designated by specification.
1082 */
1083 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1084 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1085 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1086 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1087 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1088 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1089 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1090 } else {
1091 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1092 }
1093
1094 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1095 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1096 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1097
1098 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1099 nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1100 nsp32_write1(base, PARITY_CONTROL, 0); /* parity check is disable */
1101
1102 /*
1103 * initialize MISC_WRRD register
1104 *
1105 * Note: Designated parameters is obeyed as following:
1106 * MISC_SCSI_DIRECTION_DETECTOR_SELECT: It must be set.
1107 * MISC_MASTER_TERMINATION_SELECT: It must be set.
1108 * MISC_BMREQ_NEGATE_TIMING_SEL: It should be set.
1109 * MISC_AUTOSEL_TIMING_SEL: It should be set.
1110 * MISC_BMSTOP_CHANGE2_NONDATA_PHASE: It should be set.
1111 * MISC_DELAYED_BMSTART: It's selected for safety.
1112 *
1113 * Note: If MISC_BMSTOP_CHANGE2_NONDATA_PHASE is set, then
1114 * we have to set TRANSFERCONTROL_BM_START as 0 and set
1115 * appropriate value before restarting bus master transfer.
1116 */
1117 nsp32_index_write2(base, MISC_WR,
1118 (SCSI_DIRECTION_DETECTOR_SELECT |
1119 DELAYED_BMSTART |
1120 MASTER_TERMINATION_SELECT |
1121 BMREQ_NEGATE_TIMING_SEL |
1122 AUTOSEL_TIMING_SEL |
1123 BMSTOP_CHANGE2_NONDATA_PHASE));
1124
1125 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1126 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1127 if (!(power & SENSE)) {
1128 nsp32_msg(KERN_INFO, "term power on");
1129 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1130 }
1131
1132 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1133 nsp32_write2(base, TIMER_SET, TIMER_STOP); /* Required 2 times */
1134
1135 nsp32_write1(base, SYNC_REG, 0);
1136 nsp32_write1(base, ACK_WIDTH, 0);
1137 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1138
1139 /*
1140 * enable to select designated IRQ (except for
1141 * IRQSELECT_SERR, IRQSELECT_PERR, IRQSELECT_BMCNTERR)
1142 */
1143 nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ |
1144 IRQSELECT_SCSIRESET_IRQ |
1145 IRQSELECT_FIFO_SHLD_IRQ |
1146 IRQSELECT_RESELECT_IRQ |
1147 IRQSELECT_PHASE_CHANGE_IRQ |
1148 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1149 // IRQSELECT_BMCNTERR_IRQ |
1150 IRQSELECT_TARGET_ABORT_IRQ |
1151 IRQSELECT_MASTER_ABORT_IRQ );
1152 nsp32_write2(base, IRQ_CONTROL, 0);
1153
1154 /* PCI LED off */
1155 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1156 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1157
1158 return TRUE;
1159 }
1160
1161
1162 /* interrupt routine */
1163 static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1164 {
1165 nsp32_hw_data *data = dev_id;
1166 unsigned int base = data->BaseAddress;
1167 struct scsi_cmnd *SCpnt = data->CurrentSC;
1168 unsigned short auto_stat, irq_stat, trans_stat;
1169 unsigned char busmon, busphase;
1170 unsigned long flags;
1171 int ret;
1172 int handled = 0;
1173 struct Scsi_Host *host = data->Host;
1174
1175 spin_lock_irqsave(host->host_lock, flags);
1176
1177 /*
1178 * IRQ check, then enable IRQ mask
1179 */
1180 irq_stat = nsp32_read2(base, IRQ_STATUS);
1181 nsp32_dbg(NSP32_DEBUG_INTR,
1182 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1183 /* is this interrupt comes from Ninja asic? */
1184 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1185 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);
1186 goto out2;
1187 }
1188 handled = 1;
1189 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1190
1191 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1192 busphase = busmon & BUSMON_PHASE_MASK;
1193
1194 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1195 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1196 nsp32_msg(KERN_INFO, "card disconnect");
1197 if (data->CurrentSC != NULL) {
1198 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1199 SCpnt->result = DID_BAD_TARGET << 16;
1200 nsp32_scsi_done(SCpnt);
1201 }
1202 goto out;
1203 }
1204
1205 /* Timer IRQ */
1206 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1207 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1208 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1209 goto out;
1210 }
1211
1212 /* SCSI reset */
1213 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1214 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1215 nsp32_do_bus_reset(data);
1216 if (SCpnt != NULL) {
1217 SCpnt->result = DID_RESET << 16;
1218 nsp32_scsi_done(SCpnt);
1219 }
1220 goto out;
1221 }
1222
1223 if (SCpnt == NULL) {
1224 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1225 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1226 goto out;
1227 }
1228
1229 /*
1230 * AutoSCSI Interrupt.
1231 * Note: This interrupt is occurred when AutoSCSI is finished. Then
1232 * check SCSIEXECUTEPHASE, and do appropriate action. Each phases are
1233 * recorded when AutoSCSI sequencer has been processed.
1234 */
1235 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1236 /* getting SCSI executed phase */
1237 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1238 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1239
1240 /* Selection Timeout, go busfree phase. */
1241 if (auto_stat & SELECTION_TIMEOUT) {
1242 nsp32_dbg(NSP32_DEBUG_INTR,
1243 "selection timeout occurred");
1244
1245 SCpnt->result = DID_TIME_OUT << 16;
1246 nsp32_scsi_done(SCpnt);
1247 goto out;
1248 }
1249
1250 if (auto_stat & MSGOUT_PHASE) {
1251 /*
1252 * MsgOut phase was processed.
1253 * If MSG_IN_OCCUER is not set, then MsgOut phase is
1254 * completed. Thus, msgout_len must reset. Otherwise,
1255 * nothing to do here. If MSG_OUT_OCCUER is occurred,
1256 * then we will encounter the condition and check.
1257 */
1258 if (!(auto_stat & MSG_IN_OCCUER) &&
1259 (data->msgout_len <= 3)) {
1260 /*
1261 * !MSG_IN_OCCUER && msgout_len <=3
1262 * ---> AutoSCSI with MSGOUTreg is processed.
1263 */
1264 data->msgout_len = 0;
1265 };
1266
1267 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1268 }
1269
1270 if ((auto_stat & DATA_IN_PHASE) &&
1271 (scsi_get_resid(SCpnt) > 0) &&
1272 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1273 printk( "auto+fifo\n");
1274 //nsp32_pio_read(SCpnt);
1275 }
1276
1277 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1278 /* DATA_IN_PHASE/DATA_OUT_PHASE was processed. */
1279 nsp32_dbg(NSP32_DEBUG_INTR,
1280 "Data in/out phase processed");
1281
1282 /* read BMCNT, SGT pointer addr */
1283 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1284 nsp32_read4(base, BM_CNT));
1285 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1286 nsp32_read4(base, SGT_ADR));
1287 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1288 nsp32_read4(base, SACK_CNT));
1289 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1290 nsp32_read4(base, SAVED_SACK_CNT));
1291
1292 scsi_set_resid(SCpnt, 0); /* all data transfered! */
1293 }
1294
1295 /*
1296 * MsgIn Occur
1297 */
1298 if (auto_stat & MSG_IN_OCCUER) {
1299 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1300 }
1301
1302 /*
1303 * MsgOut Occur
1304 */
1305 if (auto_stat & MSG_OUT_OCCUER) {
1306 nsp32_msgout_occur(SCpnt);
1307 }
1308
1309 /*
1310 * Bus Free Occur
1311 */
1312 if (auto_stat & BUS_FREE_OCCUER) {
1313 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1314 if (ret == TRUE) {
1315 goto out;
1316 }
1317 }
1318
1319 if (auto_stat & STATUS_PHASE) {
1320 /*
1321 * Read CSB and substitute CSB for SCpnt->result
1322 * to save status phase stutas byte.
1323 * scsi error handler checks host_byte (DID_*:
1324 * low level driver to indicate status), then checks
1325 * status_byte (SCSI status byte).
1326 */
1327 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1328 }
1329
1330 if (auto_stat & ILLEGAL_PHASE) {
1331 /* Illegal phase is detected. SACK is not back. */
1332 nsp32_msg(KERN_WARNING,
1333 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1334
1335 /* TODO: currently we don't have any action... bus reset? */
1336
1337 /*
1338 * To send back SACK, assert, wait, and negate.
1339 */
1340 nsp32_sack_assert(data);
1341 nsp32_wait_req(data, NEGATE);
1342 nsp32_sack_negate(data);
1343
1344 }
1345
1346 if (auto_stat & COMMAND_PHASE) {
1347 /* nothing to do */
1348 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1349 }
1350
1351 if (auto_stat & AUTOSCSI_BUSY) {
1352 /* AutoSCSI is running */
1353 }
1354
1355 show_autophase(auto_stat);
1356 }
1357
1358 /* FIFO_SHLD_IRQ */
1359 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1360 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1361
1362 switch(busphase) {
1363 case BUSPHASE_DATA_OUT:
1364 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1365
1366 //nsp32_pio_write(SCpnt);
1367
1368 break;
1369
1370 case BUSPHASE_DATA_IN:
1371 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1372
1373 //nsp32_pio_read(SCpnt);
1374
1375 break;
1376
1377 case BUSPHASE_STATUS:
1378 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1379
1380 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1381
1382 break;
1383 default:
1384 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1385 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1386 show_busphase(busphase);
1387 break;
1388 }
1389
1390 goto out;
1391 }
1392
1393 /* Phase Change IRQ */
1394 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1395 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1396
1397 switch(busphase) {
1398 case BUSPHASE_MESSAGE_IN:
1399 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1400 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1401 break;
1402 default:
1403 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1404 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1405 irq_stat, trans_stat);
1406 show_busphase(busphase);
1407 break;
1408 }
1409 goto out;
1410 }
1411
1412 /* PCI_IRQ */
1413 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1414 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1415 /* Do nothing */
1416 }
1417
1418 /* BMCNTERR_IRQ */
1419 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1420 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1421 /*
1422 * TODO: To be implemented improving bus master
1423 * transfer reliablity when BMCNTERR is occurred in
1424 * AutoSCSI phase described in specification.
1425 */
1426 }
1427
1428 #if 0
1429 nsp32_dbg(NSP32_DEBUG_INTR,
1430 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1431 show_busphase(busphase);
1432 #endif
1433
1434 out:
1435 /* disable IRQ mask */
1436 nsp32_write2(base, IRQ_CONTROL, 0);
1437
1438 out2:
1439 spin_unlock_irqrestore(host->host_lock, flags);
1440
1441 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1442
1443 return IRQ_RETVAL(handled);
1444 }
1445
1446 #undef SPRINTF
1447 #define SPRINTF(args...) \
1448 do { \
1449 if(length > (pos - buffer)) { \
1450 pos += snprintf(pos, length - (pos - buffer) + 1, ## args); \
1451 nsp32_dbg(NSP32_DEBUG_PROC, "buffer=0x%p pos=0x%p length=%d %d\n", buffer, pos, length, length - (pos - buffer));\
1452 } \
1453 } while(0)
1454
1455 static int nsp32_proc_info(struct Scsi_Host *host, char *buffer, char **start,
1456 off_t offset, int length, int inout)
1457 {
1458 char *pos = buffer;
1459 int thislength;
1460 unsigned long flags;
1461 nsp32_hw_data *data;
1462 int hostno;
1463 unsigned int base;
1464 unsigned char mode_reg;
1465 int id, speed;
1466 long model;
1467
1468 /* Write is not supported, just return. */
1469 if (inout == TRUE) {
1470 return -EINVAL;
1471 }
1472
1473 hostno = host->host_no;
1474 data = (nsp32_hw_data *)host->hostdata;
1475 base = host->io_port;
1476
1477 SPRINTF("NinjaSCSI-32 status\n\n");
1478 SPRINTF("Driver version: %s, $Revision: 1.33 $\n", nsp32_release_version);
1479 SPRINTF("SCSI host No.: %d\n", hostno);
1480 SPRINTF("IRQ: %d\n", host->irq);
1481 SPRINTF("IO: 0x%lx-0x%lx\n", host->io_port, host->io_port + host->n_io_port - 1);
1482 SPRINTF("MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1);
1483 SPRINTF("sg_tablesize: %d\n", host->sg_tablesize);
1484 SPRINTF("Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1485
1486 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1487 model = data->pci_devid->driver_data;
1488
1489 #ifdef CONFIG_PM
1490 SPRINTF("Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no");
1491 #endif
1492 SPRINTF("OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1493
1494 spin_lock_irqsave(&(data->Lock), flags);
1495 SPRINTF("CurrentSC: 0x%p\n\n", data->CurrentSC);
1496 spin_unlock_irqrestore(&(data->Lock), flags);
1497
1498
1499 SPRINTF("SDTR status\n");
1500 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1501
1502 SPRINTF("id %d: ", id);
1503
1504 if (id == host->this_id) {
1505 SPRINTF("----- NinjaSCSI-32 host adapter\n");
1506 continue;
1507 }
1508
1509 if (data->target[id].sync_flag == SDTR_DONE) {
1510 if (data->target[id].period == 0 &&
1511 data->target[id].offset == ASYNC_OFFSET ) {
1512 SPRINTF("async");
1513 } else {
1514 SPRINTF(" sync");
1515 }
1516 } else {
1517 SPRINTF(" none");
1518 }
1519
1520 if (data->target[id].period != 0) {
1521
1522 speed = 1000000 / (data->target[id].period * 4);
1523
1524 SPRINTF(" transfer %d.%dMB/s, offset %d",
1525 speed / 1000,
1526 speed % 1000,
1527 data->target[id].offset
1528 );
1529 }
1530 SPRINTF("\n");
1531 }
1532
1533
1534 thislength = pos - (buffer + offset);
1535
1536 if(thislength < 0) {
1537 *start = NULL;
1538 return 0;
1539 }
1540
1541
1542 thislength = min(thislength, length);
1543 *start = buffer + offset;
1544
1545 return thislength;
1546 }
1547 #undef SPRINTF
1548
1549
1550
1551 /*
1552 * Reset parameters and call scsi_done for data->cur_lunt.
1553 * Be careful setting SCpnt->result = DID_* before calling this function.
1554 */
1555 static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1556 {
1557 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1558 unsigned int base = SCpnt->device->host->io_port;
1559
1560 scsi_dma_unmap(SCpnt);
1561
1562 /*
1563 * clear TRANSFERCONTROL_BM_START
1564 */
1565 nsp32_write2(base, TRANSFER_CONTROL, 0);
1566 nsp32_write4(base, BM_CNT, 0);
1567
1568 /*
1569 * call scsi_done
1570 */
1571 (*SCpnt->scsi_done)(SCpnt);
1572
1573 /*
1574 * reset parameters
1575 */
1576 data->cur_lunt->SCpnt = NULL;
1577 data->cur_lunt = NULL;
1578 data->cur_target = NULL;
1579 data->CurrentSC = NULL;
1580 }
1581
1582
1583 /*
1584 * Bus Free Occur
1585 *
1586 * Current Phase is BUSFREE. AutoSCSI is automatically execute BUSFREE phase
1587 * with ACK reply when below condition is matched:
1588 * MsgIn 00: Command Complete.
1589 * MsgIn 02: Save Data Pointer.
1590 * MsgIn 04: Diconnect.
1591 * In other case, unexpected BUSFREE is detected.
1592 */
1593 static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1594 {
1595 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1596 unsigned int base = SCpnt->device->host->io_port;
1597
1598 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1599 show_autophase(execph);
1600
1601 nsp32_write4(base, BM_CNT, 0);
1602 nsp32_write2(base, TRANSFER_CONTROL, 0);
1603
1604 /*
1605 * MsgIn 02: Save Data Pointer
1606 *
1607 * VALID:
1608 * Save Data Pointer is received. Adjust pointer.
1609 *
1610 * NO-VALID:
1611 * SCSI-3 says if Save Data Pointer is not received, then we restart
1612 * processing and we can't adjust any SCSI data pointer in next data
1613 * phase.
1614 */
1615 if (execph & MSGIN_02_VALID) {
1616 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1617
1618 /*
1619 * Check sack_cnt/saved_sack_cnt, then adjust sg table if
1620 * needed.
1621 */
1622 if (!(execph & MSGIN_00_VALID) &&
1623 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1624 unsigned int sacklen, s_sacklen;
1625
1626 /*
1627 * Read SACK count and SAVEDSACK count, then compare.
1628 */
1629 sacklen = nsp32_read4(base, SACK_CNT );
1630 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1631
1632 /*
1633 * If SAVEDSACKCNT == 0, it means SavedDataPointer is
1634 * come after data transfering.
1635 */
1636 if (s_sacklen > 0) {
1637 /*
1638 * Comparing between sack and savedsack to
1639 * check the condition of AutoMsgIn03.
1640 *
1641 * If they are same, set msgin03 == TRUE,
1642 * COMMANDCONTROL_AUTO_MSGIN_03 is enabled at
1643 * reselection. On the other hand, if they
1644 * aren't same, set msgin03 == FALSE, and
1645 * COMMANDCONTROL_AUTO_MSGIN_03 is disabled at
1646 * reselection.
1647 */
1648 if (sacklen != s_sacklen) {
1649 data->cur_lunt->msgin03 = FALSE;
1650 } else {
1651 data->cur_lunt->msgin03 = TRUE;
1652 }
1653
1654 nsp32_adjust_busfree(SCpnt, s_sacklen);
1655 }
1656 }
1657
1658 /* This value has not substitude with valid value yet... */
1659 //data->cur_lunt->save_datp = data->cur_datp;
1660 } else {
1661 /*
1662 * no processing.
1663 */
1664 }
1665
1666 if (execph & MSGIN_03_VALID) {
1667 /* MsgIn03 was valid to be processed. No need processing. */
1668 }
1669
1670 /*
1671 * target SDTR check
1672 */
1673 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1674 /*
1675 * SDTR negotiation pulled by the initiator has not
1676 * finished yet. Fall back to ASYNC mode.
1677 */
1678 nsp32_set_async(data, data->cur_target);
1679 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1680 data->cur_target->sync_flag |= SDTR_DONE;
1681 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1682 /*
1683 * SDTR negotiation pulled by the target has been
1684 * negotiating.
1685 */
1686 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1687 /*
1688 * If valid message is received, then
1689 * negotiation is succeeded.
1690 */
1691 } else {
1692 /*
1693 * On the contrary, if unexpected bus free is
1694 * occurred, then negotiation is failed. Fall
1695 * back to ASYNC mode.
1696 */
1697 nsp32_set_async(data, data->cur_target);
1698 }
1699 data->cur_target->sync_flag &= ~SDTR_TARGET;
1700 data->cur_target->sync_flag |= SDTR_DONE;
1701 }
1702
1703 /*
1704 * It is always ensured by SCSI standard that initiator
1705 * switches into Bus Free Phase after
1706 * receiving message 00 (Command Complete), 04 (Disconnect).
1707 * It's the reason that processing here is valid.
1708 */
1709 if (execph & MSGIN_00_VALID) {
1710 /* MsgIn 00: Command Complete */
1711 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1712
1713 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1714 SCpnt->SCp.Message = 0;
1715 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1716 "normal end stat=0x%x resid=0x%x\n",
1717 SCpnt->SCp.Status, scsi_get_resid(SCpnt));
1718 SCpnt->result = (DID_OK << 16) |
1719 (SCpnt->SCp.Message << 8) |
1720 (SCpnt->SCp.Status << 0);
1721 nsp32_scsi_done(SCpnt);
1722 /* All operation is done */
1723 return TRUE;
1724 } else if (execph & MSGIN_04_VALID) {
1725 /* MsgIn 04: Disconnect */
1726 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1727 SCpnt->SCp.Message = 4;
1728
1729 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1730 return TRUE;
1731 } else {
1732 /* Unexpected bus free */
1733 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1734
1735 /* DID_ERROR? */
1736 //SCpnt->result = (DID_OK << 16) | (SCpnt->SCp.Message << 8) | (SCpnt->SCp.Status << 0);
1737 SCpnt->result = DID_ERROR << 16;
1738 nsp32_scsi_done(SCpnt);
1739 return TRUE;
1740 }
1741 return FALSE;
1742 }
1743
1744
1745 /*
1746 * nsp32_adjust_busfree - adjusting SG table
1747 *
1748 * Note: This driver adjust the SG table using SCSI ACK
1749 * counter instead of BMCNT counter!
1750 */
1751 static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1752 {
1753 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1754 int old_entry = data->cur_entry;
1755 int new_entry;
1756 int sg_num = data->cur_lunt->sg_num;
1757 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1758 unsigned int restlen, sentlen;
1759 u32_le len, addr;
1760
1761 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1762
1763 /* adjust saved SACK count with 4 byte start address boundary */
1764 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1765
1766 /*
1767 * calculate new_entry from sack count and each sgt[].len
1768 * calculate the byte which is intent to send
1769 */
1770 sentlen = 0;
1771 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1772 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1773 if (sentlen > s_sacklen) {
1774 break;
1775 }
1776 }
1777
1778 /* all sgt is processed */
1779 if (new_entry == sg_num) {
1780 goto last;
1781 }
1782
1783 if (sentlen == s_sacklen) {
1784 /* XXX: confirm it's ok or not */
1785 /* In this case, it's ok because we are at
1786 the head element of the sg. restlen is correctly calculated. */
1787 }
1788
1789 /* calculate the rest length for transfering */
1790 restlen = sentlen - s_sacklen;
1791
1792 /* update adjusting current SG table entry */
1793 len = le32_to_cpu(sgt[new_entry].len);
1794 addr = le32_to_cpu(sgt[new_entry].addr);
1795 addr += (len - restlen);
1796 sgt[new_entry].addr = cpu_to_le32(addr);
1797 sgt[new_entry].len = cpu_to_le32(restlen);
1798
1799 /* set cur_entry with new_entry */
1800 data->cur_entry = new_entry;
1801
1802 return;
1803
1804 last:
1805 if (scsi_get_resid(SCpnt) < sentlen) {
1806 nsp32_msg(KERN_ERR, "resid underflow");
1807 }
1808
1809 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1810 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1811
1812 /* update hostdata and lun */
1813
1814 return;
1815 }
1816
1817
1818 /*
1819 * It's called MsgOut phase occur.
1820 * NinjaSCSI-32Bi/UDE automatically processes up to 3 messages in
1821 * message out phase. It, however, has more than 3 messages,
1822 * HBA creates the interrupt and we have to process by hand.
1823 */
1824 static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1825 {
1826 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1827 unsigned int base = SCpnt->device->host->io_port;
1828 //unsigned short command;
1829 long new_sgtp;
1830 int i;
1831
1832 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1833 "enter: msgout_len: 0x%x", data->msgout_len);
1834
1835 /*
1836 * If MsgOut phase is occurred without having any
1837 * message, then No_Operation is sent (SCSI-2).
1838 */
1839 if (data->msgout_len == 0) {
1840 nsp32_build_nop(SCpnt);
1841 }
1842
1843 /*
1844 * Set SGTP ADDR current entry for restarting AUTOSCSI,
1845 * because SGTP is incremented next point.
1846 * There is few statement in the specification...
1847 */
1848 new_sgtp = data->cur_lunt->sglun_paddr +
1849 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
1850
1851 /*
1852 * send messages
1853 */
1854 for (i = 0; i < data->msgout_len; i++) {
1855 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1856 "%d : 0x%x", i, data->msgoutbuf[i]);
1857
1858 /*
1859 * Check REQ is asserted.
1860 */
1861 nsp32_wait_req(data, ASSERT);
1862
1863 if (i == (data->msgout_len - 1)) {
1864 /*
1865 * If the last message, set the AutoSCSI restart
1866 * before send back the ack message. AutoSCSI
1867 * restart automatically negate ATN signal.
1868 */
1869 //command = (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
1870 //nsp32_restart_autoscsi(SCpnt, command);
1871 nsp32_write2(base, COMMAND_CONTROL,
1872 (CLEAR_CDB_FIFO_POINTER |
1873 AUTO_COMMAND_PHASE |
1874 AUTOSCSI_RESTART |
1875 AUTO_MSGIN_00_OR_04 |
1876 AUTO_MSGIN_02 ));
1877 }
1878 /*
1879 * Write data with SACK, then wait sack is
1880 * automatically negated.
1881 */
1882 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1883 nsp32_wait_sack(data, NEGATE);
1884
1885 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1886 nsp32_read1(base, SCSI_BUS_MONITOR));
1887 };
1888
1889 data->msgout_len = 0;
1890
1891 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1892 }
1893
1894 /*
1895 * Restart AutoSCSI
1896 *
1897 * Note: Restarting AutoSCSI needs set:
1898 * SYNC_REG, ACK_WIDTH, SGT_ADR, TRANSFER_CONTROL
1899 */
1900 static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1901 {
1902 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1903 unsigned int base = data->BaseAddress;
1904 unsigned short transfer = 0;
1905
1906 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1907
1908 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1909 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1910 }
1911
1912 /*
1913 * set SYNC_REG
1914 * Don't set BM_START_ADR before setting this register.
1915 */
1916 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1917
1918 /*
1919 * set ACKWIDTH
1920 */
1921 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1922
1923 /*
1924 * set SREQ hazard killer sampling rate
1925 */
1926 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1927
1928 /*
1929 * set SGT ADDR (physical address)
1930 */
1931 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1932
1933 /*
1934 * set TRANSFER CONTROL REG
1935 */
1936 transfer = 0;
1937 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1938 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1939 if (scsi_bufflen(SCpnt) > 0) {
1940 transfer |= BM_START;
1941 }
1942 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1943 transfer |= CB_MMIO_MODE;
1944 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1945 transfer |= CB_IO_MODE;
1946 }
1947 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1948
1949 /*
1950 * restart AutoSCSI
1951 *
1952 * TODO: COMMANDCONTROL_AUTO_COMMAND_PHASE is needed ?
1953 */
1954 command |= (CLEAR_CDB_FIFO_POINTER |
1955 AUTO_COMMAND_PHASE |
1956 AUTOSCSI_RESTART );
1957 nsp32_write2(base, COMMAND_CONTROL, command);
1958
1959 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1960 }
1961
1962
1963 /*
1964 * cannot run automatically message in occur
1965 */
1966 static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1967 unsigned long irq_status,
1968 unsigned short execph)
1969 {
1970 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1971 unsigned int base = SCpnt->device->host->io_port;
1972 unsigned char msg;
1973 unsigned char msgtype;
1974 unsigned char newlun;
1975 unsigned short command = 0;
1976 int msgclear = TRUE;
1977 long new_sgtp;
1978 int ret;
1979
1980 /*
1981 * read first message
1982 * Use SCSIDATA_W_ACK instead of SCSIDATAIN, because the procedure
1983 * of Message-In have to be processed before sending back SCSI ACK.
1984 */
1985 msg = nsp32_read1(base, SCSI_DATA_IN);
1986 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1987 msgtype = data->msginbuf[0];
1988 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1989 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1990 data->msgin_len, msg, msgtype);
1991
1992 /*
1993 * TODO: We need checking whether bus phase is message in?
1994 */
1995
1996 /*
1997 * assert SCSI ACK
1998 */
1999 nsp32_sack_assert(data);
2000
2001 /*
2002 * processing IDENTIFY
2003 */
2004 if (msgtype & 0x80) {
2005 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
2006 /* Invalid (non reselect) phase */
2007 goto reject;
2008 }
2009
2010 newlun = msgtype & 0x1f; /* TODO: SPI-3 compliant? */
2011 ret = nsp32_reselection(SCpnt, newlun);
2012 if (ret == TRUE) {
2013 goto restart;
2014 } else {
2015 goto reject;
2016 }
2017 }
2018
2019 /*
2020 * processing messages except for IDENTIFY
2021 *
2022 * TODO: Messages are all SCSI-2 terminology. SCSI-3 compliance is TODO.
2023 */
2024 switch (msgtype) {
2025 /*
2026 * 1-byte message
2027 */
2028 case COMMAND_COMPLETE:
2029 case DISCONNECT:
2030 /*
2031 * These messages should not be occurred.
2032 * They should be processed on AutoSCSI sequencer.
2033 */
2034 nsp32_msg(KERN_WARNING,
2035 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
2036 break;
2037
2038 case RESTORE_POINTERS:
2039 /*
2040 * AutoMsgIn03 is disabled, and HBA gets this message.
2041 */
2042
2043 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
2044 unsigned int s_sacklen;
2045
2046 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
2047 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
2048 nsp32_adjust_busfree(SCpnt, s_sacklen);
2049 } else {
2050 /* No need to rewrite SGT */
2051 }
2052 }
2053 data->cur_lunt->msgin03 = FALSE;
2054
2055 /* Update with the new value */
2056
2057 /* reset SACK/SavedACK counter (or ALL clear?) */
2058 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2059
2060 /*
2061 * set new sg pointer
2062 */
2063 new_sgtp = data->cur_lunt->sglun_paddr +
2064 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2065 nsp32_write4(base, SGT_ADR, new_sgtp);
2066
2067 break;
2068
2069 case SAVE_POINTERS:
2070 /*
2071 * These messages should not be occurred.
2072 * They should be processed on AutoSCSI sequencer.
2073 */
2074 nsp32_msg (KERN_WARNING,
2075 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2076
2077 break;
2078
2079 case MESSAGE_REJECT:
2080 /* If previous message_out is sending SDTR, and get
2081 message_reject from target, SDTR negotiation is failed */
2082 if (data->cur_target->sync_flag &
2083 (SDTR_INITIATOR | SDTR_TARGET)) {
2084 /*
2085 * Current target is negotiating SDTR, but it's
2086 * failed. Fall back to async transfer mode, and set
2087 * SDTR_DONE.
2088 */
2089 nsp32_set_async(data, data->cur_target);
2090 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2091 data->cur_target->sync_flag |= SDTR_DONE;
2092
2093 }
2094 break;
2095
2096 case LINKED_CMD_COMPLETE:
2097 case LINKED_FLG_CMD_COMPLETE:
2098 /* queue tag is not supported currently */
2099 nsp32_msg (KERN_WARNING,
2100 "unsupported message: 0x%x", msgtype);
2101 break;
2102
2103 case INITIATE_RECOVERY:
2104 /* staring ECA (Extended Contingent Allegiance) state. */
2105 /* This message is declined in SPI2 or later. */
2106
2107 goto reject;
2108
2109 /*
2110 * 2-byte message
2111 */
2112 case SIMPLE_QUEUE_TAG:
2113 case 0x23:
2114 /*
2115 * 0x23: Ignore_Wide_Residue is not declared in scsi.h.
2116 * No support is needed.
2117 */
2118 if (data->msgin_len >= 1) {
2119 goto reject;
2120 }
2121
2122 /* current position is 1-byte of 2 byte */
2123 msgclear = FALSE;
2124
2125 break;
2126
2127 /*
2128 * extended message
2129 */
2130 case EXTENDED_MESSAGE:
2131 if (data->msgin_len < 1) {
2132 /*
2133 * Current position does not reach 2-byte
2134 * (2-byte is extended message length).
2135 */
2136 msgclear = FALSE;
2137 break;
2138 }
2139
2140 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2141 /*
2142 * Current extended message has msginbuf[1] + 2
2143 * (msgin_len starts counting from 0, so buf[1] + 1).
2144 * If current message position is not finished,
2145 * continue receiving message.
2146 */
2147 msgclear = FALSE;
2148 break;
2149 }
2150
2151 /*
2152 * Reach here means regular length of each type of
2153 * extended messages.
2154 */
2155 switch (data->msginbuf[2]) {
2156 case EXTENDED_MODIFY_DATA_POINTER:
2157 /* TODO */
2158 goto reject; /* not implemented yet */
2159 break;
2160
2161 case EXTENDED_SDTR:
2162 /*
2163 * Exchange this message between initiator and target.
2164 */
2165 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2166 /*
2167 * received inappropriate message.
2168 */
2169 goto reject;
2170 break;
2171 }
2172
2173 nsp32_analyze_sdtr(SCpnt);
2174
2175 break;
2176
2177 case EXTENDED_EXTENDED_IDENTIFY:
2178 /* SCSI-I only, not supported. */
2179 goto reject; /* not implemented yet */
2180
2181 break;
2182
2183 case EXTENDED_WDTR:
2184 goto reject; /* not implemented yet */
2185
2186 break;
2187
2188 default:
2189 goto reject;
2190 }
2191 break;
2192
2193 default:
2194 goto reject;
2195 }
2196
2197 restart:
2198 if (msgclear == TRUE) {
2199 data->msgin_len = 0;
2200
2201 /*
2202 * If restarting AutoSCSI, but there are some message to out
2203 * (msgout_len > 0), set AutoATN, and set SCSIMSGOUT as 0
2204 * (MV_VALID = 0). When commandcontrol is written with
2205 * AutoSCSI restart, at the same time MsgOutOccur should be
2206 * happened (however, such situation is really possible...?).
2207 */
2208 if (data->msgout_len > 0) {
2209 nsp32_write4(base, SCSI_MSG_OUT, 0);
2210 command |= AUTO_ATN;
2211 }
2212
2213 /*
2214 * restart AutoSCSI
2215 * If it's failed, COMMANDCONTROL_AUTO_COMMAND_PHASE is needed.
2216 */
2217 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2218
2219 /*
2220 * If current msgin03 is TRUE, then flag on.
2221 */
2222 if (data->cur_lunt->msgin03 == TRUE) {
2223 command |= AUTO_MSGIN_03;
2224 }
2225 data->cur_lunt->msgin03 = FALSE;
2226 } else {
2227 data->msgin_len++;
2228 }
2229
2230 /*
2231 * restart AutoSCSI
2232 */
2233 nsp32_restart_autoscsi(SCpnt, command);
2234
2235 /*
2236 * wait SCSI REQ negate for REQ-ACK handshake
2237 */
2238 nsp32_wait_req(data, NEGATE);
2239
2240 /*
2241 * negate SCSI ACK
2242 */
2243 nsp32_sack_negate(data);
2244
2245 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2246
2247 return;
2248
2249 reject:
2250 nsp32_msg(KERN_WARNING,
2251 "invalid or unsupported MessageIn, rejected. "
2252 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2253 msg, data->msgin_len, msgtype);
2254 nsp32_build_reject(SCpnt);
2255 data->msgin_len = 0;
2256
2257 goto restart;
2258 }
2259
2260 /*
2261 *
2262 */
2263 static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2264 {
2265 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2266 nsp32_target *target = data->cur_target;
2267 nsp32_sync_table *synct;
2268 unsigned char get_period = data->msginbuf[3];
2269 unsigned char get_offset = data->msginbuf[4];
2270 int entry;
2271 int syncnum;
2272
2273 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2274
2275 synct = data->synct;
2276 syncnum = data->syncnum;
2277
2278 /*
2279 * If this inititor sent the SDTR message, then target responds SDTR,
2280 * initiator SYNCREG, ACKWIDTH from SDTR parameter.
2281 * Messages are not appropriate, then send back reject message.
2282 * If initiator did not send the SDTR, but target sends SDTR,
2283 * initiator calculator the appropriate parameter and send back SDTR.
2284 */
2285 if (target->sync_flag & SDTR_INITIATOR) {
2286 /*
2287 * Initiator sent SDTR, the target responds and
2288 * send back negotiation SDTR.
2289 */
2290 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2291
2292 target->sync_flag &= ~SDTR_INITIATOR;
2293 target->sync_flag |= SDTR_DONE;
2294
2295 /*
2296 * offset:
2297 */
2298 if (get_offset > SYNC_OFFSET) {
2299 /*
2300 * Negotiation is failed, the target send back
2301 * unexpected offset value.
2302 */
2303 goto reject;
2304 }
2305
2306 if (get_offset == ASYNC_OFFSET) {
2307 /*
2308 * Negotiation is succeeded, the target want
2309 * to fall back into asynchronous transfer mode.
2310 */
2311 goto async;
2312 }
2313
2314 /*
2315 * period:
2316 * Check whether sync period is too short. If too short,
2317 * fall back to async mode. If it's ok, then investigate
2318 * the received sync period. If sync period is acceptable
2319 * between sync table start_period and end_period, then
2320 * set this I_T nexus as sent offset and period.
2321 * If it's not acceptable, send back reject and fall back
2322 * to async mode.
2323 */
2324 if (get_period < data->synct[0].period_num) {
2325 /*
2326 * Negotiation is failed, the target send back
2327 * unexpected period value.
2328 */
2329 goto reject;
2330 }
2331
2332 entry = nsp32_search_period_entry(data, target, get_period);
2333
2334 if (entry < 0) {
2335 /*
2336 * Target want to use long period which is not
2337 * acceptable NinjaSCSI-32Bi/UDE.
2338 */
2339 goto reject;
2340 }
2341
2342 /*
2343 * Set new sync table and offset in this I_T nexus.
2344 */
2345 nsp32_set_sync_entry(data, target, entry, get_offset);
2346 } else {
2347 /* Target send SDTR to initiator. */
2348 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2349
2350 target->sync_flag |= SDTR_INITIATOR;
2351
2352 /* offset: */
2353 if (get_offset > SYNC_OFFSET) {
2354 /* send back as SYNC_OFFSET */
2355 get_offset = SYNC_OFFSET;
2356 }
2357
2358 /* period: */
2359 if (get_period < data->synct[0].period_num) {
2360 get_period = data->synct[0].period_num;
2361 }
2362
2363 entry = nsp32_search_period_entry(data, target, get_period);
2364
2365 if (get_offset == ASYNC_OFFSET || entry < 0) {
2366 nsp32_set_async(data, target);
2367 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2368 } else {
2369 nsp32_set_sync_entry(data, target, entry, get_offset);
2370 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2371 }
2372 }
2373
2374 target->period = get_period;
2375 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2376 return;
2377
2378 reject:
2379 /*
2380 * If the current message is unacceptable, send back to the target
2381 * with reject message.
2382 */
2383 nsp32_build_reject(SCpnt);
2384
2385 async:
2386 nsp32_set_async(data, target); /* set as ASYNC transfer mode */
2387
2388 target->period = 0;
2389 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2390 return;
2391 }
2392
2393
2394 /*
2395 * Search config entry number matched in sync_table from given
2396 * target and speed period value. If failed to search, return negative value.
2397 */
2398 static int nsp32_search_period_entry(nsp32_hw_data *data,
2399 nsp32_target *target,
2400 unsigned char period)
2401 {
2402 int i;
2403
2404 if (target->limit_entry >= data->syncnum) {
2405 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2406 target->limit_entry = 0;
2407 }
2408
2409 for (i = target->limit_entry; i < data->syncnum; i++) {
2410 if (period >= data->synct[i].start_period &&
2411 period <= data->synct[i].end_period) {
2412 break;
2413 }
2414 }
2415
2416 /*
2417 * Check given period value is over the sync_table value.
2418 * If so, return max value.
2419 */
2420 if (i == data->syncnum) {
2421 i = -1;
2422 }
2423
2424 return i;
2425 }
2426
2427
2428 /*
2429 * target <-> initiator use ASYNC transfer
2430 */
2431 static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2432 {
2433 unsigned char period = data->synct[target->limit_entry].period_num;
2434
2435 target->offset = ASYNC_OFFSET;
2436 target->period = 0;
2437 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2438 target->ackwidth = 0;
2439 target->sample_reg = 0;
2440
2441 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2442 }
2443
2444
2445 /*
2446 * target <-> initiator use maximum SYNC transfer
2447 */
2448 static void nsp32_set_max_sync(nsp32_hw_data *data,
2449 nsp32_target *target,
2450 unsigned char *period,
2451 unsigned char *offset)
2452 {
2453 unsigned char period_num, ackwidth;
2454
2455 period_num = data->synct[target->limit_entry].period_num;
2456 *period = data->synct[target->limit_entry].start_period;
2457 ackwidth = data->synct[target->limit_entry].ackwidth;
2458 *offset = SYNC_OFFSET;
2459
2460 target->syncreg = TO_SYNCREG(period_num, *offset);
2461 target->ackwidth = ackwidth;
2462 target->offset = *offset;
2463 target->sample_reg = 0; /* disable SREQ sampling */
2464 }
2465
2466
2467 /*
2468 * target <-> initiator use entry number speed
2469 */
2470 static void nsp32_set_sync_entry(nsp32_hw_data *data,
2471 nsp32_target *target,
2472 int entry,
2473 unsigned char offset)
2474 {
2475 unsigned char period, ackwidth, sample_rate;
2476
2477 period = data->synct[entry].period_num;
2478 ackwidth = data->synct[entry].ackwidth;
2479 offset = offset;
2480 sample_rate = data->synct[entry].sample_rate;
2481
2482 target->syncreg = TO_SYNCREG(period, offset);
2483 target->ackwidth = ackwidth;
2484 target->offset = offset;
2485 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2486
2487 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2488 }
2489
2490
2491 /*
2492 * It waits until SCSI REQ becomes assertion or negation state.
2493 *
2494 * Note: If nsp32_msgin_occur is called, we asserts SCSI ACK. Then
2495 * connected target responds SCSI REQ negation. We have to wait
2496 * SCSI REQ becomes negation in order to negate SCSI ACK signal for
2497 * REQ-ACK handshake.
2498 */
2499 static void nsp32_wait_req(nsp32_hw_data *data, int state)
2500 {
2501 unsigned int base = data->BaseAddress;
2502 int wait_time = 0;
2503 unsigned char bus, req_bit;
2504
2505 if (!((state == ASSERT) || (state == NEGATE))) {
2506 nsp32_msg(KERN_ERR, "unknown state designation");
2507 }
2508 /* REQ is BIT(5) */
2509 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2510
2511 do {
2512 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2513 if ((bus & BUSMON_REQ) == req_bit) {
2514 nsp32_dbg(NSP32_DEBUG_WAIT,
2515 "wait_time: %d", wait_time);
2516 return;
2517 }
2518 udelay(1);
2519 wait_time++;
2520 } while (wait_time < REQSACK_TIMEOUT_TIME);
2521
2522 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2523 }
2524
2525 /*
2526 * It waits until SCSI SACK becomes assertion or negation state.
2527 */
2528 static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2529 {
2530 unsigned int base = data->BaseAddress;
2531 int wait_time = 0;
2532 unsigned char bus, ack_bit;
2533
2534 if (!((state == ASSERT) || (state == NEGATE))) {
2535 nsp32_msg(KERN_ERR, "unknown state designation");
2536 }
2537 /* ACK is BIT(4) */
2538 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2539
2540 do {
2541 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2542 if ((bus & BUSMON_ACK) == ack_bit) {
2543 nsp32_dbg(NSP32_DEBUG_WAIT,
2544 "wait_time: %d", wait_time);
2545 return;
2546 }
2547 udelay(1);
2548 wait_time++;
2549 } while (wait_time < REQSACK_TIMEOUT_TIME);
2550
2551 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2552 }
2553
2554 /*
2555 * assert SCSI ACK
2556 *
2557 * Note: SCSI ACK assertion needs with ACKENB=1, AUTODIRECTION=1.
2558 */
2559 static void nsp32_sack_assert(nsp32_hw_data *data)
2560 {
2561 unsigned int base = data->BaseAddress;
2562 unsigned char busctrl;
2563
2564 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2565 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2566 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2567 }
2568
2569 /*
2570 * negate SCSI ACK
2571 */
2572 static void nsp32_sack_negate(nsp32_hw_data *data)
2573 {
2574 unsigned int base = data->BaseAddress;
2575 unsigned char busctrl;
2576
2577 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2578 busctrl &= ~BUSCTL_ACK;
2579 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2580 }
2581
2582
2583
2584 /*
2585 * Note: n_io_port is defined as 0x7f because I/O register port is
2586 * assigned as:
2587 * 0x800-0x8ff: memory mapped I/O port
2588 * 0x900-0xbff: (map same 0x800-0x8ff I/O port image repeatedly)
2589 * 0xc00-0xfff: CardBus status registers
2590 */
2591 static int nsp32_detect(struct pci_dev *pdev)
2592 {
2593 struct Scsi_Host *host; /* registered host structure */
2594 struct resource *res;
2595 nsp32_hw_data *data;
2596 int ret;
2597 int i, j;
2598
2599 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2600
2601 /*
2602 * register this HBA as SCSI device
2603 */
2604 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2605 if (host == NULL) {
2606 nsp32_msg (KERN_ERR, "failed to scsi register");
2607 goto err;
2608 }
2609
2610 /*
2611 * set nsp32_hw_data
2612 */
2613 data = (nsp32_hw_data *)host->hostdata;
2614
2615 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2616
2617 host->irq = data->IrqNumber;
2618 host->io_port = data->BaseAddress;
2619 host->unique_id = data->BaseAddress;
2620 host->n_io_port = data->NumAddress;
2621 host->base = (unsigned long)data->MmioAddress;
2622
2623 data->Host = host;
2624 spin_lock_init(&(data->Lock));
2625
2626 data->cur_lunt = NULL;
2627 data->cur_target = NULL;
2628
2629 /*
2630 * Bus master transfer mode is supported currently.
2631 */
2632 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2633
2634 /*
2635 * Set clock div, CLOCK_4 (HBA has own external clock, and
2636 * dividing * 100ns/4).
2637 * Currently CLOCK_4 has only tested, not for CLOCK_2/PCICLK yet.
2638 */
2639 data->clock = CLOCK_4;
2640
2641 /*
2642 * Select appropriate nsp32_sync_table and set I_CLOCKDIV.
2643 */
2644 switch (data->clock) {
2645 case CLOCK_4:
2646 /* If data->clock is CLOCK_4, then select 40M sync table. */
2647 data->synct = nsp32_sync_table_40M;
2648 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2649 break;
2650 case CLOCK_2:
2651 /* If data->clock is CLOCK_2, then select 20M sync table. */
2652 data->synct = nsp32_sync_table_20M;
2653 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2654 break;
2655 case PCICLK:
2656 /* If data->clock is PCICLK, then select pci sync table. */
2657 data->synct = nsp32_sync_table_pci;
2658 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2659 break;
2660 default:
2661 nsp32_msg(KERN_WARNING,
2662 "Invalid clock div is selected, set CLOCK_4.");
2663 /* Use default value CLOCK_4 */
2664 data->clock = CLOCK_4;
2665 data->synct = nsp32_sync_table_40M;
2666 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2667 }
2668
2669 /*
2670 * setup nsp32_lunt
2671 */
2672
2673 /*
2674 * setup DMA
2675 */
2676 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
2677 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2678 goto scsi_unregister;
2679 }
2680
2681 /*
2682 * allocate autoparam DMA resource.
2683 */
2684 data->autoparam = pci_alloc_consistent(pdev, sizeof(nsp32_autoparam), &(data->auto_paddr));
2685 if (data->autoparam == NULL) {
2686 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2687 goto scsi_unregister;
2688 }
2689
2690 /*
2691 * allocate scatter-gather DMA resource.
2692 */
2693 data->sg_list = pci_alloc_consistent(pdev, NSP32_SG_TABLE_SIZE,
2694 &(data->sg_paddr));
2695 if (data->sg_list == NULL) {
2696 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2697 goto free_autoparam;
2698 }
2699
2700 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2701 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2702 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2703 nsp32_lunt tmp = {
2704 .SCpnt = NULL,
2705 .save_datp = 0,
2706 .msgin03 = FALSE,
2707 .sg_num = 0,
2708 .cur_entry = 0,
2709 .sglun = &(data->sg_list[offset]),
2710 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2711 };
2712
2713 data->lunt[i][j] = tmp;
2714 }
2715 }
2716
2717 /*
2718 * setup target
2719 */
2720 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2721 nsp32_target *target = &(data->target[i]);
2722
2723 target->limit_entry = 0;
2724 target->sync_flag = 0;
2725 nsp32_set_async(data, target);
2726 }
2727
2728 /*
2729 * EEPROM check
2730 */
2731 ret = nsp32_getprom_param(data);
2732 if (ret == FALSE) {
2733 data->resettime = 3; /* default 3 */
2734 }
2735
2736 /*
2737 * setup HBA
2738 */
2739 nsp32hw_init(data);
2740
2741 snprintf(data->info_str, sizeof(data->info_str),
2742 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2743 host->irq, host->io_port, host->n_io_port);
2744
2745 /*
2746 * SCSI bus reset
2747 *
2748 * Note: It's important to reset SCSI bus in initialization phase.
2749 * NinjaSCSI-32Bi/UDE HBA EEPROM seems to exchange SDTR when
2750 * system is coming up, so SCSI devices connected to HBA is set as
2751 * un-asynchronous mode. It brings the merit that this HBA is
2752 * ready to start synchronous transfer without any preparation,
2753 * but we are difficult to control transfer speed. In addition,
2754 * it prevents device transfer speed from effecting EEPROM start-up
2755 * SDTR. NinjaSCSI-32Bi/UDE has the feature if EEPROM is set as
2756 * Auto Mode, then FAST-10M is selected when SCSI devices are
2757 * connected same or more than 4 devices. It should be avoided
2758 * depending on this specification. Thus, resetting the SCSI bus
2759 * restores all connected SCSI devices to asynchronous mode, then
2760 * this driver set SDTR safely later, and we can control all SCSI
2761 * device transfer mode.
2762 */
2763 nsp32_do_bus_reset(data);
2764
2765 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2766 if (ret < 0) {
2767 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2768 "SCSI PCI controller. Interrupt: %d", host->irq);
2769 goto free_sg_list;
2770 }
2771
2772 /*
2773 * PCI IO register
2774 */
2775 res = request_region(host->io_port, host->n_io_port, "nsp32");
2776 if (res == NULL) {
2777 nsp32_msg(KERN_ERR,
2778 "I/O region 0x%lx+0x%lx is already used",
2779 data->BaseAddress, data->NumAddress);
2780 goto free_irq;
2781 }
2782
2783 ret = scsi_add_host(host, &pdev->dev);
2784 if (ret) {
2785 nsp32_msg(KERN_ERR, "failed to add scsi host");
2786 goto free_region;
2787 }
2788 scsi_scan_host(host);
2789 pci_set_drvdata(pdev, host);
2790 return 0;
2791
2792 free_region:
2793 release_region(host->io_port, host->n_io_port);
2794
2795 free_irq:
2796 free_irq(host->irq, data);
2797
2798 free_sg_list:
2799 pci_free_consistent(pdev, NSP32_SG_TABLE_SIZE,
2800 data->sg_list, data->sg_paddr);
2801
2802 free_autoparam:
2803 pci_free_consistent(pdev, sizeof(nsp32_autoparam),
2804 data->autoparam, data->auto_paddr);
2805
2806 scsi_unregister:
2807 scsi_host_put(host);
2808
2809 err:
2810 return 1;
2811 }
2812
2813 static int nsp32_release(struct Scsi_Host *host)
2814 {
2815 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2816
2817 if (data->autoparam) {
2818 pci_free_consistent(data->Pci, sizeof(nsp32_autoparam),
2819 data->autoparam, data->auto_paddr);
2820 }
2821
2822 if (data->sg_list) {
2823 pci_free_consistent(data->Pci, NSP32_SG_TABLE_SIZE,
2824 data->sg_list, data->sg_paddr);
2825 }
2826
2827 if (host->irq) {
2828 free_irq(host->irq, data);
2829 }
2830
2831 if (host->io_port && host->n_io_port) {
2832 release_region(host->io_port, host->n_io_port);
2833 }
2834
2835 if (data->MmioAddress) {
2836 iounmap(data->MmioAddress);
2837 }
2838
2839 return 0;
2840 }
2841
2842 static const char *nsp32_info(struct Scsi_Host *shpnt)
2843 {
2844 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2845
2846 return data->info_str;
2847 }
2848
2849
2850 /****************************************************************************
2851 * error handler
2852 */
2853 static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2854 {
2855 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2856 unsigned int base = SCpnt->device->host->io_port;
2857
2858 nsp32_msg(KERN_WARNING, "abort");
2859
2860 if (data->cur_lunt->SCpnt == NULL) {
2861 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2862 return FAILED;
2863 }
2864
2865 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2866 /* reset SDTR negotiation */
2867 data->cur_target->sync_flag = 0;
2868 nsp32_set_async(data, data->cur_target);
2869 }
2870
2871 nsp32_write2(base, TRANSFER_CONTROL, 0);
2872 nsp32_write2(base, BM_CNT, 0);
2873
2874 SCpnt->result = DID_ABORT << 16;
2875 nsp32_scsi_done(SCpnt);
2876
2877 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2878 return SUCCESS;
2879 }
2880
2881 static int nsp32_eh_bus_reset(struct scsi_cmnd *SCpnt)
2882 {
2883 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2884 unsigned int base = SCpnt->device->host->io_port;
2885
2886 spin_lock_irq(SCpnt->device->host->host_lock);
2887
2888 nsp32_msg(KERN_INFO, "Bus Reset");
2889 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2890
2891 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2892 nsp32_do_bus_reset(data);
2893 nsp32_write2(base, IRQ_CONTROL, 0);
2894
2895 spin_unlock_irq(SCpnt->device->host->host_lock);
2896 return SUCCESS; /* SCSI bus reset is succeeded at any time. */
2897 }
2898
2899 static void nsp32_do_bus_reset(nsp32_hw_data *data)
2900 {
2901 unsigned int base = data->BaseAddress;
2902 unsigned short intrdat;
2903 int i;
2904
2905 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2906
2907 /*
2908 * stop all transfer
2909 * clear TRANSFERCONTROL_BM_START
2910 * clear counter
2911 */
2912 nsp32_write2(base, TRANSFER_CONTROL, 0);
2913 nsp32_write4(base, BM_CNT, 0);
2914 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2915
2916 /*
2917 * fall back to asynchronous transfer mode
2918 * initialize SDTR negotiation flag
2919 */
2920 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2921 nsp32_target *target = &data->target[i];
2922
2923 target->sync_flag = 0;
2924 nsp32_set_async(data, target);
2925 }
2926
2927 /*
2928 * reset SCSI bus
2929 */
2930 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2931 udelay(RESET_HOLD_TIME);
2932 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2933 for(i = 0; i < 5; i++) {
2934 intrdat = nsp32_read2(base, IRQ_STATUS); /* dummy read */
2935 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2936 }
2937
2938 data->CurrentSC = NULL;
2939 }
2940
2941 static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2942 {
2943 struct Scsi_Host *host = SCpnt->device->host;
2944 unsigned int base = SCpnt->device->host->io_port;
2945 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2946
2947 nsp32_msg(KERN_INFO, "Host Reset");
2948 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2949
2950 spin_lock_irq(SCpnt->device->host->host_lock);
2951
2952 nsp32hw_init(data);
2953 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2954 nsp32_do_bus_reset(data);
2955 nsp32_write2(base, IRQ_CONTROL, 0);
2956
2957 spin_unlock_irq(SCpnt->device->host->host_lock);
2958 return SUCCESS; /* Host reset is succeeded at any time. */
2959 }
2960
2961
2962 /**************************************************************************
2963 * EEPROM handler
2964 */
2965
2966 /*
2967 * getting EEPROM parameter
2968 */
2969 static int nsp32_getprom_param(nsp32_hw_data *data)
2970 {
2971 int vendor = data->pci_devid->vendor;
2972 int device = data->pci_devid->device;
2973 int ret, val, i;
2974
2975 /*
2976 * EEPROM checking.
2977 */
2978 ret = nsp32_prom_read(data, 0x7e);
2979 if (ret != 0x55) {
2980 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2981 return FALSE;
2982 }
2983 ret = nsp32_prom_read(data, 0x7f);
2984 if (ret != 0xaa) {
2985 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2986 return FALSE;
2987 }
2988
2989 /*
2990 * check EEPROM type
2991 */
2992 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2993 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2994 ret = nsp32_getprom_c16(data);
2995 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2996 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2997 ret = nsp32_getprom_at24(data);
2998 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2999 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
3000 ret = nsp32_getprom_at24(data);
3001 } else {
3002 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
3003 ret = FALSE;
3004 }
3005
3006 /* for debug : SPROM data full checking */
3007 for (i = 0; i <= 0x1f; i++) {
3008 val = nsp32_prom_read(data, i);
3009 nsp32_dbg(NSP32_DEBUG_EEPROM,
3010 "rom address 0x%x : 0x%x", i, val);
3011 }
3012
3013 return ret;
3014 }
3015
3016
3017 /*
3018 * AT24C01A (Logitec: LHA-600S), AT24C02 (Melco Buffalo: IFC-USLP) data map:
3019 *
3020 * ROMADDR
3021 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3022 * Value 0x0: ASYNC, 0x0c: Ultra-20M, 0x19: Fast-10M
3023 * 0x07 : HBA Synchronous Transfer Period
3024 * Value 0: AutoSync, 1: Manual Setting
3025 * 0x08 - 0x0f : Not Used? (0x0)
3026 * 0x10 : Bus Termination
3027 * Value 0: Auto[ON], 1: ON, 2: OFF
3028 * 0x11 : Not Used? (0)
3029 * 0x12 : Bus Reset Delay Time (0x03)
3030 * 0x13 : Bootable CD Support
3031 * Value 0: Disable, 1: Enable
3032 * 0x14 : Device Scan
3033 * Bit 7 6 5 4 3 2 1 0
3034 * | <----------------->
3035 * | SCSI ID: Value 0: Skip, 1: YES
3036 * |-> Value 0: ALL scan, Value 1: Manual
3037 * 0x15 - 0x1b : Not Used? (0)
3038 * 0x1c : Constant? (0x01) (clock div?)
3039 * 0x1d - 0x7c : Not Used (0xff)
3040 * 0x7d : Not Used? (0xff)
3041 * 0x7e : Constant (0x55), Validity signature
3042 * 0x7f : Constant (0xaa), Validity signature
3043 */
3044 static int nsp32_getprom_at24(nsp32_hw_data *data)
3045 {
3046 int ret, i;
3047 int auto_sync;
3048 nsp32_target *target;
3049 int entry;
3050
3051 /*
3052 * Reset time which is designated by EEPROM.
3053 *
3054 * TODO: Not used yet.
3055 */
3056 data->resettime = nsp32_prom_read(data, 0x12);
3057
3058 /*
3059 * HBA Synchronous Transfer Period
3060 *
3061 * Note: auto_sync = 0: auto, 1: manual. Ninja SCSI HBA spec says
3062 * that if auto_sync is 0 (auto), and connected SCSI devices are
3063 * same or lower than 3, then transfer speed is set as ULTRA-20M.
3064 * On the contrary if connected SCSI devices are same or higher
3065 * than 4, then transfer speed is set as FAST-10M.
3066 *
3067 * I break this rule. The number of connected SCSI devices are
3068 * only ignored. If auto_sync is 0 (auto), then transfer speed is
3069 * forced as ULTRA-20M.
3070 */
3071 ret = nsp32_prom_read(data, 0x07);
3072 switch (ret) {
3073 case 0:
3074 auto_sync = TRUE;
3075 break;
3076 case 1:
3077 auto_sync = FALSE;
3078 break;
3079 default:
3080 nsp32_msg(KERN_WARNING,
3081 "Unsupported Auto Sync mode. Fall back to manual mode.");
3082 auto_sync = TRUE;
3083 }
3084
3085 if (trans_mode == ULTRA20M_MODE) {
3086 auto_sync = TRUE;
3087 }
3088
3089 /*
3090 * each device Synchronous Transfer Period
3091 */
3092 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3093 target = &data->target[i];
3094 if (auto_sync == TRUE) {
3095 target->limit_entry = 0; /* set as ULTRA20M */
3096 } else {
3097 ret = nsp32_prom_read(data, i);
3098 entry = nsp32_search_period_entry(data, target, ret);
3099 if (entry < 0) {
3100 /* search failed... set maximum speed */
3101 entry = 0;
3102 }
3103 target->limit_entry = entry;
3104 }
3105 }
3106
3107 return TRUE;
3108 }
3109
3110
3111 /*
3112 * C16 110 (I-O Data: SC-NBD) data map:
3113 *
3114 * ROMADDR
3115 * 0x00 - 0x06 : Device Synchronous Transfer Period (SCSI ID 0 - 6)
3116 * Value 0x0: 20MB/S, 0x1: 10MB/S, 0x2: 5MB/S, 0x3: ASYNC
3117 * 0x07 : 0 (HBA Synchronous Transfer Period: Auto Sync)
3118 * 0x08 - 0x0f : Not Used? (0x0)
3119 * 0x10 : Transfer Mode
3120 * Value 0: PIO, 1: Busmater
3121 * 0x11 : Bus Reset Delay Time (0x00-0x20)
3122 * 0x12 : Bus Termination
3123 * Value 0: Disable, 1: Enable
3124 * 0x13 - 0x19 : Disconnection
3125 * Value 0: Disable, 1: Enable
3126 * 0x1a - 0x7c : Not Used? (0)
3127 * 0x7d : Not Used? (0xf8)
3128 * 0x7e : Constant (0x55), Validity signature
3129 * 0x7f : Constant (0xaa), Validity signature
3130 */
3131 static int nsp32_getprom_c16(nsp32_hw_data *data)
3132 {
3133 int ret, i;
3134 nsp32_target *target;
3135 int entry, val;
3136
3137 /*
3138 * Reset time which is designated by EEPROM.
3139 *
3140 * TODO: Not used yet.
3141 */
3142 data->resettime = nsp32_prom_read(data, 0x11);
3143
3144 /*
3145 * each device Synchronous Transfer Period
3146 */
3147 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3148 target = &data->target[i];
3149 ret = nsp32_prom_read(data, i);
3150 switch (ret) {
3151 case 0: /* 20MB/s */
3152 val = 0x0c;
3153 break;
3154 case 1: /* 10MB/s */
3155 val = 0x19;
3156 break;
3157 case 2: /* 5MB/s */
3158 val = 0x32;
3159 break;
3160 case 3: /* ASYNC */
3161 val = 0x00;
3162 break;
3163 default: /* default 20MB/s */
3164 val = 0x0c;
3165 break;
3166 }
3167 entry = nsp32_search_period_entry(data, target, val);
3168 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3169 /* search failed... set maximum speed */
3170 entry = 0;
3171 }
3172 target->limit_entry = entry;
3173 }
3174
3175 return TRUE;
3176 }
3177
3178
3179 /*
3180 * Atmel AT24C01A (drived in 5V) serial EEPROM routines
3181 */
3182 static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3183 {
3184 int i, val;
3185
3186 /* start condition */
3187 nsp32_prom_start(data);
3188
3189 /* device address */
3190 nsp32_prom_write_bit(data, 1); /* 1 */
3191 nsp32_prom_write_bit(data, 0); /* 0 */
3192 nsp32_prom_write_bit(data, 1); /* 1 */
3193 nsp32_prom_write_bit(data, 0); /* 0 */
3194 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3195 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3196 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3197
3198 /* R/W: W for dummy write */
3199 nsp32_prom_write_bit(data, 0);
3200
3201 /* ack */
3202 nsp32_prom_write_bit(data, 0);
3203
3204 /* word address */
3205 for (i = 7; i >= 0; i--) {
3206 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3207 }
3208
3209 /* ack */
3210 nsp32_prom_write_bit(data, 0);
3211
3212 /* start condition */
3213 nsp32_prom_start(data);
3214
3215 /* device address */
3216 nsp32_prom_write_bit(data, 1); /* 1 */
3217 nsp32_prom_write_bit(data, 0); /* 0 */
3218 nsp32_prom_write_bit(data, 1); /* 1 */
3219 nsp32_prom_write_bit(data, 0); /* 0 */
3220 nsp32_prom_write_bit(data, 0); /* A2: 0 (GND) */
3221 nsp32_prom_write_bit(data, 0); /* A1: 0 (GND) */
3222 nsp32_prom_write_bit(data, 0); /* A0: 0 (GND) */
3223
3224 /* R/W: R */
3225 nsp32_prom_write_bit(data, 1);
3226
3227 /* ack */
3228 nsp32_prom_write_bit(data, 0);
3229
3230 /* data... */
3231 val = 0;
3232 for (i = 7; i >= 0; i--) {
3233 val += (nsp32_prom_read_bit(data) << i);
3234 }
3235
3236 /* no ack */
3237 nsp32_prom_write_bit(data, 1);
3238
3239 /* stop condition */
3240 nsp32_prom_stop(data);
3241
3242 return val;
3243 }
3244
3245 static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3246 {
3247 int base = data->BaseAddress;
3248 int tmp;
3249
3250 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3251
3252 if (val == 0) {
3253 tmp &= ~bit;
3254 } else {
3255 tmp |= bit;
3256 }
3257
3258 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3259
3260 udelay(10);
3261 }
3262
3263 static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3264 {
3265 int base = data->BaseAddress;
3266 int tmp, ret;
3267
3268 if (bit != SDA) {
3269 nsp32_msg(KERN_ERR, "return value is not appropriate");
3270 return 0;
3271 }
3272
3273
3274 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3275
3276 if (tmp == 0) {
3277 ret = 0;
3278 } else {
3279 ret = 1;
3280 }
3281
3282 udelay(10);
3283
3284 return ret;
3285 }
3286
3287 static void nsp32_prom_start (nsp32_hw_data *data)
3288 {
3289 /* start condition */
3290 nsp32_prom_set(data, SCL, 1);
3291 nsp32_prom_set(data, SDA, 1);
3292 nsp32_prom_set(data, ENA, 1); /* output mode */
3293 nsp32_prom_set(data, SDA, 0); /* keeping SCL=1 and transiting
3294 * SDA 1->0 is start condition */
3295 nsp32_prom_set(data, SCL, 0);
3296 }
3297
3298 static void nsp32_prom_stop (nsp32_hw_data *data)
3299 {
3300 /* stop condition */
3301 nsp32_prom_set(data, SCL, 1);
3302 nsp32_prom_set(data, SDA, 0);
3303 nsp32_prom_set(data, ENA, 1); /* output mode */
3304 nsp32_prom_set(data, SDA, 1);
3305 nsp32_prom_set(data, SCL, 0);
3306 }
3307
3308 static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3309 {
3310 /* write */
3311 nsp32_prom_set(data, SDA, val);
3312 nsp32_prom_set(data, SCL, 1 );
3313 nsp32_prom_set(data, SCL, 0 );
3314 }
3315
3316 static int nsp32_prom_read_bit(nsp32_hw_data *data)
3317 {
3318 int val;
3319
3320 /* read */
3321 nsp32_prom_set(data, ENA, 0); /* input mode */
3322 nsp32_prom_set(data, SCL, 1);
3323
3324 val = nsp32_prom_get(data, SDA);
3325
3326 nsp32_prom_set(data, SCL, 0);
3327 nsp32_prom_set(data, ENA, 1); /* output mode */
3328
3329 return val;
3330 }
3331
3332
3333 /**************************************************************************
3334 * Power Management
3335 */
3336 #ifdef CONFIG_PM
3337
3338 /* Device suspended */
3339 static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3340 {
3341 struct Scsi_Host *host = pci_get_drvdata(pdev);
3342
3343 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state=%ld, slot=%s, host=0x%p", pdev, state, pci_name(pdev), host);
3344
3345 pci_save_state (pdev);
3346 pci_disable_device (pdev);
3347 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3348
3349 return 0;
3350 }
3351
3352 /* Device woken up */
3353 static int nsp32_resume(struct pci_dev *pdev)
3354 {
3355 struct Scsi_Host *host = pci_get_drvdata(pdev);
3356 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3357 unsigned short reg;
3358
3359 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", pdev, pci_name(pdev), host);
3360
3361 pci_set_power_state(pdev, PCI_D0);
3362 pci_enable_wake (pdev, PCI_D0, 0);
3363 pci_restore_state (pdev);
3364
3365 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3366
3367 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3368
3369 if (reg == 0xffff) {
3370 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3371 return 0;
3372 }
3373
3374 nsp32hw_init (data);
3375 nsp32_do_bus_reset(data);
3376
3377 nsp32_msg(KERN_INFO, "resume success");
3378
3379 return 0;
3380 }
3381
3382 #endif
3383
3384 /************************************************************************
3385 * PCI/Cardbus probe/remove routine
3386 */
3387 static int __devinit nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3388 {
3389 int ret;
3390 nsp32_hw_data *data = &nsp32_data_base;
3391
3392 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3393
3394 ret = pci_enable_device(pdev);
3395 if (ret) {
3396 nsp32_msg(KERN_ERR, "failed to enable pci device");
3397 return ret;
3398 }
3399
3400 data->Pci = pdev;
3401 data->pci_devid = id;
3402 data->IrqNumber = pdev->irq;
3403 data->BaseAddress = pci_resource_start(pdev, 0);
3404 data->NumAddress = pci_resource_len (pdev, 0);
3405 data->MmioAddress = ioremap_nocache(pci_resource_start(pdev, 1),
3406 pci_resource_len (pdev, 1));
3407 data->MmioLength = pci_resource_len (pdev, 1);
3408
3409 pci_set_master(pdev);
3410
3411 ret = nsp32_detect(pdev);
3412
3413 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3414 pdev->irq,
3415 data->MmioAddress, data->MmioLength,
3416 pci_name(pdev),
3417 nsp32_model[id->driver_data]);
3418
3419 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3420
3421 return ret;
3422 }
3423
3424 static void __devexit nsp32_remove(struct pci_dev *pdev)
3425 {
3426 struct Scsi_Host *host = pci_get_drvdata(pdev);
3427
3428 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3429
3430 scsi_remove_host(host);
3431
3432 nsp32_release(host);
3433
3434 scsi_host_put(host);
3435 }
3436
3437 static struct pci_driver nsp32_driver = {
3438 .name = "nsp32",
3439 .id_table = nsp32_pci_table,
3440 .probe = nsp32_probe,
3441 .remove = __devexit_p(nsp32_remove),
3442 #ifdef CONFIG_PM
3443 .suspend = nsp32_suspend,
3444 .resume = nsp32_resume,
3445 #endif
3446 };
3447
3448 /*********************************************************************
3449 * Moule entry point
3450 */
3451 static int __init init_nsp32(void) {
3452 nsp32_msg(KERN_INFO, "loading...");
3453 return pci_register_driver(&nsp32_driver);
3454 }
3455
3456 static void __exit exit_nsp32(void) {
3457 nsp32_msg(KERN_INFO, "unloading...");
3458 pci_unregister_driver(&nsp32_driver);
3459 }
3460
3461 module_init(init_nsp32);
3462 module_exit(exit_nsp32);
3463
3464 /* end */
WRT350N Kernel Patches