arch/sparc64/kernel/pci_iommu.c

   1 /* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
   2  * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
   3  *
   4  * Copyright (C) 1999 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/sched.h>
  10 #include <linux/mm.h>
  11 #include <linux/delay.h>
  12
  13 #include <asm/pbm.h>
  14
  15 #include "iommu_common.h"
  16
  17 #define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
  18         ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
  19
  20 /* Accessing IOMMU and Streaming Buffer registers.
  21  * REG parameter is a physical address.  All registers
  22  * are 64-bits in size.
  23  */
  24 #define pci_iommu_read(__reg) \
  25 ({      u64 __ret; \
  26         __asm__ __volatile__("ldxa [%1] %2, %0" \
  27                              : "=r" (__ret) \
  28                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  29                              : "memory"); \
  30         __ret; \
  31 })
  32 #define pci_iommu_write(__reg, __val) \
  33         __asm__ __volatile__("stxa %0, [%1] %2" \
  34                              : /* no outputs */ \
  35                              : "r" (__val), "r" (__reg), \
  36                                "i" (ASI_PHYS_BYPASS_EC_E))
  37
  38 /* Must be invoked under the IOMMU lock. */
  39 static void __iommu_flushall(struct pci_iommu *iommu)
  40 {
  41         unsigned long tag;
  42         int entry;
  43
  44         tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
  45         for (entry = 0; entry < 16; entry++) {
  46                 pci_iommu_write(tag, 0);
  47                 tag += 8;
  48         }
  49
  50         /* Ensure completion of previous PIO writes. */
  51         (void) pci_iommu_read(iommu->write_complete_reg);
  52
  53         /* Now update everyone's flush point. */
  54         for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
  55                 iommu->alloc_info[entry].flush =
  56                         iommu->alloc_info[entry].next;
  57         }
  58 }
  59
  60 #define IOPTE_CONSISTENT(CTX) \
  61         (IOPTE_VALID | IOPTE_CACHE | \
  62          (((CTX) << 47) & IOPTE_CONTEXT))
  63
  64 #define IOPTE_STREAMING(CTX) \
  65         (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
  66
  67 /* Existing mappings are never marked invalid, instead they
  68  * are pointed to a dummy page.
  69  */
  70 #define IOPTE_IS_DUMMY(iommu, iopte)    \
  71         ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
  72
  73 static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
  74 {
  75         unsigned long val = iopte_val(*iopte);
  76
  77         val &= ~IOPTE_PAGE;
  78         val |= iommu->dummy_page_pa;
  79
  80         iopte_val(*iopte) = val;
  81 }
  82
  83 void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize)
  84 {
  85         int i;
  86
  87         tsbsize /= sizeof(iopte_t);
  88
  89         for (i = 0; i < tsbsize; i++)
  90                 iopte_make_dummy(iommu, &iommu->page_table[i]);
  91 }
  92
  93 static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
  94 {
  95         iopte_t *iopte, *limit, *first;
  96         unsigned long cnum, ent, flush_point;
  97
  98         cnum = 0;
  99         while ((1UL << cnum) < npages)
 100                 cnum++;
 101         iopte  = (iommu->page_table +
 102                   (cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
 103
 104         if (cnum == 0)
 105                 limit = (iommu->page_table +
 106                          iommu->lowest_consistent_map);
 107         else
 108                 limit = (iopte +
 109                          (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
 110
 111         iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
 112         flush_point = iommu->alloc_info[cnum].flush;
 113
 114         first = iopte;
 115         for (;;) {
 116                 if (IOPTE_IS_DUMMY(iommu, iopte)) {
 117                         if ((iopte + (1 << cnum)) >= limit)
 118                                 ent = 0;
 119                         else
 120                                 ent = ent + 1;
 121                         iommu->alloc_info[cnum].next = ent;
 122                         if (ent == flush_point)
 123                                 __iommu_flushall(iommu);
 124                         break;
 125                 }
 126                 iopte += (1 << cnum);
 127                 ent++;
 128                 if (iopte >= limit) {
 129                         iopte = (iommu->page_table +
 130                                  (cnum <<
 131                                   (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
 132                         ent = 0;
 133                 }
 134                 if (ent == flush_point)
 135                         __iommu_flushall(iommu);
 136                 if (iopte == first)
 137                         goto bad;
 138         }
 139
 140         /* I've got your streaming cluster right here buddy boy... */
 141         return iopte;
 142
 143 bad:
 144         printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
 145                npages);
 146         return NULL;
 147 }
 148
 149 static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
 150                                    unsigned long npages, unsigned long ctx)
 151 {
 152         unsigned long cnum, ent;
 153
 154         cnum = 0;
 155         while ((1UL << cnum) < npages)
 156                 cnum++;
 157
 158         ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
 159                 >> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
 160
 161         /* If the global flush might not have caught this entry,
 162          * adjust the flush point such that we will flush before
 163          * ever trying to reuse it.
 164          */
 165 #define between(X,Y,Z)  (((Z) - (Y)) >= ((X) - (Y)))
 166         if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
 167                 iommu->alloc_info[cnum].flush = ent;
 168 #undef between
 169 }
 170
 171 /* We allocate consistent mappings from the end of cluster zero. */
 172 static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
 173 {
 174         iopte_t *iopte;
 175
 176         iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
 177         while (iopte > iommu->page_table) {
 178                 iopte--;
 179                 if (IOPTE_IS_DUMMY(iommu, iopte)) {
 180                         unsigned long tmp = npages;
 181
 182                         while (--tmp) {
 183                                 iopte--;
 184                                 if (!IOPTE_IS_DUMMY(iommu, iopte))
 185                                         break;
 186                         }
 187                         if (tmp == 0) {
 188                                 u32 entry = (iopte - iommu->page_table);
 189
 190                                 if (entry < iommu->lowest_consistent_map)
 191                                         iommu->lowest_consistent_map = entry;
 192                                 return iopte;
 193                         }
 194                 }
 195         }
 196         return NULL;
 197 }
 198
 199 static int iommu_alloc_ctx(struct pci_iommu *iommu)
 200 {
 201         int lowest = iommu->ctx_lowest_free;
 202         int sz = IOMMU_NUM_CTXS - lowest;
 203         int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
 204
 205         if (unlikely(n == sz)) {
 206                 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
 207                 if (unlikely(n == lowest)) {
 208                         printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
 209                         n = 0;
 210                 }
 211         }
 212         if (n)
 213                 __set_bit(n, iommu->ctx_bitmap);
 214
 215         return n;
 216 }
 217
 218 static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
 219 {
 220         if (likely(ctx)) {
 221                 __clear_bit(ctx, iommu->ctx_bitmap);
 222                 if (ctx < iommu->ctx_lowest_free)
 223                         iommu->ctx_lowest_free = ctx;
 224         }
 225 }
 226
 227 /* Allocate and map kernel buffer of size SIZE using consistent mode
 228  * DMA for PCI device PDEV.  Return non-NULL cpu-side address if
 229  * successful and set *DMA_ADDRP to the PCI side dma address.
 230  */
 231 void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
 232 {
 233         struct pcidev_cookie *pcp;
 234         struct pci_iommu *iommu;
 235         iopte_t *iopte;
 236         unsigned long flags, order, first_page, ctx;
 237         void *ret;
 238         int npages;
 239
 240         size = IO_PAGE_ALIGN(size);
 241         order = get_order(size);
 242         if (order >= 10)
 243                 return NULL;
 244
 245         first_page = __get_free_pages(GFP_ATOMIC, order);
 246         if (first_page == 0UL)
 247                 return NULL;
 248         memset((char *)first_page, 0, PAGE_SIZE << order);
 249
 250         pcp = pdev->sysdata;
 251         iommu = pcp->pbm->iommu;
 252
 253         spin_lock_irqsave(&iommu->lock, flags);
 254         iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
 255         if (iopte == NULL) {
 256                 spin_unlock_irqrestore(&iommu->lock, flags);
 257                 free_pages(first_page, order);
 258                 return NULL;
 259         }
 260
 261         *dma_addrp = (iommu->page_table_map_base +
 262                       ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
 263         ret = (void *) first_page;
 264         npages = size >> IO_PAGE_SHIFT;
 265         ctx = 0;
 266         if (iommu->iommu_ctxflush)
 267                 ctx = iommu_alloc_ctx(iommu);
 268         first_page = __pa(first_page);
 269         while (npages--) {
 270                 iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
 271                                      IOPTE_WRITE |
 272                                      (first_page & IOPTE_PAGE));
 273                 iopte++;
 274                 first_page += IO_PAGE_SIZE;
 275         }
 276
 277         {
 278                 int i;
 279                 u32 daddr = *dma_addrp;
 280
 281                 npages = size >> IO_PAGE_SHIFT;
 282                 for (i = 0; i < npages; i++) {
 283                         pci_iommu_write(iommu->iommu_flush, daddr);
 284                         daddr += IO_PAGE_SIZE;
 285                 }
 286         }
 287
 288         spin_unlock_irqrestore(&iommu->lock, flags);
 289
 290         return ret;
 291 }
 292
 293 /* Free and unmap a consistent DMA translation. */
 294 void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
 295 {
 296         struct pcidev_cookie *pcp;
 297         struct pci_iommu *iommu;
 298         iopte_t *iopte;
 299         unsigned long flags, order, npages, i, ctx;
 300
 301         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 302         pcp = pdev->sysdata;
 303         iommu = pcp->pbm->iommu;
 304         iopte = iommu->page_table +
 305                 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 306
 307         spin_lock_irqsave(&iommu->lock, flags);
 308
 309         if ((iopte - iommu->page_table) ==
 310             iommu->lowest_consistent_map) {
 311                 iopte_t *walk = iopte + npages;
 312                 iopte_t *limit;
 313
 314                 limit = (iommu->page_table +
 315                          (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
 316                 while (walk < limit) {
 317                         if (!IOPTE_IS_DUMMY(iommu, walk))
 318                                 break;
 319                         walk++;
 320                 }
 321                 iommu->lowest_consistent_map =
 322                         (walk - iommu->page_table);
 323         }
 324
 325         /* Data for consistent mappings cannot enter the streaming
 326          * buffers, so we only need to update the TSB.  We flush
 327          * the IOMMU here as well to prevent conflicts with the
 328          * streaming mapping deferred tlb flush scheme.
 329          */
 330
 331         ctx = 0;
 332         if (iommu->iommu_ctxflush)
 333                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 334
 335         for (i = 0; i < npages; i++, iopte++)
 336                 iopte_make_dummy(iommu, iopte);
 337
 338         if (iommu->iommu_ctxflush) {
 339                 pci_iommu_write(iommu->iommu_ctxflush, ctx);
 340         } else {
 341                 for (i = 0; i < npages; i++) {
 342                         u32 daddr = dvma + (i << IO_PAGE_SHIFT);
 343
 344                         pci_iommu_write(iommu->iommu_flush, daddr);
 345                 }
 346         }
 347
 348         iommu_free_ctx(iommu, ctx);
 349
 350         spin_unlock_irqrestore(&iommu->lock, flags);
 351
 352         order = get_order(size);
 353         if (order < 10)
 354                 free_pages((unsigned long)cpu, order);
 355 }
 356
 357 /* Map a single buffer at PTR of SZ bytes for PCI DMA
 358  * in streaming mode.
 359  */
 360 dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
 361 {
 362         struct pcidev_cookie *pcp;
 363         struct pci_iommu *iommu;
 364         struct pci_strbuf *strbuf;
 365         iopte_t *base;
 366         unsigned long flags, npages, oaddr;
 367         unsigned long i, base_paddr, ctx;
 368         u32 bus_addr, ret;
 369         unsigned long iopte_protection;
 370
 371         pcp = pdev->sysdata;
 372         iommu = pcp->pbm->iommu;
 373         strbuf = &pcp->pbm->stc;
 374
 375         if (direction == PCI_DMA_NONE)
 376                 BUG();
 377
 378         oaddr = (unsigned long)ptr;
 379         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 380         npages >>= IO_PAGE_SHIFT;
 381
 382         spin_lock_irqsave(&iommu->lock, flags);
 383
 384         base = alloc_streaming_cluster(iommu, npages);
 385         if (base == NULL)
 386                 goto bad;
 387         bus_addr = (iommu->page_table_map_base +
 388                     ((base - iommu->page_table) << IO_PAGE_SHIFT));
 389         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 390         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 391         ctx = 0;
 392         if (iommu->iommu_ctxflush)
 393                 ctx = iommu_alloc_ctx(iommu);
 394         if (strbuf->strbuf_enabled)
 395                 iopte_protection = IOPTE_STREAMING(ctx);
 396         else
 397                 iopte_protection = IOPTE_CONSISTENT(ctx);
 398         if (direction != PCI_DMA_TODEVICE)
 399                 iopte_protection |= IOPTE_WRITE;
 400
 401         for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
 402                 iopte_val(*base) = iopte_protection | base_paddr;
 403
 404         spin_unlock_irqrestore(&iommu->lock, flags);
 405
 406         return ret;
 407
 408 bad:
 409         spin_unlock_irqrestore(&iommu->lock, flags);
 410         return PCI_DMA_ERROR_CODE;
 411 }
 412
 413 static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
 414 {
 415         int limit;
 416
 417         if (strbuf->strbuf_ctxflush &&
 418             iommu->iommu_ctxflush) {
 419                 unsigned long matchreg, flushreg;
 420                 u64 val;
 421
 422                 flushreg = strbuf->strbuf_ctxflush;
 423                 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
 424
 425                 pci_iommu_write(flushreg, ctx);
 426                 val = pci_iommu_read(matchreg);
 427                 val &= 0xffff;
 428                 if (!val)
 429                         goto do_flush_sync;
 430
 431                 while (val) {
 432                         if (val & 0x1)
 433                                 pci_iommu_write(flushreg, ctx);
 434                         val >>= 1;
 435                 }
 436                 val = pci_iommu_read(matchreg);
 437                 if (unlikely(val)) {
 438                         printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
 439                                "timeout matchreg[%lx] ctx[%lx]\n",
 440                                val, ctx);
 441                         goto do_page_flush;
 442                 }
 443         } else {
 444                 unsigned long i;
 445
 446         do_page_flush:
 447                 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
 448                         pci_iommu_write(strbuf->strbuf_pflush, vaddr);
 449         }
 450
 451 do_flush_sync:
 452         /* If the device could not have possibly put dirty data into
 453          * the streaming cache, no flush-flag synchronization needs
 454          * to be performed.
 455          */
 456         if (direction == PCI_DMA_TODEVICE)
 457                 return;
 458
 459         PCI_STC_FLUSHFLAG_INIT(strbuf);
 460         pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
 461         (void) pci_iommu_read(iommu->write_complete_reg);
 462
 463         limit = 100000;
 464         while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
 465                 limit--;
 466                 if (!limit)
 467                         break;
 468                 udelay(1);
 469                 membar("#LoadLoad");
 470         }
 471         if (!limit)
 472                 printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "
 473                        "vaddr[%08x] ctx[%lx] npages[%ld]\n",
 474                        vaddr, ctx, npages);
 475 }
 476
 477 /* Unmap a single streaming mode DMA translation. */
 478 void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
 479 {
 480         struct pcidev_cookie *pcp;
 481         struct pci_iommu *iommu;
 482         struct pci_strbuf *strbuf;
 483         iopte_t *base;
 484         unsigned long flags, npages, ctx;
 485
 486         if (direction == PCI_DMA_NONE)
 487                 BUG();
 488
 489         pcp = pdev->sysdata;
 490         iommu = pcp->pbm->iommu;
 491         strbuf = &pcp->pbm->stc;
 492
 493         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 494         npages >>= IO_PAGE_SHIFT;
 495         base = iommu->page_table +
 496                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 497 #ifdef DEBUG_PCI_IOMMU
 498         if (IOPTE_IS_DUMMY(iommu, base))
 499                 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
 500                        bus_addr, sz, __builtin_return_address(0));
 501 #endif
 502         bus_addr &= IO_PAGE_MASK;
 503
 504         spin_lock_irqsave(&iommu->lock, flags);
 505
 506         /* Record the context, if any. */
 507         ctx = 0;
 508         if (iommu->iommu_ctxflush)
 509                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 510
 511         /* Step 1: Kick data out of streaming buffers if necessary. */
 512         if (strbuf->strbuf_enabled)
 513                 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 514
 515         /* Step 2: Clear out first TSB entry. */
 516         iopte_make_dummy(iommu, base);
 517
 518         free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
 519                                npages, ctx);
 520
 521         iommu_free_ctx(iommu, ctx);
 522
 523         spin_unlock_irqrestore(&iommu->lock, flags);
 524 }
 525
 526 #define SG_ENT_PHYS_ADDRESS(SG) \
 527         (__pa(page_address((SG)->page)) + (SG)->offset)
 528
 529 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
 530                            int nused, int nelems, unsigned long iopte_protection)
 531 {
 532         struct scatterlist *dma_sg = sg;
 533         struct scatterlist *sg_end = sg + nelems;
 534         int i;
 535
 536         for (i = 0; i < nused; i++) {
 537                 unsigned long pteval = ~0UL;
 538                 u32 dma_npages;
 539
 540                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
 541                               dma_sg->dma_length +
 542                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
 543                 do {
 544                         unsigned long offset;
 545                         signed int len;
 546
 547                         /* If we are here, we know we have at least one
 548                          * more page to map.  So walk forward until we
 549                          * hit a page crossing, and begin creating new
 550                          * mappings from that spot.
 551                          */
 552                         for (;;) {
 553                                 unsigned long tmp;
 554
 555                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
 556                                 len = sg->length;
 557                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
 558                                         pteval = tmp & IO_PAGE_MASK;
 559                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
 560                                         break;
 561                                 }
 562                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
 563                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
 564                                         offset = 0UL;
 565                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
 566                                         break;
 567                                 }
 568                                 sg++;
 569                         }
 570
 571                         pteval = iopte_protection | (pteval & IOPTE_PAGE);
 572                         while (len > 0) {
 573                                 *iopte++ = __iopte(pteval);
 574                                 pteval += IO_PAGE_SIZE;
 575                                 len -= (IO_PAGE_SIZE - offset);
 576                                 offset = 0;
 577                                 dma_npages--;
 578                         }
 579
 580                         pteval = (pteval & IOPTE_PAGE) + len;
 581                         sg++;
 582
 583                         /* Skip over any tail mappings we've fully mapped,
 584                          * adjusting pteval along the way.  Stop when we
 585                          * detect a page crossing event.
 586                          */
 587                         while (sg < sg_end &&
 588                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
 589                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
 590                                ((pteval ^
 591                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
 592                                 pteval += sg->length;
 593                                 sg++;
 594                         }
 595                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
 596                                 pteval = ~0UL;
 597                 } while (dma_npages != 0);
 598                 dma_sg++;
 599         }
 600 }
 601
 602 /* Map a set of buffers described by SGLIST with NELEMS array
 603  * elements in streaming mode for PCI DMA.
 604  * When making changes here, inspect the assembly output. I was having
 605  * hard time to kepp this routine out of using stack slots for holding variables.
 606  */
 607 int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 608 {
 609         struct pcidev_cookie *pcp;
 610         struct pci_iommu *iommu;
 611         struct pci_strbuf *strbuf;
 612         unsigned long flags, ctx, npages, iopte_protection;
 613         iopte_t *base;
 614         u32 dma_base;
 615         struct scatterlist *sgtmp;
 616         int used;
 617
 618         /* Fast path single entry scatterlists. */
 619         if (nelems == 1) {
 620                 sglist->dma_address =
 621                         pci_map_single(pdev,
 622                                        (page_address(sglist->page) + sglist->offset),
 623                                        sglist->length, direction);
 624                 sglist->dma_length = sglist->length;
 625                 return 1;
 626         }
 627
 628         pcp = pdev->sysdata;
 629         iommu = pcp->pbm->iommu;
 630         strbuf = &pcp->pbm->stc;
 631
 632         if (direction == PCI_DMA_NONE)
 633                 BUG();
 634
 635         /* Step 1: Prepare scatter list. */
 636
 637         npages = prepare_sg(sglist, nelems);
 638
 639         /* Step 2: Allocate a cluster. */
 640
 641         spin_lock_irqsave(&iommu->lock, flags);
 642
 643         base = alloc_streaming_cluster(iommu, npages);
 644         if (base == NULL)
 645                 goto bad;
 646         dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
 647
 648         /* Step 3: Normalize DMA addresses. */
 649         used = nelems;
 650
 651         sgtmp = sglist;
 652         while (used && sgtmp->dma_length) {
 653                 sgtmp->dma_address += dma_base;
 654                 sgtmp++;
 655                 used--;
 656         }
 657         used = nelems - used;
 658
 659         /* Step 4: Choose a context if necessary. */
 660         ctx = 0;
 661         if (iommu->iommu_ctxflush)
 662                 ctx = iommu_alloc_ctx(iommu);
 663
 664         /* Step 5: Create the mappings. */
 665         if (strbuf->strbuf_enabled)
 666                 iopte_protection = IOPTE_STREAMING(ctx);
 667         else
 668                 iopte_protection = IOPTE_CONSISTENT(ctx);
 669         if (direction != PCI_DMA_TODEVICE)
 670                 iopte_protection |= IOPTE_WRITE;
 671         fill_sg (base, sglist, used, nelems, iopte_protection);
 672 #ifdef VERIFY_SG
 673         verify_sglist(sglist, nelems, base, npages);
 674 #endif
 675
 676         spin_unlock_irqrestore(&iommu->lock, flags);
 677
 678         return used;
 679
 680 bad:
 681         spin_unlock_irqrestore(&iommu->lock, flags);
 682         return PCI_DMA_ERROR_CODE;
 683 }
 684
 685 /* Unmap a set of streaming mode DMA translations. */
 686 void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 687 {
 688         struct pcidev_cookie *pcp;
 689         struct pci_iommu *iommu;
 690         struct pci_strbuf *strbuf;
 691         iopte_t *base;
 692         unsigned long flags, ctx, i, npages;
 693         u32 bus_addr;
 694
 695         if (direction == PCI_DMA_NONE)
 696                 BUG();
 697
 698         pcp = pdev->sysdata;
 699         iommu = pcp->pbm->iommu;
 700         strbuf = &pcp->pbm->stc;
 701
 702         bus_addr = sglist->dma_address & IO_PAGE_MASK;
 703
 704         for (i = 1; i < nelems; i++)
 705                 if (sglist[i].dma_length == 0)
 706                         break;
 707         i--;
 708         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
 709
 710         base = iommu->page_table +
 711                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 712
 713 #ifdef DEBUG_PCI_IOMMU
 714         if (IOPTE_IS_DUMMY(iommu, base))
 715                 printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
 716 #endif
 717
 718         spin_lock_irqsave(&iommu->lock, flags);
 719
 720         /* Record the context, if any. */
 721         ctx = 0;
 722         if (iommu->iommu_ctxflush)
 723                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 724
 725         /* Step 1: Kick data out of streaming buffers if necessary. */
 726         if (strbuf->strbuf_enabled)
 727                 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 728
 729         /* Step 2: Clear out first TSB entry. */
 730         iopte_make_dummy(iommu, base);
 731
 732         free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
 733                                npages, ctx);
 734
 735         iommu_free_ctx(iommu, ctx);
 736
 737         spin_unlock_irqrestore(&iommu->lock, flags);
 738 }
 739
 740 /* Make physical memory consistent for a single
 741  * streaming mode DMA translation after a transfer.
 742  */
 743 void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
 744 {
 745         struct pcidev_cookie *pcp;
 746         struct pci_iommu *iommu;
 747         struct pci_strbuf *strbuf;
 748         unsigned long flags, ctx, npages;
 749
 750         pcp = pdev->sysdata;
 751         iommu = pcp->pbm->iommu;
 752         strbuf = &pcp->pbm->stc;
 753
 754         if (!strbuf->strbuf_enabled)
 755                 return;
 756
 757         spin_lock_irqsave(&iommu->lock, flags);
 758
 759         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 760         npages >>= IO_PAGE_SHIFT;
 761         bus_addr &= IO_PAGE_MASK;
 762
 763         /* Step 1: Record the context, if any. */
 764         ctx = 0;
 765         if (iommu->iommu_ctxflush &&
 766             strbuf->strbuf_ctxflush) {
 767                 iopte_t *iopte;
 768
 769                 iopte = iommu->page_table +
 770                         ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
 771                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 772         }
 773
 774         /* Step 2: Kick data out of streaming buffers. */
 775         pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 776
 777         spin_unlock_irqrestore(&iommu->lock, flags);
 778 }
 779
 780 /* Make physical memory consistent for a set of streaming
 781  * mode DMA translations after a transfer.
 782  */
 783 void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
 784 {
 785         struct pcidev_cookie *pcp;
 786         struct pci_iommu *iommu;
 787         struct pci_strbuf *strbuf;
 788         unsigned long flags, ctx, npages, i;
 789         u32 bus_addr;
 790
 791         pcp = pdev->sysdata;
 792         iommu = pcp->pbm->iommu;
 793         strbuf = &pcp->pbm->stc;
 794
 795         if (!strbuf->strbuf_enabled)
 796                 return;
 797
 798         spin_lock_irqsave(&iommu->lock, flags);
 799
 800         /* Step 1: Record the context, if any. */
 801         ctx = 0;
 802         if (iommu->iommu_ctxflush &&
 803             strbuf->strbuf_ctxflush) {
 804                 iopte_t *iopte;
 805
 806                 iopte = iommu->page_table +
 807                         ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 808                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 809         }
 810
 811         /* Step 2: Kick data out of streaming buffers. */
 812         bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
 813         for(i = 1; i < nelems; i++)
 814                 if (!sglist[i].dma_length)
 815                         break;
 816         i--;
 817         npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
 818                   - bus_addr) >> IO_PAGE_SHIFT;
 819         pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 820
 821         spin_unlock_irqrestore(&iommu->lock, flags);
 822 }
 823
 824 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
 825 {
 826         struct pci_dev *ali_isa_bridge;
 827         u8 val;
 828
 829         /* ALI sound chips generate 31-bits of DMA, a special register
 830          * determines what bit 31 is emitted as.
 831          */
 832         ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
 833                                          PCI_DEVICE_ID_AL_M1533,
 834                                          NULL);
 835
 836         pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
 837         if (set_bit)
 838                 val |= 0x01;
 839         else
 840                 val &= ~0x01;
 841         pci_write_config_byte(ali_isa_bridge, 0x7e, val);
 842         pci_dev_put(ali_isa_bridge);
 843 }
 844
 845 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
 846 {
 847         struct pcidev_cookie *pcp = pdev->sysdata;
 848         u64 dma_addr_mask;
 849
 850         if (pdev == NULL) {
 851                 dma_addr_mask = 0xffffffff;
 852         } else {
 853                 struct pci_iommu *iommu = pcp->pbm->iommu;
 854
 855                 dma_addr_mask = iommu->dma_addr_mask;
 856
 857                 if (pdev->vendor == PCI_VENDOR_ID_AL &&
 858                     pdev->device == PCI_DEVICE_ID_AL_M5451 &&
 859                     device_mask == 0x7fffffff) {
 860                         ali_sound_dma_hack(pdev,
 861                                            (dma_addr_mask & 0x80000000) != 0);
 862                         return 1;
 863                 }
 864         }
 865
 866         if (device_mask >= (1UL << 32UL))
 867                 return 0;
 868
 869         return (device_mask & dma_addr_mask) == dma_addr_mask;
 870 }