drivers/char/rocket.c

   1 /*
   2  * RocketPort device driver for Linux
   3  *
   4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
   5  *
   6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Kernel Synchronization:
  25  *
  26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
  27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
  28  * are not used.
  29  *
  30  * Critical data:
  31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of
  32  *    serial port state information and the xmit_buf circular buffer.  Protected by
  33  *    a per port spinlock.
  34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  35  *    is data to be transmitted.  Protected by atomic bit operations.
  36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
  37  *
  38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  39  * simultaneous access to the same port by more than one process.
  40  */
  41
  42 /****** Defines ******/
  43 #define ROCKET_PARANOIA_CHECK
  44 #define ROCKET_DISABLE_SIMUSAGE
  45
  46 #undef ROCKET_SOFT_FLOW
  47 #undef ROCKET_DEBUG_OPEN
  48 #undef ROCKET_DEBUG_INTR
  49 #undef ROCKET_DEBUG_WRITE
  50 #undef ROCKET_DEBUG_FLOW
  51 #undef ROCKET_DEBUG_THROTTLE
  52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  53 #undef ROCKET_DEBUG_RECEIVE
  54 #undef ROCKET_DEBUG_HANGUP
  55 #undef REV_PCI_ORDER
  56 #undef ROCKET_DEBUG_IO
  57
  58 #define POLL_PERIOD HZ/100      /*  Polling period .01 seconds (10ms) */
  59
  60 /****** Kernel includes ******/
  61
  62 #include <linux/module.h>
  63 #include <linux/errno.h>
  64 #include <linux/major.h>
  65 #include <linux/kernel.h>
  66 #include <linux/signal.h>
  67 #include <linux/slab.h>
  68 #include <linux/mm.h>
  69 #include <linux/sched.h>
  70 #include <linux/timer.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/tty.h>
  73 #include <linux/tty_driver.h>
  74 #include <linux/tty_flip.h>
  75 #include <linux/string.h>
  76 #include <linux/fcntl.h>
  77 #include <linux/ptrace.h>
  78 #include <linux/mutex.h>
  79 #include <linux/ioport.h>
  80 #include <linux/delay.h>
  81 #include <linux/completion.h>
  82 #include <linux/wait.h>
  83 #include <linux/pci.h>
  84 #include <asm/uaccess.h>
  85 #include <asm/atomic.h>
  86 #include <linux/bitops.h>
  87 #include <linux/spinlock.h>
  88 #include <linux/init.h>
  89
  90 /****** RocketPort includes ******/
  91
  92 #include "rocket_int.h"
  93 #include "rocket.h"
  94
  95 #define ROCKET_VERSION "2.09"
  96 #define ROCKET_DATE "12-June-2003"
  97
  98 /****** RocketPort Local Variables ******/
  99
 100 static void rp_do_poll(unsigned long dummy);
 101
 102 static struct tty_driver *rocket_driver;
 103
 104 static struct rocket_version driver_version = {
 105         ROCKET_VERSION, ROCKET_DATE
 106 };
 107
 108 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
 109 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
 110                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
 111 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
 112 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
 113
 114 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
 115 static unsigned long board2;
 116 static unsigned long board3;
 117 static unsigned long board4;
 118 static unsigned long controller;
 119 static int support_low_speed;
 120 static unsigned long modem1;
 121 static unsigned long modem2;
 122 static unsigned long modem3;
 123 static unsigned long modem4;
 124 static unsigned long pc104_1[8];
 125 static unsigned long pc104_2[8];
 126 static unsigned long pc104_3[8];
 127 static unsigned long pc104_4[8];
 128 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
 129
 130 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
 131 static unsigned long rcktpt_io_addr[NUM_BOARDS];
 132 static int rcktpt_type[NUM_BOARDS];
 133 static int is_PCI[NUM_BOARDS];
 134 static rocketModel_t rocketModel[NUM_BOARDS];
 135 static int max_board;
 136
 137 /*
 138  * The following arrays define the interrupt bits corresponding to each AIOP.
 139  * These bits are different between the ISA and regular PCI boards and the
 140  * Universal PCI boards.
 141  */
 142
 143 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
 144         AIOP_INTR_BIT_0,
 145         AIOP_INTR_BIT_1,
 146         AIOP_INTR_BIT_2,
 147         AIOP_INTR_BIT_3
 148 };
 149
 150 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
 151         UPCI_AIOP_INTR_BIT_0,
 152         UPCI_AIOP_INTR_BIT_1,
 153         UPCI_AIOP_INTR_BIT_2,
 154         UPCI_AIOP_INTR_BIT_3
 155 };
 156
 157 static Byte_t RData[RDATASIZE] = {
 158         0x00, 0x09, 0xf6, 0x82,
 159         0x02, 0x09, 0x86, 0xfb,
 160         0x04, 0x09, 0x00, 0x0a,
 161         0x06, 0x09, 0x01, 0x0a,
 162         0x08, 0x09, 0x8a, 0x13,
 163         0x0a, 0x09, 0xc5, 0x11,
 164         0x0c, 0x09, 0x86, 0x85,
 165         0x0e, 0x09, 0x20, 0x0a,
 166         0x10, 0x09, 0x21, 0x0a,
 167         0x12, 0x09, 0x41, 0xff,
 168         0x14, 0x09, 0x82, 0x00,
 169         0x16, 0x09, 0x82, 0x7b,
 170         0x18, 0x09, 0x8a, 0x7d,
 171         0x1a, 0x09, 0x88, 0x81,
 172         0x1c, 0x09, 0x86, 0x7a,
 173         0x1e, 0x09, 0x84, 0x81,
 174         0x20, 0x09, 0x82, 0x7c,
 175         0x22, 0x09, 0x0a, 0x0a
 176 };
 177
 178 static Byte_t RRegData[RREGDATASIZE] = {
 179         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
 180         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
 181         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
 182         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
 183         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
 184         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
 185         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
 186         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
 187         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
 188         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
 189         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
 190         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
 191         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
 192 };
 193
 194 static CONTROLLER_T sController[CTL_SIZE] = {
 195         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 196          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 197         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 198          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 199         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 200          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 201         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 202          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
 203 };
 204
 205 static Byte_t sBitMapClrTbl[8] = {
 206         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
 207 };
 208
 209 static Byte_t sBitMapSetTbl[8] = {
 210         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
 211 };
 212
 213 static int sClockPrescale = 0x14;
 214
 215 /*
 216  *  Line number is the ttySIx number (x), the Minor number.  We
 217  *  assign them sequentially, starting at zero.  The following
 218  *  array keeps track of the line number assigned to a given board/aiop/channel.
 219  */
 220 static unsigned char lineNumbers[MAX_RP_PORTS];
 221 static unsigned long nextLineNumber;
 222
 223 /*****  RocketPort Static Prototypes   *********/
 224 static int __init init_ISA(int i);
 225 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
 226 static void rp_flush_buffer(struct tty_struct *tty);
 227 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
 228 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
 229 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
 230 static void rp_start(struct tty_struct *tty);
 231 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
 232                      int ChanNum);
 233 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
 234 static void sFlushRxFIFO(CHANNEL_T * ChP);
 235 static void sFlushTxFIFO(CHANNEL_T * ChP);
 236 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
 237 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
 238 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
 239 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
 240 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
 241 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
 242                               ByteIO_t * AiopIOList, int AiopIOListSize,
 243                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
 244                               int PeriodicOnly, int altChanRingIndicator,
 245                               int UPCIRingInd);
 246 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
 247                            ByteIO_t * AiopIOList, int AiopIOListSize,
 248                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
 249 static int sReadAiopID(ByteIO_t io);
 250 static int sReadAiopNumChan(WordIO_t io);
 251
 252 MODULE_AUTHOR("Theodore Ts'o");
 253 MODULE_DESCRIPTION("Comtrol RocketPort driver");
 254 module_param(board1, ulong, 0);
 255 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
 256 module_param(board2, ulong, 0);
 257 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
 258 module_param(board3, ulong, 0);
 259 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
 260 module_param(board4, ulong, 0);
 261 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
 262 module_param(controller, ulong, 0);
 263 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
 264 module_param(support_low_speed, bool, 0);
 265 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
 266 module_param(modem1, ulong, 0);
 267 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
 268 module_param(modem2, ulong, 0);
 269 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
 270 module_param(modem3, ulong, 0);
 271 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
 272 module_param(modem4, ulong, 0);
 273 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
 274 module_param_array(pc104_1, ulong, NULL, 0);
 275 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
 276 module_param_array(pc104_2, ulong, NULL, 0);
 277 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
 278 module_param_array(pc104_3, ulong, NULL, 0);
 279 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
 280 module_param_array(pc104_4, ulong, NULL, 0);
 281 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
 282
 283 static int rp_init(void);
 284 static void rp_cleanup_module(void);
 285
 286 module_init(rp_init);
 287 module_exit(rp_cleanup_module);
 288
 289
 290 MODULE_LICENSE("Dual BSD/GPL");
 291
 292 /*************************************************************************/
 293 /*                     Module code starts here                           */
 294
 295 static inline int rocket_paranoia_check(struct r_port *info,
 296                                         const char *routine)
 297 {
 298 #ifdef ROCKET_PARANOIA_CHECK
 299         if (!info)
 300                 return 1;
 301         if (info->magic != RPORT_MAGIC) {
 302                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
 303                                 "struct in %s\n", routine);
 304                 return 1;
 305         }
 306 #endif
 307         return 0;
 308 }
 309
 310
 311 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals
 312  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the
 313  *  tty layer.
 314  */
 315 static void rp_do_receive(struct r_port *info,
 316                           struct tty_struct *tty,
 317                           CHANNEL_t * cp, unsigned int ChanStatus)
 318 {
 319         unsigned int CharNStat;
 320         int ToRecv, wRecv, space;
 321         unsigned char *cbuf;
 322
 323         ToRecv = sGetRxCnt(cp);
 324 #ifdef ROCKET_DEBUG_INTR
 325         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
 326 #endif
 327         if (ToRecv == 0)
 328                 return;
 329
 330         /*
 331          * if status indicates there are errored characters in the
 332          * FIFO, then enter status mode (a word in FIFO holds
 333          * character and status).
 334          */
 335         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
 336                 if (!(ChanStatus & STATMODE)) {
 337 #ifdef ROCKET_DEBUG_RECEIVE
 338                         printk(KERN_INFO "Entering STATMODE...\n");
 339 #endif
 340                         ChanStatus |= STATMODE;
 341                         sEnRxStatusMode(cp);
 342                 }
 343         }
 344
 345         /*
 346          * if we previously entered status mode, then read down the
 347          * FIFO one word at a time, pulling apart the character and
 348          * the status.  Update error counters depending on status
 349          */
 350         if (ChanStatus & STATMODE) {
 351 #ifdef ROCKET_DEBUG_RECEIVE
 352                 printk(KERN_INFO "Ignore %x, read %x...\n",
 353                         info->ignore_status_mask, info->read_status_mask);
 354 #endif
 355                 while (ToRecv) {
 356                         char flag;
 357
 358                         CharNStat = sInW(sGetTxRxDataIO(cp));
 359 #ifdef ROCKET_DEBUG_RECEIVE
 360                         printk(KERN_INFO "%x...\n", CharNStat);
 361 #endif
 362                         if (CharNStat & STMBREAKH)
 363                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
 364                         if (CharNStat & info->ignore_status_mask) {
 365                                 ToRecv--;
 366                                 continue;
 367                         }
 368                         CharNStat &= info->read_status_mask;
 369                         if (CharNStat & STMBREAKH)
 370                                 flag = TTY_BREAK;
 371                         else if (CharNStat & STMPARITYH)
 372                                 flag = TTY_PARITY;
 373                         else if (CharNStat & STMFRAMEH)
 374                                 flag = TTY_FRAME;
 375                         else if (CharNStat & STMRCVROVRH)
 376                                 flag = TTY_OVERRUN;
 377                         else
 378                                 flag = TTY_NORMAL;
 379                         tty_insert_flip_char(tty, CharNStat & 0xff, flag);
 380                         ToRecv--;
 381                 }
 382
 383                 /*
 384                  * after we've emptied the FIFO in status mode, turn
 385                  * status mode back off
 386                  */
 387                 if (sGetRxCnt(cp) == 0) {
 388 #ifdef ROCKET_DEBUG_RECEIVE
 389                         printk(KERN_INFO "Status mode off.\n");
 390 #endif
 391                         sDisRxStatusMode(cp);
 392                 }
 393         } else {
 394                 /*
 395                  * we aren't in status mode, so read down the FIFO two
 396                  * characters at time by doing repeated word IO
 397                  * transfer.
 398                  */
 399                 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
 400                 if (space < ToRecv) {
 401 #ifdef ROCKET_DEBUG_RECEIVE
 402                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
 403 #endif
 404                         if (space <= 0)
 405                                 return;
 406                         ToRecv = space;
 407                 }
 408                 wRecv = ToRecv >> 1;
 409                 if (wRecv)
 410                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
 411                 if (ToRecv & 1)
 412                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
 413         }
 414         /*  Push the data up to the tty layer */
 415         tty_flip_buffer_push(tty);
 416 }
 417
 418 /*
 419  *  Serial port transmit data function.  Called from the timer polling loop as a
 420  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
 421  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is
 422  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
 423  */
 424 static void rp_do_transmit(struct r_port *info)
 425 {
 426         int c;
 427         CHANNEL_t *cp = &info->channel;
 428         struct tty_struct *tty;
 429         unsigned long flags;
 430
 431 #ifdef ROCKET_DEBUG_INTR
 432         printk(KERN_DEBUG "%s\n", __func__);
 433 #endif
 434         if (!info)
 435                 return;
 436         if (!info->tty) {
 437                 printk(KERN_WARNING "rp: WARNING %s called with "
 438                                 "info->tty==NULL\n", __func__);
 439                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 440                 return;
 441         }
 442
 443         spin_lock_irqsave(&info->slock, flags);
 444         tty = info->tty;
 445         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 446
 447         /*  Loop sending data to FIFO until done or FIFO full */
 448         while (1) {
 449                 if (tty->stopped || tty->hw_stopped)
 450                         break;
 451                 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
 452                 if (c <= 0 || info->xmit_fifo_room <= 0)
 453                         break;
 454                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
 455                 if (c & 1)
 456                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
 457                 info->xmit_tail += c;
 458                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
 459                 info->xmit_cnt -= c;
 460                 info->xmit_fifo_room -= c;
 461 #ifdef ROCKET_DEBUG_INTR
 462                 printk(KERN_INFO "tx %d chars...\n", c);
 463 #endif
 464         }
 465
 466         if (info->xmit_cnt == 0)
 467                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 468
 469         if (info->xmit_cnt < WAKEUP_CHARS) {
 470                 tty_wakeup(tty);
 471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
 472                 wake_up_interruptible(&tty->poll_wait);
 473 #endif
 474         }
 475
 476         spin_unlock_irqrestore(&info->slock, flags);
 477
 478 #ifdef ROCKET_DEBUG_INTR
 479         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
 480                info->xmit_tail, info->xmit_fifo_room);
 481 #endif
 482 }
 483
 484 /*
 485  *  Called when a serial port signals it has read data in it's RX FIFO.
 486  *  It checks what interrupts are pending and services them, including
 487  *  receiving serial data.
 488  */
 489 static void rp_handle_port(struct r_port *info)
 490 {
 491         CHANNEL_t *cp;
 492         struct tty_struct *tty;
 493         unsigned int IntMask, ChanStatus;
 494
 495         if (!info)
 496                 return;
 497
 498         if ((info->flags & ROCKET_INITIALIZED) == 0) {
 499                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 500                                 "info->flags & NOT_INIT\n");
 501                 return;
 502         }
 503         if (!info->tty) {
 504                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 505                                 "info->tty==NULL\n");
 506                 return;
 507         }
 508         cp = &info->channel;
 509         tty = info->tty;
 510
 511         IntMask = sGetChanIntID(cp) & info->intmask;
 512 #ifdef ROCKET_DEBUG_INTR
 513         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
 514 #endif
 515         ChanStatus = sGetChanStatus(cp);
 516         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
 517                 rp_do_receive(info, tty, cp, ChanStatus);
 518         }
 519         if (IntMask & DELTA_CD) {       /* CD change  */
 520 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
 521                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
 522                        (ChanStatus & CD_ACT) ? "on" : "off");
 523 #endif
 524                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
 525 #ifdef ROCKET_DEBUG_HANGUP
 526                         printk(KERN_INFO "CD drop, calling hangup.\n");
 527 #endif
 528                         tty_hangup(tty);
 529                 }
 530                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
 531                 wake_up_interruptible(&info->open_wait);
 532         }
 533 #ifdef ROCKET_DEBUG_INTR
 534         if (IntMask & DELTA_CTS) {      /* CTS change */
 535                 printk(KERN_INFO "CTS change...\n");
 536         }
 537         if (IntMask & DELTA_DSR) {      /* DSR change */
 538                 printk(KERN_INFO "DSR change...\n");
 539         }
 540 #endif
 541 }
 542
 543 /*
 544  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
 545  */
 546 static void rp_do_poll(unsigned long dummy)
 547 {
 548         CONTROLLER_t *ctlp;
 549         int ctrl, aiop, ch, line;
 550         unsigned int xmitmask, i;
 551         unsigned int CtlMask;
 552         unsigned char AiopMask;
 553         Word_t bit;
 554
 555         /*  Walk through all the boards (ctrl's) */
 556         for (ctrl = 0; ctrl < max_board; ctrl++) {
 557                 if (rcktpt_io_addr[ctrl] <= 0)
 558                         continue;
 559
 560                 /*  Get a ptr to the board's control struct */
 561                 ctlp = sCtlNumToCtlPtr(ctrl);
 562
 563                 /*  Get the interrupt status from the board */
 564 #ifdef CONFIG_PCI
 565                 if (ctlp->BusType == isPCI)
 566                         CtlMask = sPCIGetControllerIntStatus(ctlp);
 567                 else
 568 #endif
 569                         CtlMask = sGetControllerIntStatus(ctlp);
 570
 571                 /*  Check if any AIOP read bits are set */
 572                 for (aiop = 0; CtlMask; aiop++) {
 573                         bit = ctlp->AiopIntrBits[aiop];
 574                         if (CtlMask & bit) {
 575                                 CtlMask &= ~bit;
 576                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
 577
 578                                 /*  Check if any port read bits are set */
 579                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
 580                                         if (AiopMask & 1) {
 581
 582                                                 /*  Get the line number (/dev/ttyRx number). */
 583                                                 /*  Read the data from the port. */
 584                                                 line = GetLineNumber(ctrl, aiop, ch);
 585                                                 rp_handle_port(rp_table[line]);
 586                                         }
 587                                 }
 588                         }
 589                 }
 590
 591                 xmitmask = xmit_flags[ctrl];
 592
 593                 /*
 594                  *  xmit_flags contains bit-significant flags, indicating there is data
 595                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
 596                  *  1, ... (32 total possible).  The variable i has the aiop and ch
 597                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
 598                  */
 599                 if (xmitmask) {
 600                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
 601                                 if (xmitmask & (1 << i)) {
 602                                         aiop = (i & 0x18) >> 3;
 603                                         ch = i & 0x07;
 604                                         line = GetLineNumber(ctrl, aiop, ch);
 605                                         rp_do_transmit(rp_table[line]);
 606                                 }
 607                         }
 608                 }
 609         }
 610
 611         /*
 612          * Reset the timer so we get called at the next clock tick (10ms).
 613          */
 614         if (atomic_read(&rp_num_ports_open))
 615                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 616 }
 617
 618 /*
 619  *  Initializes the r_port structure for a port, as well as enabling the port on
 620  *  the board.
 621  *  Inputs:  board, aiop, chan numbers
 622  */
 623 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
 624 {
 625         unsigned rocketMode;
 626         struct r_port *info;
 627         int line;
 628         CONTROLLER_T *ctlp;
 629
 630         /*  Get the next available line number */
 631         line = SetLineNumber(board, aiop, chan);
 632
 633         ctlp = sCtlNumToCtlPtr(board);
 634
 635         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
 636         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
 637         if (!info) {
 638                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
 639                                 line);
 640                 return;
 641         }
 642
 643         info->magic = RPORT_MAGIC;
 644         info->line = line;
 645         info->ctlp = ctlp;
 646         info->board = board;
 647         info->aiop = aiop;
 648         info->chan = chan;
 649         info->closing_wait = 3000;
 650         info->close_delay = 50;
 651         init_waitqueue_head(&info->open_wait);
 652         init_completion(&info->close_wait);
 653         info->flags &= ~ROCKET_MODE_MASK;
 654         switch (pc104[board][line]) {
 655         case 422:
 656                 info->flags |= ROCKET_MODE_RS422;
 657                 break;
 658         case 485:
 659                 info->flags |= ROCKET_MODE_RS485;
 660                 break;
 661         case 232:
 662         default:
 663                 info->flags |= ROCKET_MODE_RS232;
 664                 break;
 665         }
 666
 667         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
 668         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
 669                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
 670                                 board, aiop, chan);
 671                 kfree(info);
 672                 return;
 673         }
 674
 675         rocketMode = info->flags & ROCKET_MODE_MASK;
 676
 677         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
 678                 sEnRTSToggle(&info->channel);
 679         else
 680                 sDisRTSToggle(&info->channel);
 681
 682         if (ctlp->boardType == ROCKET_TYPE_PC104) {
 683                 switch (rocketMode) {
 684                 case ROCKET_MODE_RS485:
 685                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
 686                         break;
 687                 case ROCKET_MODE_RS422:
 688                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
 689                         break;
 690                 case ROCKET_MODE_RS232:
 691                 default:
 692                         if (info->flags & ROCKET_RTS_TOGGLE)
 693                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
 694                         else
 695                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
 696                         break;
 697                 }
 698         }
 699         spin_lock_init(&info->slock);
 700         mutex_init(&info->write_mtx);
 701         rp_table[line] = info;
 702         tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
 703                         NULL);
 704 }
 705
 706 /*
 707  *  Configures a rocketport port according to its termio settings.  Called from
 708  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
 709  */
 710 static void configure_r_port(struct r_port *info,
 711                              struct ktermios *old_termios)
 712 {
 713         unsigned cflag;
 714         unsigned long flags;
 715         unsigned rocketMode;
 716         int bits, baud, divisor;
 717         CHANNEL_t *cp;
 718         struct ktermios *t = info->tty->termios;
 719
 720         cp = &info->channel;
 721         cflag = t->c_cflag;
 722
 723         /* Byte size and parity */
 724         if ((cflag & CSIZE) == CS8) {
 725                 sSetData8(cp);
 726                 bits = 10;
 727         } else {
 728                 sSetData7(cp);
 729                 bits = 9;
 730         }
 731         if (cflag & CSTOPB) {
 732                 sSetStop2(cp);
 733                 bits++;
 734         } else {
 735                 sSetStop1(cp);
 736         }
 737
 738         if (cflag & PARENB) {
 739                 sEnParity(cp);
 740                 bits++;
 741                 if (cflag & PARODD) {
 742                         sSetOddParity(cp);
 743                 } else {
 744                         sSetEvenParity(cp);
 745                 }
 746         } else {
 747                 sDisParity(cp);
 748         }
 749
 750         /* baud rate */
 751         baud = tty_get_baud_rate(info->tty);
 752         if (!baud)
 753                 baud = 9600;
 754         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
 755         if ((divisor >= 8192 || divisor < 0) && old_termios) {
 756                 baud = tty_termios_baud_rate(old_termios);
 757                 if (!baud)
 758                         baud = 9600;
 759                 divisor = (rp_baud_base[info->board] / baud) - 1;
 760         }
 761         if (divisor >= 8192 || divisor < 0) {
 762                 baud = 9600;
 763                 divisor = (rp_baud_base[info->board] / baud) - 1;
 764         }
 765         info->cps = baud / bits;
 766         sSetBaud(cp, divisor);
 767
 768         /* FIXME: Should really back compute a baud rate from the divisor */
 769         tty_encode_baud_rate(info->tty, baud, baud);
 770
 771         if (cflag & CRTSCTS) {
 772                 info->intmask |= DELTA_CTS;
 773                 sEnCTSFlowCtl(cp);
 774         } else {
 775                 info->intmask &= ~DELTA_CTS;
 776                 sDisCTSFlowCtl(cp);
 777         }
 778         if (cflag & CLOCAL) {
 779                 info->intmask &= ~DELTA_CD;
 780         } else {
 781                 spin_lock_irqsave(&info->slock, flags);
 782                 if (sGetChanStatus(cp) & CD_ACT)
 783                         info->cd_status = 1;
 784                 else
 785                         info->cd_status = 0;
 786                 info->intmask |= DELTA_CD;
 787                 spin_unlock_irqrestore(&info->slock, flags);
 788         }
 789
 790         /*
 791          * Handle software flow control in the board
 792          */
 793 #ifdef ROCKET_SOFT_FLOW
 794         if (I_IXON(info->tty)) {
 795                 sEnTxSoftFlowCtl(cp);
 796                 if (I_IXANY(info->tty)) {
 797                         sEnIXANY(cp);
 798                 } else {
 799                         sDisIXANY(cp);
 800                 }
 801                 sSetTxXONChar(cp, START_CHAR(info->tty));
 802                 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
 803         } else {
 804                 sDisTxSoftFlowCtl(cp);
 805                 sDisIXANY(cp);
 806                 sClrTxXOFF(cp);
 807         }
 808 #endif
 809
 810         /*
 811          * Set up ignore/read mask words
 812          */
 813         info->read_status_mask = STMRCVROVRH | 0xFF;
 814         if (I_INPCK(info->tty))
 815                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
 816         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
 817                 info->read_status_mask |= STMBREAKH;
 818
 819         /*
 820          * Characters to ignore
 821          */
 822         info->ignore_status_mask = 0;
 823         if (I_IGNPAR(info->tty))
 824                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
 825         if (I_IGNBRK(info->tty)) {
 826                 info->ignore_status_mask |= STMBREAKH;
 827                 /*
 828                  * If we're ignoring parity and break indicators,
 829                  * ignore overruns too.  (For real raw support).
 830                  */
 831                 if (I_IGNPAR(info->tty))
 832                         info->ignore_status_mask |= STMRCVROVRH;
 833         }
 834
 835         rocketMode = info->flags & ROCKET_MODE_MASK;
 836
 837         if ((info->flags & ROCKET_RTS_TOGGLE)
 838             || (rocketMode == ROCKET_MODE_RS485))
 839                 sEnRTSToggle(cp);
 840         else
 841                 sDisRTSToggle(cp);
 842
 843         sSetRTS(&info->channel);
 844
 845         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
 846                 switch (rocketMode) {
 847                 case ROCKET_MODE_RS485:
 848                         sSetInterfaceMode(cp, InterfaceModeRS485);
 849                         break;
 850                 case ROCKET_MODE_RS422:
 851                         sSetInterfaceMode(cp, InterfaceModeRS422);
 852                         break;
 853                 case ROCKET_MODE_RS232:
 854                 default:
 855                         if (info->flags & ROCKET_RTS_TOGGLE)
 856                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
 857                         else
 858                                 sSetInterfaceMode(cp, InterfaceModeRS232);
 859                         break;
 860                 }
 861         }
 862 }
 863
 864 /*  info->count is considered critical, protected by spinlocks.  */
 865 static int block_til_ready(struct tty_struct *tty, struct file *filp,
 866                            struct r_port *info)
 867 {
 868         DECLARE_WAITQUEUE(wait, current);
 869         int retval;
 870         int do_clocal = 0, extra_count = 0;
 871         unsigned long flags;
 872
 873         /*
 874          * If the device is in the middle of being closed, then block
 875          * until it's done, and then try again.
 876          */
 877         if (tty_hung_up_p(filp))
 878                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 879         if (info->flags & ROCKET_CLOSING) {
 880                 if (wait_for_completion_interruptible(&info->close_wait))
 881                         return -ERESTARTSYS;
 882                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 883         }
 884
 885         /*
 886          * If non-blocking mode is set, or the port is not enabled,
 887          * then make the check up front and then exit.
 888          */
 889         if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
 890                 info->flags |= ROCKET_NORMAL_ACTIVE;
 891                 return 0;
 892         }
 893         if (tty->termios->c_cflag & CLOCAL)
 894                 do_clocal = 1;
 895
 896         /*
 897          * Block waiting for the carrier detect and the line to become free.  While we are in
 898          * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
 899          * We restore it upon exit, either normal or abnormal.
 900          */
 901         retval = 0;
 902         add_wait_queue(&info->open_wait, &wait);
 903 #ifdef ROCKET_DEBUG_OPEN
 904         printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
 905 #endif
 906         spin_lock_irqsave(&info->slock, flags);
 907
 908 #ifdef ROCKET_DISABLE_SIMUSAGE
 909         info->flags |= ROCKET_NORMAL_ACTIVE;
 910 #else
 911         if (!tty_hung_up_p(filp)) {
 912                 extra_count = 1;
 913                 info->count--;
 914         }
 915 #endif
 916         info->blocked_open++;
 917
 918         spin_unlock_irqrestore(&info->slock, flags);
 919
 920         while (1) {
 921                 if (tty->termios->c_cflag & CBAUD) {
 922                         sSetDTR(&info->channel);
 923                         sSetRTS(&info->channel);
 924                 }
 925                 set_current_state(TASK_INTERRUPTIBLE);
 926                 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
 927                         if (info->flags & ROCKET_HUP_NOTIFY)
 928                                 retval = -EAGAIN;
 929                         else
 930                                 retval = -ERESTARTSYS;
 931                         break;
 932                 }
 933                 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
 934                         break;
 935                 if (signal_pending(current)) {
 936                         retval = -ERESTARTSYS;
 937                         break;
 938                 }
 939 #ifdef ROCKET_DEBUG_OPEN
 940                 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
 941                      info->line, info->count, info->flags);
 942 #endif
 943                 schedule();     /*  Don't hold spinlock here, will hang PC */
 944         }
 945         __set_current_state(TASK_RUNNING);
 946         remove_wait_queue(&info->open_wait, &wait);
 947
 948         spin_lock_irqsave(&info->slock, flags);
 949
 950         if (extra_count)
 951                 info->count++;
 952         info->blocked_open--;
 953
 954         spin_unlock_irqrestore(&info->slock, flags);
 955
 956 #ifdef ROCKET_DEBUG_OPEN
 957         printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
 958                info->line, info->count);
 959 #endif
 960         if (retval)
 961                 return retval;
 962         info->flags |= ROCKET_NORMAL_ACTIVE;
 963         return 0;
 964 }
 965
 966 /*
 967  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in
 968  *  port's r_port struct.  Initializes the port hardware.
 969  */
 970 static int rp_open(struct tty_struct *tty, struct file *filp)
 971 {
 972         struct r_port *info;
 973         int line = 0, retval;
 974         CHANNEL_t *cp;
 975         unsigned long page;
 976
 977         line = tty->index;
 978         if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
 979                 return -ENXIO;
 980
 981         page = __get_free_page(GFP_KERNEL);
 982         if (!page)
 983                 return -ENOMEM;
 984
 985         if (info->flags & ROCKET_CLOSING) {
 986                 retval = wait_for_completion_interruptible(&info->close_wait);
 987                 free_page(page);
 988                 if (retval)
 989                         return retval;
 990                 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 991         }
 992
 993         /*
 994          * We must not sleep from here until the port is marked fully in use.
 995          */
 996         if (info->xmit_buf)
 997                 free_page(page);
 998         else
 999                 info->xmit_buf = (unsigned char *) page;
1000
1001         tty->driver_data = info;
1002         info->tty = tty;
1003
1004         if (info->count++ == 0) {
1005                 atomic_inc(&rp_num_ports_open);
1006
1007 #ifdef ROCKET_DEBUG_OPEN
1008                 printk(KERN_INFO "rocket mod++ = %d...\n",
1009                                 atomic_read(&rp_num_ports_open));
1010 #endif
1011         }
1012 #ifdef ROCKET_DEBUG_OPEN
1013         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1014 #endif
1015
1016         /*
1017          * Info->count is now 1; so it's safe to sleep now.
1018          */
1019         if ((info->flags & ROCKET_INITIALIZED) == 0) {
1020                 cp = &info->channel;
1021                 sSetRxTrigger(cp, TRIG_1);
1022                 if (sGetChanStatus(cp) & CD_ACT)
1023                         info->cd_status = 1;
1024                 else
1025                         info->cd_status = 0;
1026                 sDisRxStatusMode(cp);
1027                 sFlushRxFIFO(cp);
1028                 sFlushTxFIFO(cp);
1029
1030                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1031                 sSetRxTrigger(cp, TRIG_1);
1032
1033                 sGetChanStatus(cp);
1034                 sDisRxStatusMode(cp);
1035                 sClrTxXOFF(cp);
1036
1037                 sDisCTSFlowCtl(cp);
1038                 sDisTxSoftFlowCtl(cp);
1039
1040                 sEnRxFIFO(cp);
1041                 sEnTransmit(cp);
1042
1043                 info->flags |= ROCKET_INITIALIZED;
1044
1045                 /*
1046                  * Set up the tty->alt_speed kludge
1047                  */
1048                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1049                         info->tty->alt_speed = 57600;
1050                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1051                         info->tty->alt_speed = 115200;
1052                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1053                         info->tty->alt_speed = 230400;
1054                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1055                         info->tty->alt_speed = 460800;
1056
1057                 configure_r_port(info, NULL);
1058                 if (tty->termios->c_cflag & CBAUD) {
1059                         sSetDTR(cp);
1060                         sSetRTS(cp);
1061                 }
1062         }
1063         /*  Starts (or resets) the maint polling loop */
1064         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1065
1066         retval = block_til_ready(tty, filp, info);
1067         if (retval) {
1068 #ifdef ROCKET_DEBUG_OPEN
1069                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1070 #endif
1071                 return retval;
1072         }
1073         return 0;
1074 }
1075
1076 /*
1077  *  Exception handler that closes a serial port. info->count is considered critical.
1078  */
1079 static void rp_close(struct tty_struct *tty, struct file *filp)
1080 {
1081         struct r_port *info = (struct r_port *) tty->driver_data;
1082         unsigned long flags;
1083         int timeout;
1084         CHANNEL_t *cp;
1085
1086         if (rocket_paranoia_check(info, "rp_close"))
1087                 return;
1088
1089 #ifdef ROCKET_DEBUG_OPEN
1090         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1091 #endif
1092
1093         if (tty_hung_up_p(filp))
1094                 return;
1095         spin_lock_irqsave(&info->slock, flags);
1096
1097         if ((tty->count == 1) && (info->count != 1)) {
1098                 /*
1099                  * Uh, oh.  tty->count is 1, which means that the tty
1100                  * structure will be freed.  Info->count should always
1101                  * be one in these conditions.  If it's greater than
1102                  * one, we've got real problems, since it means the
1103                  * serial port won't be shutdown.
1104                  */
1105                 printk(KERN_WARNING "rp_close: bad serial port count; "
1106                         "tty->count is 1, info->count is %d\n", info->count);
1107                 info->count = 1;
1108         }
1109         if (--info->count < 0) {
1110                 printk(KERN_WARNING "rp_close: bad serial port count for "
1111                                 "ttyR%d: %d\n", info->line, info->count);
1112                 info->count = 0;
1113         }
1114         if (info->count) {
1115                 spin_unlock_irqrestore(&info->slock, flags);
1116                 return;
1117         }
1118         info->flags |= ROCKET_CLOSING;
1119         spin_unlock_irqrestore(&info->slock, flags);
1120
1121         cp = &info->channel;
1122
1123         /*
1124          * Notify the line discpline to only process XON/XOFF characters
1125          */
1126         tty->closing = 1;
1127
1128         /*
1129          * If transmission was throttled by the application request,
1130          * just flush the xmit buffer.
1131          */
1132         if (tty->flow_stopped)
1133                 rp_flush_buffer(tty);
1134
1135         /*
1136          * Wait for the transmit buffer to clear
1137          */
1138         if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1139                 tty_wait_until_sent(tty, info->closing_wait);
1140         /*
1141          * Before we drop DTR, make sure the UART transmitter
1142          * has completely drained; this is especially
1143          * important if there is a transmit FIFO!
1144          */
1145         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1146         if (timeout == 0)
1147                 timeout = 1;
1148         rp_wait_until_sent(tty, timeout);
1149         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1150
1151         sDisTransmit(cp);
1152         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1153         sDisCTSFlowCtl(cp);
1154         sDisTxSoftFlowCtl(cp);
1155         sClrTxXOFF(cp);
1156         sFlushRxFIFO(cp);
1157         sFlushTxFIFO(cp);
1158         sClrRTS(cp);
1159         if (C_HUPCL(tty))
1160                 sClrDTR(cp);
1161
1162         rp_flush_buffer(tty);
1163
1164         tty_ldisc_flush(tty);
1165
1166         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1167
1168         if (info->blocked_open) {
1169                 if (info->close_delay) {
1170                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
1171                 }
1172                 wake_up_interruptible(&info->open_wait);
1173         } else {
1174                 if (info->xmit_buf) {
1175                         free_page((unsigned long) info->xmit_buf);
1176                         info->xmit_buf = NULL;
1177                 }
1178         }
1179         info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1180         tty->closing = 0;
1181         complete_all(&info->close_wait);
1182         atomic_dec(&rp_num_ports_open);
1183
1184 #ifdef ROCKET_DEBUG_OPEN
1185         printk(KERN_INFO "rocket mod-- = %d...\n",
1186                         atomic_read(&rp_num_ports_open));
1187         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1188 #endif
1189
1190 }
1191
1192 static void rp_set_termios(struct tty_struct *tty,
1193                            struct ktermios *old_termios)
1194 {
1195         struct r_port *info = (struct r_port *) tty->driver_data;
1196         CHANNEL_t *cp;
1197         unsigned cflag;
1198
1199         if (rocket_paranoia_check(info, "rp_set_termios"))
1200                 return;
1201
1202         cflag = tty->termios->c_cflag;
1203
1204         /*
1205          * This driver doesn't support CS5 or CS6
1206          */
1207         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1208                 tty->termios->c_cflag =
1209                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1210         /* Or CMSPAR */
1211         tty->termios->c_cflag &= ~CMSPAR;
1212
1213         configure_r_port(info, old_termios);
1214
1215         cp = &info->channel;
1216
1217         /* Handle transition to B0 status */
1218         if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1219                 sClrDTR(cp);
1220                 sClrRTS(cp);
1221         }
1222
1223         /* Handle transition away from B0 status */
1224         if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1225                 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1226                         sSetRTS(cp);
1227                 sSetDTR(cp);
1228         }
1229
1230         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1231                 tty->hw_stopped = 0;
1232                 rp_start(tty);
1233         }
1234 }
1235
1236 static void rp_break(struct tty_struct *tty, int break_state)
1237 {
1238         struct r_port *info = (struct r_port *) tty->driver_data;
1239         unsigned long flags;
1240
1241         if (rocket_paranoia_check(info, "rp_break"))
1242                 return;
1243
1244         spin_lock_irqsave(&info->slock, flags);
1245         if (break_state == -1)
1246                 sSendBreak(&info->channel);
1247         else
1248                 sClrBreak(&info->channel);
1249         spin_unlock_irqrestore(&info->slock, flags);
1250 }
1251
1252 /*
1253  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1254  * the UPCI boards was added, it was decided to make this a function because
1255  * the macro was getting too complicated. All cases except the first one
1256  * (UPCIRingInd) are taken directly from the original macro.
1257  */
1258 static int sGetChanRI(CHANNEL_T * ChP)
1259 {
1260         CONTROLLER_t *CtlP = ChP->CtlP;
1261         int ChanNum = ChP->ChanNum;
1262         int RingInd = 0;
1263
1264         if (CtlP->UPCIRingInd)
1265                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1266         else if (CtlP->AltChanRingIndicator)
1267                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1268         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1269                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1270
1271         return RingInd;
1272 }
1273
1274 /********************************************************************************************/
1275 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1276
1277 /*
1278  *  Returns the state of the serial modem control lines.  These next 2 functions
1279  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1280  */
1281 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1282 {
1283         struct r_port *info = (struct r_port *)tty->driver_data;
1284         unsigned int control, result, ChanStatus;
1285
1286         ChanStatus = sGetChanStatusLo(&info->channel);
1287         control = info->channel.TxControl[3];
1288         result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1289                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1290                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1291                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1292                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1293                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1294
1295         return result;
1296 }
1297
1298 /*
1299  *  Sets the modem control lines
1300  */
1301 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1302                     unsigned int set, unsigned int clear)
1303 {
1304         struct r_port *info = (struct r_port *)tty->driver_data;
1305
1306         if (set & TIOCM_RTS)
1307                 info->channel.TxControl[3] |= SET_RTS;
1308         if (set & TIOCM_DTR)
1309                 info->channel.TxControl[3] |= SET_DTR;
1310         if (clear & TIOCM_RTS)
1311                 info->channel.TxControl[3] &= ~SET_RTS;
1312         if (clear & TIOCM_DTR)
1313                 info->channel.TxControl[3] &= ~SET_DTR;
1314
1315         sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1316         return 0;
1317 }
1318
1319 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1320 {
1321         struct rocket_config tmp;
1322
1323         if (!retinfo)
1324                 return -EFAULT;
1325         memset(&tmp, 0, sizeof (tmp));
1326         tmp.line = info->line;
1327         tmp.flags = info->flags;
1328         tmp.close_delay = info->close_delay;
1329         tmp.closing_wait = info->closing_wait;
1330         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1331
1332         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1333                 return -EFAULT;
1334         return 0;
1335 }
1336
1337 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1338 {
1339         struct rocket_config new_serial;
1340
1341         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1342                 return -EFAULT;
1343
1344         if (!capable(CAP_SYS_ADMIN))
1345         {
1346                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1347                         return -EPERM;
1348                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1349                 configure_r_port(info, NULL);
1350                 return 0;
1351         }
1352
1353         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1354         info->close_delay = new_serial.close_delay;
1355         info->closing_wait = new_serial.closing_wait;
1356
1357         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1358                 info->tty->alt_speed = 57600;
1359         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1360                 info->tty->alt_speed = 115200;
1361         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1362                 info->tty->alt_speed = 230400;
1363         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1364                 info->tty->alt_speed = 460800;
1365
1366         configure_r_port(info, NULL);
1367         return 0;
1368 }
1369
1370 /*
1371  *  This function fills in a rocket_ports struct with information
1372  *  about what boards/ports are in the system.  This info is passed
1373  *  to user space.  See setrocket.c where the info is used to create
1374  *  the /dev/ttyRx ports.
1375  */
1376 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1377 {
1378         struct rocket_ports tmp;
1379         int board;
1380
1381         if (!retports)
1382                 return -EFAULT;
1383         memset(&tmp, 0, sizeof (tmp));
1384         tmp.tty_major = rocket_driver->major;
1385
1386         for (board = 0; board < 4; board++) {
1387                 tmp.rocketModel[board].model = rocketModel[board].model;
1388                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1389                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1390                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1391                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1392         }
1393         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1394                 return -EFAULT;
1395         return 0;
1396 }
1397
1398 static int reset_rm2(struct r_port *info, void __user *arg)
1399 {
1400         int reset;
1401
1402         if (!capable(CAP_SYS_ADMIN))
1403                 return -EPERM;
1404
1405         if (copy_from_user(&reset, arg, sizeof (int)))
1406                 return -EFAULT;
1407         if (reset)
1408                 reset = 1;
1409
1410         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1411             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1412                 return -EINVAL;
1413
1414         if (info->ctlp->BusType == isISA)
1415                 sModemReset(info->ctlp, info->chan, reset);
1416         else
1417                 sPCIModemReset(info->ctlp, info->chan, reset);
1418
1419         return 0;
1420 }
1421
1422 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1423 {
1424         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1425                 return -EFAULT;
1426         return 0;
1427 }
1428
1429 /*  IOCTL call handler into the driver */
1430 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1431                     unsigned int cmd, unsigned long arg)
1432 {
1433         struct r_port *info = (struct r_port *) tty->driver_data;
1434         void __user *argp = (void __user *)arg;
1435
1436         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1437                 return -ENXIO;
1438
1439         switch (cmd) {
1440         case RCKP_GET_STRUCT:
1441                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1442                         return -EFAULT;
1443                 return 0;
1444         case RCKP_GET_CONFIG:
1445                 return get_config(info, argp);
1446         case RCKP_SET_CONFIG:
1447                 return set_config(info, argp);
1448         case RCKP_GET_PORTS:
1449                 return get_ports(info, argp);
1450         case RCKP_RESET_RM2:
1451                 return reset_rm2(info, argp);
1452         case RCKP_GET_VERSION:
1453                 return get_version(info, argp);
1454         default:
1455                 return -ENOIOCTLCMD;
1456         }
1457         return 0;
1458 }
1459
1460 static void rp_send_xchar(struct tty_struct *tty, char ch)
1461 {
1462         struct r_port *info = (struct r_port *) tty->driver_data;
1463         CHANNEL_t *cp;
1464
1465         if (rocket_paranoia_check(info, "rp_send_xchar"))
1466                 return;
1467
1468         cp = &info->channel;
1469         if (sGetTxCnt(cp))
1470                 sWriteTxPrioByte(cp, ch);
1471         else
1472                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1473 }
1474
1475 static void rp_throttle(struct tty_struct *tty)
1476 {
1477         struct r_port *info = (struct r_port *) tty->driver_data;
1478         CHANNEL_t *cp;
1479
1480 #ifdef ROCKET_DEBUG_THROTTLE
1481         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1482                tty->ldisc.chars_in_buffer(tty));
1483 #endif
1484
1485         if (rocket_paranoia_check(info, "rp_throttle"))
1486                 return;
1487
1488         cp = &info->channel;
1489         if (I_IXOFF(tty))
1490                 rp_send_xchar(tty, STOP_CHAR(tty));
1491
1492         sClrRTS(&info->channel);
1493 }
1494
1495 static void rp_unthrottle(struct tty_struct *tty)
1496 {
1497         struct r_port *info = (struct r_port *) tty->driver_data;
1498         CHANNEL_t *cp;
1499 #ifdef ROCKET_DEBUG_THROTTLE
1500         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1501                tty->ldisc.chars_in_buffer(tty));
1502 #endif
1503
1504         if (rocket_paranoia_check(info, "rp_throttle"))
1505                 return;
1506
1507         cp = &info->channel;
1508         if (I_IXOFF(tty))
1509                 rp_send_xchar(tty, START_CHAR(tty));
1510
1511         sSetRTS(&info->channel);
1512 }
1513
1514 /*
1515  * ------------------------------------------------------------
1516  * rp_stop() and rp_start()
1517  *
1518  * This routines are called before setting or resetting tty->stopped.
1519  * They enable or disable transmitter interrupts, as necessary.
1520  * ------------------------------------------------------------
1521  */
1522 static void rp_stop(struct tty_struct *tty)
1523 {
1524         struct r_port *info = (struct r_port *) tty->driver_data;
1525
1526 #ifdef ROCKET_DEBUG_FLOW
1527         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1528                info->xmit_cnt, info->xmit_fifo_room);
1529 #endif
1530
1531         if (rocket_paranoia_check(info, "rp_stop"))
1532                 return;
1533
1534         if (sGetTxCnt(&info->channel))
1535                 sDisTransmit(&info->channel);
1536 }
1537
1538 static void rp_start(struct tty_struct *tty)
1539 {
1540         struct r_port *info = (struct r_port *) tty->driver_data;
1541
1542 #ifdef ROCKET_DEBUG_FLOW
1543         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1544                info->xmit_cnt, info->xmit_fifo_room);
1545 #endif
1546
1547         if (rocket_paranoia_check(info, "rp_stop"))
1548                 return;
1549
1550         sEnTransmit(&info->channel);
1551         set_bit((info->aiop * 8) + info->chan,
1552                 (void *) &xmit_flags[info->board]);
1553 }
1554
1555 /*
1556  * rp_wait_until_sent() --- wait until the transmitter is empty
1557  */
1558 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1559 {
1560         struct r_port *info = (struct r_port *) tty->driver_data;
1561         CHANNEL_t *cp;
1562         unsigned long orig_jiffies;
1563         int check_time, exit_time;
1564         int txcnt;
1565
1566         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1567                 return;
1568
1569         cp = &info->channel;
1570
1571         orig_jiffies = jiffies;
1572 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1573         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1574                jiffies);
1575         printk(KERN_INFO "cps=%d...\n", info->cps);
1576 #endif
1577         while (1) {
1578                 txcnt = sGetTxCnt(cp);
1579                 if (!txcnt) {
1580                         if (sGetChanStatusLo(cp) & TXSHRMT)
1581                                 break;
1582                         check_time = (HZ / info->cps) / 5;
1583                 } else {
1584                         check_time = HZ * txcnt / info->cps;
1585                 }
1586                 if (timeout) {
1587                         exit_time = orig_jiffies + timeout - jiffies;
1588                         if (exit_time <= 0)
1589                                 break;
1590                         if (exit_time < check_time)
1591                                 check_time = exit_time;
1592                 }
1593                 if (check_time == 0)
1594                         check_time = 1;
1595 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1596                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1597                                 jiffies, check_time);
1598 #endif
1599                 msleep_interruptible(jiffies_to_msecs(check_time));
1600                 if (signal_pending(current))
1601                         break;
1602         }
1603         __set_current_state(TASK_RUNNING);
1604 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1605         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1606 #endif
1607 }
1608
1609 /*
1610  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1611  */
1612 static void rp_hangup(struct tty_struct *tty)
1613 {
1614         CHANNEL_t *cp;
1615         struct r_port *info = (struct r_port *) tty->driver_data;
1616
1617         if (rocket_paranoia_check(info, "rp_hangup"))
1618                 return;
1619
1620 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1621         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1622 #endif
1623         rp_flush_buffer(tty);
1624         if (info->flags & ROCKET_CLOSING)
1625                 return;
1626         if (info->count)
1627                 atomic_dec(&rp_num_ports_open);
1628         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1629
1630         info->count = 0;
1631         info->flags &= ~ROCKET_NORMAL_ACTIVE;
1632         info->tty = NULL;
1633
1634         cp = &info->channel;
1635         sDisRxFIFO(cp);
1636         sDisTransmit(cp);
1637         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1638         sDisCTSFlowCtl(cp);
1639         sDisTxSoftFlowCtl(cp);
1640         sClrTxXOFF(cp);
1641         info->flags &= ~ROCKET_INITIALIZED;
1642
1643         wake_up_interruptible(&info->open_wait);
1644 }
1645
1646 /*
1647  *  Exception handler - write char routine.  The RocketPort driver uses a
1648  *  double-buffering strategy, with the twist that if the in-memory CPU
1649  *  buffer is empty, and there's space in the transmit FIFO, the
1650  *  writing routines will write directly to transmit FIFO.
1651  *  Write buffer and counters protected by spinlocks
1652  */
1653 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1654 {
1655         struct r_port *info = (struct r_port *) tty->driver_data;
1656         CHANNEL_t *cp;
1657         unsigned long flags;
1658
1659         if (rocket_paranoia_check(info, "rp_put_char"))
1660                 return;
1661
1662         /*
1663          * Grab the port write mutex, locking out other processes that try to
1664          * write to this port
1665          */
1666         mutex_lock(&info->write_mtx);
1667
1668 #ifdef ROCKET_DEBUG_WRITE
1669         printk(KERN_INFO "rp_put_char %c...\n", ch);
1670 #endif
1671
1672         spin_lock_irqsave(&info->slock, flags);
1673         cp = &info->channel;
1674
1675         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1676                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1677
1678         if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1679                 info->xmit_buf[info->xmit_head++] = ch;
1680                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1681                 info->xmit_cnt++;
1682                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1683         } else {
1684                 sOutB(sGetTxRxDataIO(cp), ch);
1685                 info->xmit_fifo_room--;
1686         }
1687         spin_unlock_irqrestore(&info->slock, flags);
1688         mutex_unlock(&info->write_mtx);
1689 }
1690
1691 /*
1692  *  Exception handler - write routine, called when user app writes to the device.
1693  *  A per port write mutex is used to protect from another process writing to
1694  *  this port at the same time.  This other process could be running on the other CPU
1695  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1696  *  Spinlocks protect the info xmit members.
1697  */
1698 static int rp_write(struct tty_struct *tty,
1699                     const unsigned char *buf, int count)
1700 {
1701         struct r_port *info = (struct r_port *) tty->driver_data;
1702         CHANNEL_t *cp;
1703         const unsigned char *b;
1704         int c, retval = 0;
1705         unsigned long flags;
1706
1707         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1708                 return 0;
1709
1710         if (mutex_lock_interruptible(&info->write_mtx))
1711                 return -ERESTARTSYS;
1712
1713 #ifdef ROCKET_DEBUG_WRITE
1714         printk(KERN_INFO "rp_write %d chars...\n", count);
1715 #endif
1716         cp = &info->channel;
1717
1718         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1719                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1720
1721         /*
1722          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes
1723          *  into FIFO.  Use the write queue for temp storage.
1724          */
1725         if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1726                 c = min(count, info->xmit_fifo_room);
1727                 b = buf;
1728
1729                 /*  Push data into FIFO, 2 bytes at a time */
1730                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1731
1732                 /*  If there is a byte remaining, write it */
1733                 if (c & 1)
1734                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1735
1736                 retval += c;
1737                 buf += c;
1738                 count -= c;
1739
1740                 spin_lock_irqsave(&info->slock, flags);
1741                 info->xmit_fifo_room -= c;
1742                 spin_unlock_irqrestore(&info->slock, flags);
1743         }
1744
1745         /* If count is zero, we wrote it all and are done */
1746         if (!count)
1747                 goto end;
1748
1749         /*  Write remaining data into the port's xmit_buf */
1750         while (1) {
1751                 if (info->tty == 0)     /*   Seemingly obligatory check... */
1752                         goto end;
1753
1754                 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1755                 if (c <= 0)
1756                         break;
1757
1758                 b = buf;
1759                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1760
1761                 spin_lock_irqsave(&info->slock, flags);
1762                 info->xmit_head =
1763                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1764                 info->xmit_cnt += c;
1765                 spin_unlock_irqrestore(&info->slock, flags);
1766
1767                 buf += c;
1768                 count -= c;
1769                 retval += c;
1770         }
1771
1772         if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1773                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1774
1775 end:
1776         if (info->xmit_cnt < WAKEUP_CHARS) {
1777                 tty_wakeup(tty);
1778 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1779                 wake_up_interruptible(&tty->poll_wait);
1780 #endif
1781         }
1782         mutex_unlock(&info->write_mtx);
1783         return retval;
1784 }
1785
1786 /*
1787  * Return the number of characters that can be sent.  We estimate
1788  * only using the in-memory transmit buffer only, and ignore the
1789  * potential space in the transmit FIFO.
1790  */
1791 static int rp_write_room(struct tty_struct *tty)
1792 {
1793         struct r_port *info = (struct r_port *) tty->driver_data;
1794         int ret;
1795
1796         if (rocket_paranoia_check(info, "rp_write_room"))
1797                 return 0;
1798
1799         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1800         if (ret < 0)
1801                 ret = 0;
1802 #ifdef ROCKET_DEBUG_WRITE
1803         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1804 #endif
1805         return ret;
1806 }
1807
1808 /*
1809  * Return the number of characters in the buffer.  Again, this only
1810  * counts those characters in the in-memory transmit buffer.
1811  */
1812 static int rp_chars_in_buffer(struct tty_struct *tty)
1813 {
1814         struct r_port *info = (struct r_port *) tty->driver_data;
1815         CHANNEL_t *cp;
1816
1817         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1818                 return 0;
1819
1820         cp = &info->channel;
1821
1822 #ifdef ROCKET_DEBUG_WRITE
1823         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1824 #endif
1825         return info->xmit_cnt;
1826 }
1827
1828 /*
1829  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1830  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1831  *  do not call this function if the spinlock is already held.
1832  */
1833 static void rp_flush_buffer(struct tty_struct *tty)
1834 {
1835         struct r_port *info = (struct r_port *) tty->driver_data;
1836         CHANNEL_t *cp;
1837         unsigned long flags;
1838
1839         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1840                 return;
1841
1842         spin_lock_irqsave(&info->slock, flags);
1843         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1844         spin_unlock_irqrestore(&info->slock, flags);
1845
1846 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1847         wake_up_interruptible(&tty->poll_wait);
1848 #endif
1849         tty_wakeup(tty);
1850
1851         cp = &info->channel;
1852         sFlushTxFIFO(cp);
1853 }
1854
1855 #ifdef CONFIG_PCI
1856
1857 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1858         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1859         { }
1860 };
1861 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1862
1863 /*
1864  *  Called when a PCI card is found.  Retrieves and stores model information,
1865  *  init's aiopic and serial port hardware.
1866  *  Inputs:  i is the board number (0-n)
1867  */
1868 static __init int register_PCI(int i, struct pci_dev *dev)
1869 {
1870         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1871         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1872         char *str, *board_type;
1873         CONTROLLER_t *ctlp;
1874
1875         int fast_clock = 0;
1876         int altChanRingIndicator = 0;
1877         int ports_per_aiop = 8;
1878         WordIO_t ConfigIO = 0;
1879         ByteIO_t UPCIRingInd = 0;
1880
1881         if (!dev || pci_enable_device(dev))
1882                 return 0;
1883
1884         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1885
1886         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1887         rocketModel[i].loadrm2 = 0;
1888         rocketModel[i].startingPortNumber = nextLineNumber;
1889
1890         /*  Depending on the model, set up some config variables */
1891         switch (dev->device) {
1892         case PCI_DEVICE_ID_RP4QUAD:
1893                 str = "Quadcable";
1894                 max_num_aiops = 1;
1895                 ports_per_aiop = 4;
1896                 rocketModel[i].model = MODEL_RP4QUAD;
1897                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1898                 rocketModel[i].numPorts = 4;
1899                 break;
1900         case PCI_DEVICE_ID_RP8OCTA:
1901                 str = "Octacable";
1902                 max_num_aiops = 1;
1903                 rocketModel[i].model = MODEL_RP8OCTA;
1904                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1905                 rocketModel[i].numPorts = 8;
1906                 break;
1907         case PCI_DEVICE_ID_URP8OCTA:
1908                 str = "Octacable";
1909                 max_num_aiops = 1;
1910                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1911                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1912                 rocketModel[i].numPorts = 8;
1913                 break;
1914         case PCI_DEVICE_ID_RP8INTF:
1915                 str = "8";
1916                 max_num_aiops = 1;
1917                 rocketModel[i].model = MODEL_RP8INTF;
1918                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1919                 rocketModel[i].numPorts = 8;
1920                 break;
1921         case PCI_DEVICE_ID_URP8INTF:
1922                 str = "8";
1923                 max_num_aiops = 1;
1924                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1925                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1926                 rocketModel[i].numPorts = 8;
1927                 break;
1928         case PCI_DEVICE_ID_RP8J:
1929                 str = "8J";
1930                 max_num_aiops = 1;
1931                 rocketModel[i].model = MODEL_RP8J;
1932                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1933                 rocketModel[i].numPorts = 8;
1934                 break;
1935         case PCI_DEVICE_ID_RP4J:
1936                 str = "4J";
1937                 max_num_aiops = 1;
1938                 ports_per_aiop = 4;
1939                 rocketModel[i].model = MODEL_RP4J;
1940                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1941                 rocketModel[i].numPorts = 4;
1942                 break;
1943         case PCI_DEVICE_ID_RP8SNI:
1944                 str = "8 (DB78 Custom)";
1945                 max_num_aiops = 1;
1946                 rocketModel[i].model = MODEL_RP8SNI;
1947                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1948                 rocketModel[i].numPorts = 8;
1949                 break;
1950         case PCI_DEVICE_ID_RP16SNI:
1951                 str = "16 (DB78 Custom)";
1952                 max_num_aiops = 2;
1953                 rocketModel[i].model = MODEL_RP16SNI;
1954                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1955                 rocketModel[i].numPorts = 16;
1956                 break;
1957         case PCI_DEVICE_ID_RP16INTF:
1958                 str = "16";
1959                 max_num_aiops = 2;
1960                 rocketModel[i].model = MODEL_RP16INTF;
1961                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1962                 rocketModel[i].numPorts = 16;
1963                 break;
1964         case PCI_DEVICE_ID_URP16INTF:
1965                 str = "16";
1966                 max_num_aiops = 2;
1967                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1968                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1969                 rocketModel[i].numPorts = 16;
1970                 break;
1971         case PCI_DEVICE_ID_CRP16INTF:
1972                 str = "16";
1973                 max_num_aiops = 2;
1974                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1975                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1976                 rocketModel[i].numPorts = 16;
1977                 break;
1978         case PCI_DEVICE_ID_RP32INTF:
1979                 str = "32";
1980                 max_num_aiops = 4;
1981                 rocketModel[i].model = MODEL_RP32INTF;
1982                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1983                 rocketModel[i].numPorts = 32;
1984                 break;
1985         case PCI_DEVICE_ID_URP32INTF:
1986                 str = "32";
1987                 max_num_aiops = 4;
1988                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1989                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1990                 rocketModel[i].numPorts = 32;
1991                 break;
1992         case PCI_DEVICE_ID_RPP4:
1993                 str = "Plus Quadcable";
1994                 max_num_aiops = 1;
1995                 ports_per_aiop = 4;
1996                 altChanRingIndicator++;
1997                 fast_clock++;
1998                 rocketModel[i].model = MODEL_RPP4;
1999                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2000                 rocketModel[i].numPorts = 4;
2001                 break;
2002         case PCI_DEVICE_ID_RPP8:
2003                 str = "Plus Octacable";
2004                 max_num_aiops = 2;
2005                 ports_per_aiop = 4;
2006                 altChanRingIndicator++;
2007                 fast_clock++;
2008                 rocketModel[i].model = MODEL_RPP8;
2009                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2010                 rocketModel[i].numPorts = 8;
2011                 break;
2012         case PCI_DEVICE_ID_RP2_232:
2013                 str = "Plus 2 (RS-232)";
2014                 max_num_aiops = 1;
2015                 ports_per_aiop = 2;
2016                 altChanRingIndicator++;
2017                 fast_clock++;
2018                 rocketModel[i].model = MODEL_RP2_232;
2019                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2020                 rocketModel[i].numPorts = 2;
2021                 break;
2022         case PCI_DEVICE_ID_RP2_422:
2023                 str = "Plus 2 (RS-422)";
2024                 max_num_aiops = 1;
2025                 ports_per_aiop = 2;
2026                 altChanRingIndicator++;
2027                 fast_clock++;
2028                 rocketModel[i].model = MODEL_RP2_422;
2029                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2030                 rocketModel[i].numPorts = 2;
2031                 break;
2032         case PCI_DEVICE_ID_RP6M:
2033
2034                 max_num_aiops = 1;
2035                 ports_per_aiop = 6;
2036                 str = "6-port";
2037
2038                 /*  If revision is 1, the rocketmodem flash must be loaded.
2039                  *  If it is 2 it is a "socketed" version. */
2040                 if (dev->revision == 1) {
2041                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2042                         rocketModel[i].loadrm2 = 1;
2043                 } else {
2044                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2045                 }
2046
2047                 rocketModel[i].model = MODEL_RP6M;
2048                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2049                 rocketModel[i].numPorts = 6;
2050                 break;
2051         case PCI_DEVICE_ID_RP4M:
2052                 max_num_aiops = 1;
2053                 ports_per_aiop = 4;
2054                 str = "4-port";
2055                 if (dev->revision == 1) {
2056                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2057                         rocketModel[i].loadrm2 = 1;
2058                 } else {
2059                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
2060                 }
2061
2062                 rocketModel[i].model = MODEL_RP4M;
2063                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2064                 rocketModel[i].numPorts = 4;
2065                 break;
2066         default:
2067                 str = "(unknown/unsupported)";
2068                 max_num_aiops = 0;
2069                 break;
2070         }
2071
2072         /*
2073          * Check for UPCI boards.
2074          */
2075
2076         switch (dev->device) {
2077         case PCI_DEVICE_ID_URP32INTF:
2078         case PCI_DEVICE_ID_URP8INTF:
2079         case PCI_DEVICE_ID_URP16INTF:
2080         case PCI_DEVICE_ID_CRP16INTF:
2081         case PCI_DEVICE_ID_URP8OCTA:
2082                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2083                 ConfigIO = pci_resource_start(dev, 1);
2084                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2085                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2086
2087                         /*
2088                          * Check for octa or quad cable.
2089                          */
2090                         if (!
2091                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2092                              PCI_GPIO_CTRL_8PORT)) {
2093                                 str = "Quadcable";
2094                                 ports_per_aiop = 4;
2095                                 rocketModel[i].numPorts = 4;
2096                         }
2097                 }
2098                 break;
2099         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2100                 str = "8 ports";
2101                 max_num_aiops = 1;
2102                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2103                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2104                 rocketModel[i].numPorts = 8;
2105                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2106                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2107                 ConfigIO = pci_resource_start(dev, 1);
2108                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2109                 break;
2110         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2111                 str = "4 ports";
2112                 max_num_aiops = 1;
2113                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2114                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2115                 rocketModel[i].numPorts = 4;
2116                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2117                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2118                 ConfigIO = pci_resource_start(dev, 1);
2119                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2120                 break;
2121         default:
2122                 break;
2123         }
2124
2125         switch (rcktpt_type[i]) {
2126         case ROCKET_TYPE_MODEM:
2127                 board_type = "RocketModem";
2128                 break;
2129         case ROCKET_TYPE_MODEMII:
2130                 board_type = "RocketModem II";
2131                 break;
2132         case ROCKET_TYPE_MODEMIII:
2133                 board_type = "RocketModem III";
2134                 break;
2135         default:
2136                 board_type = "RocketPort";
2137                 break;
2138         }
2139
2140         if (fast_clock) {
2141                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2142                 rp_baud_base[i] = 921600;
2143         } else {
2144                 /*
2145                  * If support_low_speed is set, use the slow clock
2146                  * prescale, which supports 50 bps
2147                  */
2148                 if (support_low_speed) {
2149                         /* mod 9 (divide by 10) prescale */
2150                         sClockPrescale = 0x19;
2151                         rp_baud_base[i] = 230400;
2152                 } else {
2153                         /* mod 4 (devide by 5) prescale */
2154                         sClockPrescale = 0x14;
2155                         rp_baud_base[i] = 460800;
2156                 }
2157         }
2158
2159         for (aiop = 0; aiop < max_num_aiops; aiop++)
2160                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2161         ctlp = sCtlNumToCtlPtr(i);
2162         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2163         for (aiop = 0; aiop < max_num_aiops; aiop++)
2164                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2165
2166         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2167                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2168                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2169                 rocketModel[i].startingPortNumber,
2170                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2171
2172         if (num_aiops <= 0) {
2173                 rcktpt_io_addr[i] = 0;
2174                 return (0);
2175         }
2176         is_PCI[i] = 1;
2177
2178         /*  Reset the AIOPIC, init the serial ports */
2179         for (aiop = 0; aiop < num_aiops; aiop++) {
2180                 sResetAiopByNum(ctlp, aiop);
2181                 num_chan = ports_per_aiop;
2182                 for (chan = 0; chan < num_chan; chan++)
2183                         init_r_port(i, aiop, chan, dev);
2184         }
2185
2186         /*  Rocket modems must be reset */
2187         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2188             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2189             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2190                 num_chan = ports_per_aiop;
2191                 for (chan = 0; chan < num_chan; chan++)
2192                         sPCIModemReset(ctlp, chan, 1);
2193                 msleep(500);
2194                 for (chan = 0; chan < num_chan; chan++)
2195                         sPCIModemReset(ctlp, chan, 0);
2196                 msleep(500);
2197                 rmSpeakerReset(ctlp, rocketModel[i].model);
2198         }
2199         return (1);
2200 }
2201
2202 /*
2203  *  Probes for PCI cards, inits them if found
2204  *  Input:   board_found = number of ISA boards already found, or the
2205  *           starting board number
2206  *  Returns: Number of PCI boards found
2207  */
2208 static int __init init_PCI(int boards_found)
2209 {
2210         struct pci_dev *dev = NULL;
2211         int count = 0;
2212
2213         /*  Work through the PCI device list, pulling out ours */
2214         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2215                 if (register_PCI(count + boards_found, dev))
2216                         count++;
2217         }
2218         return (count);
2219 }
2220
2221 #endif                          /* CONFIG_PCI */
2222
2223 /*
2224  *  Probes for ISA cards
2225  *  Input:   i = the board number to look for
2226  *  Returns: 1 if board found, 0 else
2227  */
2228 static int __init init_ISA(int i)
2229 {
2230         int num_aiops, num_chan = 0, total_num_chan = 0;
2231         int aiop, chan;
2232         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2233         CONTROLLER_t *ctlp;
2234         char *type_string;
2235
2236         /*  If io_addr is zero, no board configured */
2237         if (rcktpt_io_addr[i] == 0)
2238                 return (0);
2239
2240         /*  Reserve the IO region */
2241         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2242                 printk(KERN_ERR "Unable to reserve IO region for configured "
2243                                 "ISA RocketPort at address 0x%lx, board not "
2244                                 "installed...\n", rcktpt_io_addr[i]);
2245                 rcktpt_io_addr[i] = 0;
2246                 return (0);
2247         }
2248
2249         ctlp = sCtlNumToCtlPtr(i);
2250
2251         ctlp->boardType = rcktpt_type[i];
2252
2253         switch (rcktpt_type[i]) {
2254         case ROCKET_TYPE_PC104:
2255                 type_string = "(PC104)";
2256                 break;
2257         case ROCKET_TYPE_MODEM:
2258                 type_string = "(RocketModem)";
2259                 break;
2260         case ROCKET_TYPE_MODEMII:
2261                 type_string = "(RocketModem II)";
2262                 break;
2263         default:
2264                 type_string = "";
2265                 break;
2266         }
2267
2268         /*
2269          * If support_low_speed is set, use the slow clock prescale,
2270          * which supports 50 bps
2271          */
2272         if (support_low_speed) {
2273                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2274                 rp_baud_base[i] = 230400;
2275         } else {
2276                 sClockPrescale = 0x14;  /* mod 4 (devide by 5) prescale */
2277                 rp_baud_base[i] = 460800;
2278         }
2279
2280         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2281                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2282
2283         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2284
2285         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2286                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2287                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2288         }
2289
2290         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2291         if (num_aiops <= 0) {
2292                 release_region(rcktpt_io_addr[i], 64);
2293                 rcktpt_io_addr[i] = 0;
2294                 return (0);
2295         }
2296
2297         rocketModel[i].startingPortNumber = nextLineNumber;
2298
2299         for (aiop = 0; aiop < num_aiops; aiop++) {
2300                 sResetAiopByNum(ctlp, aiop);
2301                 sEnAiop(ctlp, aiop);
2302                 num_chan = sGetAiopNumChan(ctlp, aiop);
2303                 total_num_chan += num_chan;
2304                 for (chan = 0; chan < num_chan; chan++)
2305                         init_r_port(i, aiop, chan, NULL);
2306         }
2307         is_PCI[i] = 0;
2308         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2309                 num_chan = sGetAiopNumChan(ctlp, 0);
2310                 total_num_chan = num_chan;
2311                 for (chan = 0; chan < num_chan; chan++)
2312                         sModemReset(ctlp, chan, 1);
2313                 msleep(500);
2314                 for (chan = 0; chan < num_chan; chan++)
2315                         sModemReset(ctlp, chan, 0);
2316                 msleep(500);
2317                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2318         } else {
2319                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2320         }
2321         rocketModel[i].numPorts = total_num_chan;
2322         rocketModel[i].model = MODEL_ISA;
2323
2324         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2325                i, rcktpt_io_addr[i], num_aiops, type_string);
2326
2327         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2328                rocketModel[i].modelString,
2329                rocketModel[i].startingPortNumber,
2330                rocketModel[i].startingPortNumber +
2331                rocketModel[i].numPorts - 1);
2332
2333         return (1);
2334 }
2335
2336 static const struct tty_operations rocket_ops = {
2337         .open = rp_open,
2338         .close = rp_close,
2339         .write = rp_write,
2340         .put_char = rp_put_char,
2341         .write_room = rp_write_room,
2342         .chars_in_buffer = rp_chars_in_buffer,
2343         .flush_buffer = rp_flush_buffer,
2344         .ioctl = rp_ioctl,
2345         .throttle = rp_throttle,
2346         .unthrottle = rp_unthrottle,
2347         .set_termios = rp_set_termios,
2348         .stop = rp_stop,
2349         .start = rp_start,
2350         .hangup = rp_hangup,
2351         .break_ctl = rp_break,
2352         .send_xchar = rp_send_xchar,
2353         .wait_until_sent = rp_wait_until_sent,
2354         .tiocmget = rp_tiocmget,
2355         .tiocmset = rp_tiocmset,
2356 };
2357
2358 /*
2359  * The module "startup" routine; it's run when the module is loaded.
2360  */
2361 static int __init rp_init(void)
2362 {
2363         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2364
2365         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2366                ROCKET_VERSION, ROCKET_DATE);
2367
2368         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2369         if (!rocket_driver)
2370                 goto err;
2371
2372         /*
2373          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is
2374          *  zero, use the default controller IO address of board1 + 0x40.
2375          */
2376         if (board1) {
2377                 if (controller == 0)
2378                         controller = board1 + 0x40;
2379         } else {
2380                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2381         }
2382
2383         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2384         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2385                 printk(KERN_ERR "Unable to reserve IO region for first "
2386                         "configured ISA RocketPort controller 0x%lx.  "
2387                         "Driver exiting\n", controller);
2388                 ret = -EBUSY;
2389                 goto err_tty;
2390         }
2391
2392         /*  Store ISA variable retrieved from command line or .conf file. */
2393         rcktpt_io_addr[0] = board1;
2394         rcktpt_io_addr[1] = board2;
2395         rcktpt_io_addr[2] = board3;
2396         rcktpt_io_addr[3] = board4;
2397
2398         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2399         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2400         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2401         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2402         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2403         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2404         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2405         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2406
2407         /*
2408          * Set up the tty driver structure and then register this
2409          * driver with the tty layer.
2410          */
2411
2412         rocket_driver->owner = THIS_MODULE;
2413         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2414         rocket_driver->name = "ttyR";
2415         rocket_driver->driver_name = "Comtrol RocketPort";
2416         rocket_driver->major = TTY_ROCKET_MAJOR;
2417         rocket_driver->minor_start = 0;
2418         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2419         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2420         rocket_driver->init_termios = tty_std_termios;
2421         rocket_driver->init_termios.c_cflag =
2422             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2423         rocket_driver->init_termios.c_ispeed = 9600;
2424         rocket_driver->init_termios.c_ospeed = 9600;
2425 #ifdef ROCKET_SOFT_FLOW
2426         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2427 #endif
2428         tty_set_operations(rocket_driver, &rocket_ops);
2429
2430         ret = tty_register_driver(rocket_driver);
2431         if (ret < 0) {
2432                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2433                 goto err_tty;
2434         }
2435
2436 #ifdef ROCKET_DEBUG_OPEN
2437         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2438 #endif
2439
2440         /*
2441          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2442          *  will be initialized here.
2443          */
2444         isa_boards_found = 0;
2445         pci_boards_found = 0;
2446
2447         for (i = 0; i < NUM_BOARDS; i++) {
2448                 if (init_ISA(i))
2449                         isa_boards_found++;
2450         }
2451
2452 #ifdef CONFIG_PCI
2453         if (isa_boards_found < NUM_BOARDS)
2454                 pci_boards_found = init_PCI(isa_boards_found);
2455 #endif
2456
2457         max_board = pci_boards_found + isa_boards_found;
2458
2459         if (max_board == 0) {
2460                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2461                 ret = -ENXIO;
2462                 goto err_ttyu;
2463         }
2464
2465         return 0;
2466 err_ttyu:
2467         tty_unregister_driver(rocket_driver);
2468 err_tty:
2469         put_tty_driver(rocket_driver);
2470 err:
2471         return ret;
2472 }
2473
2474
2475 static void rp_cleanup_module(void)
2476 {
2477         int retval;
2478         int i;
2479
2480         del_timer_sync(&rocket_timer);
2481
2482         retval = tty_unregister_driver(rocket_driver);
2483         if (retval)
2484                 printk(KERN_ERR "Error %d while trying to unregister "
2485                        "rocketport driver\n", -retval);
2486
2487         for (i = 0; i < MAX_RP_PORTS; i++)
2488                 if (rp_table[i]) {
2489                         tty_unregister_device(rocket_driver, i);
2490                         kfree(rp_table[i]);
2491                 }
2492
2493         put_tty_driver(rocket_driver);
2494
2495         for (i = 0; i < NUM_BOARDS; i++) {
2496                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2497                         continue;
2498                 release_region(rcktpt_io_addr[i], 64);
2499         }
2500         if (controller)
2501                 release_region(controller, 4);
2502 }
2503
2504 /***************************************************************************
2505 Function: sInitController
2506 Purpose:  Initialization of controller global registers and controller
2507           structure.
2508 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2509                           IRQNum,Frequency,PeriodicOnly)
2510           CONTROLLER_T *CtlP; Ptr to controller structure
2511           int CtlNum; Controller number
2512           ByteIO_t MudbacIO; Mudbac base I/O address.
2513           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2514              This list must be in the order the AIOPs will be found on the
2515              controller.  Once an AIOP in the list is not found, it is
2516              assumed that there are no more AIOPs on the controller.
2517           int AiopIOListSize; Number of addresses in AiopIOList
2518           int IRQNum; Interrupt Request number.  Can be any of the following:
2519                          0: Disable global interrupts
2520                          3: IRQ 3
2521                          4: IRQ 4
2522                          5: IRQ 5
2523                          9: IRQ 9
2524                          10: IRQ 10
2525                          11: IRQ 11
2526                          12: IRQ 12
2527                          15: IRQ 15
2528           Byte_t Frequency: A flag identifying the frequency
2529                    of the periodic interrupt, can be any one of the following:
2530                       FREQ_DIS - periodic interrupt disabled
2531                       FREQ_137HZ - 137 Hertz
2532                       FREQ_69HZ - 69 Hertz
2533                       FREQ_34HZ - 34 Hertz
2534                       FREQ_17HZ - 17 Hertz
2535                       FREQ_9HZ - 9 Hertz
2536                       FREQ_4HZ - 4 Hertz
2537                    If IRQNum is set to 0 the Frequency parameter is
2538                    overidden, it is forced to a value of FREQ_DIS.
2539           int PeriodicOnly: 1 if all interrupts except the periodic
2540                                interrupt are to be blocked.
2541                             0 is both the periodic interrupt and
2542                                other channel interrupts are allowed.
2543                             If IRQNum is set to 0 the PeriodicOnly parameter is
2544                                overidden, it is forced to a value of 0.
2545 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2546                initialization failed.
2547
2548 Comments:
2549           If periodic interrupts are to be disabled but AIOP interrupts
2550           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2551
2552           If interrupts are to be completely disabled set IRQNum to 0.
2553
2554           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2555           invalid combination.
2556
2557           This function performs initialization of global interrupt modes,
2558           but it does not actually enable global interrupts.  To enable
2559           and disable global interrupts use functions sEnGlobalInt() and
2560           sDisGlobalInt().  Enabling of global interrupts is normally not
2561           done until all other initializations are complete.
2562
2563           Even if interrupts are globally enabled, they must also be
2564           individually enabled for each channel that is to generate
2565           interrupts.
2566
2567 Warnings: No range checking on any of the parameters is done.
2568
2569           No context switches are allowed while executing this function.
2570
2571           After this function all AIOPs on the controller are disabled,
2572           they can be enabled with sEnAiop().
2573 */
2574 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2575                            ByteIO_t * AiopIOList, int AiopIOListSize,
2576                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2577 {
2578         int i;
2579         ByteIO_t io;
2580         int done;
2581
2582         CtlP->AiopIntrBits = aiop_intr_bits;
2583         CtlP->AltChanRingIndicator = 0;
2584         CtlP->CtlNum = CtlNum;
2585         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2586         CtlP->BusType = isISA;
2587         CtlP->MBaseIO = MudbacIO;
2588         CtlP->MReg1IO = MudbacIO + 1;
2589         CtlP->MReg2IO = MudbacIO + 2;
2590         CtlP->MReg3IO = MudbacIO + 3;
2591 #if 1
2592         CtlP->MReg2 = 0;        /* interrupt disable */
2593         CtlP->MReg3 = 0;        /* no periodic interrupts */
2594 #else
2595         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2596                 CtlP->MReg2 = 0;        /* interrupt disable */
2597                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2598         } else {
2599                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2600                 CtlP->MReg3 = Frequency;        /* set frequency */
2601                 if (PeriodicOnly) {     /* periodic interrupt only */
2602                         CtlP->MReg3 |= PERIODIC_ONLY;
2603                 }
2604         }
2605 #endif
2606         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2607         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2608         sControllerEOI(CtlP);   /* clear EOI if warm init */
2609         /* Init AIOPs */
2610         CtlP->NumAiop = 0;
2611         for (i = done = 0; i < AiopIOListSize; i++) {
2612                 io = AiopIOList[i];
2613                 CtlP->AiopIO[i] = (WordIO_t) io;
2614                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2615                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2616                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2617                 if (done)
2618                         continue;
2619                 sEnAiop(CtlP, i);       /* enable the AIOP */
2620                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2621                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2622                         done = 1;       /* done looking for AIOPs */
2623                 else {
2624                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2625                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2626                         sOutB(io + _INDX_DATA, sClockPrescale);
2627                         CtlP->NumAiop++;        /* bump count of AIOPs */
2628                 }
2629                 sDisAiop(CtlP, i);      /* disable AIOP */
2630         }
2631
2632         if (CtlP->NumAiop == 0)
2633                 return (-1);
2634         else
2635                 return (CtlP->NumAiop);
2636 }
2637
2638 /***************************************************************************
2639 Function: sPCIInitController
2640 Purpose:  Initialization of controller global registers and controller
2641           structure.
2642 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2643                           IRQNum,Frequency,PeriodicOnly)
2644           CONTROLLER_T *CtlP; Ptr to controller structure
2645           int CtlNum; Controller number
2646           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2647              This list must be in the order the AIOPs will be found on the
2648              controller.  Once an AIOP in the list is not found, it is
2649              assumed that there are no more AIOPs on the controller.
2650           int AiopIOListSize; Number of addresses in AiopIOList
2651           int IRQNum; Interrupt Request number.  Can be any of the following:
2652                          0: Disable global interrupts
2653                          3: IRQ 3
2654                          4: IRQ 4
2655                          5: IRQ 5
2656                          9: IRQ 9
2657                          10: IRQ 10
2658                          11: IRQ 11
2659                          12: IRQ 12
2660                          15: IRQ 15
2661           Byte_t Frequency: A flag identifying the frequency
2662                    of the periodic interrupt, can be any one of the following:
2663                       FREQ_DIS - periodic interrupt disabled
2664                       FREQ_137HZ - 137 Hertz
2665                       FREQ_69HZ - 69 Hertz
2666                       FREQ_34HZ - 34 Hertz
2667                       FREQ_17HZ - 17 Hertz
2668                       FREQ_9HZ - 9 Hertz
2669                       FREQ_4HZ - 4 Hertz
2670                    If IRQNum is set to 0 the Frequency parameter is
2671                    overidden, it is forced to a value of FREQ_DIS.
2672           int PeriodicOnly: 1 if all interrupts except the periodic
2673                                interrupt are to be blocked.
2674                             0 is both the periodic interrupt and
2675                                other channel interrupts are allowed.
2676                             If IRQNum is set to 0 the PeriodicOnly parameter is
2677                                overidden, it is forced to a value of 0.
2678 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2679                initialization failed.
2680
2681 Comments:
2682           If periodic interrupts are to be disabled but AIOP interrupts
2683           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2684
2685           If interrupts are to be completely disabled set IRQNum to 0.
2686
2687           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2688           invalid combination.
2689
2690           This function performs initialization of global interrupt modes,
2691           but it does not actually enable global interrupts.  To enable
2692           and disable global interrupts use functions sEnGlobalInt() and
2693           sDisGlobalInt().  Enabling of global interrupts is normally not
2694           done until all other initializations are complete.
2695
2696           Even if interrupts are globally enabled, they must also be
2697           individually enabled for each channel that is to generate
2698           interrupts.
2699
2700 Warnings: No range checking on any of the parameters is done.
2701
2702           No context switches are allowed while executing this function.
2703
2704           After this function all AIOPs on the controller are disabled,
2705           they can be enabled with sEnAiop().
2706 */
2707 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2708                               ByteIO_t * AiopIOList, int AiopIOListSize,
2709                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2710                               int PeriodicOnly, int altChanRingIndicator,
2711                               int UPCIRingInd)
2712 {
2713         int i;
2714         ByteIO_t io;
2715
2716         CtlP->AltChanRingIndicator = altChanRingIndicator;
2717         CtlP->UPCIRingInd = UPCIRingInd;
2718         CtlP->CtlNum = CtlNum;
2719         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2720         CtlP->BusType = isPCI;  /* controller release 1 */
2721
2722         if (ConfigIO) {
2723                 CtlP->isUPCI = 1;
2724                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2725                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2726                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2727         } else {
2728                 CtlP->isUPCI = 0;
2729                 CtlP->PCIIO =
2730                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2731                 CtlP->AiopIntrBits = aiop_intr_bits;
2732         }
2733
2734         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
2735         /* Init AIOPs */
2736         CtlP->NumAiop = 0;
2737         for (i = 0; i < AiopIOListSize; i++) {
2738                 io = AiopIOList[i];
2739                 CtlP->AiopIO[i] = (WordIO_t) io;
2740                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2741
2742                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2743                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2744                         break;  /* done looking for AIOPs */
2745
2746                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2747                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2748                 sOutB(io + _INDX_DATA, sClockPrescale);
2749                 CtlP->NumAiop++;        /* bump count of AIOPs */
2750         }
2751
2752         if (CtlP->NumAiop == 0)
2753                 return (-1);
2754         else
2755                 return (CtlP->NumAiop);
2756 }
2757
2758 /***************************************************************************
2759 Function: sReadAiopID
2760 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2761 Call:     sReadAiopID(io)
2762           ByteIO_t io: AIOP base I/O address
2763 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2764                  is replace by an identifying number.
2765           Flag AIOPID_NULL if no valid AIOP is found
2766 Warnings: No context switches are allowed while executing this function.
2767
2768 */
2769 static int sReadAiopID(ByteIO_t io)
2770 {
2771         Byte_t AiopID;          /* ID byte from AIOP */
2772
2773         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2774         sOutB(io + _CMD_REG, 0x0);
2775         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2776         if (AiopID == 0x06)
2777                 return (1);
2778         else                    /* AIOP does not exist */
2779                 return (-1);
2780 }
2781
2782 /***************************************************************************
2783 Function: sReadAiopNumChan
2784 Purpose:  Read the number of channels available in an AIOP directly from
2785           an AIOP.
2786 Call:     sReadAiopNumChan(io)
2787           WordIO_t io: AIOP base I/O address
2788 Return:   int: The number of channels available
2789 Comments: The number of channels is determined by write/reads from identical
2790           offsets within the SRAM address spaces for channels 0 and 4.
2791           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2792           AIOP, otherwise it is an 8 channel.
2793 Warnings: No context switches are allowed while executing this function.
2794 */
2795 static int sReadAiopNumChan(WordIO_t io)
2796 {
2797         Word_t x;
2798         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2799
2800         /* write to chan 0 SRAM */
2801         sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2802         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2803         x = sInW(io + _INDX_DATA);
2804         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2805         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2806                 return (8);
2807         else
2808                 return (4);
2809 }
2810
2811 /***************************************************************************
2812 Function: sInitChan
2813 Purpose:  Initialization of a channel and channel structure
2814 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2815           CONTROLLER_T *CtlP; Ptr to controller structure
2816           CHANNEL_T *ChP; Ptr to channel structure
2817           int AiopNum; AIOP number within controller
2818           int ChanNum; Channel number within AIOP
2819 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2820                number exceeds number of channels available in AIOP.
2821 Comments: This function must be called before a channel can be used.
2822 Warnings: No range checking on any of the parameters is done.
2823
2824           No context switches are allowed while executing this function.
2825 */
2826 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2827                      int ChanNum)
2828 {
2829         int i;
2830         WordIO_t AiopIO;
2831         WordIO_t ChIOOff;
2832         Byte_t *ChR;
2833         Word_t ChOff;
2834         static Byte_t R[4];
2835         int brd9600;
2836
2837         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2838                 return 0;       /* exceeds num chans in AIOP */
2839
2840         /* Channel, AIOP, and controller identifiers */
2841         ChP->CtlP = CtlP;
2842         ChP->ChanID = CtlP->AiopID[AiopNum];
2843         ChP->AiopNum = AiopNum;
2844         ChP->ChanNum = ChanNum;
2845
2846         /* Global direct addresses */
2847         AiopIO = CtlP->AiopIO[AiopNum];
2848         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2849         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2850         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2851         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2852         ChP->IndexData = AiopIO + _INDX_DATA;
2853
2854         /* Channel direct addresses */
2855         ChIOOff = AiopIO + ChP->ChanNum * 2;
2856         ChP->TxRxData = ChIOOff + _TD0;
2857         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2858         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2859         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2860
2861         /* Initialize the channel from the RData array */
2862         for (i = 0; i < RDATASIZE; i += 4) {
2863                 R[0] = RData[i];
2864                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2865                 R[2] = RData[i + 2];
2866                 R[3] = RData[i + 3];
2867                 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2868         }
2869
2870         ChR = ChP->R;
2871         for (i = 0; i < RREGDATASIZE; i += 4) {
2872                 ChR[i] = RRegData[i];
2873                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2874                 ChR[i + 2] = RRegData[i + 2];
2875                 ChR[i + 3] = RRegData[i + 3];
2876         }
2877
2878         /* Indexed registers */
2879         ChOff = (Word_t) ChanNum *0x1000;
2880
2881         if (sClockPrescale == 0x14)
2882                 brd9600 = 47;
2883         else
2884                 brd9600 = 23;
2885
2886         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2887         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2888         ChP->BaudDiv[2] = (Byte_t) brd9600;
2889         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2890         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2891
2892         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2893         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2894         ChP->TxControl[2] = 0;
2895         ChP->TxControl[3] = 0;
2896         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2897
2898         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2899         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2900         ChP->RxControl[2] = 0;
2901         ChP->RxControl[3] = 0;
2902         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2903
2904         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2905         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2906         ChP->TxEnables[2] = 0;
2907         ChP->TxEnables[3] = 0;
2908         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2909
2910         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2911         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2912         ChP->TxCompare[2] = 0;
2913         ChP->TxCompare[3] = 0;
2914         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2915
2916         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2917         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2918         ChP->TxReplace1[2] = 0;
2919         ChP->TxReplace1[3] = 0;
2920         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2921
2922         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2923         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2924         ChP->TxReplace2[2] = 0;
2925         ChP->TxReplace2[3] = 0;
2926         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2927
2928         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2929         ChP->TxFIFO = ChOff + _TX_FIFO;
2930
2931         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2932         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2933         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2934         sOutW(ChP->IndexData, 0);
2935         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2936         ChP->RxFIFO = ChOff + _RX_FIFO;
2937
2938         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2939         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2940         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2941         sOutW(ChP->IndexData, 0);
2942         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2943         sOutW(ChP->IndexData, 0);
2944         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2945         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2946         sOutB(ChP->IndexData, 0);
2947         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2948         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2949         sOutB(ChP->IndexData, 0);
2950         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2951         sEnRxProcessor(ChP);    /* start the Rx processor */
2952
2953         return 1;
2954 }
2955
2956 /***************************************************************************
2957 Function: sStopRxProcessor
2958 Purpose:  Stop the receive processor from processing a channel.
2959 Call:     sStopRxProcessor(ChP)
2960           CHANNEL_T *ChP; Ptr to channel structure
2961
2962 Comments: The receive processor can be started again with sStartRxProcessor().
2963           This function causes the receive processor to skip over the
2964           stopped channel.  It does not stop it from processing other channels.
2965
2966 Warnings: No context switches are allowed while executing this function.
2967
2968           Do not leave the receive processor stopped for more than one
2969           character time.
2970
2971           After calling this function a delay of 4 uS is required to ensure
2972           that the receive processor is no longer processing this channel.
2973 */
2974 static void sStopRxProcessor(CHANNEL_T * ChP)
2975 {
2976         Byte_t R[4];
2977
2978         R[0] = ChP->R[0];
2979         R[1] = ChP->R[1];
2980         R[2] = 0x0a;
2981         R[3] = ChP->R[3];
2982         sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
2983 }
2984
2985 /***************************************************************************
2986 Function: sFlushRxFIFO
2987 Purpose:  Flush the Rx FIFO
2988 Call:     sFlushRxFIFO(ChP)
2989           CHANNEL_T *ChP; Ptr to channel structure
2990 Return:   void
2991 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2992           while it is being flushed the receive processor is stopped
2993           and the transmitter is disabled.  After these operations a
2994           4 uS delay is done before clearing the pointers to allow
2995           the receive processor to stop.  These items are handled inside
2996           this function.
2997 Warnings: No context switches are allowed while executing this function.
2998 */
2999 static void sFlushRxFIFO(CHANNEL_T * ChP)
3000 {
3001         int i;
3002         Byte_t Ch;              /* channel number within AIOP */
3003         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
3004
3005         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
3006                 return;         /* don't need to flush */
3007
3008         RxFIFOEnabled = 0;
3009         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
3010                 RxFIFOEnabled = 1;
3011                 sDisRxFIFO(ChP);        /* disable it */
3012                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
3013                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
3014         }
3015         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
3016         Ch = (Byte_t) sGetChanNum(ChP);
3017         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
3018         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
3019         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
3020         sOutW(ChP->IndexData, 0);
3021         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
3022         sOutW(ChP->IndexData, 0);
3023         if (RxFIFOEnabled)
3024                 sEnRxFIFO(ChP); /* enable Rx FIFO */
3025 }
3026
3027 /***************************************************************************
3028 Function: sFlushTxFIFO
3029 Purpose:  Flush the Tx FIFO
3030 Call:     sFlushTxFIFO(ChP)
3031           CHANNEL_T *ChP; Ptr to channel structure
3032 Return:   void
3033 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3034           while it is being flushed the receive processor is stopped
3035           and the transmitter is disabled.  After these operations a
3036           4 uS delay is done before clearing the pointers to allow
3037           the receive processor to stop.  These items are handled inside
3038           this function.
3039 Warnings: No context switches are allowed while executing this function.
3040 */
3041 static void sFlushTxFIFO(CHANNEL_T * ChP)
3042 {
3043         int i;
3044         Byte_t Ch;              /* channel number within AIOP */
3045         int TxEnabled;          /* 1 if transmitter enabled */
3046
3047         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
3048                 return;         /* don't need to flush */
3049
3050         TxEnabled = 0;
3051         if (ChP->TxControl[3] & TX_ENABLE) {
3052                 TxEnabled = 1;
3053                 sDisTransmit(ChP);      /* disable transmitter */
3054         }
3055         sStopRxProcessor(ChP);  /* stop Rx processor */
3056         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
3057                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
3058         Ch = (Byte_t) sGetChanNum(ChP);
3059         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
3060         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
3061         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
3062         sOutW(ChP->IndexData, 0);
3063         if (TxEnabled)
3064                 sEnTransmit(ChP);       /* enable transmitter */
3065         sStartRxProcessor(ChP); /* restart Rx processor */
3066 }
3067
3068 /***************************************************************************
3069 Function: sWriteTxPrioByte
3070 Purpose:  Write a byte of priority transmit data to a channel
3071 Call:     sWriteTxPrioByte(ChP,Data)
3072           CHANNEL_T *ChP; Ptr to channel structure
3073           Byte_t Data; The transmit data byte
3074
3075 Return:   int: 1 if the bytes is successfully written, otherwise 0.
3076
3077 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3078
3079 Warnings: No context switches are allowed while executing this function.
3080 */
3081 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3082 {
3083         Byte_t DWBuf[4];        /* buffer for double word writes */
3084         Word_t *WordPtr;        /* must be far because Win SS != DS */
3085         register DWordIO_t IndexAddr;
3086
3087         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
3088                 IndexAddr = ChP->IndexAddr;
3089                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
3090                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3091                         return (0);     /* nothing sent */
3092
3093                 WordPtr = (Word_t *) (&DWBuf[0]);
3094                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
3095
3096                 DWBuf[2] = Data;        /* data byte value */
3097                 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0])));  /* write it out */
3098
3099                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
3100
3101                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3102                 DWBuf[3] = 0;   /* priority buffer pointer */
3103                 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0])));  /* write it out */
3104         } else {                /* write it to Tx FIFO */
3105
3106                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3107         }
3108         return (1);             /* 1 byte sent */
3109 }
3110
3111 /***************************************************************************
3112 Function: sEnInterrupts
3113 Purpose:  Enable one or more interrupts for a channel
3114 Call:     sEnInterrupts(ChP,Flags)
3115           CHANNEL_T *ChP; Ptr to channel structure
3116           Word_t Flags: Interrupt enable flags, can be any combination
3117              of the following flags:
3118                 TXINT_EN:   Interrupt on Tx FIFO empty
3119                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3120                             sSetRxTrigger())
3121                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3122                 MCINT_EN:   Interrupt on modem input change
3123                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3124                             Interrupt Channel Register.
3125 Return:   void
3126 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3127           enabled.  If an interrupt enable flag is not set in Flags, that
3128           interrupt will not be changed.  Interrupts can be disabled with
3129           function sDisInterrupts().
3130
3131           This function sets the appropriate bit for the channel in the AIOP's
3132           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3133           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3134
3135           Interrupts must also be globally enabled before channel interrupts
3136           will be passed on to the host.  This is done with function
3137           sEnGlobalInt().
3138
3139           In some cases it may be desirable to disable interrupts globally but
3140           enable channel interrupts.  This would allow the global interrupt
3141           status register to be used to determine which AIOPs need service.
3142 */
3143 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3144 {
3145         Byte_t Mask;            /* Interrupt Mask Register */
3146
3147         ChP->RxControl[2] |=
3148             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3149
3150         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3151
3152         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3153
3154         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3155
3156         if (Flags & CHANINT_EN) {
3157                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3158                 sOutB(ChP->IntMask, Mask);
3159         }
3160 }
3161
3162 /***************************************************************************
3163 Function: sDisInterrupts
3164 Purpose:  Disable one or more interrupts for a channel
3165 Call:     sDisInterrupts(ChP,Flags)
3166           CHANNEL_T *ChP; Ptr to channel structure
3167           Word_t Flags: Interrupt flags, can be any combination
3168              of the following flags:
3169                 TXINT_EN:   Interrupt on Tx FIFO empty
3170                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3171                             sSetRxTrigger())
3172                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3173                 MCINT_EN:   Interrupt on modem input change
3174                 CHANINT_EN: Disable channel interrupt signal to the
3175                             AIOP's Interrupt Channel Register.
3176 Return:   void
3177 Comments: If an interrupt flag is set in Flags, that interrupt will be
3178           disabled.  If an interrupt flag is not set in Flags, that
3179           interrupt will not be changed.  Interrupts can be enabled with
3180           function sEnInterrupts().
3181
3182           This function clears the appropriate bit for the channel in the AIOP's
3183           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3184           this channel's bit from being set in the AIOP's Interrupt Channel
3185           Register.
3186 */
3187 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3188 {
3189         Byte_t Mask;            /* Interrupt Mask Register */
3190
3191         ChP->RxControl[2] &=
3192             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3193         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3194         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3195         sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3196
3197         if (Flags & CHANINT_EN) {
3198                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3199                 sOutB(ChP->IntMask, Mask);
3200         }
3201 }
3202
3203 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3204 {
3205         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3206 }
3207
3208 /*
3209  *  Not an official SSCI function, but how to reset RocketModems.
3210  *  ISA bus version
3211  */
3212 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3213 {
3214         ByteIO_t addr;
3215         Byte_t val;
3216
3217         addr = CtlP->AiopIO[0] + 0x400;
3218         val = sInB(CtlP->MReg3IO);
3219         /* if AIOP[1] is not enabled, enable it */
3220         if ((val & 2) == 0) {
3221                 val = sInB(CtlP->MReg2IO);
3222                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3223                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3224         }
3225
3226         sEnAiop(CtlP, 1);
3227         if (!on)
3228                 addr += 8;
3229         sOutB(addr + chan, 0);  /* apply or remove reset */
3230         sDisAiop(CtlP, 1);
3231 }
3232
3233 /*
3234  *  Not an official SSCI function, but how to reset RocketModems.
3235  *  PCI bus version
3236  */
3237 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3238 {
3239         ByteIO_t addr;
3240
3241         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3242         if (!on)
3243                 addr += 8;
3244         sOutB(addr + chan, 0);  /* apply or remove reset */
3245 }
3246
3247 /*  Resets the speaker controller on RocketModem II and III devices */
3248 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3249 {
3250         ByteIO_t addr;
3251
3252         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3253         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3254                 addr = CtlP->AiopIO[0] + 0x4F;
3255                 sOutB(addr, 0);
3256         }
3257
3258         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3259         if ((model == MODEL_UPCI_RM3_8PORT)
3260             || (model == MODEL_UPCI_RM3_4PORT)) {
3261                 addr = CtlP->AiopIO[0] + 0x88;
3262                 sOutB(addr, 0);
3263         }
3264 }
3265
3266 /*  Returns the line number given the controller (board), aiop and channel number */
3267 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3268 {
3269         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3270 }
3271
3272 /*
3273  *  Stores the line number associated with a given controller (board), aiop
3274  *  and channel number.
3275  *  Returns:  The line number assigned
3276  */
3277 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3278 {
3279         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3280         return (nextLineNumber - 1);
3281 }