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x86: coding style fixes in arch/x86/lib/io_64.c
[wrt350n-kernel.git] / drivers / scsi / aic7xxx / aic7xxx_core.c
blob6d2ae641273c9fe56826043fb623761fe1063bb9
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
41 */
42
43 #ifdef __linux__
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
47 #else
48 #include <dev/aic7xxx/aic7xxx_osm.h>
49 #include <dev/aic7xxx/aic7xxx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
51 #endif
52
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
55 {
56 "NONE",
57 "aic7770",
58 "aic7850",
59 "aic7855",
60 "aic7859",
61 "aic7860",
62 "aic7870",
63 "aic7880",
64 "aic7895",
65 "aic7895C",
66 "aic7890/91",
67 "aic7896/97",
68 "aic7892",
69 "aic7899"
70 };
71 static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names);
72
73 /*
74 * Hardware error codes.
75 */
76 struct ahc_hard_error_entry {
77 uint8_t errno;
78 char *errmesg;
79 };
80
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82 { ILLHADDR, "Illegal Host Access" },
83 { ILLSADDR, "Illegal Sequencer Address referrenced" },
84 { ILLOPCODE, "Illegal Opcode in sequencer program" },
85 { SQPARERR, "Sequencer Parity Error" },
86 { DPARERR, "Data-path Parity Error" },
87 { MPARERR, "Scratch or SCB Memory Parity Error" },
88 { PCIERRSTAT, "PCI Error detected" },
89 { CIOPARERR, "CIOBUS Parity Error" },
90 };
91 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
92
93 static struct ahc_phase_table_entry ahc_phase_table[] =
94 {
95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
99 { P_COMMAND, MSG_NOOP, "in Command phase" },
100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
103 { P_BUSFREE, MSG_NOOP, "while idle" },
104 { 0, MSG_NOOP, "in unknown phase" }
105 };
106
107 /*
108 * In most cases we only wish to itterate over real phases, so
109 * exclude the last element from the count.
110 */
111 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
112
113 /*
114 * Valid SCSIRATE values. (p. 3-17)
115 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg.
117 */
118 static struct ahc_syncrate ahc_syncrates[] =
119 {
120 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" },
122 { 0x03, 0x000, 10, "40.0" },
123 { 0x04, 0x000, 11, "33.0" },
124 { 0x05, 0x100, 12, "20.0" },
125 { 0x06, 0x110, 15, "16.0" },
126 { 0x07, 0x120, 18, "13.4" },
127 { 0x08, 0x000, 25, "10.0" },
128 { 0x19, 0x010, 31, "8.0" },
129 { 0x1a, 0x020, 37, "6.67" },
130 { 0x1b, 0x030, 43, "5.7" },
131 { 0x1c, 0x040, 50, "5.0" },
132 { 0x00, 0x050, 56, "4.4" },
133 { 0x00, 0x060, 62, "4.0" },
134 { 0x00, 0x070, 68, "3.6" },
135 { 0x00, 0x000, 0, NULL }
136 };
137
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
140
141 /**************************** Function Declarations ***************************/
142 static void ahc_force_renegotiation(struct ahc_softc *ahc,
143 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145 ahc_alloc_tstate(struct ahc_softc *ahc,
146 u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void ahc_free_tstate(struct ahc_softc *ahc,
149 u_int scsi_id, char channel, int force);
150 #endif
151 static struct ahc_syncrate*
152 ahc_devlimited_syncrate(struct ahc_softc *ahc,
153 struct ahc_initiator_tinfo *,
154 u_int *period,
155 u_int *ppr_options,
156 role_t role);
157 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
159 struct ahc_devinfo *devinfo);
160 static void ahc_scb_devinfo(struct ahc_softc *ahc,
161 struct ahc_devinfo *devinfo,
162 struct scb *scb);
163 static void ahc_assert_atn(struct ahc_softc *ahc);
164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
166 struct scb *scb);
167 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo);
169 static void ahc_construct_sdtr(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 u_int period, u_int offset);
172 static void ahc_construct_wdtr(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo,
174 u_int bus_width);
175 static void ahc_construct_ppr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset,
178 u_int bus_width, u_int ppr_options);
179 static void ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void ahc_handle_message_phase(struct ahc_softc *ahc);
182 typedef enum {
183 AHCMSG_1B,
184 AHCMSG_2B,
185 AHCMSG_EXT
186 } ahc_msgtype;
187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188 u_int msgval, int full);
189 static int ahc_parse_msg(struct ahc_softc *ahc,
190 struct ahc_devinfo *devinfo);
191 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
192 struct ahc_devinfo *devinfo);
193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo);
195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void ahc_handle_devreset(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo,
198 cam_status status, char *message,
199 int verbose_level);
200 #ifdef AHC_TARGET_MODE
201 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
203 struct scb *scb);
204 #endif
205
206 static bus_dmamap_callback_t ahc_dmamap_cb;
207 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int ahc_init_scbdata(struct ahc_softc *ahc);
209 static void ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
211 struct scb *prev_scb,
212 struct scb *scb);
213 static int ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215 u_int prev, u_int scbptr);
216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
218 u_int scbpos, u_int prev);
219 static void ahc_reset_current_bus(struct ahc_softc *ahc);
220 #ifdef AHC_DUMP_SEQ
221 static void ahc_dumpseq(struct ahc_softc *ahc);
222 #endif
223 static int ahc_loadseq(struct ahc_softc *ahc);
224 static int ahc_check_patch(struct ahc_softc *ahc,
225 struct patch **start_patch,
226 u_int start_instr, u_int *skip_addr);
227 static void ahc_download_instr(struct ahc_softc *ahc,
228 u_int instrptr, uint8_t *dconsts);
229 #ifdef AHC_TARGET_MODE
230 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
231 struct ahc_tmode_lstate *lstate,
232 u_int initiator_id,
233 u_int event_type,
234 u_int event_arg);
235 static void ahc_update_scsiid(struct ahc_softc *ahc,
236 u_int targid_mask);
237 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
238 struct target_cmd *cmd);
239 #endif
240 /************************* Sequencer Execution Control ************************/
241 /*
242 * Restart the sequencer program from address zero
243 */
244 void
245 ahc_restart(struct ahc_softc *ahc)
246 {
247
248 ahc_pause(ahc);
249
250 /* No more pending messages. */
251 ahc_clear_msg_state(ahc);
252
253 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
254 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
255 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
256 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
257 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
258 ahc_outb(ahc, SAVED_LUN, 0xFF);
259
260 /*
261 * Ensure that the sequencer's idea of TQINPOS
262 * matches our own. The sequencer increments TQINPOS
263 * only after it sees a DMA complete and a reset could
264 * occur before the increment leaving the kernel to believe
265 * the command arrived but the sequencer to not.
266 */
267 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
268
269 /* Always allow reselection */
270 ahc_outb(ahc, SCSISEQ,
271 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
272 if ((ahc->features & AHC_CMD_CHAN) != 0) {
273 /* Ensure that no DMA operations are in progress */
274 ahc_outb(ahc, CCSCBCNT, 0);
275 ahc_outb(ahc, CCSGCTL, 0);
276 ahc_outb(ahc, CCSCBCTL, 0);
277 }
278 /*
279 * If we were in the process of DMA'ing SCB data into
280 * an SCB, replace that SCB on the free list. This prevents
281 * an SCB leak.
282 */
283 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
284 ahc_add_curscb_to_free_list(ahc);
285 ahc_outb(ahc, SEQ_FLAGS2,
286 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
287 }
288
289 /*
290 * Clear any pending sequencer interrupt. It is no
291 * longer relevant since we're resetting the Program
292 * Counter.
293 */
294 ahc_outb(ahc, CLRINT, CLRSEQINT);
295
296 ahc_outb(ahc, MWI_RESIDUAL, 0);
297 ahc_outb(ahc, SEQCTL, ahc->seqctl);
298 ahc_outb(ahc, SEQADDR0, 0);
299 ahc_outb(ahc, SEQADDR1, 0);
300
301 ahc_unpause(ahc);
302 }
303
304 /************************* Input/Output Queues ********************************/
305 void
306 ahc_run_qoutfifo(struct ahc_softc *ahc)
307 {
308 struct scb *scb;
309 u_int scb_index;
310
311 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
312 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
313
314 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
315 if ((ahc->qoutfifonext & 0x03) == 0x03) {
316 u_int modnext;
317
318 /*
319 * Clear 32bits of QOUTFIFO at a time
320 * so that we don't clobber an incoming
321 * byte DMA to the array on architectures
322 * that only support 32bit load and store
323 * operations.
324 */
325 modnext = ahc->qoutfifonext & ~0x3;
326 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
327 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
328 ahc->shared_data_dmamap,
329 /*offset*/modnext, /*len*/4,
330 BUS_DMASYNC_PREREAD);
331 }
332 ahc->qoutfifonext++;
333
334 scb = ahc_lookup_scb(ahc, scb_index);
335 if (scb == NULL) {
336 printf("%s: WARNING no command for scb %d "
337 "(cmdcmplt)\nQOUTPOS = %d\n",
338 ahc_name(ahc), scb_index,
339 (ahc->qoutfifonext - 1) & 0xFF);
340 continue;
341 }
342
343 /*
344 * Save off the residual
345 * if there is one.
346 */
347 ahc_update_residual(ahc, scb);
348 ahc_done(ahc, scb);
349 }
350 }
351
352 void
353 ahc_run_untagged_queues(struct ahc_softc *ahc)
354 {
355 int i;
356
357 for (i = 0; i < 16; i++)
358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
359 }
360
361 void
362 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
363 {
364 struct scb *scb;
365
366 if (ahc->untagged_queue_lock != 0)
367 return;
368
369 if ((scb = TAILQ_FIRST(queue)) != NULL
370 && (scb->flags & SCB_ACTIVE) == 0) {
371 scb->flags |= SCB_ACTIVE;
372 ahc_queue_scb(ahc, scb);
373 }
374 }
375
376 /************************* Interrupt Handling *********************************/
377 void
378 ahc_handle_brkadrint(struct ahc_softc *ahc)
379 {
380 /*
381 * We upset the sequencer :-(
382 * Lookup the error message
383 */
384 int i;
385 int error;
386
387 error = ahc_inb(ahc, ERROR);
388 for (i = 0; error != 1 && i < num_errors; i++)
389 error >>= 1;
390 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
391 ahc_name(ahc), ahc_hard_errors[i].errmesg,
392 ahc_inb(ahc, SEQADDR0) |
393 (ahc_inb(ahc, SEQADDR1) << 8));
394
395 ahc_dump_card_state(ahc);
396
397 /* Tell everyone that this HBA is no longer available */
398 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
399 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
400 CAM_NO_HBA);
401
402 /* Disable all interrupt sources by resetting the controller */
403 ahc_shutdown(ahc);
404 }
405
406 void
407 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
408 {
409 struct scb *scb;
410 struct ahc_devinfo devinfo;
411
412 ahc_fetch_devinfo(ahc, &devinfo);
413
414 /*
415 * Clear the upper byte that holds SEQINT status
416 * codes and clear the SEQINT bit. We will unpause
417 * the sequencer, if appropriate, after servicing
418 * the request.
419 */
420 ahc_outb(ahc, CLRINT, CLRSEQINT);
421 switch (intstat & SEQINT_MASK) {
422 case BAD_STATUS:
423 {
424 u_int scb_index;
425 struct hardware_scb *hscb;
426
427 /*
428 * Set the default return value to 0 (don't
429 * send sense). The sense code will change
430 * this if needed.
431 */
432 ahc_outb(ahc, RETURN_1, 0);
433
434 /*
435 * The sequencer will notify us when a command
436 * has an error that would be of interest to
437 * the kernel. This allows us to leave the sequencer
438 * running in the common case of command completes
439 * without error. The sequencer will already have
440 * dma'd the SCB back up to us, so we can reference
441 * the in kernel copy directly.
442 */
443 scb_index = ahc_inb(ahc, SCB_TAG);
444 scb = ahc_lookup_scb(ahc, scb_index);
445 if (scb == NULL) {
446 ahc_print_devinfo(ahc, &devinfo);
447 printf("ahc_intr - referenced scb "
448 "not valid during seqint 0x%x scb(%d)\n",
449 intstat, scb_index);
450 ahc_dump_card_state(ahc);
451 panic("for safety");
452 goto unpause;
453 }
454
455 hscb = scb->hscb;
456
457 /* Don't want to clobber the original sense code */
458 if ((scb->flags & SCB_SENSE) != 0) {
459 /*
460 * Clear the SCB_SENSE Flag and have
461 * the sequencer do a normal command
462 * complete.
463 */
464 scb->flags &= ~SCB_SENSE;
465 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
466 break;
467 }
468 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
469 /* Freeze the queue until the client sees the error. */
470 ahc_freeze_devq(ahc, scb);
471 ahc_freeze_scb(scb);
472 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
473 switch (hscb->shared_data.status.scsi_status) {
474 case SCSI_STATUS_OK:
475 printf("%s: Interrupted for staus of 0???\n",
476 ahc_name(ahc));
477 break;
478 case SCSI_STATUS_CMD_TERMINATED:
479 case SCSI_STATUS_CHECK_COND:
480 {
481 struct ahc_dma_seg *sg;
482 struct scsi_sense *sc;
483 struct ahc_initiator_tinfo *targ_info;
484 struct ahc_tmode_tstate *tstate;
485 struct ahc_transinfo *tinfo;
486 #ifdef AHC_DEBUG
487 if (ahc_debug & AHC_SHOW_SENSE) {
488 ahc_print_path(ahc, scb);
489 printf("SCB %d: requests Check Status\n",
490 scb->hscb->tag);
491 }
492 #endif
493
494 if (ahc_perform_autosense(scb) == 0)
495 break;
496
497 targ_info = ahc_fetch_transinfo(ahc,
498 devinfo.channel,
499 devinfo.our_scsiid,
500 devinfo.target,
501 &tstate);
502 tinfo = &targ_info->curr;
503 sg = scb->sg_list;
504 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
505 /*
506 * Save off the residual if there is one.
507 */
508 ahc_update_residual(ahc, scb);
509 #ifdef AHC_DEBUG
510 if (ahc_debug & AHC_SHOW_SENSE) {
511 ahc_print_path(ahc, scb);
512 printf("Sending Sense\n");
513 }
514 #endif
515 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
516 sg->len = ahc_get_sense_bufsize(ahc, scb);
517 sg->len |= AHC_DMA_LAST_SEG;
518
519 /* Fixup byte order */
520 sg->addr = ahc_htole32(sg->addr);
521 sg->len = ahc_htole32(sg->len);
522
523 sc->opcode = REQUEST_SENSE;
524 sc->byte2 = 0;
525 if (tinfo->protocol_version <= SCSI_REV_2
526 && SCB_GET_LUN(scb) < 8)
527 sc->byte2 = SCB_GET_LUN(scb) << 5;
528 sc->unused[0] = 0;
529 sc->unused[1] = 0;
530 sc->length = sg->len;
531 sc->control = 0;
532
533 /*
534 * We can't allow the target to disconnect.
535 * This will be an untagged transaction and
536 * having the target disconnect will make this
537 * transaction indestinguishable from outstanding
538 * tagged transactions.
539 */
540 hscb->control = 0;
541
542 /*
543 * This request sense could be because the
544 * the device lost power or in some other
545 * way has lost our transfer negotiations.
546 * Renegotiate if appropriate. Unit attention
547 * errors will be reported before any data
548 * phases occur.
549 */
550 if (ahc_get_residual(scb)
551 == ahc_get_transfer_length(scb)) {
552 ahc_update_neg_request(ahc, &devinfo,
553 tstate, targ_info,
554 AHC_NEG_IF_NON_ASYNC);
555 }
556 if (tstate->auto_negotiate & devinfo.target_mask) {
557 hscb->control |= MK_MESSAGE;
558 scb->flags &= ~SCB_NEGOTIATE;
559 scb->flags |= SCB_AUTO_NEGOTIATE;
560 }
561 hscb->cdb_len = sizeof(*sc);
562 hscb->dataptr = sg->addr;
563 hscb->datacnt = sg->len;
564 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
565 hscb->sgptr = ahc_htole32(hscb->sgptr);
566 scb->sg_count = 1;
567 scb->flags |= SCB_SENSE;
568 ahc_qinfifo_requeue_tail(ahc, scb);
569 ahc_outb(ahc, RETURN_1, SEND_SENSE);
570 /*
571 * Ensure we have enough time to actually
572 * retrieve the sense.
573 */
574 ahc_scb_timer_reset(scb, 5 * 1000000);
575 break;
576 }
577 default:
578 break;
579 }
580 break;
581 }
582 case NO_MATCH:
583 {
584 /* Ensure we don't leave the selection hardware on */
585 ahc_outb(ahc, SCSISEQ,
586 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
587
588 printf("%s:%c:%d: no active SCB for reconnecting "
589 "target - issuing BUS DEVICE RESET\n",
590 ahc_name(ahc), devinfo.channel, devinfo.target);
591 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
592 "ARG_1 == 0x%x ACCUM = 0x%x\n",
593 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
594 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
595 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
596 "SINDEX == 0x%x\n",
597 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
598 ahc_index_busy_tcl(ahc,
599 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
600 ahc_inb(ahc, SAVED_LUN))),
601 ahc_inb(ahc, SINDEX));
602 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
603 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
604 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
605 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
606 ahc_inb(ahc, SCB_CONTROL));
607 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
608 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
609 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
610 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
611 ahc_dump_card_state(ahc);
612 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
613 ahc->msgout_len = 1;
614 ahc->msgout_index = 0;
615 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
616 ahc_outb(ahc, MSG_OUT, HOST_MSG);
617 ahc_assert_atn(ahc);
618 break;
619 }
620 case SEND_REJECT:
621 {
622 u_int rejbyte = ahc_inb(ahc, ACCUM);
623 printf("%s:%c:%d: Warning - unknown message received from "
624 "target (0x%x). Rejecting\n",
625 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
626 break;
627 }
628 case PROTO_VIOLATION:
629 {
630 ahc_handle_proto_violation(ahc);
631 break;
632 }
633 case IGN_WIDE_RES:
634 ahc_handle_ign_wide_residue(ahc, &devinfo);
635 break;
636 case PDATA_REINIT:
637 ahc_reinitialize_dataptrs(ahc);
638 break;
639 case BAD_PHASE:
640 {
641 u_int lastphase;
642
643 lastphase = ahc_inb(ahc, LASTPHASE);
644 printf("%s:%c:%d: unknown scsi bus phase %x, "
645 "lastphase = 0x%x. Attempting to continue\n",
646 ahc_name(ahc), devinfo.channel, devinfo.target,
647 lastphase, ahc_inb(ahc, SCSISIGI));
648 break;
649 }
650 case MISSED_BUSFREE:
651 {
652 u_int lastphase;
653
654 lastphase = ahc_inb(ahc, LASTPHASE);
655 printf("%s:%c:%d: Missed busfree. "
656 "Lastphase = 0x%x, Curphase = 0x%x\n",
657 ahc_name(ahc), devinfo.channel, devinfo.target,
658 lastphase, ahc_inb(ahc, SCSISIGI));
659 ahc_restart(ahc);
660 return;
661 }
662 case HOST_MSG_LOOP:
663 {
664 /*
665 * The sequencer has encountered a message phase
666 * that requires host assistance for completion.
667 * While handling the message phase(s), we will be
668 * notified by the sequencer after each byte is
669 * transfered so we can track bus phase changes.
670 *
671 * If this is the first time we've seen a HOST_MSG_LOOP
672 * interrupt, initialize the state of the host message
673 * loop.
674 */
675 if (ahc->msg_type == MSG_TYPE_NONE) {
676 struct scb *scb;
677 u_int scb_index;
678 u_int bus_phase;
679
680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
681 if (bus_phase != P_MESGIN
682 && bus_phase != P_MESGOUT) {
683 printf("ahc_intr: HOST_MSG_LOOP bad "
684 "phase 0x%x\n",
685 bus_phase);
686 /*
687 * Probably transitioned to bus free before
688 * we got here. Just punt the message.
689 */
690 ahc_clear_intstat(ahc);
691 ahc_restart(ahc);
692 return;
693 }
694
695 scb_index = ahc_inb(ahc, SCB_TAG);
696 scb = ahc_lookup_scb(ahc, scb_index);
697 if (devinfo.role == ROLE_INITIATOR) {
698 if (scb == NULL)
699 panic("HOST_MSG_LOOP with "
700 "invalid SCB %x\n", scb_index);
701
702 if (bus_phase == P_MESGOUT)
703 ahc_setup_initiator_msgout(ahc,
704 &devinfo,
705 scb);
706 else {
707 ahc->msg_type =
708 MSG_TYPE_INITIATOR_MSGIN;
709 ahc->msgin_index = 0;
710 }
711 }
712 #ifdef AHC_TARGET_MODE
713 else {
714 if (bus_phase == P_MESGOUT) {
715 ahc->msg_type =
716 MSG_TYPE_TARGET_MSGOUT;
717 ahc->msgin_index = 0;
718 }
719 else
720 ahc_setup_target_msgin(ahc,
721 &devinfo,
722 scb);
723 }
724 #endif
725 }
726
727 ahc_handle_message_phase(ahc);
728 break;
729 }
730 case PERR_DETECTED:
731 {
732 /*
733 * If we've cleared the parity error interrupt
734 * but the sequencer still believes that SCSIPERR
735 * is true, it must be that the parity error is
736 * for the currently presented byte on the bus,
737 * and we are not in a phase (data-in) where we will
738 * eventually ack this byte. Ack the byte and
739 * throw it away in the hope that the target will
740 * take us to message out to deliver the appropriate
741 * error message.
742 */
743 if ((intstat & SCSIINT) == 0
744 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
745
746 if ((ahc->features & AHC_DT) == 0) {
747 u_int curphase;
748
749 /*
750 * The hardware will only let you ack bytes
751 * if the expected phase in SCSISIGO matches
752 * the current phase. Make sure this is
753 * currently the case.
754 */
755 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
756 ahc_outb(ahc, LASTPHASE, curphase);
757 ahc_outb(ahc, SCSISIGO, curphase);
758 }
759 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
760 int wait;
761
762 /*
763 * In a data phase. Faster to bitbucket
764 * the data than to individually ack each
765 * byte. This is also the only strategy
766 * that will work with AUTOACK enabled.
767 */
768 ahc_outb(ahc, SXFRCTL1,
769 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
770 wait = 5000;
771 while (--wait != 0) {
772 if ((ahc_inb(ahc, SCSISIGI)
773 & (CDI|MSGI)) != 0)
774 break;
775 ahc_delay(100);
776 }
777 ahc_outb(ahc, SXFRCTL1,
778 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
779 if (wait == 0) {
780 struct scb *scb;
781 u_int scb_index;
782
783 ahc_print_devinfo(ahc, &devinfo);
784 printf("Unable to clear parity error. "
785 "Resetting bus.\n");
786 scb_index = ahc_inb(ahc, SCB_TAG);
787 scb = ahc_lookup_scb(ahc, scb_index);
788 if (scb != NULL)
789 ahc_set_transaction_status(scb,
790 CAM_UNCOR_PARITY);
791 ahc_reset_channel(ahc, devinfo.channel,
792 /*init reset*/TRUE);
793 }
794 } else {
795 ahc_inb(ahc, SCSIDATL);
796 }
797 }
798 break;
799 }
800 case DATA_OVERRUN:
801 {
802 /*
803 * When the sequencer detects an overrun, it
804 * places the controller in "BITBUCKET" mode
805 * and allows the target to complete its transfer.
806 * Unfortunately, none of the counters get updated
807 * when the controller is in this mode, so we have
808 * no way of knowing how large the overrun was.
809 */
810 u_int scbindex = ahc_inb(ahc, SCB_TAG);
811 u_int lastphase = ahc_inb(ahc, LASTPHASE);
812 u_int i;
813
814 scb = ahc_lookup_scb(ahc, scbindex);
815 for (i = 0; i < num_phases; i++) {
816 if (lastphase == ahc_phase_table[i].phase)
817 break;
818 }
819 ahc_print_path(ahc, scb);
820 printf("data overrun detected %s."
821 " Tag == 0x%x.\n",
822 ahc_phase_table[i].phasemsg,
823 scb->hscb->tag);
824 ahc_print_path(ahc, scb);
825 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
826 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
827 ahc_get_transfer_length(scb), scb->sg_count);
828 if (scb->sg_count > 0) {
829 for (i = 0; i < scb->sg_count; i++) {
830
831 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
832 i,
833 (ahc_le32toh(scb->sg_list[i].len) >> 24
834 & SG_HIGH_ADDR_BITS),
835 ahc_le32toh(scb->sg_list[i].addr),
836 ahc_le32toh(scb->sg_list[i].len)
837 & AHC_SG_LEN_MASK);
838 }
839 }
840 /*
841 * Set this and it will take effect when the
842 * target does a command complete.
843 */
844 ahc_freeze_devq(ahc, scb);
845 if ((scb->flags & SCB_SENSE) == 0) {
846 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
847 } else {
848 scb->flags &= ~SCB_SENSE;
849 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
850 }
851 ahc_freeze_scb(scb);
852
853 if ((ahc->features & AHC_ULTRA2) != 0) {
854 /*
855 * Clear the channel in case we return
856 * to data phase later.
857 */
858 ahc_outb(ahc, SXFRCTL0,
859 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
860 ahc_outb(ahc, SXFRCTL0,
861 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
862 }
863 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
864 u_int dscommand1;
865
866 /* Ensure HHADDR is 0 for future DMA operations. */
867 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
868 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
869 ahc_outb(ahc, HADDR, 0);
870 ahc_outb(ahc, DSCOMMAND1, dscommand1);
871 }
872 break;
873 }
874 case MKMSG_FAILED:
875 {
876 u_int scbindex;
877
878 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
879 ahc_name(ahc), devinfo.channel, devinfo.target,
880 devinfo.lun);
881 scbindex = ahc_inb(ahc, SCB_TAG);
882 scb = ahc_lookup_scb(ahc, scbindex);
883 if (scb != NULL
884 && (scb->flags & SCB_RECOVERY_SCB) != 0)
885 /*
886 * Ensure that we didn't put a second instance of this
887 * SCB into the QINFIFO.
888 */
889 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
890 SCB_GET_CHANNEL(ahc, scb),
891 SCB_GET_LUN(scb), scb->hscb->tag,
892 ROLE_INITIATOR, /*status*/0,
893 SEARCH_REMOVE);
894 break;
895 }
896 case NO_FREE_SCB:
897 {
898 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
899 ahc_dump_card_state(ahc);
900 panic("for safety");
901 break;
902 }
903 case SCB_MISMATCH:
904 {
905 u_int scbptr;
906
907 scbptr = ahc_inb(ahc, SCBPTR);
908 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
909 scbptr, ahc_inb(ahc, ARG_1),
910 ahc->scb_data->hscbs[scbptr].tag);
911 ahc_dump_card_state(ahc);
912 panic("for saftey");
913 break;
914 }
915 case OUT_OF_RANGE:
916 {
917 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
918 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
919 "ARG_1 == 0x%x ACCUM = 0x%x\n",
920 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
921 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
922 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
923 "SINDEX == 0x%x\n, A == 0x%x\n",
924 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
925 ahc_index_busy_tcl(ahc,
926 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
927 ahc_inb(ahc, SAVED_LUN))),
928 ahc_inb(ahc, SINDEX),
929 ahc_inb(ahc, ACCUM));
930 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
931 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
932 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
933 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
934 ahc_inb(ahc, SCB_CONTROL));
935 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
936 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
937 ahc_dump_card_state(ahc);
938 panic("for safety");
939 break;
940 }
941 default:
942 printf("ahc_intr: seqint, "
943 "intstat == 0x%x, scsisigi = 0x%x\n",
944 intstat, ahc_inb(ahc, SCSISIGI));
945 break;
946 }
947 unpause:
948 /*
949 * The sequencer is paused immediately on
950 * a SEQINT, so we should restart it when
951 * we're done.
952 */
953 ahc_unpause(ahc);
954 }
955
956 void
957 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
958 {
959 u_int scb_index;
960 u_int status0;
961 u_int status;
962 struct scb *scb;
963 char cur_channel;
964 char intr_channel;
965
966 if ((ahc->features & AHC_TWIN) != 0
967 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
968 cur_channel = 'B';
969 else
970 cur_channel = 'A';
971 intr_channel = cur_channel;
972
973 if ((ahc->features & AHC_ULTRA2) != 0)
974 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
975 else
976 status0 = 0;
977 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
978 if (status == 0 && status0 == 0) {
979 if ((ahc->features & AHC_TWIN) != 0) {
980 /* Try the other channel */
981 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
982 status = ahc_inb(ahc, SSTAT1)
983 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
984 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
985 }
986 if (status == 0) {
987 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
988 ahc_outb(ahc, CLRINT, CLRSCSIINT);
989 ahc_unpause(ahc);
990 return;
991 }
992 }
993
994 /* Make sure the sequencer is in a safe location. */
995 ahc_clear_critical_section(ahc);
996
997 scb_index = ahc_inb(ahc, SCB_TAG);
998 scb = ahc_lookup_scb(ahc, scb_index);
999 if (scb != NULL
1000 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1001 scb = NULL;
1002
1003 if ((ahc->features & AHC_ULTRA2) != 0
1004 && (status0 & IOERR) != 0) {
1005 int now_lvd;
1006
1007 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1008 printf("%s: Transceiver State Has Changed to %s mode\n",
1009 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1010 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1011 /*
1012 * When transitioning to SE mode, the reset line
1013 * glitches, triggering an arbitration bug in some
1014 * Ultra2 controllers. This bug is cleared when we
1015 * assert the reset line. Since a reset glitch has
1016 * already occurred with this transition and a
1017 * transceiver state change is handled just like
1018 * a bus reset anyway, asserting the reset line
1019 * ourselves is safe.
1020 */
1021 ahc_reset_channel(ahc, intr_channel,
1022 /*Initiate Reset*/now_lvd == 0);
1023 } else if ((status & SCSIRSTI) != 0) {
1024 printf("%s: Someone reset channel %c\n",
1025 ahc_name(ahc), intr_channel);
1026 if (intr_channel != cur_channel)
1027 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1028 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1029 } else if ((status & SCSIPERR) != 0) {
1030 /*
1031 * Determine the bus phase and queue an appropriate message.
1032 * SCSIPERR is latched true as soon as a parity error
1033 * occurs. If the sequencer acked the transfer that
1034 * caused the parity error and the currently presented
1035 * transfer on the bus has correct parity, SCSIPERR will
1036 * be cleared by CLRSCSIPERR. Use this to determine if
1037 * we should look at the last phase the sequencer recorded,
1038 * or the current phase presented on the bus.
1039 */
1040 struct ahc_devinfo devinfo;
1041 u_int mesg_out;
1042 u_int curphase;
1043 u_int errorphase;
1044 u_int lastphase;
1045 u_int scsirate;
1046 u_int i;
1047 u_int sstat2;
1048 int silent;
1049
1050 lastphase = ahc_inb(ahc, LASTPHASE);
1051 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1052 sstat2 = ahc_inb(ahc, SSTAT2);
1053 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1054 /*
1055 * For all phases save DATA, the sequencer won't
1056 * automatically ack a byte that has a parity error
1057 * in it. So the only way that the current phase
1058 * could be 'data-in' is if the parity error is for
1059 * an already acked byte in the data phase. During
1060 * synchronous data-in transfers, we may actually
1061 * ack bytes before latching the current phase in
1062 * LASTPHASE, leading to the discrepancy between
1063 * curphase and lastphase.
1064 */
1065 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1066 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1067 errorphase = curphase;
1068 else
1069 errorphase = lastphase;
1070
1071 for (i = 0; i < num_phases; i++) {
1072 if (errorphase == ahc_phase_table[i].phase)
1073 break;
1074 }
1075 mesg_out = ahc_phase_table[i].mesg_out;
1076 silent = FALSE;
1077 if (scb != NULL) {
1078 if (SCB_IS_SILENT(scb))
1079 silent = TRUE;
1080 else
1081 ahc_print_path(ahc, scb);
1082 scb->flags |= SCB_TRANSMISSION_ERROR;
1083 } else
1084 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1085 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1086 scsirate = ahc_inb(ahc, SCSIRATE);
1087 if (silent == FALSE) {
1088 printf("parity error detected %s. "
1089 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1090 ahc_phase_table[i].phasemsg,
1091 ahc_inw(ahc, SEQADDR0),
1092 scsirate);
1093 if ((ahc->features & AHC_DT) != 0) {
1094 if ((sstat2 & CRCVALERR) != 0)
1095 printf("\tCRC Value Mismatch\n");
1096 if ((sstat2 & CRCENDERR) != 0)
1097 printf("\tNo terminal CRC packet "
1098 "recevied\n");
1099 if ((sstat2 & CRCREQERR) != 0)
1100 printf("\tIllegal CRC packet "
1101 "request\n");
1102 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1103 printf("\tUnexpected %sDT Data Phase\n",
1104 (scsirate & SINGLE_EDGE)
1105 ? "" : "non-");
1106 }
1107 }
1108
1109 if ((ahc->features & AHC_DT) != 0
1110 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1111 /*
1112 * This error applies regardless of
1113 * data direction, so ignore the value
1114 * in the phase table.
1115 */
1116 mesg_out = MSG_INITIATOR_DET_ERR;
1117 }
1118
1119 /*
1120 * We've set the hardware to assert ATN if we
1121 * get a parity error on "in" phases, so all we
1122 * need to do is stuff the message buffer with
1123 * the appropriate message. "In" phases have set
1124 * mesg_out to something other than MSG_NOP.
1125 */
1126 if (mesg_out != MSG_NOOP) {
1127 if (ahc->msg_type != MSG_TYPE_NONE)
1128 ahc->send_msg_perror = TRUE;
1129 else
1130 ahc_outb(ahc, MSG_OUT, mesg_out);
1131 }
1132 /*
1133 * Force a renegotiation with this target just in
1134 * case we are out of sync for some external reason
1135 * unknown (or unreported) by the target.
1136 */
1137 ahc_fetch_devinfo(ahc, &devinfo);
1138 ahc_force_renegotiation(ahc, &devinfo);
1139
1140 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1141 ahc_unpause(ahc);
1142 } else if ((status & SELTO) != 0) {
1143 u_int scbptr;
1144
1145 /* Stop the selection */
1146 ahc_outb(ahc, SCSISEQ, 0);
1147
1148 /* No more pending messages */
1149 ahc_clear_msg_state(ahc);
1150
1151 /* Clear interrupt state */
1152 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1153 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1154
1155 /*
1156 * Although the driver does not care about the
1157 * 'Selection in Progress' status bit, the busy
1158 * LED does. SELINGO is only cleared by a sucessfull
1159 * selection, so we must manually clear it to insure
1160 * the LED turns off just incase no future successful
1161 * selections occur (e.g. no devices on the bus).
1162 */
1163 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1164
1165 scbptr = ahc_inb(ahc, WAITING_SCBH);
1166 ahc_outb(ahc, SCBPTR, scbptr);
1167 scb_index = ahc_inb(ahc, SCB_TAG);
1168
1169 scb = ahc_lookup_scb(ahc, scb_index);
1170 if (scb == NULL) {
1171 printf("%s: ahc_intr - referenced scb not "
1172 "valid during SELTO scb(%d, %d)\n",
1173 ahc_name(ahc), scbptr, scb_index);
1174 ahc_dump_card_state(ahc);
1175 } else {
1176 struct ahc_devinfo devinfo;
1177 #ifdef AHC_DEBUG
1178 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1179 ahc_print_path(ahc, scb);
1180 printf("Saw Selection Timeout for SCB 0x%x\n",
1181 scb_index);
1182 }
1183 #endif
1184 ahc_scb_devinfo(ahc, &devinfo, scb);
1185 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1186 ahc_freeze_devq(ahc, scb);
1187
1188 /*
1189 * Cancel any pending transactions on the device
1190 * now that it seems to be missing. This will
1191 * also revert us to async/narrow transfers until
1192 * we can renegotiate with the device.
1193 */
1194 ahc_handle_devreset(ahc, &devinfo,
1195 CAM_SEL_TIMEOUT,
1196 "Selection Timeout",
1197 /*verbose_level*/1);
1198 }
1199 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1200 ahc_restart(ahc);
1201 } else if ((status & BUSFREE) != 0
1202 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1203 struct ahc_devinfo devinfo;
1204 u_int lastphase;
1205 u_int saved_scsiid;
1206 u_int saved_lun;
1207 u_int target;
1208 u_int initiator_role_id;
1209 char channel;
1210 int printerror;
1211
1212 /*
1213 * Clear our selection hardware as soon as possible.
1214 * We may have an entry in the waiting Q for this target,
1215 * that is affected by this busfree and we don't want to
1216 * go about selecting the target while we handle the event.
1217 */
1218 ahc_outb(ahc, SCSISEQ,
1219 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1220
1221 /*
1222 * Disable busfree interrupts and clear the busfree
1223 * interrupt status. We do this here so that several
1224 * bus transactions occur prior to clearing the SCSIINT
1225 * latch. It can take a bit for the clearing to take effect.
1226 */
1227 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1228 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1229
1230 /*
1231 * Look at what phase we were last in.
1232 * If its message out, chances are pretty good
1233 * that the busfree was in response to one of
1234 * our abort requests.
1235 */
1236 lastphase = ahc_inb(ahc, LASTPHASE);
1237 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1238 saved_lun = ahc_inb(ahc, SAVED_LUN);
1239 target = SCSIID_TARGET(ahc, saved_scsiid);
1240 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1241 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1242 ahc_compile_devinfo(&devinfo, initiator_role_id,
1243 target, saved_lun, channel, ROLE_INITIATOR);
1244 printerror = 1;
1245
1246 if (lastphase == P_MESGOUT) {
1247 u_int tag;
1248
1249 tag = SCB_LIST_NULL;
1250 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1251 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1252 if (ahc->msgout_buf[ahc->msgout_index - 1]
1253 == MSG_ABORT_TAG)
1254 tag = scb->hscb->tag;
1255 ahc_print_path(ahc, scb);
1256 printf("SCB %d - Abort%s Completed.\n",
1257 scb->hscb->tag, tag == SCB_LIST_NULL ?
1258 "" : " Tag");
1259 ahc_abort_scbs(ahc, target, channel,
1260 saved_lun, tag,
1261 ROLE_INITIATOR,
1262 CAM_REQ_ABORTED);
1263 printerror = 0;
1264 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1265 MSG_BUS_DEV_RESET, TRUE)) {
1266 #ifdef __FreeBSD__
1267 /*
1268 * Don't mark the user's request for this BDR
1269 * as completing with CAM_BDR_SENT. CAM3
1270 * specifies CAM_REQ_CMP.
1271 */
1272 if (scb != NULL
1273 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1274 && ahc_match_scb(ahc, scb, target, channel,
1275 CAM_LUN_WILDCARD,
1276 SCB_LIST_NULL,
1277 ROLE_INITIATOR)) {
1278 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1279 }
1280 #endif
1281 ahc_compile_devinfo(&devinfo,
1282 initiator_role_id,
1283 target,
1284 CAM_LUN_WILDCARD,
1285 channel,
1286 ROLE_INITIATOR);
1287 ahc_handle_devreset(ahc, &devinfo,
1288 CAM_BDR_SENT,
1289 "Bus Device Reset",
1290 /*verbose_level*/0);
1291 printerror = 0;
1292 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1293 MSG_EXT_PPR, FALSE)) {
1294 struct ahc_initiator_tinfo *tinfo;
1295 struct ahc_tmode_tstate *tstate;
1296
1297 /*
1298 * PPR Rejected. Try non-ppr negotiation
1299 * and retry command.
1300 */
1301 tinfo = ahc_fetch_transinfo(ahc,
1302 devinfo.channel,
1303 devinfo.our_scsiid,
1304 devinfo.target,
1305 &tstate);
1306 tinfo->curr.transport_version = 2;
1307 tinfo->goal.transport_version = 2;
1308 tinfo->goal.ppr_options = 0;
1309 ahc_qinfifo_requeue_tail(ahc, scb);
1310 printerror = 0;
1311 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1312 MSG_EXT_WDTR, FALSE)) {
1313 /*
1314 * Negotiation Rejected. Go-narrow and
1315 * retry command.
1316 */
1317 ahc_set_width(ahc, &devinfo,
1318 MSG_EXT_WDTR_BUS_8_BIT,
1319 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1320 /*paused*/TRUE);
1321 ahc_qinfifo_requeue_tail(ahc, scb);
1322 printerror = 0;
1323 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1324 MSG_EXT_SDTR, FALSE)) {
1325 /*
1326 * Negotiation Rejected. Go-async and
1327 * retry command.
1328 */
1329 ahc_set_syncrate(ahc, &devinfo,
1330 /*syncrate*/NULL,
1331 /*period*/0, /*offset*/0,
1332 /*ppr_options*/0,
1333 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1334 /*paused*/TRUE);
1335 ahc_qinfifo_requeue_tail(ahc, scb);
1336 printerror = 0;
1337 }
1338 }
1339 if (printerror != 0) {
1340 u_int i;
1341
1342 if (scb != NULL) {
1343 u_int tag;
1344
1345 if ((scb->hscb->control & TAG_ENB) != 0)
1346 tag = scb->hscb->tag;
1347 else
1348 tag = SCB_LIST_NULL;
1349 ahc_print_path(ahc, scb);
1350 ahc_abort_scbs(ahc, target, channel,
1351 SCB_GET_LUN(scb), tag,
1352 ROLE_INITIATOR,
1353 CAM_UNEXP_BUSFREE);
1354 } else {
1355 /*
1356 * We had not fully identified this connection,
1357 * so we cannot abort anything.
1358 */
1359 printf("%s: ", ahc_name(ahc));
1360 }
1361 for (i = 0; i < num_phases; i++) {
1362 if (lastphase == ahc_phase_table[i].phase)
1363 break;
1364 }
1365 if (lastphase != P_BUSFREE) {
1366 /*
1367 * Renegotiate with this device at the
1368 * next oportunity just in case this busfree
1369 * is due to a negotiation mismatch with the
1370 * device.
1371 */
1372 ahc_force_renegotiation(ahc, &devinfo);
1373 }
1374 printf("Unexpected busfree %s\n"
1375 "SEQADDR == 0x%x\n",
1376 ahc_phase_table[i].phasemsg,
1377 ahc_inb(ahc, SEQADDR0)
1378 | (ahc_inb(ahc, SEQADDR1) << 8));
1379 }
1380 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1381 ahc_restart(ahc);
1382 } else {
1383 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1384 ahc_name(ahc), status);
1385 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1386 }
1387 }
1388
1389 /*
1390 * Force renegotiation to occur the next time we initiate
1391 * a command to the current device.
1392 */
1393 static void
1394 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1395 {
1396 struct ahc_initiator_tinfo *targ_info;
1397 struct ahc_tmode_tstate *tstate;
1398
1399 targ_info = ahc_fetch_transinfo(ahc,
1400 devinfo->channel,
1401 devinfo->our_scsiid,
1402 devinfo->target,
1403 &tstate);
1404 ahc_update_neg_request(ahc, devinfo, tstate,
1405 targ_info, AHC_NEG_IF_NON_ASYNC);
1406 }
1407
1408 #define AHC_MAX_STEPS 2000
1409 void
1410 ahc_clear_critical_section(struct ahc_softc *ahc)
1411 {
1412 int stepping;
1413 int steps;
1414 u_int simode0;
1415 u_int simode1;
1416
1417 if (ahc->num_critical_sections == 0)
1418 return;
1419
1420 stepping = FALSE;
1421 steps = 0;
1422 simode0 = 0;
1423 simode1 = 0;
1424 for (;;) {
1425 struct cs *cs;
1426 u_int seqaddr;
1427 u_int i;
1428
1429 seqaddr = ahc_inb(ahc, SEQADDR0)
1430 | (ahc_inb(ahc, SEQADDR1) << 8);
1431
1432 /*
1433 * Seqaddr represents the next instruction to execute,
1434 * so we are really executing the instruction just
1435 * before it.
1436 */
1437 if (seqaddr != 0)
1438 seqaddr -= 1;
1439 cs = ahc->critical_sections;
1440 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1441
1442 if (cs->begin < seqaddr && cs->end >= seqaddr)
1443 break;
1444 }
1445
1446 if (i == ahc->num_critical_sections)
1447 break;
1448
1449 if (steps > AHC_MAX_STEPS) {
1450 printf("%s: Infinite loop in critical section\n",
1451 ahc_name(ahc));
1452 ahc_dump_card_state(ahc);
1453 panic("critical section loop");
1454 }
1455
1456 steps++;
1457 if (stepping == FALSE) {
1458
1459 /*
1460 * Disable all interrupt sources so that the
1461 * sequencer will not be stuck by a pausing
1462 * interrupt condition while we attempt to
1463 * leave a critical section.
1464 */
1465 simode0 = ahc_inb(ahc, SIMODE0);
1466 ahc_outb(ahc, SIMODE0, 0);
1467 simode1 = ahc_inb(ahc, SIMODE1);
1468 if ((ahc->features & AHC_DT) != 0)
1469 /*
1470 * On DT class controllers, we
1471 * use the enhanced busfree logic.
1472 * Unfortunately we cannot re-enable
1473 * busfree detection within the
1474 * current connection, so we must
1475 * leave it on while single stepping.
1476 */
1477 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1478 else
1479 ahc_outb(ahc, SIMODE1, 0);
1480 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1481 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1482 stepping = TRUE;
1483 }
1484 if ((ahc->features & AHC_DT) != 0) {
1485 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1486 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1487 }
1488 ahc_outb(ahc, HCNTRL, ahc->unpause);
1489 while (!ahc_is_paused(ahc))
1490 ahc_delay(200);
1491 }
1492 if (stepping) {
1493 ahc_outb(ahc, SIMODE0, simode0);
1494 ahc_outb(ahc, SIMODE1, simode1);
1495 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1496 }
1497 }
1498
1499 /*
1500 * Clear any pending interrupt status.
1501 */
1502 void
1503 ahc_clear_intstat(struct ahc_softc *ahc)
1504 {
1505 /* Clear any interrupt conditions this may have caused */
1506 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1507 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1508 CLRREQINIT);
1509 ahc_flush_device_writes(ahc);
1510 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1511 ahc_flush_device_writes(ahc);
1512 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1513 ahc_flush_device_writes(ahc);
1514 }
1515
1516 /**************************** Debugging Routines ******************************/
1517 #ifdef AHC_DEBUG
1518 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1519 #endif
1520
1521 void
1522 ahc_print_scb(struct scb *scb)
1523 {
1524 int i;
1525
1526 struct hardware_scb *hscb = scb->hscb;
1527
1528 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1529 (void *)scb,
1530 hscb->control,
1531 hscb->scsiid,
1532 hscb->lun,
1533 hscb->cdb_len);
1534 printf("Shared Data: ");
1535 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1536 printf("%#02x", hscb->shared_data.cdb[i]);
1537 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1538 ahc_le32toh(hscb->dataptr),
1539 ahc_le32toh(hscb->datacnt),
1540 ahc_le32toh(hscb->sgptr),
1541 hscb->tag);
1542 if (scb->sg_count > 0) {
1543 for (i = 0; i < scb->sg_count; i++) {
1544 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1545 i,
1546 (ahc_le32toh(scb->sg_list[i].len) >> 24
1547 & SG_HIGH_ADDR_BITS),
1548 ahc_le32toh(scb->sg_list[i].addr),
1549 ahc_le32toh(scb->sg_list[i].len));
1550 }
1551 }
1552 }
1553
1554 /************************* Transfer Negotiation *******************************/
1555 /*
1556 * Allocate per target mode instance (ID we respond to as a target)
1557 * transfer negotiation data structures.
1558 */
1559 static struct ahc_tmode_tstate *
1560 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1561 {
1562 struct ahc_tmode_tstate *master_tstate;
1563 struct ahc_tmode_tstate *tstate;
1564 int i;
1565
1566 master_tstate = ahc->enabled_targets[ahc->our_id];
1567 if (channel == 'B') {
1568 scsi_id += 8;
1569 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1570 }
1571 if (ahc->enabled_targets[scsi_id] != NULL
1572 && ahc->enabled_targets[scsi_id] != master_tstate)
1573 panic("%s: ahc_alloc_tstate - Target already allocated",
1574 ahc_name(ahc));
1575 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1576 M_DEVBUF, M_NOWAIT);
1577 if (tstate == NULL)
1578 return (NULL);
1579
1580 /*
1581 * If we have allocated a master tstate, copy user settings from
1582 * the master tstate (taken from SRAM or the EEPROM) for this
1583 * channel, but reset our current and goal settings to async/narrow
1584 * until an initiator talks to us.
1585 */
1586 if (master_tstate != NULL) {
1587 memcpy(tstate, master_tstate, sizeof(*tstate));
1588 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1589 tstate->ultraenb = 0;
1590 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1591 memset(&tstate->transinfo[i].curr, 0,
1592 sizeof(tstate->transinfo[i].curr));
1593 memset(&tstate->transinfo[i].goal, 0,
1594 sizeof(tstate->transinfo[i].goal));
1595 }
1596 } else
1597 memset(tstate, 0, sizeof(*tstate));
1598 ahc->enabled_targets[scsi_id] = tstate;
1599 return (tstate);
1600 }
1601
1602 #ifdef AHC_TARGET_MODE
1603 /*
1604 * Free per target mode instance (ID we respond to as a target)
1605 * transfer negotiation data structures.
1606 */
1607 static void
1608 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1609 {
1610 struct ahc_tmode_tstate *tstate;
1611
1612 /*
1613 * Don't clean up our "master" tstate.
1614 * It has our default user settings.
1615 */
1616 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1617 || (channel == 'A' && scsi_id == ahc->our_id))
1618 && force == FALSE)
1619 return;
1620
1621 if (channel == 'B')
1622 scsi_id += 8;
1623 tstate = ahc->enabled_targets[scsi_id];
1624 if (tstate != NULL)
1625 free(tstate, M_DEVBUF);
1626 ahc->enabled_targets[scsi_id] = NULL;
1627 }
1628 #endif
1629
1630 /*
1631 * Called when we have an active connection to a target on the bus,
1632 * this function finds the nearest syncrate to the input period limited
1633 * by the capabilities of the bus connectivity of and sync settings for
1634 * the target.
1635 */
1636 struct ahc_syncrate *
1637 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1638 struct ahc_initiator_tinfo *tinfo,
1639 u_int *period, u_int *ppr_options, role_t role)
1640 {
1641 struct ahc_transinfo *transinfo;
1642 u_int maxsync;
1643
1644 if ((ahc->features & AHC_ULTRA2) != 0) {
1645 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1646 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1647 maxsync = AHC_SYNCRATE_DT;
1648 } else {
1649 maxsync = AHC_SYNCRATE_ULTRA;
1650 /* Can't do DT on an SE bus */
1651 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1652 }
1653 } else if ((ahc->features & AHC_ULTRA) != 0) {
1654 maxsync = AHC_SYNCRATE_ULTRA;
1655 } else {
1656 maxsync = AHC_SYNCRATE_FAST;
1657 }
1658 /*
1659 * Never allow a value higher than our current goal
1660 * period otherwise we may allow a target initiated
1661 * negotiation to go above the limit as set by the
1662 * user. In the case of an initiator initiated
1663 * sync negotiation, we limit based on the user
1664 * setting. This allows the system to still accept
1665 * incoming negotiations even if target initiated
1666 * negotiation is not performed.
1667 */
1668 if (role == ROLE_TARGET)
1669 transinfo = &tinfo->user;
1670 else
1671 transinfo = &tinfo->goal;
1672 *ppr_options &= transinfo->ppr_options;
1673 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1674 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
1675 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1676 }
1677 if (transinfo->period == 0) {
1678 *period = 0;
1679 *ppr_options = 0;
1680 return (NULL);
1681 }
1682 *period = max(*period, (u_int)transinfo->period);
1683 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1684 }
1685
1686 /*
1687 * Look up the valid period to SCSIRATE conversion in our table.
1688 * Return the period and offset that should be sent to the target
1689 * if this was the beginning of an SDTR.
1690 */
1691 struct ahc_syncrate *
1692 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1693 u_int *ppr_options, u_int maxsync)
1694 {
1695 struct ahc_syncrate *syncrate;
1696
1697 if ((ahc->features & AHC_DT) == 0)
1698 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1699
1700 /* Skip all DT only entries if DT is not available */
1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1702 && maxsync < AHC_SYNCRATE_ULTRA2)
1703 maxsync = AHC_SYNCRATE_ULTRA2;
1704
1705 /* Now set the maxsync based on the card capabilities
1706 * DT is already done above */
1707 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
1708 && maxsync < AHC_SYNCRATE_ULTRA)
1709 maxsync = AHC_SYNCRATE_ULTRA;
1710 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
1711 && maxsync < AHC_SYNCRATE_FAST)
1712 maxsync = AHC_SYNCRATE_FAST;
1713
1714 for (syncrate = &ahc_syncrates[maxsync];
1715 syncrate->rate != NULL;
1716 syncrate++) {
1717
1718 /*
1719 * The Ultra2 table doesn't go as low
1720 * as for the Fast/Ultra cards.
1721 */
1722 if ((ahc->features & AHC_ULTRA2) != 0
1723 && (syncrate->sxfr_u2 == 0))
1724 break;
1725
1726 if (*period <= syncrate->period) {
1727 /*
1728 * When responding to a target that requests
1729 * sync, the requested rate may fall between
1730 * two rates that we can output, but still be
1731 * a rate that we can receive. Because of this,
1732 * we want to respond to the target with
1733 * the same rate that it sent to us even
1734 * if the period we use to send data to it
1735 * is lower. Only lower the response period
1736 * if we must.
1737 */
1738 if (syncrate == &ahc_syncrates[maxsync])
1739 *period = syncrate->period;
1740
1741 /*
1742 * At some speeds, we only support
1743 * ST transfers.
1744 */
1745 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1746 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1747 break;
1748 }
1749 }
1750
1751 if ((*period == 0)
1752 || (syncrate->rate == NULL)
1753 || ((ahc->features & AHC_ULTRA2) != 0
1754 && (syncrate->sxfr_u2 == 0))) {
1755 /* Use asynchronous transfers. */
1756 *period = 0;
1757 syncrate = NULL;
1758 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1759 }
1760 return (syncrate);
1761 }
1762
1763 /*
1764 * Convert from an entry in our syncrate table to the SCSI equivalent
1765 * sync "period" factor.
1766 */
1767 u_int
1768 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1769 {
1770 struct ahc_syncrate *syncrate;
1771
1772 if ((ahc->features & AHC_ULTRA2) != 0)
1773 scsirate &= SXFR_ULTRA2;
1774 else
1775 scsirate &= SXFR;
1776
1777 /* now set maxsync based on card capabilities */
1778 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
1779 maxsync = AHC_SYNCRATE_ULTRA2;
1780 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
1781 && maxsync < AHC_SYNCRATE_ULTRA)
1782 maxsync = AHC_SYNCRATE_ULTRA;
1783 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
1784 && maxsync < AHC_SYNCRATE_FAST)
1785 maxsync = AHC_SYNCRATE_FAST;
1786
1787
1788 syncrate = &ahc_syncrates[maxsync];
1789 while (syncrate->rate != NULL) {
1790
1791 if ((ahc->features & AHC_ULTRA2) != 0) {
1792 if (syncrate->sxfr_u2 == 0)
1793 break;
1794 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1795 return (syncrate->period);
1796 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1797 return (syncrate->period);
1798 }
1799 syncrate++;
1800 }
1801 return (0); /* async */
1802 }
1803
1804 /*
1805 * Truncate the given synchronous offset to a value the
1806 * current adapter type and syncrate are capable of.
1807 */
1808 void
1809 ahc_validate_offset(struct ahc_softc *ahc,
1810 struct ahc_initiator_tinfo *tinfo,
1811 struct ahc_syncrate *syncrate,
1812 u_int *offset, int wide, role_t role)
1813 {
1814 u_int maxoffset;
1815
1816 /* Limit offset to what we can do */
1817 if (syncrate == NULL) {
1818 maxoffset = 0;
1819 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1820 maxoffset = MAX_OFFSET_ULTRA2;
1821 } else {
1822 if (wide)
1823 maxoffset = MAX_OFFSET_16BIT;
1824 else
1825 maxoffset = MAX_OFFSET_8BIT;
1826 }
1827 *offset = min(*offset, maxoffset);
1828 if (tinfo != NULL) {
1829 if (role == ROLE_TARGET)
1830 *offset = min(*offset, (u_int)tinfo->user.offset);
1831 else
1832 *offset = min(*offset, (u_int)tinfo->goal.offset);
1833 }
1834 }
1835
1836 /*
1837 * Truncate the given transfer width parameter to a value the
1838 * current adapter type is capable of.
1839 */
1840 void
1841 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1842 u_int *bus_width, role_t role)
1843 {
1844 switch (*bus_width) {
1845 default:
1846 if (ahc->features & AHC_WIDE) {
1847 /* Respond Wide */
1848 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1849 break;
1850 }
1851 /* FALLTHROUGH */
1852 case MSG_EXT_WDTR_BUS_8_BIT:
1853 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1854 break;
1855 }
1856 if (tinfo != NULL) {
1857 if (role == ROLE_TARGET)
1858 *bus_width = min((u_int)tinfo->user.width, *bus_width);
1859 else
1860 *bus_width = min((u_int)tinfo->goal.width, *bus_width);
1861 }
1862 }
1863
1864 /*
1865 * Update the bitmask of targets for which the controller should
1866 * negotiate with at the next convenient oportunity. This currently
1867 * means the next time we send the initial identify messages for
1868 * a new transaction.
1869 */
1870 int
1871 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1872 struct ahc_tmode_tstate *tstate,
1873 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1874 {
1875 u_int auto_negotiate_orig;
1876
1877 auto_negotiate_orig = tstate->auto_negotiate;
1878 if (neg_type == AHC_NEG_ALWAYS) {
1879 /*
1880 * Force our "current" settings to be
1881 * unknown so that unless a bus reset
1882 * occurs the need to renegotiate is
1883 * recorded persistently.
1884 */
1885 if ((ahc->features & AHC_WIDE) != 0)
1886 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1887 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1888 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1889 }
1890 if (tinfo->curr.period != tinfo->goal.period
1891 || tinfo->curr.width != tinfo->goal.width
1892 || tinfo->curr.offset != tinfo->goal.offset
1893 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1894 || (neg_type == AHC_NEG_IF_NON_ASYNC
1895 && (tinfo->goal.offset != 0
1896 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1897 || tinfo->goal.ppr_options != 0)))
1898 tstate->auto_negotiate |= devinfo->target_mask;
1899 else
1900 tstate->auto_negotiate &= ~devinfo->target_mask;
1901
1902 return (auto_negotiate_orig != tstate->auto_negotiate);
1903 }
1904
1905 /*
1906 * Update the user/goal/curr tables of synchronous negotiation
1907 * parameters as well as, in the case of a current or active update,
1908 * any data structures on the host controller. In the case of an
1909 * active update, the specified target is currently talking to us on
1910 * the bus, so the transfer parameter update must take effect
1911 * immediately.
1912 */
1913 void
1914 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1915 struct ahc_syncrate *syncrate, u_int period,
1916 u_int offset, u_int ppr_options, u_int type, int paused)
1917 {
1918 struct ahc_initiator_tinfo *tinfo;
1919 struct ahc_tmode_tstate *tstate;
1920 u_int old_period;
1921 u_int old_offset;
1922 u_int old_ppr;
1923 int active;
1924 int update_needed;
1925
1926 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1927 update_needed = 0;
1928
1929 if (syncrate == NULL) {
1930 period = 0;
1931 offset = 0;
1932 }
1933
1934 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1935 devinfo->target, &tstate);
1936
1937 if ((type & AHC_TRANS_USER) != 0) {
1938 tinfo->user.period = period;
1939 tinfo->user.offset = offset;
1940 tinfo->user.ppr_options = ppr_options;
1941 }
1942
1943 if ((type & AHC_TRANS_GOAL) != 0) {
1944 tinfo->goal.period = period;
1945 tinfo->goal.offset = offset;
1946 tinfo->goal.ppr_options = ppr_options;
1947 }
1948
1949 old_period = tinfo->curr.period;
1950 old_offset = tinfo->curr.offset;
1951 old_ppr = tinfo->curr.ppr_options;
1952
1953 if ((type & AHC_TRANS_CUR) != 0
1954 && (old_period != period
1955 || old_offset != offset
1956 || old_ppr != ppr_options)) {
1957 u_int scsirate;
1958
1959 update_needed++;
1960 scsirate = tinfo->scsirate;
1961 if ((ahc->features & AHC_ULTRA2) != 0) {
1962
1963 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1964 if (syncrate != NULL) {
1965 scsirate |= syncrate->sxfr_u2;
1966 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1967 scsirate |= ENABLE_CRC;
1968 else
1969 scsirate |= SINGLE_EDGE;
1970 }
1971 } else {
1972
1973 scsirate &= ~(SXFR|SOFS);
1974 /*
1975 * Ensure Ultra mode is set properly for
1976 * this target.
1977 */
1978 tstate->ultraenb &= ~devinfo->target_mask;
1979 if (syncrate != NULL) {
1980 if (syncrate->sxfr & ULTRA_SXFR) {
1981 tstate->ultraenb |=
1982 devinfo->target_mask;
1983 }
1984 scsirate |= syncrate->sxfr & SXFR;
1985 scsirate |= offset & SOFS;
1986 }
1987 if (active) {
1988 u_int sxfrctl0;
1989
1990 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1991 sxfrctl0 &= ~FAST20;
1992 if (tstate->ultraenb & devinfo->target_mask)
1993 sxfrctl0 |= FAST20;
1994 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1995 }
1996 }
1997 if (active) {
1998 ahc_outb(ahc, SCSIRATE, scsirate);
1999 if ((ahc->features & AHC_ULTRA2) != 0)
2000 ahc_outb(ahc, SCSIOFFSET, offset);
2001 }
2002
2003 tinfo->scsirate = scsirate;
2004 tinfo->curr.period = period;
2005 tinfo->curr.offset = offset;
2006 tinfo->curr.ppr_options = ppr_options;
2007
2008 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2009 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2010 if (bootverbose) {
2011 if (offset != 0) {
2012 printf("%s: target %d synchronous at %sMHz%s, "
2013 "offset = 0x%x\n", ahc_name(ahc),
2014 devinfo->target, syncrate->rate,
2015 (ppr_options & MSG_EXT_PPR_DT_REQ)
2016 ? " DT" : "", offset);
2017 } else {
2018 printf("%s: target %d using "
2019 "asynchronous transfers\n",
2020 ahc_name(ahc), devinfo->target);
2021 }
2022 }
2023 }
2024
2025 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2026 tinfo, AHC_NEG_TO_GOAL);
2027
2028 if (update_needed)
2029 ahc_update_pending_scbs(ahc);
2030 }
2031
2032 /*
2033 * Update the user/goal/curr tables of wide negotiation
2034 * parameters as well as, in the case of a current or active update,
2035 * any data structures on the host controller. In the case of an
2036 * active update, the specified target is currently talking to us on
2037 * the bus, so the transfer parameter update must take effect
2038 * immediately.
2039 */
2040 void
2041 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2042 u_int width, u_int type, int paused)
2043 {
2044 struct ahc_initiator_tinfo *tinfo;
2045 struct ahc_tmode_tstate *tstate;
2046 u_int oldwidth;
2047 int active;
2048 int update_needed;
2049
2050 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2051 update_needed = 0;
2052 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2053 devinfo->target, &tstate);
2054
2055 if ((type & AHC_TRANS_USER) != 0)
2056 tinfo->user.width = width;
2057
2058 if ((type & AHC_TRANS_GOAL) != 0)
2059 tinfo->goal.width = width;
2060
2061 oldwidth = tinfo->curr.width;
2062 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2063 u_int scsirate;
2064
2065 update_needed++;
2066 scsirate = tinfo->scsirate;
2067 scsirate &= ~WIDEXFER;
2068 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2069 scsirate |= WIDEXFER;
2070
2071 tinfo->scsirate = scsirate;
2072
2073 if (active)
2074 ahc_outb(ahc, SCSIRATE, scsirate);
2075
2076 tinfo->curr.width = width;
2077
2078 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2079 CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2080 if (bootverbose) {
2081 printf("%s: target %d using %dbit transfers\n",
2082 ahc_name(ahc), devinfo->target,
2083 8 * (0x01 << width));
2084 }
2085 }
2086
2087 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2088 tinfo, AHC_NEG_TO_GOAL);
2089 if (update_needed)
2090 ahc_update_pending_scbs(ahc);
2091 }
2092
2093 /*
2094 * Update the current state of tagged queuing for a given target.
2095 */
2096 static void
2097 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
2098 struct ahc_devinfo *devinfo, ahc_queue_alg alg)
2099 {
2100 struct scsi_device *sdev = cmd->device;
2101
2102 ahc_platform_set_tags(ahc, sdev, devinfo, alg);
2103 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2104 devinfo->lun, AC_TRANSFER_NEG);
2105 }
2106
2107 /*
2108 * When the transfer settings for a connection change, update any
2109 * in-transit SCBs to contain the new data so the hardware will
2110 * be set correctly during future (re)selections.
2111 */
2112 static void
2113 ahc_update_pending_scbs(struct ahc_softc *ahc)
2114 {
2115 struct scb *pending_scb;
2116 int pending_scb_count;
2117 int i;
2118 int paused;
2119 u_int saved_scbptr;
2120
2121 /*
2122 * Traverse the pending SCB list and ensure that all of the
2123 * SCBs there have the proper settings.
2124 */
2125 pending_scb_count = 0;
2126 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2127 struct ahc_devinfo devinfo;
2128 struct hardware_scb *pending_hscb;
2129 struct ahc_initiator_tinfo *tinfo;
2130 struct ahc_tmode_tstate *tstate;
2131
2132 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2133 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2134 devinfo.our_scsiid,
2135 devinfo.target, &tstate);
2136 pending_hscb = pending_scb->hscb;
2137 pending_hscb->control &= ~ULTRAENB;
2138 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2139 pending_hscb->control |= ULTRAENB;
2140 pending_hscb->scsirate = tinfo->scsirate;
2141 pending_hscb->scsioffset = tinfo->curr.offset;
2142 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2143 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2144 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2145 pending_hscb->control &= ~MK_MESSAGE;
2146 }
2147 ahc_sync_scb(ahc, pending_scb,
2148 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2149 pending_scb_count++;
2150 }
2151
2152 if (pending_scb_count == 0)
2153 return;
2154
2155 if (ahc_is_paused(ahc)) {
2156 paused = 1;
2157 } else {
2158 paused = 0;
2159 ahc_pause(ahc);
2160 }
2161
2162 saved_scbptr = ahc_inb(ahc, SCBPTR);
2163 /* Ensure that the hscbs down on the card match the new information */
2164 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2165 struct hardware_scb *pending_hscb;
2166 u_int control;
2167 u_int scb_tag;
2168
2169 ahc_outb(ahc, SCBPTR, i);
2170 scb_tag = ahc_inb(ahc, SCB_TAG);
2171 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2172 if (pending_scb == NULL)
2173 continue;
2174
2175 pending_hscb = pending_scb->hscb;
2176 control = ahc_inb(ahc, SCB_CONTROL);
2177 control &= ~(ULTRAENB|MK_MESSAGE);
2178 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2179 ahc_outb(ahc, SCB_CONTROL, control);
2180 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2181 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2182 }
2183 ahc_outb(ahc, SCBPTR, saved_scbptr);
2184
2185 if (paused == 0)
2186 ahc_unpause(ahc);
2187 }
2188
2189 /**************************** Pathing Information *****************************/
2190 static void
2191 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2192 {
2193 u_int saved_scsiid;
2194 role_t role;
2195 int our_id;
2196
2197 if (ahc_inb(ahc, SSTAT0) & TARGET)
2198 role = ROLE_TARGET;
2199 else
2200 role = ROLE_INITIATOR;
2201
2202 if (role == ROLE_TARGET
2203 && (ahc->features & AHC_MULTI_TID) != 0
2204 && (ahc_inb(ahc, SEQ_FLAGS)
2205 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2206 /* We were selected, so pull our id from TARGIDIN */
2207 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2208 } else if ((ahc->features & AHC_ULTRA2) != 0)
2209 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2210 else
2211 our_id = ahc_inb(ahc, SCSIID) & OID;
2212
2213 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2214 ahc_compile_devinfo(devinfo,
2215 our_id,
2216 SCSIID_TARGET(ahc, saved_scsiid),
2217 ahc_inb(ahc, SAVED_LUN),
2218 SCSIID_CHANNEL(ahc, saved_scsiid),
2219 role);
2220 }
2221
2222 struct ahc_phase_table_entry*
2223 ahc_lookup_phase_entry(int phase)
2224 {
2225 struct ahc_phase_table_entry *entry;
2226 struct ahc_phase_table_entry *last_entry;
2227
2228 /*
2229 * num_phases doesn't include the default entry which
2230 * will be returned if the phase doesn't match.
2231 */
2232 last_entry = &ahc_phase_table[num_phases];
2233 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2234 if (phase == entry->phase)
2235 break;
2236 }
2237 return (entry);
2238 }
2239
2240 void
2241 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2242 u_int lun, char channel, role_t role)
2243 {
2244 devinfo->our_scsiid = our_id;
2245 devinfo->target = target;
2246 devinfo->lun = lun;
2247 devinfo->target_offset = target;
2248 devinfo->channel = channel;
2249 devinfo->role = role;
2250 if (channel == 'B')
2251 devinfo->target_offset += 8;
2252 devinfo->target_mask = (0x01 << devinfo->target_offset);
2253 }
2254
2255 void
2256 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2257 {
2258 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2259 devinfo->target, devinfo->lun);
2260 }
2261
2262 static void
2263 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2264 struct scb *scb)
2265 {
2266 role_t role;
2267 int our_id;
2268
2269 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2270 role = ROLE_INITIATOR;
2271 if ((scb->flags & SCB_TARGET_SCB) != 0)
2272 role = ROLE_TARGET;
2273 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2274 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2275 }
2276
2277
2278 /************************ Message Phase Processing ****************************/
2279 static void
2280 ahc_assert_atn(struct ahc_softc *ahc)
2281 {
2282 u_int scsisigo;
2283
2284 scsisigo = ATNO;
2285 if ((ahc->features & AHC_DT) == 0)
2286 scsisigo |= ahc_inb(ahc, SCSISIGI);
2287 ahc_outb(ahc, SCSISIGO, scsisigo);
2288 }
2289
2290 /*
2291 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2292 * or enters the initial message out phase, we are interrupted. Fill our
2293 * outgoing message buffer with the appropriate message and beging handing
2294 * the message phase(s) manually.
2295 */
2296 static void
2297 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2298 struct scb *scb)
2299 {
2300 /*
2301 * To facilitate adding multiple messages together,
2302 * each routine should increment the index and len
2303 * variables instead of setting them explicitly.
2304 */
2305 ahc->msgout_index = 0;
2306 ahc->msgout_len = 0;
2307
2308 if ((scb->flags & SCB_DEVICE_RESET) == 0
2309 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2310 u_int identify_msg;
2311
2312 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2313 if ((scb->hscb->control & DISCENB) != 0)
2314 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2315 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2316 ahc->msgout_len++;
2317
2318 if ((scb->hscb->control & TAG_ENB) != 0) {
2319 ahc->msgout_buf[ahc->msgout_index++] =
2320 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2321 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2322 ahc->msgout_len += 2;
2323 }
2324 }
2325
2326 if (scb->flags & SCB_DEVICE_RESET) {
2327 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2328 ahc->msgout_len++;
2329 ahc_print_path(ahc, scb);
2330 printf("Bus Device Reset Message Sent\n");
2331 /*
2332 * Clear our selection hardware in advance of
2333 * the busfree. We may have an entry in the waiting
2334 * Q for this target, and we don't want to go about
2335 * selecting while we handle the busfree and blow it
2336 * away.
2337 */
2338 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2339 } else if ((scb->flags & SCB_ABORT) != 0) {
2340 if ((scb->hscb->control & TAG_ENB) != 0)
2341 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2342 else
2343 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2344 ahc->msgout_len++;
2345 ahc_print_path(ahc, scb);
2346 printf("Abort%s Message Sent\n",
2347 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2348 /*
2349 * Clear our selection hardware in advance of
2350 * the busfree. We may have an entry in the waiting
2351 * Q for this target, and we don't want to go about
2352 * selecting while we handle the busfree and blow it
2353 * away.
2354 */
2355 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2356 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2357 ahc_build_transfer_msg(ahc, devinfo);
2358 } else {
2359 printf("ahc_intr: AWAITING_MSG for an SCB that "
2360 "does not have a waiting message\n");
2361 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2362 devinfo->target_mask);
2363 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2364 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2365 ahc_inb(ahc, MSG_OUT), scb->flags);
2366 }
2367
2368 /*
2369 * Clear the MK_MESSAGE flag from the SCB so we aren't
2370 * asked to send this message again.
2371 */
2372 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2373 scb->hscb->control &= ~MK_MESSAGE;
2374 ahc->msgout_index = 0;
2375 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2376 }
2377
2378 /*
2379 * Build an appropriate transfer negotiation message for the
2380 * currently active target.
2381 */
2382 static void
2383 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2384 {
2385 /*
2386 * We need to initiate transfer negotiations.
2387 * If our current and goal settings are identical,
2388 * we want to renegotiate due to a check condition.
2389 */
2390 struct ahc_initiator_tinfo *tinfo;
2391 struct ahc_tmode_tstate *tstate;
2392 struct ahc_syncrate *rate;
2393 int dowide;
2394 int dosync;
2395 int doppr;
2396 u_int period;
2397 u_int ppr_options;
2398 u_int offset;
2399
2400 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2401 devinfo->target, &tstate);
2402 /*
2403 * Filter our period based on the current connection.
2404 * If we can't perform DT transfers on this segment (not in LVD
2405 * mode for instance), then our decision to issue a PPR message
2406 * may change.
2407 */
2408 period = tinfo->goal.period;
2409 offset = tinfo->goal.offset;
2410 ppr_options = tinfo->goal.ppr_options;
2411 /* Target initiated PPR is not allowed in the SCSI spec */
2412 if (devinfo->role == ROLE_TARGET)
2413 ppr_options = 0;
2414 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2415 &ppr_options, devinfo->role);
2416 dowide = tinfo->curr.width != tinfo->goal.width;
2417 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2418 /*
2419 * Only use PPR if we have options that need it, even if the device
2420 * claims to support it. There might be an expander in the way
2421 * that doesn't.
2422 */
2423 doppr = ppr_options != 0;
2424
2425 if (!dowide && !dosync && !doppr) {
2426 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2427 dosync = tinfo->goal.offset != 0;
2428 }
2429
2430 if (!dowide && !dosync && !doppr) {
2431 /*
2432 * Force async with a WDTR message if we have a wide bus,
2433 * or just issue an SDTR with a 0 offset.
2434 */
2435 if ((ahc->features & AHC_WIDE) != 0)
2436 dowide = 1;
2437 else
2438 dosync = 1;
2439
2440 if (bootverbose) {
2441 ahc_print_devinfo(ahc, devinfo);
2442 printf("Ensuring async\n");
2443 }
2444 }
2445
2446 /* Target initiated PPR is not allowed in the SCSI spec */
2447 if (devinfo->role == ROLE_TARGET)
2448 doppr = 0;
2449
2450 /*
2451 * Both the PPR message and SDTR message require the
2452 * goal syncrate to be limited to what the target device
2453 * is capable of handling (based on whether an LVD->SE
2454 * expander is on the bus), so combine these two cases.
2455 * Regardless, guarantee that if we are using WDTR and SDTR
2456 * messages that WDTR comes first.
2457 */
2458 if (doppr || (dosync && !dowide)) {
2459
2460 offset = tinfo->goal.offset;
2461 ahc_validate_offset(ahc, tinfo, rate, &offset,
2462 doppr ? tinfo->goal.width
2463 : tinfo->curr.width,
2464 devinfo->role);
2465 if (doppr) {
2466 ahc_construct_ppr(ahc, devinfo, period, offset,
2467 tinfo->goal.width, ppr_options);
2468 } else {
2469 ahc_construct_sdtr(ahc, devinfo, period, offset);
2470 }
2471 } else {
2472 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2473 }
2474 }
2475
2476 /*
2477 * Build a synchronous negotiation message in our message
2478 * buffer based on the input parameters.
2479 */
2480 static void
2481 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2482 u_int period, u_int offset)
2483 {
2484 if (offset == 0)
2485 period = AHC_ASYNC_XFER_PERIOD;
2486 ahc->msgout_index += spi_populate_sync_msg(
2487 ahc->msgout_buf + ahc->msgout_index, period, offset);
2488 ahc->msgout_len += 5;
2489 if (bootverbose) {
2490 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2491 ahc_name(ahc), devinfo->channel, devinfo->target,
2492 devinfo->lun, period, offset);
2493 }
2494 }
2495
2496 /*
2497 * Build a wide negotiation message in our message
2498 * buffer based on the input parameters.
2499 */
2500 static void
2501 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2502 u_int bus_width)
2503 {
2504 ahc->msgout_index += spi_populate_width_msg(
2505 ahc->msgout_buf + ahc->msgout_index, bus_width);
2506 ahc->msgout_len += 4;
2507 if (bootverbose) {
2508 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2509 ahc_name(ahc), devinfo->channel, devinfo->target,
2510 devinfo->lun, bus_width);
2511 }
2512 }
2513
2514 /*
2515 * Build a parallel protocol request message in our message
2516 * buffer based on the input parameters.
2517 */
2518 static void
2519 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2520 u_int period, u_int offset, u_int bus_width,
2521 u_int ppr_options)
2522 {
2523 if (offset == 0)
2524 period = AHC_ASYNC_XFER_PERIOD;
2525 ahc->msgout_index += spi_populate_ppr_msg(
2526 ahc->msgout_buf + ahc->msgout_index, period, offset,
2527 bus_width, ppr_options);
2528 ahc->msgout_len += 8;
2529 if (bootverbose) {
2530 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2531 "offset %x, ppr_options %x\n", ahc_name(ahc),
2532 devinfo->channel, devinfo->target, devinfo->lun,
2533 bus_width, period, offset, ppr_options);
2534 }
2535 }
2536
2537 /*
2538 * Clear any active message state.
2539 */
2540 static void
2541 ahc_clear_msg_state(struct ahc_softc *ahc)
2542 {
2543 ahc->msgout_len = 0;
2544 ahc->msgin_index = 0;
2545 ahc->msg_type = MSG_TYPE_NONE;
2546 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2547 /*
2548 * The target didn't care to respond to our
2549 * message request, so clear ATN.
2550 */
2551 ahc_outb(ahc, CLRSINT1, CLRATNO);
2552 }
2553 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2554 ahc_outb(ahc, SEQ_FLAGS2,
2555 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2556 }
2557
2558 static void
2559 ahc_handle_proto_violation(struct ahc_softc *ahc)
2560 {
2561 struct ahc_devinfo devinfo;
2562 struct scb *scb;
2563 u_int scbid;
2564 u_int seq_flags;
2565 u_int curphase;
2566 u_int lastphase;
2567 int found;
2568
2569 ahc_fetch_devinfo(ahc, &devinfo);
2570 scbid = ahc_inb(ahc, SCB_TAG);
2571 scb = ahc_lookup_scb(ahc, scbid);
2572 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2573 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2574 lastphase = ahc_inb(ahc, LASTPHASE);
2575 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2576
2577 /*
2578 * The reconnecting target either did not send an
2579 * identify message, or did, but we didn't find an SCB
2580 * to match.
2581 */
2582 ahc_print_devinfo(ahc, &devinfo);
2583 printf("Target did not send an IDENTIFY message. "
2584 "LASTPHASE = 0x%x.\n", lastphase);
2585 scb = NULL;
2586 } else if (scb == NULL) {
2587 /*
2588 * We don't seem to have an SCB active for this
2589 * transaction. Print an error and reset the bus.
2590 */
2591 ahc_print_devinfo(ahc, &devinfo);
2592 printf("No SCB found during protocol violation\n");
2593 goto proto_violation_reset;
2594 } else {
2595 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2596 if ((seq_flags & NO_CDB_SENT) != 0) {
2597 ahc_print_path(ahc, scb);
2598 printf("No or incomplete CDB sent to device.\n");
2599 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2600 /*
2601 * The target never bothered to provide status to
2602 * us prior to completing the command. Since we don't
2603 * know the disposition of this command, we must attempt
2604 * to abort it. Assert ATN and prepare to send an abort
2605 * message.
2606 */
2607 ahc_print_path(ahc, scb);
2608 printf("Completed command without status.\n");
2609 } else {
2610 ahc_print_path(ahc, scb);
2611 printf("Unknown protocol violation.\n");
2612 ahc_dump_card_state(ahc);
2613 }
2614 }
2615 if ((lastphase & ~P_DATAIN_DT) == 0
2616 || lastphase == P_COMMAND) {
2617 proto_violation_reset:
2618 /*
2619 * Target either went directly to data/command
2620 * phase or didn't respond to our ATN.
2621 * The only safe thing to do is to blow
2622 * it away with a bus reset.
2623 */
2624 found = ahc_reset_channel(ahc, 'A', TRUE);
2625 printf("%s: Issued Channel %c Bus Reset. "
2626 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2627 } else {
2628 /*
2629 * Leave the selection hardware off in case
2630 * this abort attempt will affect yet to
2631 * be sent commands.
2632 */
2633 ahc_outb(ahc, SCSISEQ,
2634 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2635 ahc_assert_atn(ahc);
2636 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2637 if (scb == NULL) {
2638 ahc_print_devinfo(ahc, &devinfo);
2639 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2640 ahc->msgout_len = 1;
2641 ahc->msgout_index = 0;
2642 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2643 } else {
2644 ahc_print_path(ahc, scb);
2645 scb->flags |= SCB_ABORT;
2646 }
2647 printf("Protocol violation %s. Attempting to abort.\n",
2648 ahc_lookup_phase_entry(curphase)->phasemsg);
2649 }
2650 }
2651
2652 /*
2653 * Manual message loop handler.
2654 */
2655 static void
2656 ahc_handle_message_phase(struct ahc_softc *ahc)
2657 {
2658 struct ahc_devinfo devinfo;
2659 u_int bus_phase;
2660 int end_session;
2661
2662 ahc_fetch_devinfo(ahc, &devinfo);
2663 end_session = FALSE;
2664 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2665
2666 reswitch:
2667 switch (ahc->msg_type) {
2668 case MSG_TYPE_INITIATOR_MSGOUT:
2669 {
2670 int lastbyte;
2671 int phasemis;
2672 int msgdone;
2673
2674 if (ahc->msgout_len == 0)
2675 panic("HOST_MSG_LOOP interrupt with no active message");
2676
2677 #ifdef AHC_DEBUG
2678 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2679 ahc_print_devinfo(ahc, &devinfo);
2680 printf("INITIATOR_MSG_OUT");
2681 }
2682 #endif
2683 phasemis = bus_phase != P_MESGOUT;
2684 if (phasemis) {
2685 #ifdef AHC_DEBUG
2686 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2687 printf(" PHASEMIS %s\n",
2688 ahc_lookup_phase_entry(bus_phase)
2689 ->phasemsg);
2690 }
2691 #endif
2692 if (bus_phase == P_MESGIN) {
2693 /*
2694 * Change gears and see if
2695 * this messages is of interest to
2696 * us or should be passed back to
2697 * the sequencer.
2698 */
2699 ahc_outb(ahc, CLRSINT1, CLRATNO);
2700 ahc->send_msg_perror = FALSE;
2701 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2702 ahc->msgin_index = 0;
2703 goto reswitch;
2704 }
2705 end_session = TRUE;
2706 break;
2707 }
2708
2709 if (ahc->send_msg_perror) {
2710 ahc_outb(ahc, CLRSINT1, CLRATNO);
2711 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2712 #ifdef AHC_DEBUG
2713 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2714 printf(" byte 0x%x\n", ahc->send_msg_perror);
2715 #endif
2716 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2717 break;
2718 }
2719
2720 msgdone = ahc->msgout_index == ahc->msgout_len;
2721 if (msgdone) {
2722 /*
2723 * The target has requested a retry.
2724 * Re-assert ATN, reset our message index to
2725 * 0, and try again.
2726 */
2727 ahc->msgout_index = 0;
2728 ahc_assert_atn(ahc);
2729 }
2730
2731 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2732 if (lastbyte) {
2733 /* Last byte is signified by dropping ATN */
2734 ahc_outb(ahc, CLRSINT1, CLRATNO);
2735 }
2736
2737 /*
2738 * Clear our interrupt status and present
2739 * the next byte on the bus.
2740 */
2741 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2742 #ifdef AHC_DEBUG
2743 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2744 printf(" byte 0x%x\n",
2745 ahc->msgout_buf[ahc->msgout_index]);
2746 #endif
2747 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2748 break;
2749 }
2750 case MSG_TYPE_INITIATOR_MSGIN:
2751 {
2752 int phasemis;
2753 int message_done;
2754
2755 #ifdef AHC_DEBUG
2756 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2757 ahc_print_devinfo(ahc, &devinfo);
2758 printf("INITIATOR_MSG_IN");
2759 }
2760 #endif
2761 phasemis = bus_phase != P_MESGIN;
2762 if (phasemis) {
2763 #ifdef AHC_DEBUG
2764 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2765 printf(" PHASEMIS %s\n",
2766 ahc_lookup_phase_entry(bus_phase)
2767 ->phasemsg);
2768 }
2769 #endif
2770 ahc->msgin_index = 0;
2771 if (bus_phase == P_MESGOUT
2772 && (ahc->send_msg_perror == TRUE
2773 || (ahc->msgout_len != 0
2774 && ahc->msgout_index == 0))) {
2775 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2776 goto reswitch;
2777 }
2778 end_session = TRUE;
2779 break;
2780 }
2781
2782 /* Pull the byte in without acking it */
2783 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2784 #ifdef AHC_DEBUG
2785 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2786 printf(" byte 0x%x\n",
2787 ahc->msgin_buf[ahc->msgin_index]);
2788 #endif
2789
2790 message_done = ahc_parse_msg(ahc, &devinfo);
2791
2792 if (message_done) {
2793 /*
2794 * Clear our incoming message buffer in case there
2795 * is another message following this one.
2796 */
2797 ahc->msgin_index = 0;
2798
2799 /*
2800 * If this message illicited a response,
2801 * assert ATN so the target takes us to the
2802 * message out phase.
2803 */
2804 if (ahc->msgout_len != 0) {
2805 #ifdef AHC_DEBUG
2806 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2807 ahc_print_devinfo(ahc, &devinfo);
2808 printf("Asserting ATN for response\n");
2809 }
2810 #endif
2811 ahc_assert_atn(ahc);
2812 }
2813 } else
2814 ahc->msgin_index++;
2815
2816 if (message_done == MSGLOOP_TERMINATED) {
2817 end_session = TRUE;
2818 } else {
2819 /* Ack the byte */
2820 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2821 ahc_inb(ahc, SCSIDATL);
2822 }
2823 break;
2824 }
2825 case MSG_TYPE_TARGET_MSGIN:
2826 {
2827 int msgdone;
2828 int msgout_request;
2829
2830 if (ahc->msgout_len == 0)
2831 panic("Target MSGIN with no active message");
2832
2833 /*
2834 * If we interrupted a mesgout session, the initiator
2835 * will not know this until our first REQ. So, we
2836 * only honor mesgout requests after we've sent our
2837 * first byte.
2838 */
2839 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2840 && ahc->msgout_index > 0)
2841 msgout_request = TRUE;
2842 else
2843 msgout_request = FALSE;
2844
2845 if (msgout_request) {
2846
2847 /*
2848 * Change gears and see if
2849 * this messages is of interest to
2850 * us or should be passed back to
2851 * the sequencer.
2852 */
2853 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2854 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2855 ahc->msgin_index = 0;
2856 /* Dummy read to REQ for first byte */
2857 ahc_inb(ahc, SCSIDATL);
2858 ahc_outb(ahc, SXFRCTL0,
2859 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2860 break;
2861 }
2862
2863 msgdone = ahc->msgout_index == ahc->msgout_len;
2864 if (msgdone) {
2865 ahc_outb(ahc, SXFRCTL0,
2866 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2867 end_session = TRUE;
2868 break;
2869 }
2870
2871 /*
2872 * Present the next byte on the bus.
2873 */
2874 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2875 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2876 break;
2877 }
2878 case MSG_TYPE_TARGET_MSGOUT:
2879 {
2880 int lastbyte;
2881 int msgdone;
2882
2883 /*
2884 * The initiator signals that this is
2885 * the last byte by dropping ATN.
2886 */
2887 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2888
2889 /*
2890 * Read the latched byte, but turn off SPIOEN first
2891 * so that we don't inadvertently cause a REQ for the
2892 * next byte.
2893 */
2894 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2895 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2896 msgdone = ahc_parse_msg(ahc, &devinfo);
2897 if (msgdone == MSGLOOP_TERMINATED) {
2898 /*
2899 * The message is *really* done in that it caused
2900 * us to go to bus free. The sequencer has already
2901 * been reset at this point, so pull the ejection
2902 * handle.
2903 */
2904 return;
2905 }
2906
2907 ahc->msgin_index++;
2908
2909 /*
2910 * XXX Read spec about initiator dropping ATN too soon
2911 * and use msgdone to detect it.
2912 */
2913 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2914 ahc->msgin_index = 0;
2915
2916 /*
2917 * If this message illicited a response, transition
2918 * to the Message in phase and send it.
2919 */
2920 if (ahc->msgout_len != 0) {
2921 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2922 ahc_outb(ahc, SXFRCTL0,
2923 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2924 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2925 ahc->msgin_index = 0;
2926 break;
2927 }
2928 }
2929
2930 if (lastbyte)
2931 end_session = TRUE;
2932 else {
2933 /* Ask for the next byte. */
2934 ahc_outb(ahc, SXFRCTL0,
2935 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2936 }
2937
2938 break;
2939 }
2940 default:
2941 panic("Unknown REQINIT message type");
2942 }
2943
2944 if (end_session) {
2945 ahc_clear_msg_state(ahc);
2946 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2947 } else
2948 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2949 }
2950
2951 /*
2952 * See if we sent a particular extended message to the target.
2953 * If "full" is true, return true only if the target saw the full
2954 * message. If "full" is false, return true if the target saw at
2955 * least the first byte of the message.
2956 */
2957 static int
2958 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2959 {
2960 int found;
2961 u_int index;
2962
2963 found = FALSE;
2964 index = 0;
2965
2966 while (index < ahc->msgout_len) {
2967 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2968 u_int end_index;
2969
2970 end_index = index + 1 + ahc->msgout_buf[index + 1];
2971 if (ahc->msgout_buf[index+2] == msgval
2972 && type == AHCMSG_EXT) {
2973
2974 if (full) {
2975 if (ahc->msgout_index > end_index)
2976 found = TRUE;
2977 } else if (ahc->msgout_index > index)
2978 found = TRUE;
2979 }
2980 index = end_index;
2981 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2982 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2983
2984 /* Skip tag type and tag id or residue param*/
2985 index += 2;
2986 } else {
2987 /* Single byte message */
2988 if (type == AHCMSG_1B
2989 && ahc->msgout_buf[index] == msgval
2990 && ahc->msgout_index > index)
2991 found = TRUE;
2992 index++;
2993 }
2994
2995 if (found)
2996 break;
2997 }
2998 return (found);
2999 }
3000
3001 /*
3002 * Wait for a complete incoming message, parse it, and respond accordingly.
3003 */
3004 static int
3005 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3006 {
3007 struct ahc_initiator_tinfo *tinfo;
3008 struct ahc_tmode_tstate *tstate;
3009 int reject;
3010 int done;
3011 int response;
3012 u_int targ_scsirate;
3013
3014 done = MSGLOOP_IN_PROG;
3015 response = FALSE;
3016 reject = FALSE;
3017 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3018 devinfo->target, &tstate);
3019 targ_scsirate = tinfo->scsirate;
3020
3021 /*
3022 * Parse as much of the message as is available,
3023 * rejecting it if we don't support it. When
3024 * the entire message is available and has been
3025 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3026 * that we have parsed an entire message.
3027 *
3028 * In the case of extended messages, we accept the length
3029 * byte outright and perform more checking once we know the
3030 * extended message type.
3031 */
3032 switch (ahc->msgin_buf[0]) {
3033 case MSG_DISCONNECT:
3034 case MSG_SAVEDATAPOINTER:
3035 case MSG_CMDCOMPLETE:
3036 case MSG_RESTOREPOINTERS:
3037 case MSG_IGN_WIDE_RESIDUE:
3038 /*
3039 * End our message loop as these are messages
3040 * the sequencer handles on its own.
3041 */
3042 done = MSGLOOP_TERMINATED;
3043 break;
3044 case MSG_MESSAGE_REJECT:
3045 response = ahc_handle_msg_reject(ahc, devinfo);
3046 /* FALLTHROUGH */
3047 case MSG_NOOP:
3048 done = MSGLOOP_MSGCOMPLETE;
3049 break;
3050 case MSG_EXTENDED:
3051 {
3052 /* Wait for enough of the message to begin validation */
3053 if (ahc->msgin_index < 2)
3054 break;
3055 switch (ahc->msgin_buf[2]) {
3056 case MSG_EXT_SDTR:
3057 {
3058 struct ahc_syncrate *syncrate;
3059 u_int period;
3060 u_int ppr_options;
3061 u_int offset;
3062 u_int saved_offset;
3063
3064 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3065 reject = TRUE;
3066 break;
3067 }
3068
3069 /*
3070 * Wait until we have both args before validating
3071 * and acting on this message.
3072 *
3073 * Add one to MSG_EXT_SDTR_LEN to account for
3074 * the extended message preamble.
3075 */
3076 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3077 break;
3078
3079 period = ahc->msgin_buf[3];
3080 ppr_options = 0;
3081 saved_offset = offset = ahc->msgin_buf[4];
3082 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3083 &ppr_options,
3084 devinfo->role);
3085 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3086 targ_scsirate & WIDEXFER,
3087 devinfo->role);
3088 if (bootverbose) {
3089 printf("(%s:%c:%d:%d): Received "
3090 "SDTR period %x, offset %x\n\t"
3091 "Filtered to period %x, offset %x\n",
3092 ahc_name(ahc), devinfo->channel,
3093 devinfo->target, devinfo->lun,
3094 ahc->msgin_buf[3], saved_offset,
3095 period, offset);
3096 }
3097 ahc_set_syncrate(ahc, devinfo,
3098 syncrate, period,
3099 offset, ppr_options,
3100 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3101 /*paused*/TRUE);
3102
3103 /*
3104 * See if we initiated Sync Negotiation
3105 * and didn't have to fall down to async
3106 * transfers.
3107 */
3108 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3109 /* We started it */
3110 if (saved_offset != offset) {
3111 /* Went too low - force async */
3112 reject = TRUE;
3113 }
3114 } else {
3115 /*
3116 * Send our own SDTR in reply
3117 */
3118 if (bootverbose
3119 && devinfo->role == ROLE_INITIATOR) {
3120 printf("(%s:%c:%d:%d): Target "
3121 "Initiated SDTR\n",
3122 ahc_name(ahc), devinfo->channel,
3123 devinfo->target, devinfo->lun);
3124 }
3125 ahc->msgout_index = 0;
3126 ahc->msgout_len = 0;
3127 ahc_construct_sdtr(ahc, devinfo,
3128 period, offset);
3129 ahc->msgout_index = 0;
3130 response = TRUE;
3131 }
3132 done = MSGLOOP_MSGCOMPLETE;
3133 break;
3134 }
3135 case MSG_EXT_WDTR:
3136 {
3137 u_int bus_width;
3138 u_int saved_width;
3139 u_int sending_reply;
3140
3141 sending_reply = FALSE;
3142 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3143 reject = TRUE;
3144 break;
3145 }
3146
3147 /*
3148 * Wait until we have our arg before validating
3149 * and acting on this message.
3150 *
3151 * Add one to MSG_EXT_WDTR_LEN to account for
3152 * the extended message preamble.
3153 */
3154 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3155 break;
3156
3157 bus_width = ahc->msgin_buf[3];
3158 saved_width = bus_width;
3159 ahc_validate_width(ahc, tinfo, &bus_width,
3160 devinfo->role);
3161 if (bootverbose) {
3162 printf("(%s:%c:%d:%d): Received WDTR "
3163 "%x filtered to %x\n",
3164 ahc_name(ahc), devinfo->channel,
3165 devinfo->target, devinfo->lun,
3166 saved_width, bus_width);
3167 }
3168
3169 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3170 /*
3171 * Don't send a WDTR back to the
3172 * target, since we asked first.
3173 * If the width went higher than our
3174 * request, reject it.
3175 */
3176 if (saved_width > bus_width) {
3177 reject = TRUE;
3178 printf("(%s:%c:%d:%d): requested %dBit "
3179 "transfers. Rejecting...\n",
3180 ahc_name(ahc), devinfo->channel,
3181 devinfo->target, devinfo->lun,
3182 8 * (0x01 << bus_width));
3183 bus_width = 0;
3184 }
3185 } else {
3186 /*
3187 * Send our own WDTR in reply
3188 */
3189 if (bootverbose
3190 && devinfo->role == ROLE_INITIATOR) {
3191 printf("(%s:%c:%d:%d): Target "
3192 "Initiated WDTR\n",
3193 ahc_name(ahc), devinfo->channel,
3194 devinfo->target, devinfo->lun);
3195 }
3196 ahc->msgout_index = 0;
3197 ahc->msgout_len = 0;
3198 ahc_construct_wdtr(ahc, devinfo, bus_width);
3199 ahc->msgout_index = 0;
3200 response = TRUE;
3201 sending_reply = TRUE;
3202 }
3203 /*
3204 * After a wide message, we are async, but
3205 * some devices don't seem to honor this portion
3206 * of the spec. Force a renegotiation of the
3207 * sync component of our transfer agreement even
3208 * if our goal is async. By updating our width
3209 * after forcing the negotiation, we avoid
3210 * renegotiating for width.
3211 */
3212 ahc_update_neg_request(ahc, devinfo, tstate,
3213 tinfo, AHC_NEG_ALWAYS);
3214 ahc_set_width(ahc, devinfo, bus_width,
3215 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3216 /*paused*/TRUE);
3217 if (sending_reply == FALSE && reject == FALSE) {
3218
3219 /*
3220 * We will always have an SDTR to send.
3221 */
3222 ahc->msgout_index = 0;
3223 ahc->msgout_len = 0;
3224 ahc_build_transfer_msg(ahc, devinfo);
3225 ahc->msgout_index = 0;
3226 response = TRUE;
3227 }
3228 done = MSGLOOP_MSGCOMPLETE;
3229 break;
3230 }
3231 case MSG_EXT_PPR:
3232 {
3233 struct ahc_syncrate *syncrate;
3234 u_int period;
3235 u_int offset;
3236 u_int bus_width;
3237 u_int ppr_options;
3238 u_int saved_width;
3239 u_int saved_offset;
3240 u_int saved_ppr_options;
3241
3242 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3243 reject = TRUE;
3244 break;
3245 }
3246
3247 /*
3248 * Wait until we have all args before validating
3249 * and acting on this message.
3250 *
3251 * Add one to MSG_EXT_PPR_LEN to account for
3252 * the extended message preamble.
3253 */
3254 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3255 break;
3256
3257 period = ahc->msgin_buf[3];
3258 offset = ahc->msgin_buf[5];
3259 bus_width = ahc->msgin_buf[6];
3260 saved_width = bus_width;
3261 ppr_options = ahc->msgin_buf[7];
3262 /*
3263 * According to the spec, a DT only
3264 * period factor with no DT option
3265 * set implies async.
3266 */
3267 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3268 && period == 9)
3269 offset = 0;
3270 saved_ppr_options = ppr_options;
3271 saved_offset = offset;
3272
3273 /*
3274 * Mask out any options we don't support
3275 * on any controller. Transfer options are
3276 * only available if we are negotiating wide.
3277 */
3278 ppr_options &= MSG_EXT_PPR_DT_REQ;
3279 if (bus_width == 0)
3280 ppr_options = 0;
3281
3282 ahc_validate_width(ahc, tinfo, &bus_width,
3283 devinfo->role);
3284 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3285 &ppr_options,
3286 devinfo->role);
3287 ahc_validate_offset(ahc, tinfo, syncrate,
3288 &offset, bus_width,
3289 devinfo->role);
3290
3291 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3292 /*
3293 * If we are unable to do any of the
3294 * requested options (we went too low),
3295 * then we'll have to reject the message.
3296 */
3297 if (saved_width > bus_width
3298 || saved_offset != offset
3299 || saved_ppr_options != ppr_options) {
3300 reject = TRUE;
3301 period = 0;
3302 offset = 0;
3303 bus_width = 0;
3304 ppr_options = 0;
3305 syncrate = NULL;
3306 }
3307 } else {
3308 if (devinfo->role != ROLE_TARGET)
3309 printf("(%s:%c:%d:%d): Target "
3310 "Initiated PPR\n",
3311 ahc_name(ahc), devinfo->channel,
3312 devinfo->target, devinfo->lun);
3313 else
3314 printf("(%s:%c:%d:%d): Initiator "
3315 "Initiated PPR\n",
3316 ahc_name(ahc), devinfo->channel,
3317 devinfo->target, devinfo->lun);
3318 ahc->msgout_index = 0;
3319 ahc->msgout_len = 0;
3320 ahc_construct_ppr(ahc, devinfo, period, offset,
3321 bus_width, ppr_options);
3322 ahc->msgout_index = 0;
3323 response = TRUE;
3324 }
3325 if (bootverbose) {
3326 printf("(%s:%c:%d:%d): Received PPR width %x, "
3327 "period %x, offset %x,options %x\n"
3328 "\tFiltered to width %x, period %x, "
3329 "offset %x, options %x\n",
3330 ahc_name(ahc), devinfo->channel,
3331 devinfo->target, devinfo->lun,
3332 saved_width, ahc->msgin_buf[3],
3333 saved_offset, saved_ppr_options,
3334 bus_width, period, offset, ppr_options);
3335 }
3336 ahc_set_width(ahc, devinfo, bus_width,
3337 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3338 /*paused*/TRUE);
3339 ahc_set_syncrate(ahc, devinfo,
3340 syncrate, period,
3341 offset, ppr_options,
3342 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3343 /*paused*/TRUE);
3344 done = MSGLOOP_MSGCOMPLETE;
3345 break;
3346 }
3347 default:
3348 /* Unknown extended message. Reject it. */
3349 reject = TRUE;
3350 break;
3351 }
3352 break;
3353 }
3354 #ifdef AHC_TARGET_MODE
3355 case MSG_BUS_DEV_RESET:
3356 ahc_handle_devreset(ahc, devinfo,
3357 CAM_BDR_SENT,
3358 "Bus Device Reset Received",
3359 /*verbose_level*/0);
3360 ahc_restart(ahc);
3361 done = MSGLOOP_TERMINATED;
3362 break;
3363 case MSG_ABORT_TAG:
3364 case MSG_ABORT:
3365 case MSG_CLEAR_QUEUE:
3366 {
3367 int tag;
3368
3369 /* Target mode messages */
3370 if (devinfo->role != ROLE_TARGET) {
3371 reject = TRUE;
3372 break;
3373 }
3374 tag = SCB_LIST_NULL;
3375 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3376 tag = ahc_inb(ahc, INITIATOR_TAG);
3377 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3378 devinfo->lun, tag, ROLE_TARGET,
3379 CAM_REQ_ABORTED);
3380
3381 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3382 if (tstate != NULL) {
3383 struct ahc_tmode_lstate* lstate;
3384
3385 lstate = tstate->enabled_luns[devinfo->lun];
3386 if (lstate != NULL) {
3387 ahc_queue_lstate_event(ahc, lstate,
3388 devinfo->our_scsiid,
3389 ahc->msgin_buf[0],
3390 /*arg*/tag);
3391 ahc_send_lstate_events(ahc, lstate);
3392 }
3393 }
3394 ahc_restart(ahc);
3395 done = MSGLOOP_TERMINATED;
3396 break;
3397 }
3398 #endif
3399 case MSG_TERM_IO_PROC:
3400 default:
3401 reject = TRUE;
3402 break;
3403 }
3404
3405 if (reject) {
3406 /*
3407 * Setup to reject the message.
3408 */
3409 ahc->msgout_index = 0;
3410 ahc->msgout_len = 1;
3411 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3412 done = MSGLOOP_MSGCOMPLETE;
3413 response = TRUE;
3414 }
3415
3416 if (done != MSGLOOP_IN_PROG && !response)
3417 /* Clear the outgoing message buffer */
3418 ahc->msgout_len = 0;
3419
3420 return (done);
3421 }
3422
3423 /*
3424 * Process a message reject message.
3425 */
3426 static int
3427 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3428 {
3429 /*
3430 * What we care about here is if we had an
3431 * outstanding SDTR or WDTR message for this
3432 * target. If we did, this is a signal that
3433 * the target is refusing negotiation.
3434 */
3435 struct scb *scb;
3436 struct ahc_initiator_tinfo *tinfo;
3437 struct ahc_tmode_tstate *tstate;
3438 u_int scb_index;
3439 u_int last_msg;
3440 int response = 0;
3441
3442 scb_index = ahc_inb(ahc, SCB_TAG);
3443 scb = ahc_lookup_scb(ahc, scb_index);
3444 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3445 devinfo->our_scsiid,
3446 devinfo->target, &tstate);
3447 /* Might be necessary */
3448 last_msg = ahc_inb(ahc, LAST_MSG);
3449
3450 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3451 /*
3452 * Target does not support the PPR message.
3453 * Attempt to negotiate SPI-2 style.
3454 */
3455 if (bootverbose) {
3456 printf("(%s:%c:%d:%d): PPR Rejected. "
3457 "Trying WDTR/SDTR\n",
3458 ahc_name(ahc), devinfo->channel,
3459 devinfo->target, devinfo->lun);
3460 }
3461 tinfo->goal.ppr_options = 0;
3462 tinfo->curr.transport_version = 2;
3463 tinfo->goal.transport_version = 2;
3464 ahc->msgout_index = 0;
3465 ahc->msgout_len = 0;
3466 ahc_build_transfer_msg(ahc, devinfo);
3467 ahc->msgout_index = 0;
3468 response = 1;
3469 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3470
3471 /* note 8bit xfers */
3472 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3473 "8bit transfers\n", ahc_name(ahc),
3474 devinfo->channel, devinfo->target, devinfo->lun);
3475 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3476 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3477 /*paused*/TRUE);
3478 /*
3479 * No need to clear the sync rate. If the target
3480 * did not accept the command, our syncrate is
3481 * unaffected. If the target started the negotiation,
3482 * but rejected our response, we already cleared the
3483 * sync rate before sending our WDTR.
3484 */
3485 if (tinfo->goal.offset != tinfo->curr.offset) {
3486
3487 /* Start the sync negotiation */
3488 ahc->msgout_index = 0;
3489 ahc->msgout_len = 0;
3490 ahc_build_transfer_msg(ahc, devinfo);
3491 ahc->msgout_index = 0;
3492 response = 1;
3493 }
3494 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3495 /* note asynch xfers and clear flag */
3496 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3497 /*offset*/0, /*ppr_options*/0,
3498 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3499 /*paused*/TRUE);
3500 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3501 "Using asynchronous transfers\n",
3502 ahc_name(ahc), devinfo->channel,
3503 devinfo->target, devinfo->lun);
3504 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3505 int tag_type;
3506 int mask;
3507
3508 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3509
3510 if (tag_type == MSG_SIMPLE_TASK) {
3511 printf("(%s:%c:%d:%d): refuses tagged commands. "
3512 "Performing non-tagged I/O\n", ahc_name(ahc),
3513 devinfo->channel, devinfo->target, devinfo->lun);
3514 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
3515 mask = ~0x23;
3516 } else {
3517 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3518 "Performing simple queue tagged I/O only\n",
3519 ahc_name(ahc), devinfo->channel, devinfo->target,
3520 devinfo->lun, tag_type == MSG_ORDERED_TASK
3521 ? "ordered" : "head of queue");
3522 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
3523 mask = ~0x03;
3524 }
3525
3526 /*
3527 * Resend the identify for this CCB as the target
3528 * may believe that the selection is invalid otherwise.
3529 */
3530 ahc_outb(ahc, SCB_CONTROL,
3531 ahc_inb(ahc, SCB_CONTROL) & mask);
3532 scb->hscb->control &= mask;
3533 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3534 /*type*/MSG_SIMPLE_TASK);
3535 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3536 ahc_assert_atn(ahc);
3537
3538 /*
3539 * This transaction is now at the head of
3540 * the untagged queue for this target.
3541 */
3542 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3543 struct scb_tailq *untagged_q;
3544
3545 untagged_q =
3546 &(ahc->untagged_queues[devinfo->target_offset]);
3547 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3548 scb->flags |= SCB_UNTAGGEDQ;
3549 }
3550 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3551 scb->hscb->tag);
3552
3553 /*
3554 * Requeue all tagged commands for this target
3555 * currently in our posession so they can be
3556 * converted to untagged commands.
3557 */
3558 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3559 SCB_GET_CHANNEL(ahc, scb),
3560 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3561 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3562 SEARCH_COMPLETE);
3563 } else {
3564 /*
3565 * Otherwise, we ignore it.
3566 */
3567 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3568 ahc_name(ahc), devinfo->channel, devinfo->target,
3569 last_msg);
3570 }
3571 return (response);
3572 }
3573
3574 /*
3575 * Process an ingnore wide residue message.
3576 */
3577 static void
3578 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3579 {
3580 u_int scb_index;
3581 struct scb *scb;
3582
3583 scb_index = ahc_inb(ahc, SCB_TAG);
3584 scb = ahc_lookup_scb(ahc, scb_index);
3585 /*
3586 * XXX Actually check data direction in the sequencer?
3587 * Perhaps add datadir to some spare bits in the hscb?
3588 */
3589 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3590 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3591 /*
3592 * Ignore the message if we haven't
3593 * seen an appropriate data phase yet.
3594 */
3595 } else {
3596 /*
3597 * If the residual occurred on the last
3598 * transfer and the transfer request was
3599 * expected to end on an odd count, do
3600 * nothing. Otherwise, subtract a byte
3601 * and update the residual count accordingly.
3602 */
3603 uint32_t sgptr;
3604
3605 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3606 if ((sgptr & SG_LIST_NULL) != 0
3607 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3608 /*
3609 * If the residual occurred on the last
3610 * transfer and the transfer request was
3611 * expected to end on an odd count, do
3612 * nothing.
3613 */
3614 } else {
3615 struct ahc_dma_seg *sg;
3616 uint32_t data_cnt;
3617 uint32_t data_addr;
3618 uint32_t sglen;
3619
3620 /* Pull in all of the sgptr */
3621 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3622 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3623
3624 if ((sgptr & SG_LIST_NULL) != 0) {
3625 /*
3626 * The residual data count is not updated
3627 * for the command run to completion case.
3628 * Explicitly zero the count.
3629 */
3630 data_cnt &= ~AHC_SG_LEN_MASK;
3631 }
3632
3633 data_addr = ahc_inl(ahc, SHADDR);
3634
3635 data_cnt += 1;
3636 data_addr -= 1;
3637 sgptr &= SG_PTR_MASK;
3638
3639 sg = ahc_sg_bus_to_virt(scb, sgptr);
3640
3641 /*
3642 * The residual sg ptr points to the next S/G
3643 * to load so we must go back one.
3644 */
3645 sg--;
3646 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3647 if (sg != scb->sg_list
3648 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3649
3650 sg--;
3651 sglen = ahc_le32toh(sg->len);
3652 /*
3653 * Preserve High Address and SG_LIST bits
3654 * while setting the count to 1.
3655 */
3656 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3657 data_addr = ahc_le32toh(sg->addr)
3658 + (sglen & AHC_SG_LEN_MASK) - 1;
3659
3660 /*
3661 * Increment sg so it points to the
3662 * "next" sg.
3663 */
3664 sg++;
3665 sgptr = ahc_sg_virt_to_bus(scb, sg);
3666 }
3667 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3668 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3669 /*
3670 * Toggle the "oddness" of the transfer length
3671 * to handle this mid-transfer ignore wide
3672 * residue. This ensures that the oddness is
3673 * correct for subsequent data transfers.
3674 */
3675 ahc_outb(ahc, SCB_LUN,
3676 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3677 }
3678 }
3679 }
3680
3681
3682 /*
3683 * Reinitialize the data pointers for the active transfer
3684 * based on its current residual.
3685 */
3686 static void
3687 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3688 {
3689 struct scb *scb;
3690 struct ahc_dma_seg *sg;
3691 u_int scb_index;
3692 uint32_t sgptr;
3693 uint32_t resid;
3694 uint32_t dataptr;
3695
3696 scb_index = ahc_inb(ahc, SCB_TAG);
3697 scb = ahc_lookup_scb(ahc, scb_index);
3698 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3699 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3700 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3701 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3702
3703 sgptr &= SG_PTR_MASK;
3704 sg = ahc_sg_bus_to_virt(scb, sgptr);
3705
3706 /* The residual sg_ptr always points to the next sg */
3707 sg--;
3708
3709 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3710 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3711 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3712
3713 dataptr = ahc_le32toh(sg->addr)
3714 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3715 - resid;
3716 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3717 u_int dscommand1;
3718
3719 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3720 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3721 ahc_outb(ahc, HADDR,
3722 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3723 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3724 }
3725 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3726 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3727 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3728 ahc_outb(ahc, HADDR, dataptr);
3729 ahc_outb(ahc, HCNT + 2, resid >> 16);
3730 ahc_outb(ahc, HCNT + 1, resid >> 8);
3731 ahc_outb(ahc, HCNT, resid);
3732 if ((ahc->features & AHC_ULTRA2) == 0) {
3733 ahc_outb(ahc, STCNT + 2, resid >> 16);
3734 ahc_outb(ahc, STCNT + 1, resid >> 8);
3735 ahc_outb(ahc, STCNT, resid);
3736 }
3737 }
3738
3739 /*
3740 * Handle the effects of issuing a bus device reset message.
3741 */
3742 static void
3743 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3744 cam_status status, char *message, int verbose_level)
3745 {
3746 #ifdef AHC_TARGET_MODE
3747 struct ahc_tmode_tstate* tstate;
3748 u_int lun;
3749 #endif
3750 int found;
3751
3752 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3753 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3754 status);
3755
3756 #ifdef AHC_TARGET_MODE
3757 /*
3758 * Send an immediate notify ccb to all target mord peripheral
3759 * drivers affected by this action.
3760 */
3761 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3762 if (tstate != NULL) {
3763 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3764 struct ahc_tmode_lstate* lstate;
3765
3766 lstate = tstate->enabled_luns[lun];
3767 if (lstate == NULL)
3768 continue;
3769
3770 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3771 MSG_BUS_DEV_RESET, /*arg*/0);
3772 ahc_send_lstate_events(ahc, lstate);
3773 }
3774 }
3775 #endif
3776
3777 /*
3778 * Go back to async/narrow transfers and renegotiate.
3779 */
3780 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3781 AHC_TRANS_CUR, /*paused*/TRUE);
3782 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3783 /*period*/0, /*offset*/0, /*ppr_options*/0,
3784 AHC_TRANS_CUR, /*paused*/TRUE);
3785
3786 if (status != CAM_SEL_TIMEOUT)
3787 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3788 CAM_LUN_WILDCARD, AC_SENT_BDR);
3789
3790 if (message != NULL
3791 && (verbose_level <= bootverbose))
3792 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3793 message, devinfo->channel, devinfo->target, found);
3794 }
3795
3796 #ifdef AHC_TARGET_MODE
3797 static void
3798 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3799 struct scb *scb)
3800 {
3801
3802 /*
3803 * To facilitate adding multiple messages together,
3804 * each routine should increment the index and len
3805 * variables instead of setting them explicitly.
3806 */
3807 ahc->msgout_index = 0;
3808 ahc->msgout_len = 0;
3809
3810 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3811 ahc_build_transfer_msg(ahc, devinfo);
3812 else
3813 panic("ahc_intr: AWAITING target message with no message");
3814
3815 ahc->msgout_index = 0;
3816 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3817 }
3818 #endif
3819 /**************************** Initialization **********************************/
3820 /*
3821 * Allocate a controller structure for a new device
3822 * and perform initial initializion.
3823 */
3824 struct ahc_softc *
3825 ahc_alloc(void *platform_arg, char *name)
3826 {
3827 struct ahc_softc *ahc;
3828 int i;
3829
3830 #ifndef __FreeBSD__
3831 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3832 if (!ahc) {
3833 printf("aic7xxx: cannot malloc softc!\n");
3834 free(name, M_DEVBUF);
3835 return NULL;
3836 }
3837 #else
3838 ahc = device_get_softc((device_t)platform_arg);
3839 #endif
3840 memset(ahc, 0, sizeof(*ahc));
3841 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3842 M_DEVBUF, M_NOWAIT);
3843 if (ahc->seep_config == NULL) {
3844 #ifndef __FreeBSD__
3845 free(ahc, M_DEVBUF);
3846 #endif
3847 free(name, M_DEVBUF);
3848 return (NULL);
3849 }
3850 LIST_INIT(&ahc->pending_scbs);
3851 /* We don't know our unit number until the OSM sets it */
3852 ahc->name = name;
3853 ahc->unit = -1;
3854 ahc->description = NULL;
3855 ahc->channel = 'A';
3856 ahc->channel_b = 'B';
3857 ahc->chip = AHC_NONE;
3858 ahc->features = AHC_FENONE;
3859 ahc->bugs = AHC_BUGNONE;
3860 ahc->flags = AHC_FNONE;
3861 /*
3862 * Default to all error reporting enabled with the
3863 * sequencer operating at its fastest speed.
3864 * The bus attach code may modify this.
3865 */
3866 ahc->seqctl = FASTMODE;
3867
3868 for (i = 0; i < AHC_NUM_TARGETS; i++)
3869 TAILQ_INIT(&ahc->untagged_queues[i]);
3870 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3871 ahc_free(ahc);
3872 ahc = NULL;
3873 }
3874 return (ahc);
3875 }
3876
3877 int
3878 ahc_softc_init(struct ahc_softc *ahc)
3879 {
3880
3881 /* The IRQMS bit is only valid on VL and EISA chips */
3882 if ((ahc->chip & AHC_PCI) == 0)
3883 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3884 else
3885 ahc->unpause = 0;
3886 ahc->pause = ahc->unpause | PAUSE;
3887 /* XXX The shared scb data stuff should be deprecated */
3888 if (ahc->scb_data == NULL) {
3889 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3890 M_DEVBUF, M_NOWAIT);
3891 if (ahc->scb_data == NULL)
3892 return (ENOMEM);
3893 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3894 }
3895
3896 return (0);
3897 }
3898
3899 void
3900 ahc_set_unit(struct ahc_softc *ahc, int unit)
3901 {
3902 ahc->unit = unit;
3903 }
3904
3905 void
3906 ahc_set_name(struct ahc_softc *ahc, char *name)
3907 {
3908 if (ahc->name != NULL)
3909 free(ahc->name, M_DEVBUF);
3910 ahc->name = name;
3911 }
3912
3913 void
3914 ahc_free(struct ahc_softc *ahc)
3915 {
3916 int i;
3917
3918 switch (ahc->init_level) {
3919 default:
3920 case 5:
3921 ahc_shutdown(ahc);
3922 /* FALLTHROUGH */
3923 case 4:
3924 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3925 ahc->shared_data_dmamap);
3926 /* FALLTHROUGH */
3927 case 3:
3928 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3929 ahc->shared_data_dmamap);
3930 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3931 ahc->shared_data_dmamap);
3932 /* FALLTHROUGH */
3933 case 2:
3934 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3935 case 1:
3936 #ifndef __linux__
3937 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3938 #endif
3939 break;
3940 case 0:
3941 break;
3942 }
3943
3944 #ifndef __linux__
3945 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
3946 #endif
3947 ahc_platform_free(ahc);
3948 ahc_fini_scbdata(ahc);
3949 for (i = 0; i < AHC_NUM_TARGETS; i++) {
3950 struct ahc_tmode_tstate *tstate;
3951
3952 tstate = ahc->enabled_targets[i];
3953 if (tstate != NULL) {
3954 #ifdef AHC_TARGET_MODE
3955 int j;
3956
3957 for (j = 0; j < AHC_NUM_LUNS; j++) {
3958 struct ahc_tmode_lstate *lstate;
3959
3960 lstate = tstate->enabled_luns[j];
3961 if (lstate != NULL) {
3962 xpt_free_path(lstate->path);
3963 free(lstate, M_DEVBUF);
3964 }
3965 }
3966 #endif
3967 free(tstate, M_DEVBUF);
3968 }
3969 }
3970 #ifdef AHC_TARGET_MODE
3971 if (ahc->black_hole != NULL) {
3972 xpt_free_path(ahc->black_hole->path);
3973 free(ahc->black_hole, M_DEVBUF);
3974 }
3975 #endif
3976 if (ahc->name != NULL)
3977 free(ahc->name, M_DEVBUF);
3978 if (ahc->seep_config != NULL)
3979 free(ahc->seep_config, M_DEVBUF);
3980 #ifndef __FreeBSD__
3981 free(ahc, M_DEVBUF);
3982 #endif
3983 return;
3984 }
3985
3986 void
3987 ahc_shutdown(void *arg)
3988 {
3989 struct ahc_softc *ahc;
3990 int i;
3991
3992 ahc = (struct ahc_softc *)arg;
3993
3994 /* This will reset most registers to 0, but not all */
3995 ahc_reset(ahc, /*reinit*/FALSE);
3996 ahc_outb(ahc, SCSISEQ, 0);
3997 ahc_outb(ahc, SXFRCTL0, 0);
3998 ahc_outb(ahc, DSPCISTATUS, 0);
3999
4000 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4001 ahc_outb(ahc, i, 0);
4002 }
4003
4004 /*
4005 * Reset the controller and record some information about it
4006 * that is only available just after a reset. If "reinit" is
4007 * non-zero, this reset occured after initial configuration
4008 * and the caller requests that the chip be fully reinitialized
4009 * to a runable state. Chip interrupts are *not* enabled after
4010 * a reinitialization. The caller must enable interrupts via
4011 * ahc_intr_enable().
4012 */
4013 int
4014 ahc_reset(struct ahc_softc *ahc, int reinit)
4015 {
4016 u_int sblkctl;
4017 u_int sxfrctl1_a, sxfrctl1_b;
4018 int error;
4019 int wait;
4020
4021 /*
4022 * Preserve the value of the SXFRCTL1 register for all channels.
4023 * It contains settings that affect termination and we don't want
4024 * to disturb the integrity of the bus.
4025 */
4026 ahc_pause(ahc);
4027 sxfrctl1_b = 0;
4028 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4029 u_int sblkctl;
4030
4031 /*
4032 * Save channel B's settings in case this chip
4033 * is setup for TWIN channel operation.
4034 */
4035 sblkctl = ahc_inb(ahc, SBLKCTL);
4036 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4037 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4038 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4039 }
4040 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4041
4042 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4043
4044 /*
4045 * Ensure that the reset has finished. We delay 1000us
4046 * prior to reading the register to make sure the chip
4047 * has sufficiently completed its reset to handle register
4048 * accesses.
4049 */
4050 wait = 1000;
4051 do {
4052 ahc_delay(1000);
4053 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4054
4055 if (wait == 0) {
4056 printf("%s: WARNING - Failed chip reset! "
4057 "Trying to initialize anyway.\n", ahc_name(ahc));
4058 }
4059 ahc_outb(ahc, HCNTRL, ahc->pause);
4060
4061 /* Determine channel configuration */
4062 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4063 /* No Twin Channel PCI cards */
4064 if ((ahc->chip & AHC_PCI) != 0)
4065 sblkctl &= ~SELBUSB;
4066 switch (sblkctl) {
4067 case 0:
4068 /* Single Narrow Channel */
4069 break;
4070 case 2:
4071 /* Wide Channel */
4072 ahc->features |= AHC_WIDE;
4073 break;
4074 case 8:
4075 /* Twin Channel */
4076 ahc->features |= AHC_TWIN;
4077 break;
4078 default:
4079 printf(" Unsupported adapter type. Ignoring\n");
4080 return(-1);
4081 }
4082
4083 /*
4084 * Reload sxfrctl1.
4085 *
4086 * We must always initialize STPWEN to 1 before we
4087 * restore the saved values. STPWEN is initialized
4088 * to a tri-state condition which can only be cleared
4089 * by turning it on.
4090 */
4091 if ((ahc->features & AHC_TWIN) != 0) {
4092 u_int sblkctl;
4093
4094 sblkctl = ahc_inb(ahc, SBLKCTL);
4095 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4096 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4097 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4098 }
4099 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4100
4101 error = 0;
4102 if (reinit != 0)
4103 /*
4104 * If a recovery action has forced a chip reset,
4105 * re-initialize the chip to our liking.
4106 */
4107 error = ahc->bus_chip_init(ahc);
4108 #ifdef AHC_DUMP_SEQ
4109 else
4110 ahc_dumpseq(ahc);
4111 #endif
4112
4113 return (error);
4114 }
4115
4116 /*
4117 * Determine the number of SCBs available on the controller
4118 */
4119 int
4120 ahc_probe_scbs(struct ahc_softc *ahc) {
4121 int i;
4122
4123 for (i = 0; i < AHC_SCB_MAX; i++) {
4124
4125 ahc_outb(ahc, SCBPTR, i);
4126 ahc_outb(ahc, SCB_BASE, i);
4127 if (ahc_inb(ahc, SCB_BASE) != i)
4128 break;
4129 ahc_outb(ahc, SCBPTR, 0);
4130 if (ahc_inb(ahc, SCB_BASE) != 0)
4131 break;
4132 }
4133 return (i);
4134 }
4135
4136 static void
4137 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4138 {
4139 dma_addr_t *baddr;
4140
4141 baddr = (dma_addr_t *)arg;
4142 *baddr = segs->ds_addr;
4143 }
4144
4145 static void
4146 ahc_build_free_scb_list(struct ahc_softc *ahc)
4147 {
4148 int scbsize;
4149 int i;
4150
4151 scbsize = 32;
4152 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4153 scbsize = 64;
4154
4155 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4156 int j;
4157
4158 ahc_outb(ahc, SCBPTR, i);
4159
4160 /*
4161 * Touch all SCB bytes to avoid parity errors
4162 * should one of our debugging routines read
4163 * an otherwise uninitiatlized byte.
4164 */
4165 for (j = 0; j < scbsize; j++)
4166 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4167
4168 /* Clear the control byte. */
4169 ahc_outb(ahc, SCB_CONTROL, 0);
4170
4171 /* Set the next pointer */
4172 if ((ahc->flags & AHC_PAGESCBS) != 0)
4173 ahc_outb(ahc, SCB_NEXT, i+1);
4174 else
4175 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4176
4177 /* Make the tag number, SCSIID, and lun invalid */
4178 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4179 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4180 ahc_outb(ahc, SCB_LUN, 0xFF);
4181 }
4182
4183 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4184 /* SCB 0 heads the free list. */
4185 ahc_outb(ahc, FREE_SCBH, 0);
4186 } else {
4187 /* No free list. */
4188 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4189 }
4190
4191 /* Make sure that the last SCB terminates the free list */
4192 ahc_outb(ahc, SCBPTR, i-1);
4193 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4194 }
4195
4196 static int
4197 ahc_init_scbdata(struct ahc_softc *ahc)
4198 {
4199 struct scb_data *scb_data;
4200
4201 scb_data = ahc->scb_data;
4202 SLIST_INIT(&scb_data->free_scbs);
4203 SLIST_INIT(&scb_data->sg_maps);
4204
4205 /* Allocate SCB resources */
4206 scb_data->scbarray =
4207 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4208 M_DEVBUF, M_NOWAIT);
4209 if (scb_data->scbarray == NULL)
4210 return (ENOMEM);
4211 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4212
4213 /* Determine the number of hardware SCBs and initialize them */
4214
4215 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4216 if (ahc->scb_data->maxhscbs == 0) {
4217 printf("%s: No SCB space found\n", ahc_name(ahc));
4218 return (ENXIO);
4219 }
4220
4221 /*
4222 * Create our DMA tags. These tags define the kinds of device
4223 * accessible memory allocations and memory mappings we will
4224 * need to perform during normal operation.
4225 *
4226 * Unless we need to further restrict the allocation, we rely
4227 * on the restrictions of the parent dmat, hence the common
4228 * use of MAXADDR and MAXSIZE.
4229 */
4230
4231 /* DMA tag for our hardware scb structures */
4232 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4233 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4234 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4235 /*highaddr*/BUS_SPACE_MAXADDR,
4236 /*filter*/NULL, /*filterarg*/NULL,
4237 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4238 /*nsegments*/1,
4239 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4240 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4241 goto error_exit;
4242 }
4243
4244 scb_data->init_level++;
4245
4246 /* Allocation for our hscbs */
4247 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4248 (void **)&scb_data->hscbs,
4249 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4250 goto error_exit;
4251 }
4252
4253 scb_data->init_level++;
4254
4255 /* And permanently map them */
4256 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4257 scb_data->hscbs,
4258 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4259 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4260
4261 scb_data->init_level++;
4262
4263 /* DMA tag for our sense buffers */
4264 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4265 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4266 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4267 /*highaddr*/BUS_SPACE_MAXADDR,
4268 /*filter*/NULL, /*filterarg*/NULL,
4269 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4270 /*nsegments*/1,
4271 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4272 /*flags*/0, &scb_data->sense_dmat) != 0) {
4273 goto error_exit;
4274 }
4275
4276 scb_data->init_level++;
4277
4278 /* Allocate them */
4279 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4280 (void **)&scb_data->sense,
4281 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4282 goto error_exit;
4283 }
4284
4285 scb_data->init_level++;
4286
4287 /* And permanently map them */
4288 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4289 scb_data->sense,
4290 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4291 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4292
4293 scb_data->init_level++;
4294
4295 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4296 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4297 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4298 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4299 /*highaddr*/BUS_SPACE_MAXADDR,
4300 /*filter*/NULL, /*filterarg*/NULL,
4301 PAGE_SIZE, /*nsegments*/1,
4302 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4303 /*flags*/0, &scb_data->sg_dmat) != 0) {
4304 goto error_exit;
4305 }
4306
4307 scb_data->init_level++;
4308
4309 /* Perform initial CCB allocation */
4310 memset(scb_data->hscbs, 0,
4311 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4312 ahc_alloc_scbs(ahc);
4313
4314 if (scb_data->numscbs == 0) {
4315 printf("%s: ahc_init_scbdata - "
4316 "Unable to allocate initial scbs\n",
4317 ahc_name(ahc));
4318 goto error_exit;
4319 }
4320
4321 /*
4322 * Reserve the next queued SCB.
4323 */
4324 ahc->next_queued_scb = ahc_get_scb(ahc);
4325
4326 /*
4327 * Note that we were successfull
4328 */
4329 return (0);
4330
4331 error_exit:
4332
4333 return (ENOMEM);
4334 }
4335
4336 static void
4337 ahc_fini_scbdata(struct ahc_softc *ahc)
4338 {
4339 struct scb_data *scb_data;
4340
4341 scb_data = ahc->scb_data;
4342 if (scb_data == NULL)
4343 return;
4344
4345 switch (scb_data->init_level) {
4346 default:
4347 case 7:
4348 {
4349 struct sg_map_node *sg_map;
4350
4351 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4352 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4353 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4354 sg_map->sg_dmamap);
4355 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4356 sg_map->sg_vaddr,
4357 sg_map->sg_dmamap);
4358 free(sg_map, M_DEVBUF);
4359 }
4360 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4361 }
4362 case 6:
4363 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4364 scb_data->sense_dmamap);
4365 case 5:
4366 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4367 scb_data->sense_dmamap);
4368 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4369 scb_data->sense_dmamap);
4370 case 4:
4371 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4372 case 3:
4373 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4374 scb_data->hscb_dmamap);
4375 case 2:
4376 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4377 scb_data->hscb_dmamap);
4378 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4379 scb_data->hscb_dmamap);
4380 case 1:
4381 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4382 break;
4383 case 0:
4384 break;
4385 }
4386 if (scb_data->scbarray != NULL)
4387 free(scb_data->scbarray, M_DEVBUF);
4388 }
4389
4390 void
4391 ahc_alloc_scbs(struct ahc_softc *ahc)
4392 {
4393 struct scb_data *scb_data;
4394 struct scb *next_scb;
4395 struct sg_map_node *sg_map;
4396 dma_addr_t physaddr;
4397 struct ahc_dma_seg *segs;
4398 int newcount;
4399 int i;
4400
4401 scb_data = ahc->scb_data;
4402 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4403 /* Can't allocate any more */
4404 return;
4405
4406 next_scb = &scb_data->scbarray[scb_data->numscbs];
4407
4408 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4409
4410 if (sg_map == NULL)
4411 return;
4412
4413 /* Allocate S/G space for the next batch of SCBS */
4414 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4415 (void **)&sg_map->sg_vaddr,
4416 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4417 free(sg_map, M_DEVBUF);
4418 return;
4419 }
4420
4421 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4422
4423 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4424 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4425 &sg_map->sg_physaddr, /*flags*/0);
4426
4427 segs = sg_map->sg_vaddr;
4428 physaddr = sg_map->sg_physaddr;
4429
4430 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4431 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4432 for (i = 0; i < newcount; i++) {
4433 struct scb_platform_data *pdata;
4434 #ifndef __linux__
4435 int error;
4436 #endif
4437 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4438 M_DEVBUF, M_NOWAIT);
4439 if (pdata == NULL)
4440 break;
4441 next_scb->platform_data = pdata;
4442 next_scb->sg_map = sg_map;
4443 next_scb->sg_list = segs;
4444 /*
4445 * The sequencer always starts with the second entry.
4446 * The first entry is embedded in the scb.
4447 */
4448 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4449 next_scb->ahc_softc = ahc;
4450 next_scb->flags = SCB_FREE;
4451 #ifndef __linux__
4452 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4453 &next_scb->dmamap);
4454 if (error != 0)
4455 break;
4456 #endif
4457 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4458 next_scb->hscb->tag = ahc->scb_data->numscbs;
4459 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4460 next_scb, links.sle);
4461 segs += AHC_NSEG;
4462 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4463 next_scb++;
4464 ahc->scb_data->numscbs++;
4465 }
4466 }
4467
4468 void
4469 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4470 {
4471 int len;
4472
4473 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4474 buf += len;
4475 if ((ahc->features & AHC_TWIN) != 0)
4476 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4477 "B SCSI Id=%d, primary %c, ",
4478 ahc->our_id, ahc->our_id_b,
4479 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4480 else {
4481 const char *speed;
4482 const char *type;
4483
4484 speed = "";
4485 if ((ahc->features & AHC_ULTRA) != 0) {
4486 speed = "Ultra ";
4487 } else if ((ahc->features & AHC_DT) != 0) {
4488 speed = "Ultra160 ";
4489 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4490 speed = "Ultra2 ";
4491 }
4492 if ((ahc->features & AHC_WIDE) != 0) {
4493 type = "Wide";
4494 } else {
4495 type = "Single";
4496 }
4497 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4498 speed, type, ahc->channel, ahc->our_id);
4499 }
4500 buf += len;
4501
4502 if ((ahc->flags & AHC_PAGESCBS) != 0)
4503 sprintf(buf, "%d/%d SCBs",
4504 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4505 else
4506 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4507 }
4508
4509 int
4510 ahc_chip_init(struct ahc_softc *ahc)
4511 {
4512 int term;
4513 int error;
4514 u_int i;
4515 u_int scsi_conf;
4516 u_int scsiseq_template;
4517 uint32_t physaddr;
4518
4519 ahc_outb(ahc, SEQ_FLAGS, 0);
4520 ahc_outb(ahc, SEQ_FLAGS2, 0);
4521
4522 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4523 if (ahc->features & AHC_TWIN) {
4524
4525 /*
4526 * Setup Channel B first.
4527 */
4528 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4529 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4530 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4531 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4532 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4533 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4534 if ((ahc->features & AHC_ULTRA2) != 0)
4535 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4536 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4537 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4538
4539 /* Select Channel A */
4540 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4541 }
4542 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4543 if ((ahc->features & AHC_ULTRA2) != 0)
4544 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4545 else
4546 ahc_outb(ahc, SCSIID, ahc->our_id);
4547 scsi_conf = ahc_inb(ahc, SCSICONF);
4548 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4549 |term|ahc->seltime
4550 |ENSTIMER|ACTNEGEN);
4551 if ((ahc->features & AHC_ULTRA2) != 0)
4552 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4553 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4554 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4555
4556 /* There are no untagged SCBs active yet. */
4557 for (i = 0; i < 16; i++) {
4558 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4559 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4560 int lun;
4561
4562 /*
4563 * The SCB based BTT allows an entry per
4564 * target and lun pair.
4565 */
4566 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4567 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4568 }
4569 }
4570
4571 /* All of our queues are empty */
4572 for (i = 0; i < 256; i++)
4573 ahc->qoutfifo[i] = SCB_LIST_NULL;
4574 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4575
4576 for (i = 0; i < 256; i++)
4577 ahc->qinfifo[i] = SCB_LIST_NULL;
4578
4579 if ((ahc->features & AHC_MULTI_TID) != 0) {
4580 ahc_outb(ahc, TARGID, 0);
4581 ahc_outb(ahc, TARGID + 1, 0);
4582 }
4583
4584 /*
4585 * Tell the sequencer where it can find our arrays in memory.
4586 */
4587 physaddr = ahc->scb_data->hscb_busaddr;
4588 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4589 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4590 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4591 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4592
4593 physaddr = ahc->shared_data_busaddr;
4594 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4595 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4596 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4597 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4598
4599 /*
4600 * Initialize the group code to command length table.
4601 * This overrides the values in TARG_SCSIRATE, so only
4602 * setup the table after we have processed that information.
4603 */
4604 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4605 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4606 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4607 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4608 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4609 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4610 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4611 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4612
4613 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4614 ahc_outb(ahc, HS_MAILBOX, 0);
4615
4616 /* Tell the sequencer of our initial queue positions */
4617 if ((ahc->features & AHC_TARGETMODE) != 0) {
4618 ahc->tqinfifonext = 1;
4619 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4620 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4621 }
4622 ahc->qinfifonext = 0;
4623 ahc->qoutfifonext = 0;
4624 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4625 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4626 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4627 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4628 ahc_outb(ahc, SDSCB_QOFF, 0);
4629 } else {
4630 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4631 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4632 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4633 }
4634
4635 /* We don't have any waiting selections */
4636 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4637
4638 /* Our disconnection list is empty too */
4639 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4640
4641 /* Message out buffer starts empty */
4642 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4643
4644 /*
4645 * Setup the allowed SCSI Sequences based on operational mode.
4646 * If we are a target, we'll enalbe select in operations once
4647 * we've had a lun enabled.
4648 */
4649 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4650 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4651 scsiseq_template |= ENRSELI;
4652 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4653
4654 /* Initialize our list of free SCBs. */
4655 ahc_build_free_scb_list(ahc);
4656
4657 /*
4658 * Tell the sequencer which SCB will be the next one it receives.
4659 */
4660 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4661
4662 /*
4663 * Load the Sequencer program and Enable the adapter
4664 * in "fast" mode.
4665 */
4666 if (bootverbose)
4667 printf("%s: Downloading Sequencer Program...",
4668 ahc_name(ahc));
4669
4670 error = ahc_loadseq(ahc);
4671 if (error != 0)
4672 return (error);
4673
4674 if ((ahc->features & AHC_ULTRA2) != 0) {
4675 int wait;
4676
4677 /*
4678 * Wait for up to 500ms for our transceivers
4679 * to settle. If the adapter does not have
4680 * a cable attached, the transceivers may
4681 * never settle, so don't complain if we
4682 * fail here.
4683 */
4684 for (wait = 5000;
4685 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4686 wait--)
4687 ahc_delay(100);
4688 }
4689 ahc_restart(ahc);
4690 return (0);
4691 }
4692
4693 /*
4694 * Start the board, ready for normal operation
4695 */
4696 int
4697 ahc_init(struct ahc_softc *ahc)
4698 {
4699 int max_targ;
4700 u_int i;
4701 u_int scsi_conf;
4702 u_int ultraenb;
4703 u_int discenable;
4704 u_int tagenable;
4705 size_t driver_data_size;
4706
4707 #ifdef AHC_DEBUG
4708 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4709 ahc->flags |= AHC_SEQUENCER_DEBUG;
4710 #endif
4711
4712 #ifdef AHC_PRINT_SRAM
4713 printf("Scratch Ram:");
4714 for (i = 0x20; i < 0x5f; i++) {
4715 if (((i % 8) == 0) && (i != 0)) {
4716 printf ("\n ");
4717 }
4718 printf (" 0x%x", ahc_inb(ahc, i));
4719 }
4720 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4721 for (i = 0x70; i < 0x7f; i++) {
4722 if (((i % 8) == 0) && (i != 0)) {
4723 printf ("\n ");
4724 }
4725 printf (" 0x%x", ahc_inb(ahc, i));
4726 }
4727 }
4728 printf ("\n");
4729 /*
4730 * Reading uninitialized scratch ram may
4731 * generate parity errors.
4732 */
4733 ahc_outb(ahc, CLRINT, CLRPARERR);
4734 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4735 #endif
4736 max_targ = 15;
4737
4738 /*
4739 * Assume we have a board at this stage and it has been reset.
4740 */
4741 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4742 ahc->our_id = ahc->our_id_b = 7;
4743
4744 /*
4745 * Default to allowing initiator operations.
4746 */
4747 ahc->flags |= AHC_INITIATORROLE;
4748
4749 /*
4750 * Only allow target mode features if this unit has them enabled.
4751 */
4752 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4753 ahc->features &= ~AHC_TARGETMODE;
4754
4755 #ifndef __linux__
4756 /* DMA tag for mapping buffers into device visible space. */
4757 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4758 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4759 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4760 ? (dma_addr_t)0x7FFFFFFFFFULL
4761 : BUS_SPACE_MAXADDR_32BIT,
4762 /*highaddr*/BUS_SPACE_MAXADDR,
4763 /*filter*/NULL, /*filterarg*/NULL,
4764 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4765 /*nsegments*/AHC_NSEG,
4766 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4767 /*flags*/BUS_DMA_ALLOCNOW,
4768 &ahc->buffer_dmat) != 0) {
4769 return (ENOMEM);
4770 }
4771 #endif
4772
4773 ahc->init_level++;
4774
4775 /*
4776 * DMA tag for our command fifos and other data in system memory
4777 * the card's sequencer must be able to access. For initiator
4778 * roles, we need to allocate space for the qinfifo and qoutfifo.
4779 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4780 * When providing for the target mode role, we must additionally
4781 * provide space for the incoming target command fifo and an extra
4782 * byte to deal with a dma bug in some chip versions.
4783 */
4784 driver_data_size = 2 * 256 * sizeof(uint8_t);
4785 if ((ahc->features & AHC_TARGETMODE) != 0)
4786 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4787 + /*DMA WideOdd Bug Buffer*/1;
4788 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4789 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4790 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4791 /*highaddr*/BUS_SPACE_MAXADDR,
4792 /*filter*/NULL, /*filterarg*/NULL,
4793 driver_data_size,
4794 /*nsegments*/1,
4795 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4796 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4797 return (ENOMEM);
4798 }
4799
4800 ahc->init_level++;
4801
4802 /* Allocation of driver data */
4803 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4804 (void **)&ahc->qoutfifo,
4805 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4806 return (ENOMEM);
4807 }
4808
4809 ahc->init_level++;
4810
4811 /* And permanently map it in */
4812 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4813 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4814 &ahc->shared_data_busaddr, /*flags*/0);
4815
4816 if ((ahc->features & AHC_TARGETMODE) != 0) {
4817 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4818 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4819 ahc->dma_bug_buf = ahc->shared_data_busaddr
4820 + driver_data_size - 1;
4821 /* All target command blocks start out invalid. */
4822 for (i = 0; i < AHC_TMODE_CMDS; i++)
4823 ahc->targetcmds[i].cmd_valid = 0;
4824 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4825 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4826 }
4827 ahc->qinfifo = &ahc->qoutfifo[256];
4828
4829 ahc->init_level++;
4830
4831 /* Allocate SCB data now that buffer_dmat is initialized */
4832 if (ahc->scb_data->maxhscbs == 0)
4833 if (ahc_init_scbdata(ahc) != 0)
4834 return (ENOMEM);
4835
4836 /*
4837 * Allocate a tstate to house information for our
4838 * initiator presence on the bus as well as the user
4839 * data for any target mode initiator.
4840 */
4841 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4842 printf("%s: unable to allocate ahc_tmode_tstate. "
4843 "Failing attach\n", ahc_name(ahc));
4844 return (ENOMEM);
4845 }
4846
4847 if ((ahc->features & AHC_TWIN) != 0) {
4848 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4849 printf("%s: unable to allocate ahc_tmode_tstate. "
4850 "Failing attach\n", ahc_name(ahc));
4851 return (ENOMEM);
4852 }
4853 }
4854
4855 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4856 ahc->flags |= AHC_PAGESCBS;
4857 } else {
4858 ahc->flags &= ~AHC_PAGESCBS;
4859 }
4860
4861 #ifdef AHC_DEBUG
4862 if (ahc_debug & AHC_SHOW_MISC) {
4863 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4864 "ahc_dma %u bytes\n",
4865 ahc_name(ahc),
4866 (u_int)sizeof(struct hardware_scb),
4867 (u_int)sizeof(struct scb),
4868 (u_int)sizeof(struct ahc_dma_seg));
4869 }
4870 #endif /* AHC_DEBUG */
4871
4872 /*
4873 * Look at the information that board initialization or
4874 * the board bios has left us.
4875 */
4876 if (ahc->features & AHC_TWIN) {
4877 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4878 if ((scsi_conf & RESET_SCSI) != 0
4879 && (ahc->flags & AHC_INITIATORROLE) != 0)
4880 ahc->flags |= AHC_RESET_BUS_B;
4881 }
4882
4883 scsi_conf = ahc_inb(ahc, SCSICONF);
4884 if ((scsi_conf & RESET_SCSI) != 0
4885 && (ahc->flags & AHC_INITIATORROLE) != 0)
4886 ahc->flags |= AHC_RESET_BUS_A;
4887
4888 ultraenb = 0;
4889 tagenable = ALL_TARGETS_MASK;
4890
4891 /* Grab the disconnection disable table and invert it for our needs */
4892 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4893 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4894 "device parameters\n", ahc_name(ahc));
4895 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4896 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4897 discenable = ALL_TARGETS_MASK;
4898 if ((ahc->features & AHC_ULTRA) != 0)
4899 ultraenb = ALL_TARGETS_MASK;
4900 } else {
4901 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4902 | ahc_inb(ahc, DISC_DSB));
4903 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4904 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4905 | ahc_inb(ahc, ULTRA_ENB);
4906 }
4907
4908 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4909 max_targ = 7;
4910
4911 for (i = 0; i <= max_targ; i++) {
4912 struct ahc_initiator_tinfo *tinfo;
4913 struct ahc_tmode_tstate *tstate;
4914 u_int our_id;
4915 u_int target_id;
4916 char channel;
4917
4918 channel = 'A';
4919 our_id = ahc->our_id;
4920 target_id = i;
4921 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4922 channel = 'B';
4923 our_id = ahc->our_id_b;
4924 target_id = i % 8;
4925 }
4926 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4927 target_id, &tstate);
4928 /* Default to async narrow across the board */
4929 memset(tinfo, 0, sizeof(*tinfo));
4930 if (ahc->flags & AHC_USEDEFAULTS) {
4931 if ((ahc->features & AHC_WIDE) != 0)
4932 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4933
4934 /*
4935 * These will be truncated when we determine the
4936 * connection type we have with the target.
4937 */
4938 tinfo->user.period = ahc_syncrates->period;
4939 tinfo->user.offset = MAX_OFFSET;
4940 } else {
4941 u_int scsirate;
4942 uint16_t mask;
4943
4944 /* Take the settings leftover in scratch RAM. */
4945 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4946 mask = (0x01 << i);
4947 if ((ahc->features & AHC_ULTRA2) != 0) {
4948 u_int offset;
4949 u_int maxsync;
4950
4951 if ((scsirate & SOFS) == 0x0F) {
4952 /*
4953 * Haven't negotiated yet,
4954 * so the format is different.
4955 */
4956 scsirate = (scsirate & SXFR) >> 4
4957 | (ultraenb & mask)
4958 ? 0x08 : 0x0
4959 | (scsirate & WIDEXFER);
4960 offset = MAX_OFFSET_ULTRA2;
4961 } else
4962 offset = ahc_inb(ahc, TARG_OFFSET + i);
4963 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4964 /* Set to the lowest sync rate, 5MHz */
4965 scsirate |= 0x1c;
4966 maxsync = AHC_SYNCRATE_ULTRA2;
4967 if ((ahc->features & AHC_DT) != 0)
4968 maxsync = AHC_SYNCRATE_DT;
4969 tinfo->user.period =
4970 ahc_find_period(ahc, scsirate, maxsync);
4971 if (offset == 0)
4972 tinfo->user.period = 0;
4973 else
4974 tinfo->user.offset = MAX_OFFSET;
4975 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4976 && (ahc->features & AHC_DT) != 0)
4977 tinfo->user.ppr_options =
4978 MSG_EXT_PPR_DT_REQ;
4979 } else if ((scsirate & SOFS) != 0) {
4980 if ((scsirate & SXFR) == 0x40
4981 && (ultraenb & mask) != 0) {
4982 /* Treat 10MHz as a non-ultra speed */
4983 scsirate &= ~SXFR;
4984 ultraenb &= ~mask;
4985 }
4986 tinfo->user.period =
4987 ahc_find_period(ahc, scsirate,
4988 (ultraenb & mask)
4989 ? AHC_SYNCRATE_ULTRA
4990 : AHC_SYNCRATE_FAST);
4991 if (tinfo->user.period != 0)
4992 tinfo->user.offset = MAX_OFFSET;
4993 }
4994 if (tinfo->user.period == 0)
4995 tinfo->user.offset = 0;
4996 if ((scsirate & WIDEXFER) != 0
4997 && (ahc->features & AHC_WIDE) != 0)
4998 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4999 tinfo->user.protocol_version = 4;
5000 if ((ahc->features & AHC_DT) != 0)
5001 tinfo->user.transport_version = 3;
5002 else
5003 tinfo->user.transport_version = 2;
5004 tinfo->goal.protocol_version = 2;
5005 tinfo->goal.transport_version = 2;
5006 tinfo->curr.protocol_version = 2;
5007 tinfo->curr.transport_version = 2;
5008 }
5009 tstate->ultraenb = 0;
5010 }
5011 ahc->user_discenable = discenable;
5012 ahc->user_tagenable = tagenable;
5013
5014 return (ahc->bus_chip_init(ahc));
5015 }
5016
5017 void
5018 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5019 {
5020 u_int hcntrl;
5021
5022 hcntrl = ahc_inb(ahc, HCNTRL);
5023 hcntrl &= ~INTEN;
5024 ahc->pause &= ~INTEN;
5025 ahc->unpause &= ~INTEN;
5026 if (enable) {
5027 hcntrl |= INTEN;
5028 ahc->pause |= INTEN;
5029 ahc->unpause |= INTEN;
5030 }
5031 ahc_outb(ahc, HCNTRL, hcntrl);
5032 }
5033
5034 /*
5035 * Ensure that the card is paused in a location
5036 * outside of all critical sections and that all
5037 * pending work is completed prior to returning.
5038 * This routine should only be called from outside
5039 * an interrupt context.
5040 */
5041 void
5042 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5043 {
5044 int intstat;
5045 int maxloops;
5046 int paused;
5047
5048 maxloops = 1000;
5049 ahc->flags |= AHC_ALL_INTERRUPTS;
5050 paused = FALSE;
5051 do {
5052 if (paused) {
5053 ahc_unpause(ahc);
5054 /*
5055 * Give the sequencer some time to service
5056 * any active selections.
5057 */
5058 ahc_delay(500);
5059 }
5060 ahc_intr(ahc);
5061 ahc_pause(ahc);
5062 paused = TRUE;
5063 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5064 intstat = ahc_inb(ahc, INTSTAT);
5065 if ((intstat & INT_PEND) == 0) {
5066 ahc_clear_critical_section(ahc);
5067 intstat = ahc_inb(ahc, INTSTAT);
5068 }
5069 } while (--maxloops
5070 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5071 && ((intstat & INT_PEND) != 0
5072 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5073 if (maxloops == 0) {
5074 printf("Infinite interrupt loop, INTSTAT = %x",
5075 ahc_inb(ahc, INTSTAT));
5076 }
5077 ahc_platform_flushwork(ahc);
5078 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5079 }
5080
5081 #ifdef CONFIG_PM
5082 int
5083 ahc_suspend(struct ahc_softc *ahc)
5084 {
5085
5086 ahc_pause_and_flushwork(ahc);
5087
5088 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5089 ahc_unpause(ahc);
5090 return (EBUSY);
5091 }
5092
5093 #ifdef AHC_TARGET_MODE
5094 /*
5095 * XXX What about ATIOs that have not yet been serviced?
5096 * Perhaps we should just refuse to be suspended if we
5097 * are acting in a target role.
5098 */
5099 if (ahc->pending_device != NULL) {
5100 ahc_unpause(ahc);
5101 return (EBUSY);
5102 }
5103 #endif
5104 ahc_shutdown(ahc);
5105 return (0);
5106 }
5107
5108 int
5109 ahc_resume(struct ahc_softc *ahc)
5110 {
5111
5112 ahc_reset(ahc, /*reinit*/TRUE);
5113 ahc_intr_enable(ahc, TRUE);
5114 ahc_restart(ahc);
5115 return (0);
5116 }
5117 #endif
5118 /************************** Busy Target Table *********************************/
5119 /*
5120 * Return the untagged transaction id for a given target/channel lun.
5121 * Optionally, clear the entry.
5122 */
5123 u_int
5124 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5125 {
5126 u_int scbid;
5127 u_int target_offset;
5128
5129 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5130 u_int saved_scbptr;
5131
5132 saved_scbptr = ahc_inb(ahc, SCBPTR);
5133 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5134 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5135 ahc_outb(ahc, SCBPTR, saved_scbptr);
5136 } else {
5137 target_offset = TCL_TARGET_OFFSET(tcl);
5138 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5139 }
5140
5141 return (scbid);
5142 }
5143
5144 void
5145 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5146 {
5147 u_int target_offset;
5148
5149 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5150 u_int saved_scbptr;
5151
5152 saved_scbptr = ahc_inb(ahc, SCBPTR);
5153 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5154 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5155 ahc_outb(ahc, SCBPTR, saved_scbptr);
5156 } else {
5157 target_offset = TCL_TARGET_OFFSET(tcl);
5158 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5159 }
5160 }
5161
5162 void
5163 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5164 {
5165 u_int target_offset;
5166
5167 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5168 u_int saved_scbptr;
5169
5170 saved_scbptr = ahc_inb(ahc, SCBPTR);
5171 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5172 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5173 ahc_outb(ahc, SCBPTR, saved_scbptr);
5174 } else {
5175 target_offset = TCL_TARGET_OFFSET(tcl);
5176 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5177 }
5178 }
5179
5180 /************************** SCB and SCB queue management **********************/
5181 int
5182 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5183 char channel, int lun, u_int tag, role_t role)
5184 {
5185 int targ = SCB_GET_TARGET(ahc, scb);
5186 char chan = SCB_GET_CHANNEL(ahc, scb);
5187 int slun = SCB_GET_LUN(scb);
5188 int match;
5189
5190 match = ((chan == channel) || (channel == ALL_CHANNELS));
5191 if (match != 0)
5192 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5193 if (match != 0)
5194 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5195 if (match != 0) {
5196 #ifdef AHC_TARGET_MODE
5197 int group;
5198
5199 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5200 if (role == ROLE_INITIATOR) {
5201 match = (group != XPT_FC_GROUP_TMODE)
5202 && ((tag == scb->hscb->tag)
5203 || (tag == SCB_LIST_NULL));
5204 } else if (role == ROLE_TARGET) {
5205 match = (group == XPT_FC_GROUP_TMODE)
5206 && ((tag == scb->io_ctx->csio.tag_id)
5207 || (tag == SCB_LIST_NULL));
5208 }
5209 #else /* !AHC_TARGET_MODE */
5210 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5211 #endif /* AHC_TARGET_MODE */
5212 }
5213
5214 return match;
5215 }
5216
5217 void
5218 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5219 {
5220 int target;
5221 char channel;
5222 int lun;
5223
5224 target = SCB_GET_TARGET(ahc, scb);
5225 lun = SCB_GET_LUN(scb);
5226 channel = SCB_GET_CHANNEL(ahc, scb);
5227
5228 ahc_search_qinfifo(ahc, target, channel, lun,
5229 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5230 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5231
5232 ahc_platform_freeze_devq(ahc, scb);
5233 }
5234
5235 void
5236 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5237 {
5238 struct scb *prev_scb;
5239
5240 prev_scb = NULL;
5241 if (ahc_qinfifo_count(ahc) != 0) {
5242 u_int prev_tag;
5243 uint8_t prev_pos;
5244
5245 prev_pos = ahc->qinfifonext - 1;
5246 prev_tag = ahc->qinfifo[prev_pos];
5247 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5248 }
5249 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5250 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5251 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5252 } else {
5253 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5254 }
5255 }
5256
5257 static void
5258 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5259 struct scb *scb)
5260 {
5261 if (prev_scb == NULL) {
5262 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5263 } else {
5264 prev_scb->hscb->next = scb->hscb->tag;
5265 ahc_sync_scb(ahc, prev_scb,
5266 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5267 }
5268 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5269 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5270 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5271 }
5272
5273 static int
5274 ahc_qinfifo_count(struct ahc_softc *ahc)
5275 {
5276 uint8_t qinpos;
5277 uint8_t diff;
5278
5279 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5280 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5281 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5282 } else
5283 qinpos = ahc_inb(ahc, QINPOS);
5284 diff = ahc->qinfifonext - qinpos;
5285 return (diff);
5286 }
5287
5288 int
5289 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5290 int lun, u_int tag, role_t role, uint32_t status,
5291 ahc_search_action action)
5292 {
5293 struct scb *scb;
5294 struct scb *prev_scb;
5295 uint8_t qinstart;
5296 uint8_t qinpos;
5297 uint8_t qintail;
5298 uint8_t next;
5299 uint8_t prev;
5300 uint8_t curscbptr;
5301 int found;
5302 int have_qregs;
5303
5304 qintail = ahc->qinfifonext;
5305 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5306 if (have_qregs) {
5307 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5308 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5309 } else
5310 qinstart = ahc_inb(ahc, QINPOS);
5311 qinpos = qinstart;
5312 found = 0;
5313 prev_scb = NULL;
5314
5315 if (action == SEARCH_COMPLETE) {
5316 /*
5317 * Don't attempt to run any queued untagged transactions
5318 * until we are done with the abort process.
5319 */
5320 ahc_freeze_untagged_queues(ahc);
5321 }
5322
5323 /*
5324 * Start with an empty queue. Entries that are not chosen
5325 * for removal will be re-added to the queue as we go.
5326 */
5327 ahc->qinfifonext = qinpos;
5328 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5329
5330 while (qinpos != qintail) {
5331 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5332 if (scb == NULL) {
5333 printf("qinpos = %d, SCB index = %d\n",
5334 qinpos, ahc->qinfifo[qinpos]);
5335 panic("Loop 1\n");
5336 }
5337
5338 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5339 /*
5340 * We found an scb that needs to be acted on.
5341 */
5342 found++;
5343 switch (action) {
5344 case SEARCH_COMPLETE:
5345 {
5346 cam_status ostat;
5347 cam_status cstat;
5348
5349 ostat = ahc_get_transaction_status(scb);
5350 if (ostat == CAM_REQ_INPROG)
5351 ahc_set_transaction_status(scb, status);
5352 cstat = ahc_get_transaction_status(scb);
5353 if (cstat != CAM_REQ_CMP)
5354 ahc_freeze_scb(scb);
5355 if ((scb->flags & SCB_ACTIVE) == 0)
5356 printf("Inactive SCB in qinfifo\n");
5357 ahc_done(ahc, scb);
5358
5359 /* FALLTHROUGH */
5360 }
5361 case SEARCH_REMOVE:
5362 break;
5363 case SEARCH_COUNT:
5364 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5365 prev_scb = scb;
5366 break;
5367 }
5368 } else {
5369 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5370 prev_scb = scb;
5371 }
5372 qinpos++;
5373 }
5374
5375 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5376 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5377 } else {
5378 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5379 }
5380
5381 if (action != SEARCH_COUNT
5382 && (found != 0)
5383 && (qinstart != ahc->qinfifonext)) {
5384 /*
5385 * The sequencer may be in the process of dmaing
5386 * down the SCB at the beginning of the queue.
5387 * This could be problematic if either the first,
5388 * or the second SCB is removed from the queue
5389 * (the first SCB includes a pointer to the "next"
5390 * SCB to dma). If we have removed any entries, swap
5391 * the first element in the queue with the next HSCB
5392 * so the sequencer will notice that NEXT_QUEUED_SCB
5393 * has changed during its dma attempt and will retry
5394 * the DMA.
5395 */
5396 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5397
5398 if (scb == NULL) {
5399 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5400 found, qinstart, ahc->qinfifonext);
5401 panic("First/Second Qinfifo fixup\n");
5402 }
5403 /*
5404 * ahc_swap_with_next_hscb forces our next pointer to
5405 * point to the reserved SCB for future commands. Save
5406 * and restore our original next pointer to maintain
5407 * queue integrity.
5408 */
5409 next = scb->hscb->next;
5410 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5411 ahc_swap_with_next_hscb(ahc, scb);
5412 scb->hscb->next = next;
5413 ahc->qinfifo[qinstart] = scb->hscb->tag;
5414
5415 /* Tell the card about the new head of the qinfifo. */
5416 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5417
5418 /* Fixup the tail "next" pointer. */
5419 qintail = ahc->qinfifonext - 1;
5420 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5421 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5422 }
5423
5424 /*
5425 * Search waiting for selection list.
5426 */
5427 curscbptr = ahc_inb(ahc, SCBPTR);
5428 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5429 prev = SCB_LIST_NULL;
5430
5431 while (next != SCB_LIST_NULL) {
5432 uint8_t scb_index;
5433
5434 ahc_outb(ahc, SCBPTR, next);
5435 scb_index = ahc_inb(ahc, SCB_TAG);
5436 if (scb_index >= ahc->scb_data->numscbs) {
5437 printf("Waiting List inconsistency. "
5438 "SCB index == %d, yet numscbs == %d.",
5439 scb_index, ahc->scb_data->numscbs);
5440 ahc_dump_card_state(ahc);
5441 panic("for safety");
5442 }
5443 scb = ahc_lookup_scb(ahc, scb_index);
5444 if (scb == NULL) {
5445 printf("scb_index = %d, next = %d\n",
5446 scb_index, next);
5447 panic("Waiting List traversal\n");
5448 }
5449 if (ahc_match_scb(ahc, scb, target, channel,
5450 lun, SCB_LIST_NULL, role)) {
5451 /*
5452 * We found an scb that needs to be acted on.
5453 */
5454 found++;
5455 switch (action) {
5456 case SEARCH_COMPLETE:
5457 {
5458 cam_status ostat;
5459 cam_status cstat;
5460
5461 ostat = ahc_get_transaction_status(scb);
5462 if (ostat == CAM_REQ_INPROG)
5463 ahc_set_transaction_status(scb,
5464 status);
5465 cstat = ahc_get_transaction_status(scb);
5466 if (cstat != CAM_REQ_CMP)
5467 ahc_freeze_scb(scb);
5468 if ((scb->flags & SCB_ACTIVE) == 0)
5469 printf("Inactive SCB in Waiting List\n");
5470 ahc_done(ahc, scb);
5471 /* FALLTHROUGH */
5472 }
5473 case SEARCH_REMOVE:
5474 next = ahc_rem_wscb(ahc, next, prev);
5475 break;
5476 case SEARCH_COUNT:
5477 prev = next;
5478 next = ahc_inb(ahc, SCB_NEXT);
5479 break;
5480 }
5481 } else {
5482
5483 prev = next;
5484 next = ahc_inb(ahc, SCB_NEXT);
5485 }
5486 }
5487 ahc_outb(ahc, SCBPTR, curscbptr);
5488
5489 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5490 channel, lun, status, action);
5491
5492 if (action == SEARCH_COMPLETE)
5493 ahc_release_untagged_queues(ahc);
5494 return (found);
5495 }
5496
5497 int
5498 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
5499 int target, char channel, int lun, uint32_t status,
5500 ahc_search_action action)
5501 {
5502 struct scb *scb;
5503 int maxtarget;
5504 int found;
5505 int i;
5506
5507 if (action == SEARCH_COMPLETE) {
5508 /*
5509 * Don't attempt to run any queued untagged transactions
5510 * until we are done with the abort process.
5511 */
5512 ahc_freeze_untagged_queues(ahc);
5513 }
5514
5515 found = 0;
5516 i = 0;
5517 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5518
5519 maxtarget = 16;
5520 if (target != CAM_TARGET_WILDCARD) {
5521
5522 i = target;
5523 if (channel == 'B')
5524 i += 8;
5525 maxtarget = i + 1;
5526 }
5527 } else {
5528 maxtarget = 0;
5529 }
5530
5531 for (; i < maxtarget; i++) {
5532 struct scb_tailq *untagged_q;
5533 struct scb *next_scb;
5534
5535 untagged_q = &(ahc->untagged_queues[i]);
5536 next_scb = TAILQ_FIRST(untagged_q);
5537 while (next_scb != NULL) {
5538
5539 scb = next_scb;
5540 next_scb = TAILQ_NEXT(scb, links.tqe);
5541
5542 /*
5543 * The head of the list may be the currently
5544 * active untagged command for a device.
5545 * We're only searching for commands that
5546 * have not been started. A transaction
5547 * marked active but still in the qinfifo
5548 * is removed by the qinfifo scanning code
5549 * above.
5550 */
5551 if ((scb->flags & SCB_ACTIVE) != 0)
5552 continue;
5553
5554 if (ahc_match_scb(ahc, scb, target, channel, lun,
5555 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5556 || (ctx != NULL && ctx != scb->io_ctx))
5557 continue;
5558
5559 /*
5560 * We found an scb that needs to be acted on.
5561 */
5562 found++;
5563 switch (action) {
5564 case SEARCH_COMPLETE:
5565 {
5566 cam_status ostat;
5567 cam_status cstat;
5568
5569 ostat = ahc_get_transaction_status(scb);
5570 if (ostat == CAM_REQ_INPROG)
5571 ahc_set_transaction_status(scb, status);
5572 cstat = ahc_get_transaction_status(scb);
5573 if (cstat != CAM_REQ_CMP)
5574 ahc_freeze_scb(scb);
5575 if ((scb->flags & SCB_ACTIVE) == 0)
5576 printf("Inactive SCB in untaggedQ\n");
5577 ahc_done(ahc, scb);
5578 break;
5579 }
5580 case SEARCH_REMOVE:
5581 scb->flags &= ~SCB_UNTAGGEDQ;
5582 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5583 break;
5584 case SEARCH_COUNT:
5585 break;
5586 }
5587 }
5588 }
5589
5590 if (action == SEARCH_COMPLETE)
5591 ahc_release_untagged_queues(ahc);
5592 return (found);
5593 }
5594
5595 int
5596 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5597 int lun, u_int tag, int stop_on_first, int remove,
5598 int save_state)
5599 {
5600 struct scb *scbp;
5601 u_int next;
5602 u_int prev;
5603 u_int count;
5604 u_int active_scb;
5605
5606 count = 0;
5607 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5608 prev = SCB_LIST_NULL;
5609
5610 if (save_state) {
5611 /* restore this when we're done */
5612 active_scb = ahc_inb(ahc, SCBPTR);
5613 } else
5614 /* Silence compiler */
5615 active_scb = SCB_LIST_NULL;
5616
5617 while (next != SCB_LIST_NULL) {
5618 u_int scb_index;
5619
5620 ahc_outb(ahc, SCBPTR, next);
5621 scb_index = ahc_inb(ahc, SCB_TAG);
5622 if (scb_index >= ahc->scb_data->numscbs) {
5623 printf("Disconnected List inconsistency. "
5624 "SCB index == %d, yet numscbs == %d.",
5625 scb_index, ahc->scb_data->numscbs);
5626 ahc_dump_card_state(ahc);
5627 panic("for safety");
5628 }
5629
5630 if (next == prev) {
5631 panic("Disconnected List Loop. "
5632 "cur SCBPTR == %x, prev SCBPTR == %x.",
5633 next, prev);
5634 }
5635 scbp = ahc_lookup_scb(ahc, scb_index);
5636 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5637 tag, ROLE_INITIATOR)) {
5638 count++;
5639 if (remove) {
5640 next =
5641 ahc_rem_scb_from_disc_list(ahc, prev, next);
5642 } else {
5643 prev = next;
5644 next = ahc_inb(ahc, SCB_NEXT);
5645 }
5646 if (stop_on_first)
5647 break;
5648 } else {
5649 prev = next;
5650 next = ahc_inb(ahc, SCB_NEXT);
5651 }
5652 }
5653 if (save_state)
5654 ahc_outb(ahc, SCBPTR, active_scb);
5655 return (count);
5656 }
5657
5658 /*
5659 * Remove an SCB from the on chip list of disconnected transactions.
5660 * This is empty/unused if we are not performing SCB paging.
5661 */
5662 static u_int
5663 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5664 {
5665 u_int next;
5666
5667 ahc_outb(ahc, SCBPTR, scbptr);
5668 next = ahc_inb(ahc, SCB_NEXT);
5669
5670 ahc_outb(ahc, SCB_CONTROL, 0);
5671
5672 ahc_add_curscb_to_free_list(ahc);
5673
5674 if (prev != SCB_LIST_NULL) {
5675 ahc_outb(ahc, SCBPTR, prev);
5676 ahc_outb(ahc, SCB_NEXT, next);
5677 } else
5678 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5679
5680 return (next);
5681 }
5682
5683 /*
5684 * Add the SCB as selected by SCBPTR onto the on chip list of
5685 * free hardware SCBs. This list is empty/unused if we are not
5686 * performing SCB paging.
5687 */
5688 static void
5689 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5690 {
5691 /*
5692 * Invalidate the tag so that our abort
5693 * routines don't think it's active.
5694 */
5695 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5696
5697 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5698 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5699 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5700 }
5701 }
5702
5703 /*
5704 * Manipulate the waiting for selection list and return the
5705 * scb that follows the one that we remove.
5706 */
5707 static u_int
5708 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5709 {
5710 u_int curscb, next;
5711
5712 /*
5713 * Select the SCB we want to abort and
5714 * pull the next pointer out of it.
5715 */
5716 curscb = ahc_inb(ahc, SCBPTR);
5717 ahc_outb(ahc, SCBPTR, scbpos);
5718 next = ahc_inb(ahc, SCB_NEXT);
5719
5720 /* Clear the necessary fields */
5721 ahc_outb(ahc, SCB_CONTROL, 0);
5722
5723 ahc_add_curscb_to_free_list(ahc);
5724
5725 /* update the waiting list */
5726 if (prev == SCB_LIST_NULL) {
5727 /* First in the list */
5728 ahc_outb(ahc, WAITING_SCBH, next);
5729
5730 /*
5731 * Ensure we aren't attempting to perform
5732 * selection for this entry.
5733 */
5734 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5735 } else {
5736 /*
5737 * Select the scb that pointed to us
5738 * and update its next pointer.
5739 */
5740 ahc_outb(ahc, SCBPTR, prev);
5741 ahc_outb(ahc, SCB_NEXT, next);
5742 }
5743
5744 /*
5745 * Point us back at the original scb position.
5746 */
5747 ahc_outb(ahc, SCBPTR, curscb);
5748 return next;
5749 }
5750
5751 /******************************** Error Handling ******************************/
5752 /*
5753 * Abort all SCBs that match the given description (target/channel/lun/tag),
5754 * setting their status to the passed in status if the status has not already
5755 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5756 * is paused before it is called.
5757 */
5758 int
5759 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5760 int lun, u_int tag, role_t role, uint32_t status)
5761 {
5762 struct scb *scbp;
5763 struct scb *scbp_next;
5764 u_int active_scb;
5765 int i, j;
5766 int maxtarget;
5767 int minlun;
5768 int maxlun;
5769
5770 int found;
5771
5772 /*
5773 * Don't attempt to run any queued untagged transactions
5774 * until we are done with the abort process.
5775 */
5776 ahc_freeze_untagged_queues(ahc);
5777
5778 /* restore this when we're done */
5779 active_scb = ahc_inb(ahc, SCBPTR);
5780
5781 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5782 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5783
5784 /*
5785 * Clean out the busy target table for any untagged commands.
5786 */
5787 i = 0;
5788 maxtarget = 16;
5789 if (target != CAM_TARGET_WILDCARD) {
5790 i = target;
5791 if (channel == 'B')
5792 i += 8;
5793 maxtarget = i + 1;
5794 }
5795
5796 if (lun == CAM_LUN_WILDCARD) {
5797
5798 /*
5799 * Unless we are using an SCB based
5800 * busy targets table, there is only
5801 * one table entry for all luns of
5802 * a target.
5803 */
5804 minlun = 0;
5805 maxlun = 1;
5806 if ((ahc->flags & AHC_SCB_BTT) != 0)
5807 maxlun = AHC_NUM_LUNS;
5808 } else {
5809 minlun = lun;
5810 maxlun = lun + 1;
5811 }
5812
5813 if (role != ROLE_TARGET) {
5814 for (;i < maxtarget; i++) {
5815 for (j = minlun;j < maxlun; j++) {
5816 u_int scbid;
5817 u_int tcl;
5818
5819 tcl = BUILD_TCL(i << 4, j);
5820 scbid = ahc_index_busy_tcl(ahc, tcl);
5821 scbp = ahc_lookup_scb(ahc, scbid);
5822 if (scbp == NULL
5823 || ahc_match_scb(ahc, scbp, target, channel,
5824 lun, tag, role) == 0)
5825 continue;
5826 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5827 }
5828 }
5829
5830 /*
5831 * Go through the disconnected list and remove any entries we
5832 * have queued for completion, 0'ing their control byte too.
5833 * We save the active SCB and restore it ourselves, so there
5834 * is no reason for this search to restore it too.
5835 */
5836 ahc_search_disc_list(ahc, target, channel, lun, tag,
5837 /*stop_on_first*/FALSE, /*remove*/TRUE,
5838 /*save_state*/FALSE);
5839 }
5840
5841 /*
5842 * Go through the hardware SCB array looking for commands that
5843 * were active but not on any list. In some cases, these remnants
5844 * might not still have mappings in the scbindex array (e.g. unexpected
5845 * bus free with the same scb queued for an abort). Don't hold this
5846 * against them.
5847 */
5848 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5849 u_int scbid;
5850
5851 ahc_outb(ahc, SCBPTR, i);
5852 scbid = ahc_inb(ahc, SCB_TAG);
5853 scbp = ahc_lookup_scb(ahc, scbid);
5854 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5855 || (scbp != NULL
5856 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5857 ahc_add_curscb_to_free_list(ahc);
5858 }
5859
5860 /*
5861 * Go through the pending CCB list and look for
5862 * commands for this target that are still active.
5863 * These are other tagged commands that were
5864 * disconnected when the reset occurred.
5865 */
5866 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5867 while (scbp_next != NULL) {
5868 scbp = scbp_next;
5869 scbp_next = LIST_NEXT(scbp, pending_links);
5870 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5871 cam_status ostat;
5872
5873 ostat = ahc_get_transaction_status(scbp);
5874 if (ostat == CAM_REQ_INPROG)
5875 ahc_set_transaction_status(scbp, status);
5876 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5877 ahc_freeze_scb(scbp);
5878 if ((scbp->flags & SCB_ACTIVE) == 0)
5879 printf("Inactive SCB on pending list\n");
5880 ahc_done(ahc, scbp);
5881 found++;
5882 }
5883 }
5884 ahc_outb(ahc, SCBPTR, active_scb);
5885 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5886 ahc_release_untagged_queues(ahc);
5887 return found;
5888 }
5889
5890 static void
5891 ahc_reset_current_bus(struct ahc_softc *ahc)
5892 {
5893 uint8_t scsiseq;
5894
5895 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5896 scsiseq = ahc_inb(ahc, SCSISEQ);
5897 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5898 ahc_flush_device_writes(ahc);
5899 ahc_delay(AHC_BUSRESET_DELAY);
5900 /* Turn off the bus reset */
5901 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5902
5903 ahc_clear_intstat(ahc);
5904
5905 /* Re-enable reset interrupts */
5906 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5907 }
5908
5909 int
5910 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5911 {
5912 struct ahc_devinfo devinfo;
5913 u_int initiator, target, max_scsiid;
5914 u_int sblkctl;
5915 u_int scsiseq;
5916 u_int simode1;
5917 int found;
5918 int restart_needed;
5919 char cur_channel;
5920
5921 ahc->pending_device = NULL;
5922
5923 ahc_compile_devinfo(&devinfo,
5924 CAM_TARGET_WILDCARD,
5925 CAM_TARGET_WILDCARD,
5926 CAM_LUN_WILDCARD,
5927 channel, ROLE_UNKNOWN);
5928 ahc_pause(ahc);
5929
5930 /* Make sure the sequencer is in a safe location. */
5931 ahc_clear_critical_section(ahc);
5932
5933 /*
5934 * Run our command complete fifos to ensure that we perform
5935 * completion processing on any commands that 'completed'
5936 * before the reset occurred.
5937 */
5938 ahc_run_qoutfifo(ahc);
5939 #ifdef AHC_TARGET_MODE
5940 /*
5941 * XXX - In Twin mode, the tqinfifo may have commands
5942 * for an unaffected channel in it. However, if
5943 * we have run out of ATIO resources to drain that
5944 * queue, we may not get them all out here. Further,
5945 * the blocked transactions for the reset channel
5946 * should just be killed off, irrespecitve of whether
5947 * we are blocked on ATIO resources. Write a routine
5948 * to compact the tqinfifo appropriately.
5949 */
5950 if ((ahc->flags & AHC_TARGETROLE) != 0) {
5951 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5952 }
5953 #endif
5954
5955 /*
5956 * Reset the bus if we are initiating this reset
5957 */
5958 sblkctl = ahc_inb(ahc, SBLKCTL);
5959 cur_channel = 'A';
5960 if ((ahc->features & AHC_TWIN) != 0
5961 && ((sblkctl & SELBUSB) != 0))
5962 cur_channel = 'B';
5963 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5964 if (cur_channel != channel) {
5965 /* Case 1: Command for another bus is active
5966 * Stealthily reset the other bus without
5967 * upsetting the current bus.
5968 */
5969 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5970 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5971 #ifdef AHC_TARGET_MODE
5972 /*
5973 * Bus resets clear ENSELI, so we cannot
5974 * defer re-enabling bus reset interrupts
5975 * if we are in target mode.
5976 */
5977 if ((ahc->flags & AHC_TARGETROLE) != 0)
5978 simode1 |= ENSCSIRST;
5979 #endif
5980 ahc_outb(ahc, SIMODE1, simode1);
5981 if (initiate_reset)
5982 ahc_reset_current_bus(ahc);
5983 ahc_clear_intstat(ahc);
5984 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5985 ahc_outb(ahc, SBLKCTL, sblkctl);
5986 restart_needed = FALSE;
5987 } else {
5988 /* Case 2: A command from this bus is active or we're idle */
5989 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5990 #ifdef AHC_TARGET_MODE
5991 /*
5992 * Bus resets clear ENSELI, so we cannot
5993 * defer re-enabling bus reset interrupts
5994 * if we are in target mode.
5995 */
5996 if ((ahc->flags & AHC_TARGETROLE) != 0)
5997 simode1 |= ENSCSIRST;
5998 #endif
5999 ahc_outb(ahc, SIMODE1, simode1);
6000 if (initiate_reset)
6001 ahc_reset_current_bus(ahc);
6002 ahc_clear_intstat(ahc);
6003 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6004 restart_needed = TRUE;
6005 }
6006
6007 /*
6008 * Clean up all the state information for the
6009 * pending transactions on this bus.
6010 */
6011 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6012 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6013 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6014
6015 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6016
6017 #ifdef AHC_TARGET_MODE
6018 /*
6019 * Send an immediate notify ccb to all target more peripheral
6020 * drivers affected by this action.
6021 */
6022 for (target = 0; target <= max_scsiid; target++) {
6023 struct ahc_tmode_tstate* tstate;
6024 u_int lun;
6025
6026 tstate = ahc->enabled_targets[target];
6027 if (tstate == NULL)
6028 continue;
6029 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6030 struct ahc_tmode_lstate* lstate;
6031
6032 lstate = tstate->enabled_luns[lun];
6033 if (lstate == NULL)
6034 continue;
6035
6036 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6037 EVENT_TYPE_BUS_RESET, /*arg*/0);
6038 ahc_send_lstate_events(ahc, lstate);
6039 }
6040 }
6041 #endif
6042 /* Notify the XPT that a bus reset occurred */
6043 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6044 CAM_LUN_WILDCARD, AC_BUS_RESET);
6045
6046 /*
6047 * Revert to async/narrow transfers until we renegotiate.
6048 */
6049 for (target = 0; target <= max_scsiid; target++) {
6050
6051 if (ahc->enabled_targets[target] == NULL)
6052 continue;
6053 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6054 struct ahc_devinfo devinfo;
6055
6056 ahc_compile_devinfo(&devinfo, target, initiator,
6057 CAM_LUN_WILDCARD,
6058 channel, ROLE_UNKNOWN);
6059 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6060 AHC_TRANS_CUR, /*paused*/TRUE);
6061 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6062 /*period*/0, /*offset*/0,
6063 /*ppr_options*/0, AHC_TRANS_CUR,
6064 /*paused*/TRUE);
6065 }
6066 }
6067
6068 if (restart_needed)
6069 ahc_restart(ahc);
6070 else
6071 ahc_unpause(ahc);
6072 return found;
6073 }
6074
6075
6076 /***************************** Residual Processing ****************************/
6077 /*
6078 * Calculate the residual for a just completed SCB.
6079 */
6080 void
6081 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6082 {
6083 struct hardware_scb *hscb;
6084 struct status_pkt *spkt;
6085 uint32_t sgptr;
6086 uint32_t resid_sgptr;
6087 uint32_t resid;
6088
6089 /*
6090 * 5 cases.
6091 * 1) No residual.
6092 * SG_RESID_VALID clear in sgptr.
6093 * 2) Transferless command
6094 * 3) Never performed any transfers.
6095 * sgptr has SG_FULL_RESID set.
6096 * 4) No residual but target did not
6097 * save data pointers after the
6098 * last transfer, so sgptr was
6099 * never updated.
6100 * 5) We have a partial residual.
6101 * Use residual_sgptr to determine
6102 * where we are.
6103 */
6104
6105 hscb = scb->hscb;
6106 sgptr = ahc_le32toh(hscb->sgptr);
6107 if ((sgptr & SG_RESID_VALID) == 0)
6108 /* Case 1 */
6109 return;
6110 sgptr &= ~SG_RESID_VALID;
6111
6112 if ((sgptr & SG_LIST_NULL) != 0)
6113 /* Case 2 */
6114 return;
6115
6116 spkt = &hscb->shared_data.status;
6117 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6118 if ((sgptr & SG_FULL_RESID) != 0) {
6119 /* Case 3 */
6120 resid = ahc_get_transfer_length(scb);
6121 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6122 /* Case 4 */
6123 return;
6124 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6125 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6126 } else {
6127 struct ahc_dma_seg *sg;
6128
6129 /*
6130 * Remainder of the SG where the transfer
6131 * stopped.
6132 */
6133 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6134 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6135
6136 /* The residual sg_ptr always points to the next sg */
6137 sg--;
6138
6139 /*
6140 * Add up the contents of all residual
6141 * SG segments that are after the SG where
6142 * the transfer stopped.
6143 */
6144 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6145 sg++;
6146 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6147 }
6148 }
6149 if ((scb->flags & SCB_SENSE) == 0)
6150 ahc_set_residual(scb, resid);
6151 else
6152 ahc_set_sense_residual(scb, resid);
6153
6154 #ifdef AHC_DEBUG
6155 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6156 ahc_print_path(ahc, scb);
6157 printf("Handled %sResidual of %d bytes\n",
6158 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6159 }
6160 #endif
6161 }
6162
6163 /******************************* Target Mode **********************************/
6164 #ifdef AHC_TARGET_MODE
6165 /*
6166 * Add a target mode event to this lun's queue
6167 */
6168 static void
6169 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6170 u_int initiator_id, u_int event_type, u_int event_arg)
6171 {
6172 struct ahc_tmode_event *event;
6173 int pending;
6174
6175 xpt_freeze_devq(lstate->path, /*count*/1);
6176 if (lstate->event_w_idx >= lstate->event_r_idx)
6177 pending = lstate->event_w_idx - lstate->event_r_idx;
6178 else
6179 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6180 - (lstate->event_r_idx - lstate->event_w_idx);
6181
6182 if (event_type == EVENT_TYPE_BUS_RESET
6183 || event_type == MSG_BUS_DEV_RESET) {
6184 /*
6185 * Any earlier events are irrelevant, so reset our buffer.
6186 * This has the effect of allowing us to deal with reset
6187 * floods (an external device holding down the reset line)
6188 * without losing the event that is really interesting.
6189 */
6190 lstate->event_r_idx = 0;
6191 lstate->event_w_idx = 0;
6192 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6193 }
6194
6195 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6196 xpt_print_path(lstate->path);
6197 printf("immediate event %x:%x lost\n",
6198 lstate->event_buffer[lstate->event_r_idx].event_type,
6199 lstate->event_buffer[lstate->event_r_idx].event_arg);
6200 lstate->event_r_idx++;
6201 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6202 lstate->event_r_idx = 0;
6203 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6204 }
6205
6206 event = &lstate->event_buffer[lstate->event_w_idx];
6207 event->initiator_id = initiator_id;
6208 event->event_type = event_type;
6209 event->event_arg = event_arg;
6210 lstate->event_w_idx++;
6211 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6212 lstate->event_w_idx = 0;
6213 }
6214
6215 /*
6216 * Send any target mode events queued up waiting
6217 * for immediate notify resources.
6218 */
6219 void
6220 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6221 {
6222 struct ccb_hdr *ccbh;
6223 struct ccb_immed_notify *inot;
6224
6225 while (lstate->event_r_idx != lstate->event_w_idx
6226 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6227 struct ahc_tmode_event *event;
6228
6229 event = &lstate->event_buffer[lstate->event_r_idx];
6230 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6231 inot = (struct ccb_immed_notify *)ccbh;
6232 switch (event->event_type) {
6233 case EVENT_TYPE_BUS_RESET:
6234 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6235 break;
6236 default:
6237 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6238 inot->message_args[0] = event->event_type;
6239 inot->message_args[1] = event->event_arg;
6240 break;
6241 }
6242 inot->initiator_id = event->initiator_id;
6243 inot->sense_len = 0;
6244 xpt_done((union ccb *)inot);
6245 lstate->event_r_idx++;
6246 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6247 lstate->event_r_idx = 0;
6248 }
6249 }
6250 #endif
6251
6252 /******************** Sequencer Program Patching/Download *********************/
6253
6254 #ifdef AHC_DUMP_SEQ
6255 void
6256 ahc_dumpseq(struct ahc_softc* ahc)
6257 {
6258 int i;
6259
6260 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6261 ahc_outb(ahc, SEQADDR0, 0);
6262 ahc_outb(ahc, SEQADDR1, 0);
6263 for (i = 0; i < ahc->instruction_ram_size; i++) {
6264 uint8_t ins_bytes[4];
6265
6266 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6267 printf("0x%08x\n", ins_bytes[0] << 24
6268 | ins_bytes[1] << 16
6269 | ins_bytes[2] << 8
6270 | ins_bytes[3]);
6271 }
6272 }
6273 #endif
6274
6275 static int
6276 ahc_loadseq(struct ahc_softc *ahc)
6277 {
6278 struct cs cs_table[num_critical_sections];
6279 u_int begin_set[num_critical_sections];
6280 u_int end_set[num_critical_sections];
6281 struct patch *cur_patch;
6282 u_int cs_count;
6283 u_int cur_cs;
6284 u_int i;
6285 u_int skip_addr;
6286 u_int sg_prefetch_cnt;
6287 int downloaded;
6288 uint8_t download_consts[7];
6289
6290 /*
6291 * Start out with 0 critical sections
6292 * that apply to this firmware load.
6293 */
6294 cs_count = 0;
6295 cur_cs = 0;
6296 memset(begin_set, 0, sizeof(begin_set));
6297 memset(end_set, 0, sizeof(end_set));
6298
6299 /* Setup downloadable constant table */
6300 download_consts[QOUTFIFO_OFFSET] = 0;
6301 if (ahc->targetcmds != NULL)
6302 download_consts[QOUTFIFO_OFFSET] += 32;
6303 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6304 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6305 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6306 sg_prefetch_cnt = ahc->pci_cachesize;
6307 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6308 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6309 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6310 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6311 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6312
6313 cur_patch = patches;
6314 downloaded = 0;
6315 skip_addr = 0;
6316 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6317 ahc_outb(ahc, SEQADDR0, 0);
6318 ahc_outb(ahc, SEQADDR1, 0);
6319
6320 for (i = 0; i < sizeof(seqprog)/4; i++) {
6321 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6322 /*
6323 * Don't download this instruction as it
6324 * is in a patch that was removed.
6325 */
6326 continue;
6327 }
6328
6329 if (downloaded == ahc->instruction_ram_size) {
6330 /*
6331 * We're about to exceed the instruction
6332 * storage capacity for this chip. Fail
6333 * the load.
6334 */
6335 printf("\n%s: Program too large for instruction memory "
6336 "size of %d!\n", ahc_name(ahc),
6337 ahc->instruction_ram_size);
6338 return (ENOMEM);
6339 }
6340
6341 /*
6342 * Move through the CS table until we find a CS
6343 * that might apply to this instruction.
6344 */
6345 for (; cur_cs < num_critical_sections; cur_cs++) {
6346 if (critical_sections[cur_cs].end <= i) {
6347 if (begin_set[cs_count] == TRUE
6348 && end_set[cs_count] == FALSE) {
6349 cs_table[cs_count].end = downloaded;
6350 end_set[cs_count] = TRUE;
6351 cs_count++;
6352 }
6353 continue;
6354 }
6355 if (critical_sections[cur_cs].begin <= i
6356 && begin_set[cs_count] == FALSE) {
6357 cs_table[cs_count].begin = downloaded;
6358 begin_set[cs_count] = TRUE;
6359 }
6360 break;
6361 }
6362 ahc_download_instr(ahc, i, download_consts);
6363 downloaded++;
6364 }
6365
6366 ahc->num_critical_sections = cs_count;
6367 if (cs_count != 0) {
6368
6369 cs_count *= sizeof(struct cs);
6370 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6371 if (ahc->critical_sections == NULL)
6372 panic("ahc_loadseq: Could not malloc");
6373 memcpy(ahc->critical_sections, cs_table, cs_count);
6374 }
6375 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6376
6377 if (bootverbose) {
6378 printf(" %d instructions downloaded\n", downloaded);
6379 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6380 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6381 }
6382 return (0);
6383 }
6384
6385 static int
6386 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6387 u_int start_instr, u_int *skip_addr)
6388 {
6389 struct patch *cur_patch;
6390 struct patch *last_patch;
6391 u_int num_patches;
6392
6393 num_patches = ARRAY_SIZE(patches);
6394 last_patch = &patches[num_patches];
6395 cur_patch = *start_patch;
6396
6397 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6398
6399 if (cur_patch->patch_func(ahc) == 0) {
6400
6401 /* Start rejecting code */
6402 *skip_addr = start_instr + cur_patch->skip_instr;
6403 cur_patch += cur_patch->skip_patch;
6404 } else {
6405 /* Accepted this patch. Advance to the next
6406 * one and wait for our intruction pointer to
6407 * hit this point.
6408 */
6409 cur_patch++;
6410 }
6411 }
6412
6413 *start_patch = cur_patch;
6414 if (start_instr < *skip_addr)
6415 /* Still skipping */
6416 return (0);
6417
6418 return (1);
6419 }
6420
6421 static void
6422 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6423 {
6424 union ins_formats instr;
6425 struct ins_format1 *fmt1_ins;
6426 struct ins_format3 *fmt3_ins;
6427 u_int opcode;
6428
6429 /*
6430 * The firmware is always compiled into a little endian format.
6431 */
6432 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6433
6434 fmt1_ins = &instr.format1;
6435 fmt3_ins = NULL;
6436
6437 /* Pull the opcode */
6438 opcode = instr.format1.opcode;
6439 switch (opcode) {
6440 case AIC_OP_JMP:
6441 case AIC_OP_JC:
6442 case AIC_OP_JNC:
6443 case AIC_OP_CALL:
6444 case AIC_OP_JNE:
6445 case AIC_OP_JNZ:
6446 case AIC_OP_JE:
6447 case AIC_OP_JZ:
6448 {
6449 struct patch *cur_patch;
6450 int address_offset;
6451 u_int address;
6452 u_int skip_addr;
6453 u_int i;
6454
6455 fmt3_ins = &instr.format3;
6456 address_offset = 0;
6457 address = fmt3_ins->address;
6458 cur_patch = patches;
6459 skip_addr = 0;
6460
6461 for (i = 0; i < address;) {
6462
6463 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6464
6465 if (skip_addr > i) {
6466 int end_addr;
6467
6468 end_addr = min(address, skip_addr);
6469 address_offset += end_addr - i;
6470 i = skip_addr;
6471 } else {
6472 i++;
6473 }
6474 }
6475 address -= address_offset;
6476 fmt3_ins->address = address;
6477 /* FALLTHROUGH */
6478 }
6479 case AIC_OP_OR:
6480 case AIC_OP_AND:
6481 case AIC_OP_XOR:
6482 case AIC_OP_ADD:
6483 case AIC_OP_ADC:
6484 case AIC_OP_BMOV:
6485 if (fmt1_ins->parity != 0) {
6486 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6487 }
6488 fmt1_ins->parity = 0;
6489 if ((ahc->features & AHC_CMD_CHAN) == 0
6490 && opcode == AIC_OP_BMOV) {
6491 /*
6492 * Block move was added at the same time
6493 * as the command channel. Verify that
6494 * this is only a move of a single element
6495 * and convert the BMOV to a MOV
6496 * (AND with an immediate of FF).
6497 */
6498 if (fmt1_ins->immediate != 1)
6499 panic("%s: BMOV not supported\n",
6500 ahc_name(ahc));
6501 fmt1_ins->opcode = AIC_OP_AND;
6502 fmt1_ins->immediate = 0xff;
6503 }
6504 /* FALLTHROUGH */
6505 case AIC_OP_ROL:
6506 if ((ahc->features & AHC_ULTRA2) != 0) {
6507 int i, count;
6508
6509 /* Calculate odd parity for the instruction */
6510 for (i = 0, count = 0; i < 31; i++) {
6511 uint32_t mask;
6512
6513 mask = 0x01 << i;
6514 if ((instr.integer & mask) != 0)
6515 count++;
6516 }
6517 if ((count & 0x01) == 0)
6518 instr.format1.parity = 1;
6519 } else {
6520 /* Compress the instruction for older sequencers */
6521 if (fmt3_ins != NULL) {
6522 instr.integer =
6523 fmt3_ins->immediate
6524 | (fmt3_ins->source << 8)
6525 | (fmt3_ins->address << 16)
6526 | (fmt3_ins->opcode << 25);
6527 } else {
6528 instr.integer =
6529 fmt1_ins->immediate
6530 | (fmt1_ins->source << 8)
6531 | (fmt1_ins->destination << 16)
6532 | (fmt1_ins->ret << 24)
6533 | (fmt1_ins->opcode << 25);
6534 }
6535 }
6536 /* The sequencer is a little endian cpu */
6537 instr.integer = ahc_htole32(instr.integer);
6538 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6539 break;
6540 default:
6541 panic("Unknown opcode encountered in seq program");
6542 break;
6543 }
6544 }
6545
6546 int
6547 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6548 const char *name, u_int address, u_int value,
6549 u_int *cur_column, u_int wrap_point)
6550 {
6551 int printed;
6552 u_int printed_mask;
6553
6554 if (cur_column != NULL && *cur_column >= wrap_point) {
6555 printf("\n");
6556 *cur_column = 0;
6557 }
6558 printed = printf("%s[0x%x]", name, value);
6559 if (table == NULL) {
6560 printed += printf(" ");
6561 *cur_column += printed;
6562 return (printed);
6563 }
6564 printed_mask = 0;
6565 while (printed_mask != 0xFF) {
6566 int entry;
6567
6568 for (entry = 0; entry < num_entries; entry++) {
6569 if (((value & table[entry].mask)
6570 != table[entry].value)
6571 || ((printed_mask & table[entry].mask)
6572 == table[entry].mask))
6573 continue;
6574
6575 printed += printf("%s%s",
6576 printed_mask == 0 ? ":(" : "|",
6577 table[entry].name);
6578 printed_mask |= table[entry].mask;
6579
6580 break;
6581 }
6582 if (entry >= num_entries)
6583 break;
6584 }
6585 if (printed_mask != 0)
6586 printed += printf(") ");
6587 else
6588 printed += printf(" ");
6589 if (cur_column != NULL)
6590 *cur_column += printed;
6591 return (printed);
6592 }
6593
6594 void
6595 ahc_dump_card_state(struct ahc_softc *ahc)
6596 {
6597 struct scb *scb;
6598 struct scb_tailq *untagged_q;
6599 u_int cur_col;
6600 int paused;
6601 int target;
6602 int maxtarget;
6603 int i;
6604 uint8_t last_phase;
6605 uint8_t qinpos;
6606 uint8_t qintail;
6607 uint8_t qoutpos;
6608 uint8_t scb_index;
6609 uint8_t saved_scbptr;
6610
6611 if (ahc_is_paused(ahc)) {
6612 paused = 1;
6613 } else {
6614 paused = 0;
6615 ahc_pause(ahc);
6616 }
6617
6618 saved_scbptr = ahc_inb(ahc, SCBPTR);
6619 last_phase = ahc_inb(ahc, LASTPHASE);
6620 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6621 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6622 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6623 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6624 if (paused)
6625 printf("Card was paused\n");
6626 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6627 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6628 ahc_inb(ahc, ARG_2));
6629 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6630 ahc_inb(ahc, SCBPTR));
6631 cur_col = 0;
6632 if ((ahc->features & AHC_DT) != 0)
6633 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6634 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6635 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6636 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6637 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6638 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6639 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6640 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6641 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6642 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6643 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6644 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6645 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6646 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6647 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6648 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6649 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6650 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6651 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6652 if (cur_col != 0)
6653 printf("\n");
6654 printf("STACK:");
6655 for (i = 0; i < STACK_SIZE; i++)
6656 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6657 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6658 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6659 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6660 /* QINFIFO */
6661 printf("QINFIFO entries: ");
6662 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6663 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6664 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6665 } else
6666 qinpos = ahc_inb(ahc, QINPOS);
6667 qintail = ahc->qinfifonext;
6668 while (qinpos != qintail) {
6669 printf("%d ", ahc->qinfifo[qinpos]);
6670 qinpos++;
6671 }
6672 printf("\n");
6673
6674 printf("Waiting Queue entries: ");
6675 scb_index = ahc_inb(ahc, WAITING_SCBH);
6676 i = 0;
6677 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6678 ahc_outb(ahc, SCBPTR, scb_index);
6679 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6680 scb_index = ahc_inb(ahc, SCB_NEXT);
6681 }
6682 printf("\n");
6683
6684 printf("Disconnected Queue entries: ");
6685 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6686 i = 0;
6687 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6688 ahc_outb(ahc, SCBPTR, scb_index);
6689 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6690 scb_index = ahc_inb(ahc, SCB_NEXT);
6691 }
6692 printf("\n");
6693
6694 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6695 printf("QOUTFIFO entries: ");
6696 qoutpos = ahc->qoutfifonext;
6697 i = 0;
6698 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6699 printf("%d ", ahc->qoutfifo[qoutpos]);
6700 qoutpos++;
6701 }
6702 printf("\n");
6703
6704 printf("Sequencer Free SCB List: ");
6705 scb_index = ahc_inb(ahc, FREE_SCBH);
6706 i = 0;
6707 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6708 ahc_outb(ahc, SCBPTR, scb_index);
6709 printf("%d ", scb_index);
6710 scb_index = ahc_inb(ahc, SCB_NEXT);
6711 }
6712 printf("\n");
6713
6714 printf("Sequencer SCB Info: ");
6715 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6716 ahc_outb(ahc, SCBPTR, i);
6717 cur_col = printf("\n%3d ", i);
6718
6719 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6720 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6721 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6722 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6723 }
6724 printf("\n");
6725
6726 printf("Pending list: ");
6727 i = 0;
6728 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6729 if (i++ > 256)
6730 break;
6731 cur_col = printf("\n%3d ", scb->hscb->tag);
6732 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6733 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6734 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6735 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6736 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6737 printf("(");
6738 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6739 &cur_col, 60);
6740 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6741 printf(")");
6742 }
6743 }
6744 printf("\n");
6745
6746 printf("Kernel Free SCB list: ");
6747 i = 0;
6748 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6749 if (i++ > 256)
6750 break;
6751 printf("%d ", scb->hscb->tag);
6752 }
6753 printf("\n");
6754
6755 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6756 for (target = 0; target <= maxtarget; target++) {
6757 untagged_q = &ahc->untagged_queues[target];
6758 if (TAILQ_FIRST(untagged_q) == NULL)
6759 continue;
6760 printf("Untagged Q(%d): ", target);
6761 i = 0;
6762 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6763 if (i++ > 256)
6764 break;
6765 printf("%d ", scb->hscb->tag);
6766 }
6767 printf("\n");
6768 }
6769
6770 ahc_platform_dump_card_state(ahc);
6771 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6772 ahc_outb(ahc, SCBPTR, saved_scbptr);
6773 if (paused == 0)
6774 ahc_unpause(ahc);
6775 }
6776
6777 /************************* Target Mode ****************************************/
6778 #ifdef AHC_TARGET_MODE
6779 cam_status
6780 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6781 struct ahc_tmode_tstate **tstate,
6782 struct ahc_tmode_lstate **lstate,
6783 int notfound_failure)
6784 {
6785
6786 if ((ahc->features & AHC_TARGETMODE) == 0)
6787 return (CAM_REQ_INVALID);
6788
6789 /*
6790 * Handle the 'black hole' device that sucks up
6791 * requests to unattached luns on enabled targets.
6792 */
6793 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6794 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6795 *tstate = NULL;
6796 *lstate = ahc->black_hole;
6797 } else {
6798 u_int max_id;
6799
6800 max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
6801 if (ccb->ccb_h.target_id >= max_id)
6802 return (CAM_TID_INVALID);
6803
6804 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6805 return (CAM_LUN_INVALID);
6806
6807 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6808 *lstate = NULL;
6809 if (*tstate != NULL)
6810 *lstate =
6811 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6812 }
6813
6814 if (notfound_failure != 0 && *lstate == NULL)
6815 return (CAM_PATH_INVALID);
6816
6817 return (CAM_REQ_CMP);
6818 }
6819
6820 void
6821 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6822 {
6823 struct ahc_tmode_tstate *tstate;
6824 struct ahc_tmode_lstate *lstate;
6825 struct ccb_en_lun *cel;
6826 cam_status status;
6827 u_long s;
6828 u_int target;
6829 u_int lun;
6830 u_int target_mask;
6831 u_int our_id;
6832 int error;
6833 char channel;
6834
6835 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6836 /*notfound_failure*/FALSE);
6837
6838 if (status != CAM_REQ_CMP) {
6839 ccb->ccb_h.status = status;
6840 return;
6841 }
6842
6843 if (cam_sim_bus(sim) == 0)
6844 our_id = ahc->our_id;
6845 else
6846 our_id = ahc->our_id_b;
6847
6848 if (ccb->ccb_h.target_id != our_id) {
6849 /*
6850 * our_id represents our initiator ID, or
6851 * the ID of the first target to have an
6852 * enabled lun in target mode. There are
6853 * two cases that may preclude enabling a
6854 * target id other than our_id.
6855 *
6856 * o our_id is for an active initiator role.
6857 * Since the hardware does not support
6858 * reselections to the initiator role at
6859 * anything other than our_id, and our_id
6860 * is used by the hardware to indicate the
6861 * ID to use for both select-out and
6862 * reselect-out operations, the only target
6863 * ID we can support in this mode is our_id.
6864 *
6865 * o The MULTARGID feature is not available and
6866 * a previous target mode ID has been enabled.
6867 */
6868 if ((ahc->features & AHC_MULTIROLE) != 0) {
6869
6870 if ((ahc->features & AHC_MULTI_TID) != 0
6871 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6872 /*
6873 * Only allow additional targets if
6874 * the initiator role is disabled.
6875 * The hardware cannot handle a re-select-in
6876 * on the initiator id during a re-select-out
6877 * on a different target id.
6878 */
6879 status = CAM_TID_INVALID;
6880 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6881 || ahc->enabled_luns > 0) {
6882 /*
6883 * Only allow our target id to change
6884 * if the initiator role is not configured
6885 * and there are no enabled luns which
6886 * are attached to the currently registered
6887 * scsi id.
6888 */
6889 status = CAM_TID_INVALID;
6890 }
6891 } else if ((ahc->features & AHC_MULTI_TID) == 0
6892 && ahc->enabled_luns > 0) {
6893
6894 status = CAM_TID_INVALID;
6895 }
6896 }
6897
6898 if (status != CAM_REQ_CMP) {
6899 ccb->ccb_h.status = status;
6900 return;
6901 }
6902
6903 /*
6904 * We now have an id that is valid.
6905 * If we aren't in target mode, switch modes.
6906 */
6907 if ((ahc->flags & AHC_TARGETROLE) == 0
6908 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6909 u_long s;
6910 ahc_flag saved_flags;
6911
6912 printf("Configuring Target Mode\n");
6913 ahc_lock(ahc, &s);
6914 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6915 ccb->ccb_h.status = CAM_BUSY;
6916 ahc_unlock(ahc, &s);
6917 return;
6918 }
6919 saved_flags = ahc->flags;
6920 ahc->flags |= AHC_TARGETROLE;
6921 if ((ahc->features & AHC_MULTIROLE) == 0)
6922 ahc->flags &= ~AHC_INITIATORROLE;
6923 ahc_pause(ahc);
6924 error = ahc_loadseq(ahc);
6925 if (error != 0) {
6926 /*
6927 * Restore original configuration and notify
6928 * the caller that we cannot support target mode.
6929 * Since the adapter started out in this
6930 * configuration, the firmware load will succeed,
6931 * so there is no point in checking ahc_loadseq's
6932 * return value.
6933 */
6934 ahc->flags = saved_flags;
6935 (void)ahc_loadseq(ahc);
6936 ahc_restart(ahc);
6937 ahc_unlock(ahc, &s);
6938 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
6939 return;
6940 }
6941 ahc_restart(ahc);
6942 ahc_unlock(ahc, &s);
6943 }
6944 cel = &ccb->cel;
6945 target = ccb->ccb_h.target_id;
6946 lun = ccb->ccb_h.target_lun;
6947 channel = SIM_CHANNEL(ahc, sim);
6948 target_mask = 0x01 << target;
6949 if (channel == 'B')
6950 target_mask <<= 8;
6951
6952 if (cel->enable != 0) {
6953 u_int scsiseq;
6954
6955 /* Are we already enabled?? */
6956 if (lstate != NULL) {
6957 xpt_print_path(ccb->ccb_h.path);
6958 printf("Lun already enabled\n");
6959 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6960 return;
6961 }
6962
6963 if (cel->grp6_len != 0
6964 || cel->grp7_len != 0) {
6965 /*
6966 * Don't (yet?) support vendor
6967 * specific commands.
6968 */
6969 ccb->ccb_h.status = CAM_REQ_INVALID;
6970 printf("Non-zero Group Codes\n");
6971 return;
6972 }
6973
6974 /*
6975 * Seems to be okay.
6976 * Setup our data structures.
6977 */
6978 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6979 tstate = ahc_alloc_tstate(ahc, target, channel);
6980 if (tstate == NULL) {
6981 xpt_print_path(ccb->ccb_h.path);
6982 printf("Couldn't allocate tstate\n");
6983 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6984 return;
6985 }
6986 }
6987 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
6988 if (lstate == NULL) {
6989 xpt_print_path(ccb->ccb_h.path);
6990 printf("Couldn't allocate lstate\n");
6991 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6992 return;
6993 }
6994 memset(lstate, 0, sizeof(*lstate));
6995 status = xpt_create_path(&lstate->path, /*periph*/NULL,
6996 xpt_path_path_id(ccb->ccb_h.path),
6997 xpt_path_target_id(ccb->ccb_h.path),
6998 xpt_path_lun_id(ccb->ccb_h.path));
6999 if (status != CAM_REQ_CMP) {
7000 free(lstate, M_DEVBUF);
7001 xpt_print_path(ccb->ccb_h.path);
7002 printf("Couldn't allocate path\n");
7003 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7004 return;
7005 }
7006 SLIST_INIT(&lstate->accept_tios);
7007 SLIST_INIT(&lstate->immed_notifies);
7008 ahc_lock(ahc, &s);
7009 ahc_pause(ahc);
7010 if (target != CAM_TARGET_WILDCARD) {
7011 tstate->enabled_luns[lun] = lstate;
7012 ahc->enabled_luns++;
7013
7014 if ((ahc->features & AHC_MULTI_TID) != 0) {
7015 u_int targid_mask;
7016
7017 targid_mask = ahc_inb(ahc, TARGID)
7018 | (ahc_inb(ahc, TARGID + 1) << 8);
7019
7020 targid_mask |= target_mask;
7021 ahc_outb(ahc, TARGID, targid_mask);
7022 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7023
7024 ahc_update_scsiid(ahc, targid_mask);
7025 } else {
7026 u_int our_id;
7027 char channel;
7028
7029 channel = SIM_CHANNEL(ahc, sim);
7030 our_id = SIM_SCSI_ID(ahc, sim);
7031
7032 /*
7033 * This can only happen if selections
7034 * are not enabled
7035 */
7036 if (target != our_id) {
7037 u_int sblkctl;
7038 char cur_channel;
7039 int swap;
7040
7041 sblkctl = ahc_inb(ahc, SBLKCTL);
7042 cur_channel = (sblkctl & SELBUSB)
7043 ? 'B' : 'A';
7044 if ((ahc->features & AHC_TWIN) == 0)
7045 cur_channel = 'A';
7046 swap = cur_channel != channel;
7047 if (channel == 'A')
7048 ahc->our_id = target;
7049 else
7050 ahc->our_id_b = target;
7051
7052 if (swap)
7053 ahc_outb(ahc, SBLKCTL,
7054 sblkctl ^ SELBUSB);
7055
7056 ahc_outb(ahc, SCSIID, target);
7057
7058 if (swap)
7059 ahc_outb(ahc, SBLKCTL, sblkctl);
7060 }
7061 }
7062 } else
7063 ahc->black_hole = lstate;
7064 /* Allow select-in operations */
7065 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7066 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7067 scsiseq |= ENSELI;
7068 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7069 scsiseq = ahc_inb(ahc, SCSISEQ);
7070 scsiseq |= ENSELI;
7071 ahc_outb(ahc, SCSISEQ, scsiseq);
7072 }
7073 ahc_unpause(ahc);
7074 ahc_unlock(ahc, &s);
7075 ccb->ccb_h.status = CAM_REQ_CMP;
7076 xpt_print_path(ccb->ccb_h.path);
7077 printf("Lun now enabled for target mode\n");
7078 } else {
7079 struct scb *scb;
7080 int i, empty;
7081
7082 if (lstate == NULL) {
7083 ccb->ccb_h.status = CAM_LUN_INVALID;
7084 return;
7085 }
7086
7087 ahc_lock(ahc, &s);
7088
7089 ccb->ccb_h.status = CAM_REQ_CMP;
7090 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7091 struct ccb_hdr *ccbh;
7092
7093 ccbh = &scb->io_ctx->ccb_h;
7094 if (ccbh->func_code == XPT_CONT_TARGET_IO
7095 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7096 printf("CTIO pending\n");
7097 ccb->ccb_h.status = CAM_REQ_INVALID;
7098 ahc_unlock(ahc, &s);
7099 return;
7100 }
7101 }
7102
7103 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7104 printf("ATIOs pending\n");
7105 ccb->ccb_h.status = CAM_REQ_INVALID;
7106 }
7107
7108 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7109 printf("INOTs pending\n");
7110 ccb->ccb_h.status = CAM_REQ_INVALID;
7111 }
7112
7113 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7114 ahc_unlock(ahc, &s);
7115 return;
7116 }
7117
7118 xpt_print_path(ccb->ccb_h.path);
7119 printf("Target mode disabled\n");
7120 xpt_free_path(lstate->path);
7121 free(lstate, M_DEVBUF);
7122
7123 ahc_pause(ahc);
7124 /* Can we clean up the target too? */
7125 if (target != CAM_TARGET_WILDCARD) {
7126 tstate->enabled_luns[lun] = NULL;
7127 ahc->enabled_luns--;
7128 for (empty = 1, i = 0; i < 8; i++)
7129 if (tstate->enabled_luns[i] != NULL) {
7130 empty = 0;
7131 break;
7132 }
7133
7134 if (empty) {
7135 ahc_free_tstate(ahc, target, channel,
7136 /*force*/FALSE);
7137 if (ahc->features & AHC_MULTI_TID) {
7138 u_int targid_mask;
7139
7140 targid_mask = ahc_inb(ahc, TARGID)
7141 | (ahc_inb(ahc, TARGID + 1)
7142 << 8);
7143
7144 targid_mask &= ~target_mask;
7145 ahc_outb(ahc, TARGID, targid_mask);
7146 ahc_outb(ahc, TARGID+1,
7147 (targid_mask >> 8));
7148 ahc_update_scsiid(ahc, targid_mask);
7149 }
7150 }
7151 } else {
7152
7153 ahc->black_hole = NULL;
7154
7155 /*
7156 * We can't allow selections without
7157 * our black hole device.
7158 */
7159 empty = TRUE;
7160 }
7161 if (ahc->enabled_luns == 0) {
7162 /* Disallow select-in */
7163 u_int scsiseq;
7164
7165 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7166 scsiseq &= ~ENSELI;
7167 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7168 scsiseq = ahc_inb(ahc, SCSISEQ);
7169 scsiseq &= ~ENSELI;
7170 ahc_outb(ahc, SCSISEQ, scsiseq);
7171
7172 if ((ahc->features & AHC_MULTIROLE) == 0) {
7173 printf("Configuring Initiator Mode\n");
7174 ahc->flags &= ~AHC_TARGETROLE;
7175 ahc->flags |= AHC_INITIATORROLE;
7176 /*
7177 * Returning to a configuration that
7178 * fit previously will always succeed.
7179 */
7180 (void)ahc_loadseq(ahc);
7181 ahc_restart(ahc);
7182 /*
7183 * Unpaused. The extra unpause
7184 * that follows is harmless.
7185 */
7186 }
7187 }
7188 ahc_unpause(ahc);
7189 ahc_unlock(ahc, &s);
7190 }
7191 }
7192
7193 static void
7194 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7195 {
7196 u_int scsiid_mask;
7197 u_int scsiid;
7198
7199 if ((ahc->features & AHC_MULTI_TID) == 0)
7200 panic("ahc_update_scsiid called on non-multitid unit\n");
7201
7202 /*
7203 * Since we will rely on the TARGID mask
7204 * for selection enables, ensure that OID
7205 * in SCSIID is not set to some other ID
7206 * that we don't want to allow selections on.
7207 */
7208 if ((ahc->features & AHC_ULTRA2) != 0)
7209 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7210 else
7211 scsiid = ahc_inb(ahc, SCSIID);
7212 scsiid_mask = 0x1 << (scsiid & OID);
7213 if ((targid_mask & scsiid_mask) == 0) {
7214 u_int our_id;
7215
7216 /* ffs counts from 1 */
7217 our_id = ffs(targid_mask);
7218 if (our_id == 0)
7219 our_id = ahc->our_id;
7220 else
7221 our_id--;
7222 scsiid &= TID;
7223 scsiid |= our_id;
7224 }
7225 if ((ahc->features & AHC_ULTRA2) != 0)
7226 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7227 else
7228 ahc_outb(ahc, SCSIID, scsiid);
7229 }
7230
7231 void
7232 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7233 {
7234 struct target_cmd *cmd;
7235
7236 /*
7237 * If the card supports auto-access pause,
7238 * we can access the card directly regardless
7239 * of whether it is paused or not.
7240 */
7241 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7242 paused = TRUE;
7243
7244 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7245 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7246
7247 /*
7248 * Only advance through the queue if we
7249 * have the resources to process the command.
7250 */
7251 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7252 break;
7253
7254 cmd->cmd_valid = 0;
7255 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7256 ahc->shared_data_dmamap,
7257 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7258 sizeof(struct target_cmd),
7259 BUS_DMASYNC_PREREAD);
7260 ahc->tqinfifonext++;
7261
7262 /*
7263 * Lazily update our position in the target mode incoming
7264 * command queue as seen by the sequencer.
7265 */
7266 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7267 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7268 u_int hs_mailbox;
7269
7270 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7271 hs_mailbox &= ~HOST_TQINPOS;
7272 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7273 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7274 } else {
7275 if (!paused)
7276 ahc_pause(ahc);
7277 ahc_outb(ahc, KERNEL_TQINPOS,
7278 ahc->tqinfifonext & HOST_TQINPOS);
7279 if (!paused)
7280 ahc_unpause(ahc);
7281 }
7282 }
7283 }
7284 }
7285
7286 static int
7287 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7288 {
7289 struct ahc_tmode_tstate *tstate;
7290 struct ahc_tmode_lstate *lstate;
7291 struct ccb_accept_tio *atio;
7292 uint8_t *byte;
7293 int initiator;
7294 int target;
7295 int lun;
7296
7297 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7298 target = SCSIID_OUR_ID(cmd->scsiid);
7299 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7300
7301 byte = cmd->bytes;
7302 tstate = ahc->enabled_targets[target];
7303 lstate = NULL;
7304 if (tstate != NULL)
7305 lstate = tstate->enabled_luns[lun];
7306
7307 /*
7308 * Commands for disabled luns go to the black hole driver.
7309 */
7310 if (lstate == NULL)
7311 lstate = ahc->black_hole;
7312
7313 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7314 if (atio == NULL) {
7315 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7316 /*
7317 * Wait for more ATIOs from the peripheral driver for this lun.
7318 */
7319 if (bootverbose)
7320 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7321 return (1);
7322 } else
7323 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7324 #if 0
7325 printf("Incoming command from %d for %d:%d%s\n",
7326 initiator, target, lun,
7327 lstate == ahc->black_hole ? "(Black Holed)" : "");
7328 #endif
7329 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7330
7331 if (lstate == ahc->black_hole) {
7332 /* Fill in the wildcards */
7333 atio->ccb_h.target_id = target;
7334 atio->ccb_h.target_lun = lun;
7335 }
7336
7337 /*
7338 * Package it up and send it off to
7339 * whomever has this lun enabled.
7340 */
7341 atio->sense_len = 0;
7342 atio->init_id = initiator;
7343 if (byte[0] != 0xFF) {
7344 /* Tag was included */
7345 atio->tag_action = *byte++;
7346 atio->tag_id = *byte++;
7347 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7348 } else {
7349 atio->ccb_h.flags = 0;
7350 }
7351 byte++;
7352
7353 /* Okay. Now determine the cdb size based on the command code */
7354 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7355 case 0:
7356 atio->cdb_len = 6;
7357 break;
7358 case 1:
7359 case 2:
7360 atio->cdb_len = 10;
7361 break;
7362 case 4:
7363 atio->cdb_len = 16;
7364 break;
7365 case 5:
7366 atio->cdb_len = 12;
7367 break;
7368 case 3:
7369 default:
7370 /* Only copy the opcode. */
7371 atio->cdb_len = 1;
7372 printf("Reserved or VU command code type encountered\n");
7373 break;
7374 }
7375
7376 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7377
7378 atio->ccb_h.status |= CAM_CDB_RECVD;
7379
7380 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7381 /*
7382 * We weren't allowed to disconnect.
7383 * We're hanging on the bus until a
7384 * continue target I/O comes in response
7385 * to this accept tio.
7386 */
7387 #if 0
7388 printf("Received Immediate Command %d:%d:%d - %p\n",
7389 initiator, target, lun, ahc->pending_device);
7390 #endif
7391 ahc->pending_device = lstate;
7392 ahc_freeze_ccb((union ccb *)atio);
7393 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7394 }
7395 xpt_done((union ccb*)atio);
7396 return (0);
7397 }
7398
7399 #endif
WRT350N Kernel Patches