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[SCSI] ibmvscsi: convert kmalloc + memset to kcalloc
[wrt350n-kernel.git] / arch / arm / mach-omap2 / clock.h
blob6c78d471fab70b8ebe50c50f49401c6fb42f5747
1 /*
2 * linux/arch/arm/mach-omap24xx/clock.h
3 *
4 * Copyright (C) 2005 Texas Instruments Inc.
5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Created for OMAP2.
7 *
8 * Copyright (C) 2004 Nokia corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
18 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19
20 static void omap2_sys_clk_recalc(struct clk * clk);
21 static void omap2_clksel_recalc(struct clk * clk);
22 static void omap2_followparent_recalc(struct clk * clk);
23 static void omap2_propagate_rate(struct clk * clk);
24 static void omap2_mpu_recalc(struct clk * clk);
25 static int omap2_select_table_rate(struct clk * clk, unsigned long rate);
26 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate);
27 static void omap2_clk_disable(struct clk *clk);
28 static void omap2_sys_clk_recalc(struct clk * clk);
29 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val);
30 static u32 omap2_clksel_get_divisor(struct clk *clk);
31
32
33 #define RATE_IN_242X (1 << 0)
34 #define RATE_IN_243X (1 << 1)
35
36 /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
37 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
38 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
39 */
40 struct prcm_config {
41 unsigned long xtal_speed; /* crystal rate */
42 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
43 unsigned long mpu_speed; /* speed of MPU */
44 unsigned long cm_clksel_mpu; /* mpu divider */
45 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
46 unsigned long cm_clksel_gfx; /* gfx dividers */
47 unsigned long cm_clksel1_core; /* major subsystem dividers */
48 unsigned long cm_clksel1_pll; /* m,n */
49 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
50 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
51 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
52 unsigned char flags;
53 };
54
55 /* Mask for clksel which support parent settign in set_rate */
56 #define SRC_SEL_MASK (CM_CORE_SEL1 | CM_CORE_SEL2 | CM_WKUP_SEL1 | \
57 CM_PLL_SEL1 | CM_PLL_SEL2 | CM_SYSCLKOUT_SEL1)
58
59 /* Mask for clksel regs which support rate operations */
60 #define SRC_RATE_SEL_MASK (CM_MPU_SEL1 | CM_DSP_SEL1 | CM_GFX_SEL1 | \
61 CM_MODEM_SEL1 | CM_CORE_SEL1 | CM_CORE_SEL2 | \
62 CM_WKUP_SEL1 | CM_PLL_SEL1 | CM_PLL_SEL2 | \
63 CM_SYSCLKOUT_SEL1)
64
65 /*
66 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
67 * These configurations are characterized by voltage and speed for clocks.
68 * The device is only validated for certain combinations. One way to express
69 * these combinations is via the 'ratio's' which the clocks operate with
70 * respect to each other. These ratio sets are for a given voltage/DPLL
71 * setting. All configurations can be described by a DPLL setting and a ratio
72 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
73 *
74 * 2430 differs from 2420 in that there are no more phase synchronizers used.
75 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
76 * 2430 (iva2.1, NOdsp, mdm)
77 */
78
79 /* Core fields for cm_clksel, not ratio governed */
80 #define RX_CLKSEL_DSS1 (0x10 << 8)
81 #define RX_CLKSEL_DSS2 (0x0 << 13)
82 #define RX_CLKSEL_SSI (0x5 << 20)
83
84 /*-------------------------------------------------------------------------
85 * Voltage/DPLL ratios
86 *-------------------------------------------------------------------------*/
87
88 /* 2430 Ratio's, 2430-Ratio Config 1 */
89 #define R1_CLKSEL_L3 (4 << 0)
90 #define R1_CLKSEL_L4 (2 << 5)
91 #define R1_CLKSEL_USB (4 << 25)
92 #define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
93 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
94 R1_CLKSEL_L4 | R1_CLKSEL_L3
95 #define R1_CLKSEL_MPU (2 << 0)
96 #define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
97 #define R1_CLKSEL_DSP (2 << 0)
98 #define R1_CLKSEL_DSP_IF (2 << 5)
99 #define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
100 #define R1_CLKSEL_GFX (2 << 0)
101 #define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
102 #define R1_CLKSEL_MDM (4 << 0)
103 #define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
104
105 /* 2430-Ratio Config 2 */
106 #define R2_CLKSEL_L3 (6 << 0)
107 #define R2_CLKSEL_L4 (2 << 5)
108 #define R2_CLKSEL_USB (2 << 25)
109 #define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
110 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
111 R2_CLKSEL_L4 | R2_CLKSEL_L3
112 #define R2_CLKSEL_MPU (2 << 0)
113 #define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
114 #define R2_CLKSEL_DSP (2 << 0)
115 #define R2_CLKSEL_DSP_IF (3 << 5)
116 #define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
117 #define R2_CLKSEL_GFX (2 << 0)
118 #define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
119 #define R2_CLKSEL_MDM (6 << 0)
120 #define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
121
122 /* 2430-Ratio Bootm (BYPASS) */
123 #define RB_CLKSEL_L3 (1 << 0)
124 #define RB_CLKSEL_L4 (1 << 5)
125 #define RB_CLKSEL_USB (1 << 25)
126 #define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
127 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
128 RB_CLKSEL_L4 | RB_CLKSEL_L3
129 #define RB_CLKSEL_MPU (1 << 0)
130 #define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
131 #define RB_CLKSEL_DSP (1 << 0)
132 #define RB_CLKSEL_DSP_IF (1 << 5)
133 #define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
134 #define RB_CLKSEL_GFX (1 << 0)
135 #define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
136 #define RB_CLKSEL_MDM (1 << 0)
137 #define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
138
139 /* 2420 Ratio Equivalents */
140 #define RXX_CLKSEL_VLYNQ (0x12 << 15)
141 #define RXX_CLKSEL_SSI (0x8 << 20)
142
143 /* 2420-PRCM III 532MHz core */
144 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
145 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
146 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
147 #define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
148 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
149 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
150 RIII_CLKSEL_L3
151 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
152 #define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
153 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
154 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
155 #define RIII_SYNC_DSP (1 << 7) /* Enable sync */
156 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
157 #define RIII_SYNC_IVA (1 << 13) /* Enable sync */
158 #define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
159 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
160 RIII_CLKSEL_DSP
161 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
162 #define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
163
164 /* 2420-PRCM II 600MHz core */
165 #define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
166 #define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
167 #define RII_CLKSEL_USB (2 << 25) /* 50MHz */
168 #define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
169 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
170 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
171 RII_CLKSEL_L4 | RII_CLKSEL_L3
172 #define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
173 #define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
174 #define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
175 #define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
176 #define RII_SYNC_DSP (0 << 7) /* Bypass sync */
177 #define RII_CLKSEL_IVA (6 << 8) /* iva1 - 200MHz */
178 #define RII_SYNC_IVA (0 << 13) /* Bypass sync */
179 #define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
180 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
181 RII_CLKSEL_DSP
182 #define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
183 #define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
184
185 /* 2420-PRCM VII (boot) */
186 #define RVII_CLKSEL_L3 (1 << 0)
187 #define RVII_CLKSEL_L4 (1 << 5)
188 #define RVII_CLKSEL_DSS1 (1 << 8)
189 #define RVII_CLKSEL_DSS2 (0 << 13)
190 #define RVII_CLKSEL_VLYNQ (1 << 15)
191 #define RVII_CLKSEL_SSI (1 << 20)
192 #define RVII_CLKSEL_USB (1 << 25)
193
194 #define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
195 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
196 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
197
198 #define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
199 #define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
200
201 #define RVII_CLKSEL_DSP (1 << 0)
202 #define RVII_CLKSEL_DSP_IF (1 << 5)
203 #define RVII_SYNC_DSP (0 << 7)
204 #define RVII_CLKSEL_IVA (1 << 8)
205 #define RVII_SYNC_IVA (0 << 13)
206 #define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
207 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
208
209 #define RVII_CLKSEL_GFX (1 << 0)
210 #define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
211
212 /*-------------------------------------------------------------------------
213 * 2430 Target modes: Along with each configuration the CPU has several
214 * modes which goes along with them. Modes mainly are the addition of
215 * describe DPLL combinations to go along with a ratio.
216 *-------------------------------------------------------------------------*/
217
218 /* Hardware governed */
219 #define MX_48M_SRC (0 << 3)
220 #define MX_54M_SRC (0 << 5)
221 #define MX_APLLS_CLIKIN_12 (3 << 23)
222 #define MX_APLLS_CLIKIN_13 (2 << 23)
223 #define MX_APLLS_CLIKIN_19_2 (0 << 23)
224
225 /*
226 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
227 * #2 (ratio1) baseport-target
228 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
229 */
230 #define M5A_DPLL_MULT_12 (133 << 12)
231 #define M5A_DPLL_DIV_12 (5 << 8)
232 #define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
233 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
234 MX_APLLS_CLIKIN_12
235 #define M5A_DPLL_MULT_13 (266 << 12)
236 #define M5A_DPLL_DIV_13 (12 << 8)
237 #define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
238 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
239 MX_APLLS_CLIKIN_13
240 #define M5A_DPLL_MULT_19 (180 << 12)
241 #define M5A_DPLL_DIV_19 (12 << 8)
242 #define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
243 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
244 MX_APLLS_CLIKIN_19_2
245 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
246 #define M5B_DPLL_MULT_12 (50 << 12)
247 #define M5B_DPLL_DIV_12 (2 << 8)
248 #define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
249 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
250 MX_APLLS_CLIKIN_12
251 #define M5B_DPLL_MULT_13 (200 << 12)
252 #define M5B_DPLL_DIV_13 (12 << 8)
253
254 #define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
255 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
256 MX_APLLS_CLIKIN_13
257 #define M5B_DPLL_MULT_19 (125 << 12)
258 #define M5B_DPLL_DIV_19 (31 << 8)
259 #define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
260 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
261 MX_APLLS_CLIKIN_19_2
262 /*
263 * #4 (ratio2)
264 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
265 */
266 #define M3_DPLL_MULT_12 (55 << 12)
267 #define M3_DPLL_DIV_12 (1 << 8)
268 #define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
269 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
270 MX_APLLS_CLIKIN_12
271 #define M3_DPLL_MULT_13 (330 << 12)
272 #define M3_DPLL_DIV_13 (12 << 8)
273 #define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
274 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
275 MX_APLLS_CLIKIN_13
276 #define M3_DPLL_MULT_19 (275 << 12)
277 #define M3_DPLL_DIV_19 (15 << 8)
278 #define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
279 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
280 MX_APLLS_CLIKIN_19_2
281 /* boot (boot) */
282 #define MB_DPLL_MULT (1 << 12)
283 #define MB_DPLL_DIV (0 << 8)
284 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
285 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
286
287 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
288 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
289
290 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
291 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
292
293 /*
294 * 2430 - chassis (sedna)
295 * 165 (ratio1) same as above #2
296 * 150 (ratio1)
297 * 133 (ratio2) same as above #4
298 * 110 (ratio2) same as above #3
299 * 104 (ratio2)
300 * boot (boot)
301 */
302
303 /*
304 * 2420 Equivalent - mode registers
305 * PRCM II , target DPLL = 2*300MHz = 600MHz
306 */
307 #define MII_DPLL_MULT_12 (50 << 12)
308 #define MII_DPLL_DIV_12 (1 << 8)
309 #define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
310 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
311 MX_APLLS_CLIKIN_12
312 #define MII_DPLL_MULT_13 (300 << 12)
313 #define MII_DPLL_DIV_13 (12 << 8)
314 #define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
315 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
316 MX_APLLS_CLIKIN_13
317
318 /* PRCM III target DPLL = 2*266 = 532MHz*/
319 #define MIII_DPLL_MULT_12 (133 << 12)
320 #define MIII_DPLL_DIV_12 (5 << 8)
321 #define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
322 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
323 MX_APLLS_CLIKIN_12
324 #define MIII_DPLL_MULT_13 (266 << 12)
325 #define MIII_DPLL_DIV_13 (12 << 8)
326 #define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
327 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
328 MX_APLLS_CLIKIN_13
329
330 /* PRCM VII (boot bypass) */
331 #define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
332 #define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
333
334 /* High and low operation value */
335 #define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
336 #define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
337
338 /*
339 * These represent optimal values for common parts, it won't work for all.
340 * As long as you scale down, most parameters are still work, they just
341 * become sub-optimal. The RFR value goes in the oppisite direction. If you
342 * don't adjust it down as your clock period increases the refresh interval
343 * will not be met. Setting all parameters for complete worst case may work,
344 * but may cut memory performance by 2x. Due to errata the DLLs need to be
345 * unlocked and their value needs run time calibration. A dynamic call is
346 * need for that as no single right value exists acorss production samples.
347 *
348 * Only the FULL speed values are given. Current code is such that rate
349 * changes must be made at DPLLoutx2. The actual value adjustment for low
350 * frequency operation will be handled by omap_set_performance()
351 *
352 * By having the boot loader boot up in the fastest L4 speed available likely
353 * will result in something which you can switch between.
354 */
355 #define V24XX_SDRC_RFR_CTRL_133MHz (0x0003de00 | 1)
356 #define V24XX_SDRC_RFR_CTRL_100MHz (0x0002da01 | 1)
357 #define V24XX_SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */
358 #define V24XX_SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */
359
360 /* MPU speed defines */
361 #define S12M 12000000
362 #define S13M 13000000
363 #define S19M 19200000
364 #define S26M 26000000
365 #define S100M 100000000
366 #define S133M 133000000
367 #define S150M 150000000
368 #define S165M 165000000
369 #define S200M 200000000
370 #define S266M 266000000
371 #define S300M 300000000
372 #define S330M 330000000
373 #define S400M 400000000
374 #define S532M 532000000
375 #define S600M 600000000
376 #define S660M 660000000
377
378 /*-------------------------------------------------------------------------
379 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
380 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
381 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
382 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
383 *
384 * Filling in table based on H4 boards and 2430-SDPs variants available.
385 * There are quite a few more rates combinations which could be defined.
386 *
387 * When multiple values are defiend the start up will try and choose the
388 * fastest one. If a 'fast' value is defined, then automatically, the /2
389 * one should be included as it can be used. Generally having more that
390 * one fast set does not make sense, as static timings need to be changed
391 * to change the set. The exception is the bypass setting which is
392 * availble for low power bypass.
393 *
394 * Note: This table needs to be sorted, fastest to slowest.
395 *-------------------------------------------------------------------------*/
396 static struct prcm_config rate_table[] = {
397 /* PRCM II - FAST */
398 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
399 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
400 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
401 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
402 RATE_IN_242X},
403
404 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
405 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
406 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
407 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
408 RATE_IN_242X},
409
410 /* PRCM III - FAST */
411 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
412 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
413 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
414 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
415 RATE_IN_242X},
416
417 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
418 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
419 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
420 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
421 RATE_IN_242X},
422
423 /* PRCM II - SLOW */
424 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
425 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
426 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
427 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
428 RATE_IN_242X},
429
430 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
431 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
432 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
433 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_100MHz,
434 RATE_IN_242X},
435
436 /* PRCM III - SLOW */
437 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
438 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
439 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
440 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
441 RATE_IN_242X},
442
443 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
444 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
445 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
446 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_133MHz,
447 RATE_IN_242X},
448
449 /* PRCM-VII (boot-bypass) */
450 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
451 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
452 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
453 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
454 RATE_IN_242X},
455
456 /* PRCM-VII (boot-bypass) */
457 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
458 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
459 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
460 MX_CLKSEL2_PLL_2x_VAL, 0, V24XX_SDRC_RFR_CTRL_BYPASS,
461 RATE_IN_242X},
462
463 /* PRCM #3 - ratio2 (ES2) - FAST */
464 {S13M, S660M, S330M, R2_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
465 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
466 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
467 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
468 V24XX_SDRC_RFR_CTRL_110MHz,
469 RATE_IN_243X},
470
471 /* PRCM #5a - ratio1 - FAST */
472 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
473 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
474 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
475 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
476 V24XX_SDRC_RFR_CTRL_133MHz,
477 RATE_IN_243X},
478
479 /* PRCM #5b - ratio1 - FAST */
480 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
481 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
482 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
483 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
484 V24XX_SDRC_RFR_CTRL_100MHz,
485 RATE_IN_243X},
486
487 /* PRCM #3 - ratio2 (ES2) - SLOW */
488 {S13M, S330M, S165M, R2_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
489 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
490 R2_CM_CLKSEL1_CORE_VAL, M3_CM_CLKSEL1_PLL_13_VAL,
491 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
492 V24XX_SDRC_RFR_CTRL_110MHz,
493 RATE_IN_243X},
494
495 /* PRCM #5a - ratio1 - SLOW */
496 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
497 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
498 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
499 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
500 V24XX_SDRC_RFR_CTRL_133MHz,
501 RATE_IN_243X},
502
503 /* PRCM #5b - ratio1 - SLOW*/
504 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
505 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
506 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
507 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
508 V24XX_SDRC_RFR_CTRL_100MHz,
509 RATE_IN_243X},
510
511 /* PRCM-boot/bypass */
512 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
513 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
514 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
515 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
516 V24XX_SDRC_RFR_CTRL_BYPASS,
517 RATE_IN_243X},
518
519 /* PRCM-boot/bypass */
520 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
521 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
522 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
523 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
524 V24XX_SDRC_RFR_CTRL_BYPASS,
525 RATE_IN_243X},
526
527 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
528 };
529
530 /*-------------------------------------------------------------------------
531 * 24xx clock tree.
532 *
533 * NOTE:In many cases here we are assigning a 'default' parent. In many
534 * cases the parent is selectable. The get/set parent calls will also
535 * switch sources.
536 *
537 * Many some clocks say always_enabled, but they can be auto idled for
538 * power savings. They will always be available upon clock request.
539 *
540 * Several sources are given initial rates which may be wrong, this will
541 * be fixed up in the init func.
542 *
543 * Things are broadly separated below by clock domains. It is
544 * noteworthy that most periferals have dependencies on multiple clock
545 * domains. Many get their interface clocks from the L4 domain, but get
546 * functional clocks from fixed sources or other core domain derived
547 * clocks.
548 *-------------------------------------------------------------------------*/
549
550 /* Base external input clocks */
551 static struct clk func_32k_ck = {
552 .name = "func_32k_ck",
553 .rate = 32000,
554 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
555 RATE_FIXED | ALWAYS_ENABLED,
556 };
557
558 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
559 static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
560 .name = "osc_ck",
561 .rate = 26000000, /* fixed up in clock init */
562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
563 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
564 };
565
566 /* With out modem likely 12MHz, with modem likely 13MHz */
567 static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
568 .name = "sys_ck", /* ~ ref_clk also */
569 .parent = &osc_ck,
570 .rate = 13000000,
571 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
572 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
573 .rate_offset = 6, /* sysclkdiv 1 or 2, already handled or no boot */
574 .recalc = &omap2_sys_clk_recalc,
575 };
576
577 static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
578 .name = "alt_ck",
579 .rate = 54000000,
580 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
581 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
582 .recalc = &omap2_propagate_rate,
583 };
584
585 /*
586 * Analog domain root source clocks
587 */
588
589 /* dpll_ck, is broken out in to special cases through clksel */
590 static struct clk dpll_ck = {
591 .name = "dpll_ck",
592 .parent = &sys_ck, /* Can be func_32k also */
593 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
594 RATE_PROPAGATES | RATE_CKCTL | CM_PLL_SEL1,
595 .recalc = &omap2_clksel_recalc,
596 };
597
598 static struct clk apll96_ck = {
599 .name = "apll96_ck",
600 .parent = &sys_ck,
601 .rate = 96000000,
602 .flags = CLOCK_IN_OMAP242X |CLOCK_IN_OMAP243X |
603 RATE_FIXED | RATE_PROPAGATES,
604 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
605 .enable_bit = 0x2,
606 .recalc = &omap2_propagate_rate,
607 };
608
609 static struct clk apll54_ck = {
610 .name = "apll54_ck",
611 .parent = &sys_ck,
612 .rate = 54000000,
613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
614 RATE_FIXED | RATE_PROPAGATES,
615 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
616 .enable_bit = 0x6,
617 .recalc = &omap2_propagate_rate,
618 };
619
620 /*
621 * PRCM digital base sources
622 */
623 static struct clk func_54m_ck = {
624 .name = "func_54m_ck",
625 .parent = &apll54_ck, /* can also be alt_clk */
626 .rate = 54000000,
627 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
628 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
629 .src_offset = 5,
630 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
631 .enable_bit = 0xff,
632 .recalc = &omap2_propagate_rate,
633 };
634
635 static struct clk core_ck = {
636 .name = "core_ck",
637 .parent = &dpll_ck, /* can also be 32k */
638 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
639 ALWAYS_ENABLED | RATE_PROPAGATES,
640 .recalc = &omap2_propagate_rate,
641 };
642
643 static struct clk sleep_ck = { /* sys_clk or 32k */
644 .name = "sleep_ck",
645 .parent = &func_32k_ck,
646 .rate = 32000,
647 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
648 .recalc = &omap2_propagate_rate,
649 };
650
651 static struct clk func_96m_ck = {
652 .name = "func_96m_ck",
653 .parent = &apll96_ck,
654 .rate = 96000000,
655 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
656 RATE_FIXED | RATE_PROPAGATES,
657 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
658 .enable_bit = 0xff,
659 .recalc = &omap2_propagate_rate,
660 };
661
662 static struct clk func_48m_ck = {
663 .name = "func_48m_ck",
664 .parent = &apll96_ck, /* 96M or Alt */
665 .rate = 48000000,
666 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
667 RATE_FIXED | CM_PLL_SEL1 | RATE_PROPAGATES,
668 .src_offset = 3,
669 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
670 .enable_bit = 0xff,
671 .recalc = &omap2_propagate_rate,
672 };
673
674 static struct clk func_12m_ck = {
675 .name = "func_12m_ck",
676 .parent = &func_48m_ck,
677 .rate = 12000000,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_FIXED | RATE_PROPAGATES,
680 .recalc = &omap2_propagate_rate,
681 .enable_reg = (void __iomem *)&CM_CLKEN_PLL,
682 .enable_bit = 0xff,
683 };
684
685 /* Secure timer, only available in secure mode */
686 static struct clk wdt1_osc_ck = {
687 .name = "ck_wdt1_osc",
688 .parent = &osc_ck,
689 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
690 .recalc = &omap2_followparent_recalc,
691 };
692
693 static struct clk sys_clkout = {
694 .name = "sys_clkout",
695 .parent = &func_54m_ck,
696 .rate = 54000000,
697 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
698 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
699 .src_offset = 0,
700 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
701 .enable_bit = 7,
702 .rate_offset = 3,
703 .recalc = &omap2_clksel_recalc,
704 };
705
706 /* In 2430, new in 2420 ES2 */
707 static struct clk sys_clkout2 = {
708 .name = "sys_clkout2",
709 .parent = &func_54m_ck,
710 .rate = 54000000,
711 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
712 CM_SYSCLKOUT_SEL1 | RATE_CKCTL,
713 .src_offset = 8,
714 .enable_reg = (void __iomem *)&PRCM_CLKOUT_CTRL,
715 .enable_bit = 15,
716 .rate_offset = 11,
717 .recalc = &omap2_clksel_recalc,
718 };
719
720 static struct clk emul_ck = {
721 .name = "emul_ck",
722 .parent = &func_54m_ck,
723 .flags = CLOCK_IN_OMAP242X,
724 .enable_reg = (void __iomem *)&PRCM_CLKEMUL_CTRL,
725 .enable_bit = 0,
726 .recalc = &omap2_propagate_rate,
727
728 };
729
730 /*
731 * MPU clock domain
732 * Clocks:
733 * MPU_FCLK, MPU_ICLK
734 * INT_M_FCLK, INT_M_I_CLK
735 *
736 * - Individual clocks are hardware managed.
737 * - Base divider comes from: CM_CLKSEL_MPU
738 *
739 */
740 static struct clk mpu_ck = { /* Control cpu */
741 .name = "mpu_ck",
742 .parent = &core_ck,
743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL |
744 ALWAYS_ENABLED | CM_MPU_SEL1 | DELAYED_APP |
745 CONFIG_PARTICIPANT | RATE_PROPAGATES,
746 .rate_offset = 0, /* bits 0-4 */
747 .recalc = &omap2_clksel_recalc,
748 };
749
750 /*
751 * DSP (2430-IVA2.1) (2420-UMA+IVA1) clock domain
752 * Clocks:
753 * 2430: IVA2.1_FCLK, IVA2.1_ICLK
754 * 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
755 */
756 static struct clk iva2_1_fck = {
757 .name = "iva2_1_fck",
758 .parent = &core_ck,
759 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
760 DELAYED_APP | RATE_PROPAGATES |
761 CONFIG_PARTICIPANT,
762 .rate_offset = 0,
763 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
764 .enable_bit = 0,
765 .recalc = &omap2_clksel_recalc,
766 };
767
768 static struct clk iva2_1_ick = {
769 .name = "iva2_1_ick",
770 .parent = &iva2_1_fck,
771 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_DSP_SEL1 |
772 DELAYED_APP | CONFIG_PARTICIPANT,
773 .rate_offset = 5,
774 .recalc = &omap2_clksel_recalc,
775 };
776
777 /*
778 * Won't be too specific here. The core clock comes into this block
779 * it is divided then tee'ed. One branch goes directly to xyz enable
780 * controls. The other branch gets further divided by 2 then possibly
781 * routed into a synchronizer and out of clocks abc.
782 */
783 static struct clk dsp_fck = {
784 .name = "dsp_fck",
785 .parent = &core_ck,
786 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
787 DELAYED_APP | CONFIG_PARTICIPANT | RATE_PROPAGATES,
788 .rate_offset = 0,
789 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
790 .enable_bit = 0,
791 .recalc = &omap2_clksel_recalc,
792 };
793
794 static struct clk dsp_ick = {
795 .name = "dsp_ick", /* apparently ipi and isp */
796 .parent = &dsp_fck,
797 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1 |
798 DELAYED_APP | CONFIG_PARTICIPANT,
799 .rate_offset = 5,
800 .enable_reg = (void __iomem *)&CM_ICLKEN_DSP,
801 .enable_bit = 1, /* for ipi */
802 .recalc = &omap2_clksel_recalc,
803 };
804
805 static struct clk iva1_ifck = {
806 .name = "iva1_ifck",
807 .parent = &core_ck,
808 .flags = CLOCK_IN_OMAP242X | CM_DSP_SEL1 | RATE_CKCTL |
809 CONFIG_PARTICIPANT | RATE_PROPAGATES | DELAYED_APP,
810 .rate_offset= 8,
811 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
812 .enable_bit = 10,
813 .recalc = &omap2_clksel_recalc,
814 };
815
816 /* IVA1 mpu/int/i/f clocks are /2 of parent */
817 static struct clk iva1_mpu_int_ifck = {
818 .name = "iva1_mpu_int_ifck",
819 .parent = &iva1_ifck,
820 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_DSP_SEL1,
821 .enable_reg = (void __iomem *)&CM_FCLKEN_DSP,
822 .enable_bit = 8,
823 .recalc = &omap2_clksel_recalc,
824 };
825
826 /*
827 * L3 clock domain
828 * L3 clocks are used for both interface and functional clocks to
829 * multiple entities. Some of these clocks are completely managed
830 * by hardware, and some others allow software control. Hardware
831 * managed ones general are based on directly CLK_REQ signals and
832 * various auto idle settings. The functional spec sets many of these
833 * as 'tie-high' for their enables.
834 *
835 * I-CLOCKS:
836 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
837 * CAM, HS-USB.
838 * F-CLOCK
839 * SSI.
840 *
841 * GPMC memories and SDRC have timing and clock sensitive registers which
842 * may very well need notification when the clock changes. Currently for low
843 * operating points, these are taken care of in sleep.S.
844 */
845 static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
846 .name = "core_l3_ck",
847 .parent = &core_ck,
848 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
849 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
850 DELAYED_APP | CONFIG_PARTICIPANT |
851 RATE_PROPAGATES,
852 .rate_offset = 0,
853 .recalc = &omap2_clksel_recalc,
854 };
855
856 static struct clk usb_l4_ick = { /* FS-USB interface clock */
857 .name = "usb_l4_ick",
858 .parent = &core_l3_ck,
859 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
860 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP |
861 CONFIG_PARTICIPANT,
862 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
863 .enable_bit = 0,
864 .rate_offset = 25,
865 .recalc = &omap2_clksel_recalc,
866 };
867
868 /*
869 * SSI is in L3 management domain, its direct parent is core not l3,
870 * many core power domain entities are grouped into the L3 clock
871 * domain.
872 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK
873 *
874 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
875 */
876 static struct clk ssi_ssr_sst_fck = {
877 .name = "ssi_fck",
878 .parent = &core_ck,
879 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
880 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
881 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, /* bit 1 */
882 .enable_bit = 1,
883 .rate_offset = 20,
884 .recalc = &omap2_clksel_recalc,
885 };
886
887 /*
888 * GFX clock domain
889 * Clocks:
890 * GFX_FCLK, GFX_ICLK
891 * GFX_CG1(2d), GFX_CG2(3d)
892 *
893 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
894 * The 2d and 3d clocks run at a hardware determined
895 * divided value of fclk.
896 *
897 */
898 static struct clk gfx_3d_fck = {
899 .name = "gfx_3d_fck",
900 .parent = &core_l3_ck,
901 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
902 RATE_CKCTL | CM_GFX_SEL1,
903 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
904 .enable_bit = 2,
905 .rate_offset= 0,
906 .recalc = &omap2_clksel_recalc,
907 };
908
909 static struct clk gfx_2d_fck = {
910 .name = "gfx_2d_fck",
911 .parent = &core_l3_ck,
912 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
913 RATE_CKCTL | CM_GFX_SEL1,
914 .enable_reg = (void __iomem *)&CM_FCLKEN_GFX,
915 .enable_bit = 1,
916 .rate_offset= 0,
917 .recalc = &omap2_clksel_recalc,
918 };
919
920 static struct clk gfx_ick = {
921 .name = "gfx_ick", /* From l3 */
922 .parent = &core_l3_ck,
923 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
924 RATE_CKCTL,
925 .enable_reg = (void __iomem *)&CM_ICLKEN_GFX, /* bit 0 */
926 .enable_bit = 0,
927 .recalc = &omap2_followparent_recalc,
928 };
929
930 /*
931 * Modem clock domain (2430)
932 * CLOCKS:
933 * MDM_OSC_CLK
934 * MDM_ICLK
935 */
936 static struct clk mdm_ick = { /* used both as a ick and fck */
937 .name = "mdm_ick",
938 .parent = &core_ck,
939 .flags = CLOCK_IN_OMAP243X | RATE_CKCTL | CM_MODEM_SEL1 |
940 DELAYED_APP | CONFIG_PARTICIPANT,
941 .rate_offset = 0,
942 .enable_reg = (void __iomem *)&CM_ICLKEN_MDM,
943 .enable_bit = 0,
944 .recalc = &omap2_clksel_recalc,
945 };
946
947 static struct clk mdm_osc_ck = {
948 .name = "mdm_osc_ck",
949 .rate = 26000000,
950 .parent = &osc_ck,
951 .flags = CLOCK_IN_OMAP243X | RATE_FIXED,
952 .enable_reg = (void __iomem *)&CM_FCLKEN_MDM,
953 .enable_bit = 1,
954 .recalc = &omap2_followparent_recalc,
955 };
956
957 /*
958 * L4 clock management domain
959 *
960 * This domain contains lots of interface clocks from the L4 interface, some
961 * functional clocks. Fixed APLL functional source clocks are managed in
962 * this domain.
963 */
964 static struct clk l4_ck = { /* used both as an ick and fck */
965 .name = "l4_ck",
966 .parent = &core_l3_ck,
967 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
968 RATE_CKCTL | ALWAYS_ENABLED | CM_CORE_SEL1 |
969 DELAYED_APP | RATE_PROPAGATES,
970 .rate_offset = 5,
971 .recalc = &omap2_clksel_recalc,
972 };
973
974 static struct clk ssi_l4_ick = {
975 .name = "ssi_l4_ick",
976 .parent = &l4_ck,
977 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
978 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, /* bit 1 */
979 .enable_bit = 1,
980 .recalc = &omap2_followparent_recalc,
981 };
982
983 /*
984 * DSS clock domain
985 * CLOCKs:
986 * DSS_L4_ICLK, DSS_L3_ICLK,
987 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
988 *
989 * DSS is both initiator and target.
990 */
991 static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
992 .name = "dss_ick",
993 .parent = &l4_ck, /* really both l3 and l4 */
994 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | RATE_CKCTL,
995 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
996 .enable_bit = 0,
997 .recalc = &omap2_followparent_recalc,
998 };
999
1000 static struct clk dss1_fck = {
1001 .name = "dss1_fck",
1002 .parent = &core_ck, /* Core or sys */
1003 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1004 RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1005 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1006 .enable_bit = 0,
1007 .rate_offset = 8,
1008 .src_offset = 8,
1009 .recalc = &omap2_clksel_recalc,
1010 };
1011
1012 static struct clk dss2_fck = { /* Alt clk used in power management */
1013 .name = "dss2_fck",
1014 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
1015 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1016 RATE_CKCTL | CM_CORE_SEL1 | RATE_FIXED,
1017 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1018 .enable_bit = 1,
1019 .src_offset = 13,
1020 .recalc = &omap2_followparent_recalc,
1021 };
1022
1023 static struct clk dss_54m_fck = { /* Alt clk used in power management */
1024 .name = "dss_54m_fck", /* 54m tv clk */
1025 .parent = &func_54m_ck,
1026 .rate = 54000000,
1027 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1028 RATE_FIXED | RATE_PROPAGATES,
1029 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1030 .enable_bit = 2,
1031 .recalc = &omap2_propagate_rate,
1032 };
1033
1034 /*
1035 * CORE power domain ICLK & FCLK defines.
1036 * Many of the these can have more than one possible parent. Entries
1037 * here will likely have an L4 interface parent, and may have multiple
1038 * functional clock parents.
1039 */
1040 static struct clk gpt1_ick = {
1041 .name = "gpt1_ick",
1042 .parent = &l4_ck,
1043 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1044 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP, /* Bit0 */
1045 .enable_bit = 0,
1046 .recalc = &omap2_followparent_recalc,
1047 };
1048
1049 static struct clk gpt1_fck = {
1050 .name = "gpt1_fck",
1051 .parent = &func_32k_ck,
1052 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1053 CM_WKUP_SEL1,
1054 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP, /* Bit0 */
1055 .enable_bit = 0,
1056 .src_offset = 0,
1057 .recalc = &omap2_followparent_recalc,
1058 };
1059
1060 static struct clk gpt2_ick = {
1061 .name = "gpt2_ick",
1062 .parent = &l4_ck,
1063 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1064 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit4 */
1065 .enable_bit = 0,
1066 .recalc = &omap2_followparent_recalc,
1067 };
1068
1069 static struct clk gpt2_fck = {
1070 .name = "gpt2_fck",
1071 .parent = &func_32k_ck,
1072 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1073 CM_CORE_SEL2,
1074 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1075 .enable_bit = 4,
1076 .src_offset = 2,
1077 .recalc = &omap2_followparent_recalc,
1078 };
1079
1080 static struct clk gpt3_ick = {
1081 .name = "gpt3_ick",
1082 .parent = &l4_ck,
1083 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1084 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit5 */
1085 .enable_bit = 5,
1086 .recalc = &omap2_followparent_recalc,
1087 };
1088
1089 static struct clk gpt3_fck = {
1090 .name = "gpt3_fck",
1091 .parent = &func_32k_ck,
1092 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1093 CM_CORE_SEL2,
1094 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1095 .enable_bit = 5,
1096 .src_offset = 4,
1097 .recalc = &omap2_followparent_recalc,
1098 };
1099
1100 static struct clk gpt4_ick = {
1101 .name = "gpt4_ick",
1102 .parent = &l4_ck,
1103 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1104 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit6 */
1105 .enable_bit = 6,
1106 .recalc = &omap2_followparent_recalc,
1107 };
1108
1109 static struct clk gpt4_fck = {
1110 .name = "gpt4_fck",
1111 .parent = &func_32k_ck,
1112 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1113 CM_CORE_SEL2,
1114 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1115 .enable_bit = 6,
1116 .src_offset = 6,
1117 .recalc = &omap2_followparent_recalc,
1118 };
1119
1120 static struct clk gpt5_ick = {
1121 .name = "gpt5_ick",
1122 .parent = &l4_ck,
1123 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1124 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* Bit7 */
1125 .enable_bit = 7,
1126 .recalc = &omap2_followparent_recalc,
1127 };
1128
1129 static struct clk gpt5_fck = {
1130 .name = "gpt5_fck",
1131 .parent = &func_32k_ck,
1132 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1133 CM_CORE_SEL2,
1134 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1135 .enable_bit = 7,
1136 .src_offset = 8,
1137 .recalc = &omap2_followparent_recalc,
1138 };
1139
1140 static struct clk gpt6_ick = {
1141 .name = "gpt6_ick",
1142 .parent = &l4_ck,
1143 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1144 .enable_bit = 8,
1145 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit8 */
1146 .recalc = &omap2_followparent_recalc,
1147 };
1148
1149 static struct clk gpt6_fck = {
1150 .name = "gpt6_fck",
1151 .parent = &func_32k_ck,
1152 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1153 CM_CORE_SEL2,
1154 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1155 .enable_bit = 8,
1156 .src_offset = 10,
1157 .recalc = &omap2_followparent_recalc,
1158 };
1159
1160 static struct clk gpt7_ick = {
1161 .name = "gpt7_ick",
1162 .parent = &l4_ck,
1163 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1164 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit9 */
1165 .enable_bit = 9,
1166 .recalc = &omap2_followparent_recalc,
1167 };
1168
1169 static struct clk gpt7_fck = {
1170 .name = "gpt7_fck",
1171 .parent = &func_32k_ck,
1172 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1173 CM_CORE_SEL2,
1174 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1175 .enable_bit = 9,
1176 .src_offset = 12,
1177 .recalc = &omap2_followparent_recalc,
1178 };
1179
1180 static struct clk gpt8_ick = {
1181 .name = "gpt8_ick",
1182 .parent = &l4_ck,
1183 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1184 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit10 */
1185 .enable_bit = 10,
1186 .recalc = &omap2_followparent_recalc,
1187 };
1188
1189 static struct clk gpt8_fck = {
1190 .name = "gpt8_fck",
1191 .parent = &func_32k_ck,
1192 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1193 CM_CORE_SEL2,
1194 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1195 .enable_bit = 10,
1196 .src_offset = 14,
1197 .recalc = &omap2_followparent_recalc,
1198 };
1199
1200 static struct clk gpt9_ick = {
1201 .name = "gpt9_ick",
1202 .parent = &l4_ck,
1203 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1204 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1205 .enable_bit = 11,
1206 .recalc = &omap2_followparent_recalc,
1207 };
1208
1209 static struct clk gpt9_fck = {
1210 .name = "gpt9_fck",
1211 .parent = &func_32k_ck,
1212 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1213 CM_CORE_SEL2,
1214 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1215 .enable_bit = 11,
1216 .src_offset = 16,
1217 .recalc = &omap2_followparent_recalc,
1218 };
1219
1220 static struct clk gpt10_ick = {
1221 .name = "gpt10_ick",
1222 .parent = &l4_ck,
1223 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1224 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1225 .enable_bit = 12,
1226 .recalc = &omap2_followparent_recalc,
1227 };
1228
1229 static struct clk gpt10_fck = {
1230 .name = "gpt10_fck",
1231 .parent = &func_32k_ck,
1232 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1233 CM_CORE_SEL2,
1234 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1235 .enable_bit = 12,
1236 .src_offset = 18,
1237 .recalc = &omap2_followparent_recalc,
1238 };
1239
1240 static struct clk gpt11_ick = {
1241 .name = "gpt11_ick",
1242 .parent = &l4_ck,
1243 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1244 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1245 .enable_bit = 13,
1246 .recalc = &omap2_followparent_recalc,
1247 };
1248
1249 static struct clk gpt11_fck = {
1250 .name = "gpt11_fck",
1251 .parent = &func_32k_ck,
1252 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1253 CM_CORE_SEL2,
1254 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1255 .enable_bit = 13,
1256 .src_offset = 20,
1257 .recalc = &omap2_followparent_recalc,
1258 };
1259
1260 static struct clk gpt12_ick = {
1261 .name = "gpt12_ick",
1262 .parent = &l4_ck,
1263 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1264 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit14 */
1265 .enable_bit = 14,
1266 .recalc = &omap2_followparent_recalc,
1267 };
1268
1269 static struct clk gpt12_fck = {
1270 .name = "gpt12_fck",
1271 .parent = &func_32k_ck,
1272 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1273 CM_CORE_SEL2,
1274 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1275 .enable_bit = 14,
1276 .src_offset = 22,
1277 .recalc = &omap2_followparent_recalc,
1278 };
1279
1280 static struct clk mcbsp1_ick = {
1281 .name = "mcbsp1_ick",
1282 .parent = &l4_ck,
1283 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1284 .enable_bit = 15,
1285 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, /* bit16 */
1286 .recalc = &omap2_followparent_recalc,
1287 };
1288
1289 static struct clk mcbsp1_fck = {
1290 .name = "mcbsp1_fck",
1291 .parent = &func_96m_ck,
1292 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1293 .enable_bit = 15,
1294 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1295 .recalc = &omap2_followparent_recalc,
1296 };
1297
1298 static struct clk mcbsp2_ick = {
1299 .name = "mcbsp2_ick",
1300 .parent = &l4_ck,
1301 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1302 .enable_bit = 16,
1303 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1304 .recalc = &omap2_followparent_recalc,
1305 };
1306
1307 static struct clk mcbsp2_fck = {
1308 .name = "mcbsp2_fck",
1309 .parent = &func_96m_ck,
1310 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1311 .enable_bit = 16,
1312 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1313 .recalc = &omap2_followparent_recalc,
1314 };
1315
1316 static struct clk mcbsp3_ick = {
1317 .name = "mcbsp3_ick",
1318 .parent = &l4_ck,
1319 .flags = CLOCK_IN_OMAP243X,
1320 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1321 .enable_bit = 3,
1322 .recalc = &omap2_followparent_recalc,
1323 };
1324
1325 static struct clk mcbsp3_fck = {
1326 .name = "mcbsp3_fck",
1327 .parent = &func_96m_ck,
1328 .flags = CLOCK_IN_OMAP243X,
1329 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1330 .enable_bit = 3,
1331 .recalc = &omap2_followparent_recalc,
1332 };
1333
1334 static struct clk mcbsp4_ick = {
1335 .name = "mcbsp4_ick",
1336 .parent = &l4_ck,
1337 .flags = CLOCK_IN_OMAP243X,
1338 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1339 .enable_bit = 4,
1340 .recalc = &omap2_followparent_recalc,
1341 };
1342
1343 static struct clk mcbsp4_fck = {
1344 .name = "mcbsp4_fck",
1345 .parent = &func_96m_ck,
1346 .flags = CLOCK_IN_OMAP243X,
1347 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1348 .enable_bit = 4,
1349 .recalc = &omap2_followparent_recalc,
1350 };
1351
1352 static struct clk mcbsp5_ick = {
1353 .name = "mcbsp5_ick",
1354 .parent = &l4_ck,
1355 .flags = CLOCK_IN_OMAP243X,
1356 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1357 .enable_bit = 5,
1358 .recalc = &omap2_followparent_recalc,
1359 };
1360
1361 static struct clk mcbsp5_fck = {
1362 .name = "mcbsp5_fck",
1363 .parent = &func_96m_ck,
1364 .flags = CLOCK_IN_OMAP243X,
1365 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1366 .enable_bit = 5,
1367 .recalc = &omap2_followparent_recalc,
1368 };
1369
1370 static struct clk mcspi1_ick = {
1371 .name = "mcspi1_ick",
1372 .parent = &l4_ck,
1373 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1374 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1375 .enable_bit = 17,
1376 .recalc = &omap2_followparent_recalc,
1377 };
1378
1379 static struct clk mcspi1_fck = {
1380 .name = "mcspi1_fck",
1381 .parent = &func_48m_ck,
1382 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1383 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1384 .enable_bit = 17,
1385 .recalc = &omap2_followparent_recalc,
1386 };
1387
1388 static struct clk mcspi2_ick = {
1389 .name = "mcspi2_ick",
1390 .parent = &l4_ck,
1391 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1392 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1393 .enable_bit = 18,
1394 .recalc = &omap2_followparent_recalc,
1395 };
1396
1397 static struct clk mcspi2_fck = {
1398 .name = "mcspi2_fck",
1399 .parent = &func_48m_ck,
1400 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1401 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1402 .enable_bit = 18,
1403 .recalc = &omap2_followparent_recalc,
1404 };
1405
1406 static struct clk mcspi3_ick = {
1407 .name = "mcspi3_ick",
1408 .parent = &l4_ck,
1409 .flags = CLOCK_IN_OMAP243X,
1410 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1411 .enable_bit = 9,
1412 .recalc = &omap2_followparent_recalc,
1413 };
1414
1415 static struct clk mcspi3_fck = {
1416 .name = "mcspi3_fck",
1417 .parent = &func_48m_ck,
1418 .flags = CLOCK_IN_OMAP243X,
1419 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1420 .enable_bit = 9,
1421 .recalc = &omap2_followparent_recalc,
1422 };
1423
1424 static struct clk uart1_ick = {
1425 .name = "uart1_ick",
1426 .parent = &l4_ck,
1427 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1428 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1429 .enable_bit = 21,
1430 .recalc = &omap2_followparent_recalc,
1431 };
1432
1433 static struct clk uart1_fck = {
1434 .name = "uart1_fck",
1435 .parent = &func_48m_ck,
1436 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1437 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1438 .enable_bit = 21,
1439 .recalc = &omap2_followparent_recalc,
1440 };
1441
1442 static struct clk uart2_ick = {
1443 .name = "uart2_ick",
1444 .parent = &l4_ck,
1445 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1446 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1447 .enable_bit = 22,
1448 .recalc = &omap2_followparent_recalc,
1449 };
1450
1451 static struct clk uart2_fck = {
1452 .name = "uart2_fck",
1453 .parent = &func_48m_ck,
1454 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1455 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1456 .enable_bit = 22,
1457 .recalc = &omap2_followparent_recalc,
1458 };
1459
1460 static struct clk uart3_ick = {
1461 .name = "uart3_ick",
1462 .parent = &l4_ck,
1463 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1464 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1465 .enable_bit = 2,
1466 .recalc = &omap2_followparent_recalc,
1467 };
1468
1469 static struct clk uart3_fck = {
1470 .name = "uart3_fck",
1471 .parent = &func_48m_ck,
1472 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1473 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1474 .enable_bit = 2,
1475 .recalc = &omap2_followparent_recalc,
1476 };
1477
1478 static struct clk gpios_ick = {
1479 .name = "gpios_ick",
1480 .parent = &l4_ck,
1481 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1482 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1483 .enable_bit = 2,
1484 .recalc = &omap2_followparent_recalc,
1485 };
1486
1487 static struct clk gpios_fck = {
1488 .name = "gpios_fck",
1489 .parent = &func_32k_ck,
1490 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1491 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1492 .enable_bit = 2,
1493 .recalc = &omap2_followparent_recalc,
1494 };
1495
1496 static struct clk mpu_wdt_ick = {
1497 .name = "mpu_wdt_ick",
1498 .parent = &l4_ck,
1499 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1500 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1501 .enable_bit = 3,
1502 .recalc = &omap2_followparent_recalc,
1503 };
1504
1505 static struct clk mpu_wdt_fck = {
1506 .name = "mpu_wdt_fck",
1507 .parent = &func_32k_ck,
1508 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1509 .enable_reg = (void __iomem *)&CM_FCLKEN_WKUP,
1510 .enable_bit = 3,
1511 .recalc = &omap2_followparent_recalc,
1512 };
1513
1514 static struct clk sync_32k_ick = {
1515 .name = "sync_32k_ick",
1516 .parent = &l4_ck,
1517 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1518 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1519 .enable_bit = 1,
1520 .recalc = &omap2_followparent_recalc,
1521 };
1522 static struct clk wdt1_ick = {
1523 .name = "wdt1_ick",
1524 .parent = &l4_ck,
1525 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1526 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1527 .enable_bit = 4,
1528 .recalc = &omap2_followparent_recalc,
1529 };
1530 static struct clk omapctrl_ick = {
1531 .name = "omapctrl_ick",
1532 .parent = &l4_ck,
1533 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1534 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1535 .enable_bit = 5,
1536 .recalc = &omap2_followparent_recalc,
1537 };
1538 static struct clk icr_ick = {
1539 .name = "icr_ick",
1540 .parent = &l4_ck,
1541 .flags = CLOCK_IN_OMAP243X,
1542 .enable_reg = (void __iomem *)&CM_ICLKEN_WKUP,
1543 .enable_bit = 6,
1544 .recalc = &omap2_followparent_recalc,
1545 };
1546
1547 static struct clk cam_ick = {
1548 .name = "cam_ick",
1549 .parent = &l4_ck,
1550 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1551 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1552 .enable_bit = 31,
1553 .recalc = &omap2_followparent_recalc,
1554 };
1555
1556 static struct clk cam_fck = {
1557 .name = "cam_fck",
1558 .parent = &func_96m_ck,
1559 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1560 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1561 .enable_bit = 31,
1562 .recalc = &omap2_followparent_recalc,
1563 };
1564
1565 static struct clk mailboxes_ick = {
1566 .name = "mailboxes_ick",
1567 .parent = &l4_ck,
1568 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1569 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1570 .enable_bit = 30,
1571 .recalc = &omap2_followparent_recalc,
1572 };
1573
1574 static struct clk wdt4_ick = {
1575 .name = "wdt4_ick",
1576 .parent = &l4_ck,
1577 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1578 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1579 .enable_bit = 29,
1580 .recalc = &omap2_followparent_recalc,
1581 };
1582
1583 static struct clk wdt4_fck = {
1584 .name = "wdt4_fck",
1585 .parent = &func_32k_ck,
1586 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1587 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1588 .enable_bit = 29,
1589 .recalc = &omap2_followparent_recalc,
1590 };
1591
1592 static struct clk wdt3_ick = {
1593 .name = "wdt3_ick",
1594 .parent = &l4_ck,
1595 .flags = CLOCK_IN_OMAP242X,
1596 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1597 .enable_bit = 28,
1598 .recalc = &omap2_followparent_recalc,
1599 };
1600
1601 static struct clk wdt3_fck = {
1602 .name = "wdt3_fck",
1603 .parent = &func_32k_ck,
1604 .flags = CLOCK_IN_OMAP242X,
1605 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1606 .enable_bit = 28,
1607 .recalc = &omap2_followparent_recalc,
1608 };
1609
1610 static struct clk mspro_ick = {
1611 .name = "mspro_ick",
1612 .parent = &l4_ck,
1613 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1614 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1615 .enable_bit = 27,
1616 .recalc = &omap2_followparent_recalc,
1617 };
1618
1619 static struct clk mspro_fck = {
1620 .name = "mspro_fck",
1621 .parent = &func_96m_ck,
1622 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1623 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1624 .enable_bit = 27,
1625 .recalc = &omap2_followparent_recalc,
1626 };
1627
1628 static struct clk mmc_ick = {
1629 .name = "mmc_ick",
1630 .parent = &l4_ck,
1631 .flags = CLOCK_IN_OMAP242X,
1632 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1633 .enable_bit = 26,
1634 .recalc = &omap2_followparent_recalc,
1635 };
1636
1637 static struct clk mmc_fck = {
1638 .name = "mmc_fck",
1639 .parent = &func_96m_ck,
1640 .flags = CLOCK_IN_OMAP242X,
1641 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1642 .enable_bit = 26,
1643 .recalc = &omap2_followparent_recalc,
1644 };
1645
1646 static struct clk fac_ick = {
1647 .name = "fac_ick",
1648 .parent = &l4_ck,
1649 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1650 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1651 .enable_bit = 25,
1652 .recalc = &omap2_followparent_recalc,
1653 };
1654
1655 static struct clk fac_fck = {
1656 .name = "fac_fck",
1657 .parent = &func_12m_ck,
1658 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1659 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1660 .enable_bit = 25,
1661 .recalc = &omap2_followparent_recalc,
1662 };
1663
1664 static struct clk eac_ick = {
1665 .name = "eac_ick",
1666 .parent = &l4_ck,
1667 .flags = CLOCK_IN_OMAP242X,
1668 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1669 .enable_bit = 24,
1670 .recalc = &omap2_followparent_recalc,
1671 };
1672
1673 static struct clk eac_fck = {
1674 .name = "eac_fck",
1675 .parent = &func_96m_ck,
1676 .flags = CLOCK_IN_OMAP242X,
1677 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1678 .enable_bit = 24,
1679 .recalc = &omap2_followparent_recalc,
1680 };
1681
1682 static struct clk hdq_ick = {
1683 .name = "hdq_ick",
1684 .parent = &l4_ck,
1685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1686 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1687 .enable_bit = 23,
1688 .recalc = &omap2_followparent_recalc,
1689 };
1690
1691 static struct clk hdq_fck = {
1692 .name = "hdq_fck",
1693 .parent = &func_12m_ck,
1694 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1695 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1696 .enable_bit = 23,
1697 .recalc = &omap2_followparent_recalc,
1698 };
1699
1700 static struct clk i2c2_ick = {
1701 .name = "i2c_ick",
1702 .id = 2,
1703 .parent = &l4_ck,
1704 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1705 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1706 .enable_bit = 20,
1707 .recalc = &omap2_followparent_recalc,
1708 };
1709
1710 static struct clk i2c2_fck = {
1711 .name = "i2c_fck",
1712 .id = 2,
1713 .parent = &func_12m_ck,
1714 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1715 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1716 .enable_bit = 20,
1717 .recalc = &omap2_followparent_recalc,
1718 };
1719
1720 static struct clk i2chs2_fck = {
1721 .name = "i2chs2_fck",
1722 .parent = &func_96m_ck,
1723 .flags = CLOCK_IN_OMAP243X,
1724 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1725 .enable_bit = 20,
1726 .recalc = &omap2_followparent_recalc,
1727 };
1728
1729 static struct clk i2c1_ick = {
1730 .name = "i2c_ick",
1731 .id = 1,
1732 .parent = &l4_ck,
1733 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1734 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1735 .enable_bit = 19,
1736 .recalc = &omap2_followparent_recalc,
1737 };
1738
1739 static struct clk i2c1_fck = {
1740 .name = "i2c_fck",
1741 .id = 1,
1742 .parent = &func_12m_ck,
1743 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1744 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1745 .enable_bit = 19,
1746 .recalc = &omap2_followparent_recalc,
1747 };
1748
1749 static struct clk i2chs1_fck = {
1750 .name = "i2chs1_fck",
1751 .parent = &func_96m_ck,
1752 .flags = CLOCK_IN_OMAP243X,
1753 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1754 .enable_bit = 19,
1755 .recalc = &omap2_followparent_recalc,
1756 };
1757
1758 static struct clk vlynq_ick = {
1759 .name = "vlynq_ick",
1760 .parent = &core_l3_ck,
1761 .flags = CLOCK_IN_OMAP242X,
1762 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
1763 .enable_bit = 3,
1764 .recalc = &omap2_followparent_recalc,
1765 };
1766
1767 static struct clk vlynq_fck = {
1768 .name = "vlynq_fck",
1769 .parent = &func_96m_ck,
1770 .flags = CLOCK_IN_OMAP242X | RATE_CKCTL | CM_CORE_SEL1 | DELAYED_APP,
1771 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
1772 .enable_bit = 3,
1773 .src_offset = 15,
1774 .recalc = &omap2_followparent_recalc,
1775 };
1776
1777 static struct clk sdrc_ick = {
1778 .name = "sdrc_ick",
1779 .parent = &l4_ck,
1780 .flags = CLOCK_IN_OMAP243X,
1781 .enable_reg = (void __iomem *)&CM_ICLKEN3_CORE,
1782 .enable_bit = 2,
1783 .recalc = &omap2_followparent_recalc,
1784 };
1785
1786 static struct clk des_ick = {
1787 .name = "des_ick",
1788 .parent = &l4_ck,
1789 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1790 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1791 .enable_bit = 0,
1792 .recalc = &omap2_followparent_recalc,
1793 };
1794
1795 static struct clk sha_ick = {
1796 .name = "sha_ick",
1797 .parent = &l4_ck,
1798 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1799 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1800 .enable_bit = 1,
1801 .recalc = &omap2_followparent_recalc,
1802 };
1803
1804 static struct clk rng_ick = {
1805 .name = "rng_ick",
1806 .parent = &l4_ck,
1807 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1808 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1809 .enable_bit = 2,
1810 .recalc = &omap2_followparent_recalc,
1811 };
1812
1813 static struct clk aes_ick = {
1814 .name = "aes_ick",
1815 .parent = &l4_ck,
1816 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1817 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1818 .enable_bit = 3,
1819 .recalc = &omap2_followparent_recalc,
1820 };
1821
1822 static struct clk pka_ick = {
1823 .name = "pka_ick",
1824 .parent = &l4_ck,
1825 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1826 .enable_reg = (void __iomem *)&CM_ICLKEN4_CORE,
1827 .enable_bit = 4,
1828 .recalc = &omap2_followparent_recalc,
1829 };
1830
1831 static struct clk usb_fck = {
1832 .name = "usb_fck",
1833 .parent = &func_48m_ck,
1834 .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
1835 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1836 .enable_bit = 0,
1837 .recalc = &omap2_followparent_recalc,
1838 };
1839
1840 static struct clk usbhs_ick = {
1841 .name = "usbhs_ick",
1842 .parent = &core_l3_ck,
1843 .flags = CLOCK_IN_OMAP243X,
1844 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1845 .enable_bit = 6,
1846 .recalc = &omap2_followparent_recalc,
1847 };
1848
1849 static struct clk mmchs1_ick = {
1850 .name = "mmchs1_ick",
1851 .parent = &l4_ck,
1852 .flags = CLOCK_IN_OMAP243X,
1853 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1854 .enable_bit = 7,
1855 .recalc = &omap2_followparent_recalc,
1856 };
1857
1858 static struct clk mmchs1_fck = {
1859 .name = "mmchs1_fck",
1860 .parent = &func_96m_ck,
1861 .flags = CLOCK_IN_OMAP243X,
1862 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1863 .enable_bit = 7,
1864 .recalc = &omap2_followparent_recalc,
1865 };
1866
1867 static struct clk mmchs2_ick = {
1868 .name = "mmchs2_ick",
1869 .parent = &l4_ck,
1870 .flags = CLOCK_IN_OMAP243X,
1871 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1872 .enable_bit = 8,
1873 .recalc = &omap2_followparent_recalc,
1874 };
1875
1876 static struct clk mmchs2_fck = {
1877 .name = "mmchs2_fck",
1878 .parent = &func_96m_ck,
1879 .flags = CLOCK_IN_OMAP243X,
1880 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1881 .enable_bit = 8,
1882 .recalc = &omap2_followparent_recalc,
1883 };
1884
1885 static struct clk gpio5_ick = {
1886 .name = "gpio5_ick",
1887 .parent = &l4_ck,
1888 .flags = CLOCK_IN_OMAP243X,
1889 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1890 .enable_bit = 10,
1891 .recalc = &omap2_followparent_recalc,
1892 };
1893
1894 static struct clk gpio5_fck = {
1895 .name = "gpio5_fck",
1896 .parent = &func_32k_ck,
1897 .flags = CLOCK_IN_OMAP243X,
1898 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1899 .enable_bit = 10,
1900 .recalc = &omap2_followparent_recalc,
1901 };
1902
1903 static struct clk mdm_intc_ick = {
1904 .name = "mdm_intc_ick",
1905 .parent = &l4_ck,
1906 .flags = CLOCK_IN_OMAP243X,
1907 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
1908 .enable_bit = 11,
1909 .recalc = &omap2_followparent_recalc,
1910 };
1911
1912 static struct clk mmchsdb1_fck = {
1913 .name = "mmchsdb1_fck",
1914 .parent = &func_32k_ck,
1915 .flags = CLOCK_IN_OMAP243X,
1916 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1917 .enable_bit = 16,
1918 .recalc = &omap2_followparent_recalc,
1919 };
1920
1921 static struct clk mmchsdb2_fck = {
1922 .name = "mmchsdb2_fck",
1923 .parent = &func_32k_ck,
1924 .flags = CLOCK_IN_OMAP243X,
1925 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
1926 .enable_bit = 17,
1927 .recalc = &omap2_followparent_recalc,
1928 };
1929
1930 /*
1931 * This clock is a composite clock which does entire set changes then
1932 * forces a rebalance. It keys on the MPU speed, but it really could
1933 * be any key speed part of a set in the rate table.
1934 *
1935 * to really change a set, you need memory table sets which get changed
1936 * in sram, pre-notifiers & post notifiers, changing the top set, without
1937 * having low level display recalc's won't work... this is why dpm notifiers
1938 * work, isr's off, walk a list of clocks already _off_ and not messing with
1939 * the bus.
1940 *
1941 * This clock should have no parent. It embodies the entire upper level
1942 * active set. A parent will mess up some of the init also.
1943 */
1944 static struct clk virt_prcm_set = {
1945 .name = "virt_prcm_set",
1946 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
1947 VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
1948 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1949 .recalc = &omap2_mpu_recalc, /* sets are keyed on mpu rate */
1950 .set_rate = &omap2_select_table_rate,
1951 .round_rate = &omap2_round_to_table_rate,
1952 };
1953
1954 static struct clk *onchip_clks[] = {
1955 /* external root sources */
1956 &func_32k_ck,
1957 &osc_ck,
1958 &sys_ck,
1959 &alt_ck,
1960 /* internal analog sources */
1961 &dpll_ck,
1962 &apll96_ck,
1963 &apll54_ck,
1964 /* internal prcm root sources */
1965 &func_54m_ck,
1966 &core_ck,
1967 &sleep_ck,
1968 &func_96m_ck,
1969 &func_48m_ck,
1970 &func_12m_ck,
1971 &wdt1_osc_ck,
1972 &sys_clkout,
1973 &sys_clkout2,
1974 &emul_ck,
1975 /* mpu domain clocks */
1976 &mpu_ck,
1977 /* dsp domain clocks */
1978 &iva2_1_fck, /* 2430 */
1979 &iva2_1_ick,
1980 &dsp_ick, /* 2420 */
1981 &dsp_fck,
1982 &iva1_ifck,
1983 &iva1_mpu_int_ifck,
1984 /* GFX domain clocks */
1985 &gfx_3d_fck,
1986 &gfx_2d_fck,
1987 &gfx_ick,
1988 /* Modem domain clocks */
1989 &mdm_ick,
1990 &mdm_osc_ck,
1991 /* DSS domain clocks */
1992 &dss_ick,
1993 &dss1_fck,
1994 &dss2_fck,
1995 &dss_54m_fck,
1996 /* L3 domain clocks */
1997 &core_l3_ck,
1998 &ssi_ssr_sst_fck,
1999 &usb_l4_ick,
2000 /* L4 domain clocks */
2001 &l4_ck, /* used as both core_l4 and wu_l4 */
2002 &ssi_l4_ick,
2003 /* virtual meta-group clock */
2004 &virt_prcm_set,
2005 /* general l4 interface ck, multi-parent functional clk */
2006 &gpt1_ick,
2007 &gpt1_fck,
2008 &gpt2_ick,
2009 &gpt2_fck,
2010 &gpt3_ick,
2011 &gpt3_fck,
2012 &gpt4_ick,
2013 &gpt4_fck,
2014 &gpt5_ick,
2015 &gpt5_fck,
2016 &gpt6_ick,
2017 &gpt6_fck,
2018 &gpt7_ick,
2019 &gpt7_fck,
2020 &gpt8_ick,
2021 &gpt8_fck,
2022 &gpt9_ick,
2023 &gpt9_fck,
2024 &gpt10_ick,
2025 &gpt10_fck,
2026 &gpt11_ick,
2027 &gpt11_fck,
2028 &gpt12_ick,
2029 &gpt12_fck,
2030 &mcbsp1_ick,
2031 &mcbsp1_fck,
2032 &mcbsp2_ick,
2033 &mcbsp2_fck,
2034 &mcbsp3_ick,
2035 &mcbsp3_fck,
2036 &mcbsp4_ick,
2037 &mcbsp4_fck,
2038 &mcbsp5_ick,
2039 &mcbsp5_fck,
2040 &mcspi1_ick,
2041 &mcspi1_fck,
2042 &mcspi2_ick,
2043 &mcspi2_fck,
2044 &mcspi3_ick,
2045 &mcspi3_fck,
2046 &uart1_ick,
2047 &uart1_fck,
2048 &uart2_ick,
2049 &uart2_fck,
2050 &uart3_ick,
2051 &uart3_fck,
2052 &gpios_ick,
2053 &gpios_fck,
2054 &mpu_wdt_ick,
2055 &mpu_wdt_fck,
2056 &sync_32k_ick,
2057 &wdt1_ick,
2058 &omapctrl_ick,
2059 &icr_ick,
2060 &cam_fck,
2061 &cam_ick,
2062 &mailboxes_ick,
2063 &wdt4_ick,
2064 &wdt4_fck,
2065 &wdt3_ick,
2066 &wdt3_fck,
2067 &mspro_ick,
2068 &mspro_fck,
2069 &mmc_ick,
2070 &mmc_fck,
2071 &fac_ick,
2072 &fac_fck,
2073 &eac_ick,
2074 &eac_fck,
2075 &hdq_ick,
2076 &hdq_fck,
2077 &i2c1_ick,
2078 &i2c1_fck,
2079 &i2chs1_fck,
2080 &i2c2_ick,
2081 &i2c2_fck,
2082 &i2chs2_fck,
2083 &vlynq_ick,
2084 &vlynq_fck,
2085 &sdrc_ick,
2086 &des_ick,
2087 &sha_ick,
2088 &rng_ick,
2089 &aes_ick,
2090 &pka_ick,
2091 &usb_fck,
2092 &usbhs_ick,
2093 &mmchs1_ick,
2094 &mmchs1_fck,
2095 &mmchs2_ick,
2096 &mmchs2_fck,
2097 &gpio5_ick,
2098 &gpio5_fck,
2099 &mdm_intc_ick,
2100 &mmchsdb1_fck,
2101 &mmchsdb2_fck,
2102 };
2103
2104 #endif
WRT350N Kernel Patches