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[SCSI] ibmvscsi: convert kmalloc + memset to kcalloc
[wrt350n-kernel.git] / arch / arm / mm / alignment.c
blob705c98921c372e034af6b21ecf569872393cbe43
1 /*
2 * linux/arch/arm/mm/alignment.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb aligment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/config.h>
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/proc_fs.h>
21 #include <linux/init.h>
22
23 #include <asm/uaccess.h>
24 #include <asm/unaligned.h>
25
26 #include "fault.h"
27
28 /*
29 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
30 * /proc/sys/debug/alignment, modified and integrated into
31 * Linux 2.1 by Russell King
32 *
33 * Speed optimisations and better fault handling by Russell King.
34 *
35 * *** NOTE ***
36 * This code is not portable to processors with late data abort handling.
37 */
38 #define CODING_BITS(i) (i & 0x0e000000)
39
40 #define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
41 #define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
42 #define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
43 #define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
44 #define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
45
46 #define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
47
48 #define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
49 #define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
50
51 #define RN_BITS(i) ((i >> 16) & 15) /* Rn */
52 #define RD_BITS(i) ((i >> 12) & 15) /* Rd */
53 #define RM_BITS(i) (i & 15) /* Rm */
54
55 #define REGMASK_BITS(i) (i & 0xffff)
56 #define OFFSET_BITS(i) (i & 0x0fff)
57
58 #define IS_SHIFT(i) (i & 0x0ff0)
59 #define SHIFT_BITS(i) ((i >> 7) & 0x1f)
60 #define SHIFT_TYPE(i) (i & 0x60)
61 #define SHIFT_LSL 0x00
62 #define SHIFT_LSR 0x20
63 #define SHIFT_ASR 0x40
64 #define SHIFT_RORRRX 0x60
65
66 static unsigned long ai_user;
67 static unsigned long ai_sys;
68 static unsigned long ai_skipped;
69 static unsigned long ai_half;
70 static unsigned long ai_word;
71 static unsigned long ai_dword;
72 static unsigned long ai_multi;
73 static int ai_usermode;
74
75 #ifdef CONFIG_PROC_FS
76 static const char *usermode_action[] = {
77 "ignored",
78 "warn",
79 "fixup",
80 "fixup+warn",
81 "signal",
82 "signal+warn"
83 };
84
85 static int
86 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
87 void *data)
88 {
89 char *p = page;
90 int len;
91
92 p += sprintf(p, "User:\t\t%lu\n", ai_user);
93 p += sprintf(p, "System:\t\t%lu\n", ai_sys);
94 p += sprintf(p, "Skipped:\t%lu\n", ai_skipped);
95 p += sprintf(p, "Half:\t\t%lu\n", ai_half);
96 p += sprintf(p, "Word:\t\t%lu\n", ai_word);
97 if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
98 p += sprintf(p, "DWord:\t\t%lu\n", ai_dword);
99 p += sprintf(p, "Multi:\t\t%lu\n", ai_multi);
100 p += sprintf(p, "User faults:\t%i (%s)\n", ai_usermode,
101 usermode_action[ai_usermode]);
102
103 len = (p - page) - off;
104 if (len < 0)
105 len = 0;
106
107 *eof = (len <= count) ? 1 : 0;
108 *start = page + off;
109
110 return len;
111 }
112
113 static int proc_alignment_write(struct file *file, const char __user *buffer,
114 unsigned long count, void *data)
115 {
116 char mode;
117
118 if (count > 0) {
119 if (get_user(mode, buffer))
120 return -EFAULT;
121 if (mode >= '0' && mode <= '5')
122 ai_usermode = mode - '0';
123 }
124 return count;
125 }
126
127 #endif /* CONFIG_PROC_FS */
128
129 union offset_union {
130 unsigned long un;
131 signed long sn;
132 };
133
134 #define TYPE_ERROR 0
135 #define TYPE_FAULT 1
136 #define TYPE_LDST 2
137 #define TYPE_DONE 3
138
139 #ifdef __ARMEB__
140 #define BE 1
141 #define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
142 #define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
143 #define NEXT_BYTE "ror #24"
144 #else
145 #define BE 0
146 #define FIRST_BYTE_16
147 #define FIRST_BYTE_32
148 #define NEXT_BYTE "lsr #8"
149 #endif
150
151 #define __get8_unaligned_check(ins,val,addr,err) \
152 __asm__( \
153 "1: "ins" %1, [%2], #1\n" \
154 "2:\n" \
155 " .section .fixup,\"ax\"\n" \
156 " .align 2\n" \
157 "3: mov %0, #1\n" \
158 " b 2b\n" \
159 " .previous\n" \
160 " .section __ex_table,\"a\"\n" \
161 " .align 3\n" \
162 " .long 1b, 3b\n" \
163 " .previous\n" \
164 : "=r" (err), "=&r" (val), "=r" (addr) \
165 : "0" (err), "2" (addr))
166
167 #define __get16_unaligned_check(ins,val,addr) \
168 do { \
169 unsigned int err = 0, v, a = addr; \
170 __get8_unaligned_check(ins,v,a,err); \
171 val = v << ((BE) ? 8 : 0); \
172 __get8_unaligned_check(ins,v,a,err); \
173 val |= v << ((BE) ? 0 : 8); \
174 if (err) \
175 goto fault; \
176 } while (0)
177
178 #define get16_unaligned_check(val,addr) \
179 __get16_unaligned_check("ldrb",val,addr)
180
181 #define get16t_unaligned_check(val,addr) \
182 __get16_unaligned_check("ldrbt",val,addr)
183
184 #define __get32_unaligned_check(ins,val,addr) \
185 do { \
186 unsigned int err = 0, v, a = addr; \
187 __get8_unaligned_check(ins,v,a,err); \
188 val = v << ((BE) ? 24 : 0); \
189 __get8_unaligned_check(ins,v,a,err); \
190 val |= v << ((BE) ? 16 : 8); \
191 __get8_unaligned_check(ins,v,a,err); \
192 val |= v << ((BE) ? 8 : 16); \
193 __get8_unaligned_check(ins,v,a,err); \
194 val |= v << ((BE) ? 0 : 24); \
195 if (err) \
196 goto fault; \
197 } while (0)
198
199 #define get32_unaligned_check(val,addr) \
200 __get32_unaligned_check("ldrb",val,addr)
201
202 #define get32t_unaligned_check(val,addr) \
203 __get32_unaligned_check("ldrbt",val,addr)
204
205 #define __put16_unaligned_check(ins,val,addr) \
206 do { \
207 unsigned int err = 0, v = val, a = addr; \
208 __asm__( FIRST_BYTE_16 \
209 "1: "ins" %1, [%2], #1\n" \
210 " mov %1, %1, "NEXT_BYTE"\n" \
211 "2: "ins" %1, [%2]\n" \
212 "3:\n" \
213 " .section .fixup,\"ax\"\n" \
214 " .align 2\n" \
215 "4: mov %0, #1\n" \
216 " b 3b\n" \
217 " .previous\n" \
218 " .section __ex_table,\"a\"\n" \
219 " .align 3\n" \
220 " .long 1b, 4b\n" \
221 " .long 2b, 4b\n" \
222 " .previous\n" \
223 : "=r" (err), "=&r" (v), "=&r" (a) \
224 : "0" (err), "1" (v), "2" (a)); \
225 if (err) \
226 goto fault; \
227 } while (0)
228
229 #define put16_unaligned_check(val,addr) \
230 __put16_unaligned_check("strb",val,addr)
231
232 #define put16t_unaligned_check(val,addr) \
233 __put16_unaligned_check("strbt",val,addr)
234
235 #define __put32_unaligned_check(ins,val,addr) \
236 do { \
237 unsigned int err = 0, v = val, a = addr; \
238 __asm__( FIRST_BYTE_32 \
239 "1: "ins" %1, [%2], #1\n" \
240 " mov %1, %1, "NEXT_BYTE"\n" \
241 "2: "ins" %1, [%2], #1\n" \
242 " mov %1, %1, "NEXT_BYTE"\n" \
243 "3: "ins" %1, [%2], #1\n" \
244 " mov %1, %1, "NEXT_BYTE"\n" \
245 "4: "ins" %1, [%2]\n" \
246 "5:\n" \
247 " .section .fixup,\"ax\"\n" \
248 " .align 2\n" \
249 "6: mov %0, #1\n" \
250 " b 5b\n" \
251 " .previous\n" \
252 " .section __ex_table,\"a\"\n" \
253 " .align 3\n" \
254 " .long 1b, 6b\n" \
255 " .long 2b, 6b\n" \
256 " .long 3b, 6b\n" \
257 " .long 4b, 6b\n" \
258 " .previous\n" \
259 : "=r" (err), "=&r" (v), "=&r" (a) \
260 : "0" (err), "1" (v), "2" (a)); \
261 if (err) \
262 goto fault; \
263 } while (0)
264
265 #define put32_unaligned_check(val,addr) \
266 __put32_unaligned_check("strb", val, addr)
267
268 #define put32t_unaligned_check(val,addr) \
269 __put32_unaligned_check("strbt", val, addr)
270
271 static void
272 do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
273 {
274 if (!LDST_U_BIT(instr))
275 offset.un = -offset.un;
276
277 if (!LDST_P_BIT(instr))
278 addr += offset.un;
279
280 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
281 regs->uregs[RN_BITS(instr)] = addr;
282 }
283
284 static int
285 do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
286 {
287 unsigned int rd = RD_BITS(instr);
288
289 ai_half += 1;
290
291 if (user_mode(regs))
292 goto user;
293
294 if (LDST_L_BIT(instr)) {
295 unsigned long val;
296 get16_unaligned_check(val, addr);
297
298 /* signed half-word? */
299 if (instr & 0x40)
300 val = (signed long)((signed short) val);
301
302 regs->uregs[rd] = val;
303 } else
304 put16_unaligned_check(regs->uregs[rd], addr);
305
306 return TYPE_LDST;
307
308 user:
309 if (LDST_L_BIT(instr)) {
310 unsigned long val;
311 get16t_unaligned_check(val, addr);
312
313 /* signed half-word? */
314 if (instr & 0x40)
315 val = (signed long)((signed short) val);
316
317 regs->uregs[rd] = val;
318 } else
319 put16t_unaligned_check(regs->uregs[rd], addr);
320
321 return TYPE_LDST;
322
323 fault:
324 return TYPE_FAULT;
325 }
326
327 static int
328 do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
329 struct pt_regs *regs)
330 {
331 unsigned int rd = RD_BITS(instr);
332
333 if (((rd & 1) == 1) || (rd == 14))
334 goto bad;
335
336 ai_dword += 1;
337
338 if (user_mode(regs))
339 goto user;
340
341 if ((instr & 0xf0) == 0xd0) {
342 unsigned long val;
343 get32_unaligned_check(val, addr);
344 regs->uregs[rd] = val;
345 get32_unaligned_check(val, addr + 4);
346 regs->uregs[rd + 1] = val;
347 } else {
348 put32_unaligned_check(regs->uregs[rd], addr);
349 put32_unaligned_check(regs->uregs[rd + 1], addr + 4);
350 }
351
352 return TYPE_LDST;
353
354 user:
355 if ((instr & 0xf0) == 0xd0) {
356 unsigned long val;
357 get32t_unaligned_check(val, addr);
358 regs->uregs[rd] = val;
359 get32t_unaligned_check(val, addr + 4);
360 regs->uregs[rd + 1] = val;
361 } else {
362 put32t_unaligned_check(regs->uregs[rd], addr);
363 put32t_unaligned_check(regs->uregs[rd + 1], addr + 4);
364 }
365
366 return TYPE_LDST;
367 bad:
368 return TYPE_ERROR;
369 fault:
370 return TYPE_FAULT;
371 }
372
373 static int
374 do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
375 {
376 unsigned int rd = RD_BITS(instr);
377
378 ai_word += 1;
379
380 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
381 goto trans;
382
383 if (LDST_L_BIT(instr)) {
384 unsigned int val;
385 get32_unaligned_check(val, addr);
386 regs->uregs[rd] = val;
387 } else
388 put32_unaligned_check(regs->uregs[rd], addr);
389 return TYPE_LDST;
390
391 trans:
392 if (LDST_L_BIT(instr)) {
393 unsigned int val;
394 get32t_unaligned_check(val, addr);
395 regs->uregs[rd] = val;
396 } else
397 put32t_unaligned_check(regs->uregs[rd], addr);
398 return TYPE_LDST;
399
400 fault:
401 return TYPE_FAULT;
402 }
403
404 /*
405 * LDM/STM alignment handler.
406 *
407 * There are 4 variants of this instruction:
408 *
409 * B = rn pointer before instruction, A = rn pointer after instruction
410 * ------ increasing address ----->
411 * | | r0 | r1 | ... | rx | |
412 * PU = 01 B A
413 * PU = 11 B A
414 * PU = 00 A B
415 * PU = 10 A B
416 */
417 static int
418 do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
419 {
420 unsigned int rd, rn, correction, nr_regs, regbits;
421 unsigned long eaddr, newaddr;
422
423 if (LDM_S_BIT(instr))
424 goto bad;
425
426 correction = 4; /* processor implementation defined */
427 regs->ARM_pc += correction;
428
429 ai_multi += 1;
430
431 /* count the number of registers in the mask to be transferred */
432 nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
433
434 rn = RN_BITS(instr);
435 newaddr = eaddr = regs->uregs[rn];
436
437 if (!LDST_U_BIT(instr))
438 nr_regs = -nr_regs;
439 newaddr += nr_regs;
440 if (!LDST_U_BIT(instr))
441 eaddr = newaddr;
442
443 if (LDST_P_EQ_U(instr)) /* U = P */
444 eaddr += 4;
445
446 /*
447 * For alignment faults on the ARM922T/ARM920T the MMU makes
448 * the FSR (and hence addr) equal to the updated base address
449 * of the multiple access rather than the restored value.
450 * Switch this message off if we've got a ARM92[02], otherwise
451 * [ls]dm alignment faults are noisy!
452 */
453 #if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
454 /*
455 * This is a "hint" - we already have eaddr worked out by the
456 * processor for us.
457 */
458 if (addr != eaddr) {
459 printk(KERN_ERR "LDMSTM: PC = %08lx, instr = %08lx, "
460 "addr = %08lx, eaddr = %08lx\n",
461 instruction_pointer(regs), instr, addr, eaddr);
462 show_regs(regs);
463 }
464 #endif
465
466 if (user_mode(regs)) {
467 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
468 regbits >>= 1, rd += 1)
469 if (regbits & 1) {
470 if (LDST_L_BIT(instr)) {
471 unsigned int val;
472 get32t_unaligned_check(val, eaddr);
473 regs->uregs[rd] = val;
474 } else
475 put32t_unaligned_check(regs->uregs[rd], eaddr);
476 eaddr += 4;
477 }
478 } else {
479 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
480 regbits >>= 1, rd += 1)
481 if (regbits & 1) {
482 if (LDST_L_BIT(instr)) {
483 unsigned int val;
484 get32_unaligned_check(val, eaddr);
485 regs->uregs[rd] = val;
486 } else
487 put32_unaligned_check(regs->uregs[rd], eaddr);
488 eaddr += 4;
489 }
490 }
491
492 if (LDST_W_BIT(instr))
493 regs->uregs[rn] = newaddr;
494 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
495 regs->ARM_pc -= correction;
496 return TYPE_DONE;
497
498 fault:
499 regs->ARM_pc -= correction;
500 return TYPE_FAULT;
501
502 bad:
503 printk(KERN_ERR "Alignment trap: not handling ldm with s-bit set\n");
504 return TYPE_ERROR;
505 }
506
507 /*
508 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
509 * we can reuse ARM userland alignment fault fixups for Thumb.
510 *
511 * This implementation was initially based on the algorithm found in
512 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
513 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
514 *
515 * NOTES:
516 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
517 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
518 * decode, we return 0xdeadc0de. This should never happen under normal
519 * circumstances but if it does, we've got other problems to deal with
520 * elsewhere and we obviously can't fix those problems here.
521 */
522
523 static unsigned long
524 thumb2arm(u16 tinstr)
525 {
526 u32 L = (tinstr & (1<<11)) >> 11;
527
528 switch ((tinstr & 0xf800) >> 11) {
529 /* 6.5.1 Format 1: */
530 case 0x6000 >> 11: /* 7.1.52 STR(1) */
531 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
532 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
533 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
534 return 0xe5800000 |
535 ((tinstr & (1<<12)) << (22-12)) | /* fixup */
536 (L<<20) | /* L==1? */
537 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
538 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
539 ((tinstr & (31<<6)) >> /* immed_5 */
540 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
541 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
542 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
543 return 0xe1c000b0 |
544 (L<<20) | /* L==1? */
545 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
546 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
547 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
548 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
549
550 /* 6.5.1 Format 2: */
551 case 0x5000 >> 11:
552 case 0x5800 >> 11:
553 {
554 static const u32 subset[8] = {
555 0xe7800000, /* 7.1.53 STR(2) */
556 0xe18000b0, /* 7.1.58 STRH(2) */
557 0xe7c00000, /* 7.1.56 STRB(2) */
558 0xe19000d0, /* 7.1.34 LDRSB */
559 0xe7900000, /* 7.1.27 LDR(2) */
560 0xe19000b0, /* 7.1.33 LDRH(2) */
561 0xe7d00000, /* 7.1.31 LDRB(2) */
562 0xe19000f0 /* 7.1.35 LDRSH */
563 };
564 return subset[(tinstr & (7<<9)) >> 9] |
565 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
566 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
567 ((tinstr & (7<<6)) >> (6-0)); /* Rm */
568 }
569
570 /* 6.5.1 Format 3: */
571 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
572 /* NOTE: This case is not technically possible. We're
573 * loading 32-bit memory data via PC relative
574 * addressing mode. So we can and should eliminate
575 * this case. But I'll leave it here for now.
576 */
577 return 0xe59f0000 |
578 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
579 ((tinstr & 255) << (2-0)); /* immed_8 */
580
581 /* 6.5.1 Format 4: */
582 case 0x9000 >> 11: /* 7.1.54 STR(3) */
583 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
584 return 0xe58d0000 |
585 (L<<20) | /* L==1? */
586 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
587 ((tinstr & 255) << 2); /* immed_8 */
588
589 /* 6.6.1 Format 1: */
590 case 0xc000 >> 11: /* 7.1.51 STMIA */
591 case 0xc800 >> 11: /* 7.1.25 LDMIA */
592 {
593 u32 Rn = (tinstr & (7<<8)) >> 8;
594 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
595
596 return 0xe8800000 | W | (L<<20) | (Rn<<16) |
597 (tinstr&255);
598 }
599
600 /* 6.6.1 Format 2: */
601 case 0xb000 >> 11: /* 7.1.48 PUSH */
602 case 0xb800 >> 11: /* 7.1.47 POP */
603 if ((tinstr & (3 << 9)) == 0x0400) {
604 static const u32 subset[4] = {
605 0xe92d0000, /* STMDB sp!,{registers} */
606 0xe92d4000, /* STMDB sp!,{registers,lr} */
607 0xe8bd0000, /* LDMIA sp!,{registers} */
608 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
609 };
610 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
611 (tinstr & 255); /* register_list */
612 }
613 /* Else fall through for illegal instruction case */
614
615 default:
616 return 0xdeadc0de;
617 }
618 }
619
620 static int
621 do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
622 {
623 union offset_union offset;
624 unsigned long instr = 0, instrptr;
625 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
626 unsigned int type;
627 mm_segment_t fs;
628 unsigned int fault;
629 u16 tinstr = 0;
630
631 instrptr = instruction_pointer(regs);
632
633 fs = get_fs();
634 set_fs(KERNEL_DS);
635 if thumb_mode(regs) {
636 fault = __get_user(tinstr, (u16 *)(instrptr & ~1));
637 if (!(fault))
638 instr = thumb2arm(tinstr);
639 } else
640 fault = __get_user(instr, (u32 *)instrptr);
641 set_fs(fs);
642
643 if (fault) {
644 type = TYPE_FAULT;
645 goto bad_or_fault;
646 }
647
648 if (user_mode(regs))
649 goto user;
650
651 ai_sys += 1;
652
653 fixup:
654
655 regs->ARM_pc += thumb_mode(regs) ? 2 : 4;
656
657 switch (CODING_BITS(instr)) {
658 case 0x00000000: /* 3.13.4 load/store instruction extensions */
659 if (LDSTHD_I_BIT(instr))
660 offset.un = (instr & 0xf00) >> 4 | (instr & 15);
661 else
662 offset.un = regs->uregs[RM_BITS(instr)];
663
664 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
665 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */
666 handler = do_alignment_ldrhstrh;
667 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
668 (instr & 0x001000f0) == 0x000000f0) /* STRD */
669 handler = do_alignment_ldrdstrd;
670 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
671 goto swp;
672 else
673 goto bad;
674 break;
675
676 case 0x04000000: /* ldr or str immediate */
677 offset.un = OFFSET_BITS(instr);
678 handler = do_alignment_ldrstr;
679 break;
680
681 case 0x06000000: /* ldr or str register */
682 offset.un = regs->uregs[RM_BITS(instr)];
683
684 if (IS_SHIFT(instr)) {
685 unsigned int shiftval = SHIFT_BITS(instr);
686
687 switch(SHIFT_TYPE(instr)) {
688 case SHIFT_LSL:
689 offset.un <<= shiftval;
690 break;
691
692 case SHIFT_LSR:
693 offset.un >>= shiftval;
694 break;
695
696 case SHIFT_ASR:
697 offset.sn >>= shiftval;
698 break;
699
700 case SHIFT_RORRRX:
701 if (shiftval == 0) {
702 offset.un >>= 1;
703 if (regs->ARM_cpsr & PSR_C_BIT)
704 offset.un |= 1 << 31;
705 } else
706 offset.un = offset.un >> shiftval |
707 offset.un << (32 - shiftval);
708 break;
709 }
710 }
711 handler = do_alignment_ldrstr;
712 break;
713
714 case 0x08000000: /* ldm or stm */
715 handler = do_alignment_ldmstm;
716 break;
717
718 default:
719 goto bad;
720 }
721
722 type = handler(addr, instr, regs);
723
724 if (type == TYPE_ERROR || type == TYPE_FAULT)
725 goto bad_or_fault;
726
727 if (type == TYPE_LDST)
728 do_alignment_finish_ldst(addr, instr, regs, offset);
729
730 return 0;
731
732 bad_or_fault:
733 if (type == TYPE_ERROR)
734 goto bad;
735 regs->ARM_pc -= thumb_mode(regs) ? 2 : 4;
736 /*
737 * We got a fault - fix it up, or die.
738 */
739 do_bad_area(current, current->mm, addr, fsr, regs);
740 return 0;
741
742 swp:
743 printk(KERN_ERR "Alignment trap: not handling swp instruction\n");
744
745 bad:
746 /*
747 * Oops, we didn't handle the instruction.
748 */
749 printk(KERN_ERR "Alignment trap: not handling instruction "
750 "%0*lx at [<%08lx>]\n",
751 thumb_mode(regs) ? 4 : 8,
752 thumb_mode(regs) ? tinstr : instr, instrptr);
753 ai_skipped += 1;
754 return 1;
755
756 user:
757 ai_user += 1;
758
759 if (ai_usermode & 1)
760 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
761 "Address=0x%08lx FSR 0x%03x\n", current->comm,
762 current->pid, instrptr,
763 thumb_mode(regs) ? 4 : 8,
764 thumb_mode(regs) ? tinstr : instr,
765 addr, fsr);
766
767 if (ai_usermode & 2)
768 goto fixup;
769
770 if (ai_usermode & 4)
771 force_sig(SIGBUS, current);
772 else
773 set_cr(cr_no_alignment);
774
775 return 0;
776 }
777
778 /*
779 * This needs to be done after sysctl_init, otherwise sys/ will be
780 * overwritten. Actually, this shouldn't be in sys/ at all since
781 * it isn't a sysctl, and it doesn't contain sysctl information.
782 * We now locate it in /proc/cpu/alignment instead.
783 */
784 static int __init alignment_init(void)
785 {
786 #ifdef CONFIG_PROC_FS
787 struct proc_dir_entry *res;
788
789 res = proc_mkdir("cpu", NULL);
790 if (!res)
791 return -ENOMEM;
792
793 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
794 if (!res)
795 return -ENOMEM;
796
797 res->read_proc = proc_alignment_read;
798 res->write_proc = proc_alignment_write;
799 #endif
800
801 hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
802 hook_fault_code(3, do_alignment, SIGILL, "alignment exception");
803
804 return 0;
805 }
806
807 fs_initcall(alignment_init);
WRT350N Kernel Patches