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[PATCH] ocfs2: zero_user_page conversion
[wrt350n-kernel.git] / arch / mips / tx4938 / toshiba_rbtx4938 / setup.c
blob6ed39a5aea7262b0e9941818234e0b7cfc712771
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/console.h>
20 #include <linux/pci.h>
21 #include <linux/pm.h>
22 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24
25 #include <asm/wbflush.h>
26 #include <asm/reboot.h>
27 #include <asm/irq.h>
28 #include <asm/time.h>
29 #include <asm/uaccess.h>
30 #include <asm/io.h>
31 #include <asm/bootinfo.h>
32 #include <asm/tx4938/rbtx4938.h>
33 #ifdef CONFIG_SERIAL_TXX9
34 #include <linux/tty.h>
35 #include <linux/serial.h>
36 #include <linux/serial_core.h>
37 #endif
38 #include <linux/spi/spi.h>
39 #include <asm/tx4938/spi.h>
40 #include <asm/gpio.h>
41
42 extern void rbtx4938_time_init(void) __init;
43 extern char * __init prom_getcmdline(void);
44 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
45
46 /* These functions are used for rebooting or halting the machine*/
47 extern void rbtx4938_machine_restart(char *command);
48 extern void rbtx4938_machine_halt(void);
49 extern void rbtx4938_machine_power_off(void);
50
51 /* clocks */
52 unsigned int txx9_master_clock;
53 unsigned int txx9_cpu_clock;
54 unsigned int txx9_gbus_clock;
55
56 unsigned long rbtx4938_ce_base[8];
57 unsigned long rbtx4938_ce_size[8];
58 int txboard_pci66_mode;
59 static int tx4938_pcic_trdyto; /* default: disabled */
60 static int tx4938_pcic_retryto; /* default: disabled */
61 static int tx4938_ccfg_toeon = 1;
62
63 struct tx4938_pcic_reg *pcicptrs[4] = {
64 tx4938_pcicptr /* default setting for TX4938 */
65 };
66
67 static struct {
68 unsigned long base;
69 unsigned long size;
70 } phys_regions[16] __initdata;
71 static int num_phys_regions __initdata;
72
73 #define PHYS_REGION_MINSIZE 0x10000
74
75 void rbtx4938_machine_halt(void)
76 {
77 printk(KERN_NOTICE "System Halted\n");
78 local_irq_disable();
79
80 while (1)
81 __asm__(".set\tmips3\n\t"
82 "wait\n\t"
83 ".set\tmips0");
84 }
85
86 void rbtx4938_machine_power_off(void)
87 {
88 rbtx4938_machine_halt();
89 /* no return */
90 }
91
92 void rbtx4938_machine_restart(char *command)
93 {
94 local_irq_disable();
95
96 printk("Rebooting...");
97 *rbtx4938_softresetlock_ptr = 1;
98 *rbtx4938_sfvol_ptr = 1;
99 *rbtx4938_softreset_ptr = 1;
100 wbflush();
101
102 while(1);
103 }
104
105 void __init
106 txboard_add_phys_region(unsigned long base, unsigned long size)
107 {
108 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
109 printk("phys_region overflow\n");
110 return;
111 }
112 phys_regions[num_phys_regions].base = base;
113 phys_regions[num_phys_regions].size = size;
114 num_phys_regions++;
115 }
116 unsigned long __init
117 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
118 unsigned long size)
119 {
120 unsigned long base;
121 int i;
122
123 for (base = begin / size * size; base < end; base += size) {
124 for (i = 0; i < num_phys_regions; i++) {
125 if (phys_regions[i].size &&
126 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
127 base + (size - 1) >= phys_regions[i].base)
128 break;
129 }
130 if (i == num_phys_regions)
131 return base;
132 }
133 return 0;
134 }
135 unsigned long __init
136 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
137 unsigned long *size)
138 {
139 unsigned long sz, base;
140 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
141 base = txboard_find_free_phys_region(begin, end, sz);
142 if (base) {
143 *size = sz;
144 return base;
145 }
146 }
147 return 0;
148 }
149 unsigned long __init
150 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
151 unsigned long size)
152 {
153 unsigned long base;
154 base = txboard_find_free_phys_region(begin, end, size);
155 if (base)
156 txboard_add_phys_region(base, size);
157 return base;
158 }
159 unsigned long __init
160 txboard_request_phys_region(unsigned long size)
161 {
162 unsigned long base;
163 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
164 base = txboard_find_free_phys_region(begin, end, size);
165 if (base)
166 txboard_add_phys_region(base, size);
167 return base;
168 }
169 unsigned long __init
170 txboard_request_phys_region_shrink(unsigned long *size)
171 {
172 unsigned long base;
173 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
174 base = txboard_find_free_phys_region_shrink(begin, end, size);
175 if (base)
176 txboard_add_phys_region(base, *size);
177 return base;
178 }
179
180 #ifdef CONFIG_PCI
181 void __init
182 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
183 struct pci_controller *channel,
184 unsigned long pci_io_base,
185 int extarb)
186 {
187 int i;
188
189 /* Disable All Initiator Space */
190 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
191 TX4938_PCIC_PCICCFG_G2PMEN(1)|
192 TX4938_PCIC_PCICCFG_G2PMEN(2)|
193 TX4938_PCIC_PCICCFG_G2PIOEN);
194
195 /* GB->PCI mappings */
196 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
197 pcicptr->g2piogbase = pci_io_base |
198 #ifdef __BIG_ENDIAN
199 TX4938_PCIC_G2PIOGBASE_ECHG
200 #else
201 TX4938_PCIC_G2PIOGBASE_BSDIS
202 #endif
203 ;
204 pcicptr->g2piopbase = 0;
205 for (i = 0; i < 3; i++) {
206 pcicptr->g2pmmask[i] = 0;
207 pcicptr->g2pmgbase[i] = 0;
208 pcicptr->g2pmpbase[i] = 0;
209 }
210 if (channel->mem_resource->end) {
211 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
212 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
213 #ifdef __BIG_ENDIAN
214 TX4938_PCIC_G2PMnGBASE_ECHG
215 #else
216 TX4938_PCIC_G2PMnGBASE_BSDIS
217 #endif
218 ;
219 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
220 }
221 /* PCI->GB mappings (I/O 256B) */
222 pcicptr->p2giopbase = 0; /* 256B */
223 pcicptr->p2giogbase = 0;
224 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
225 pcicptr->p2gm0plbase = 0;
226 pcicptr->p2gm0pubase = 0;
227 pcicptr->p2gmgbase[0] = 0 |
228 TX4938_PCIC_P2GMnGBASE_TMEMEN |
229 #ifdef __BIG_ENDIAN
230 TX4938_PCIC_P2GMnGBASE_TECHG
231 #else
232 TX4938_PCIC_P2GMnGBASE_TBSDIS
233 #endif
234 ;
235 /* PCI->GB mappings (MEM 16MB) */
236 pcicptr->p2gm1plbase = 0xffffffff;
237 pcicptr->p2gm1pubase = 0xffffffff;
238 pcicptr->p2gmgbase[1] = 0;
239 /* PCI->GB mappings (MEM 1MB) */
240 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
241 pcicptr->p2gmgbase[2] = 0;
242
243 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
244 /* Enable Initiator Memory Space */
245 if (channel->mem_resource->end)
246 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
247 /* Enable Initiator I/O Space */
248 if (channel->io_resource->end)
249 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
250 /* Enable Initiator Config */
251 pcicptr->pciccfg |=
252 TX4938_PCIC_PCICCFG_ICAEN |
253 TX4938_PCIC_PCICCFG_TCAR;
254
255 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
256 pcicptr->pcicfg1 = 0;
257
258 pcicptr->g2ptocnt &= ~0xffff;
259
260 if (tx4938_pcic_trdyto >= 0) {
261 pcicptr->g2ptocnt &= ~0xff;
262 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
263 }
264
265 if (tx4938_pcic_retryto >= 0) {
266 pcicptr->g2ptocnt &= ~0xff00;
267 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
268 }
269
270 /* Clear All Local Bus Status */
271 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
272 /* Enable All Local Bus Interrupts */
273 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
274 /* Clear All Initiator Status */
275 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
276 /* Enable All Initiator Interrupts */
277 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
278 /* Clear All PCI Status Error */
279 pcicptr->pcistatus =
280 (pcicptr->pcistatus & 0x0000ffff) |
281 (TX4938_PCIC_PCISTATUS_ALL << 16);
282 /* Enable All PCI Status Error Interrupts */
283 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
284
285 if (!extarb) {
286 /* Reset Bus Arbiter */
287 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
288 pcicptr->pbabm = 0;
289 /* Enable Bus Arbiter */
290 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
291 }
292
293 /* PCIC Int => IRC IRQ16 */
294 pcicptr->pcicfg2 =
295 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
296
297 pcicptr->pcistatus = PCI_COMMAND_MASTER |
298 PCI_COMMAND_MEMORY |
299 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
300 }
301
302 int __init
303 tx4938_report_pciclk(void)
304 {
305 unsigned long pcode = TX4938_REV_PCODE();
306 int pciclk = 0;
307 printk("TX%lx PCIC --%s PCICLK:",
308 pcode,
309 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
310 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
311
312 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
313 case TX4938_CCFG_PCIDIVMODE_4:
314 pciclk = txx9_cpu_clock / 4; break;
315 case TX4938_CCFG_PCIDIVMODE_4_5:
316 pciclk = txx9_cpu_clock * 2 / 9; break;
317 case TX4938_CCFG_PCIDIVMODE_5:
318 pciclk = txx9_cpu_clock / 5; break;
319 case TX4938_CCFG_PCIDIVMODE_5_5:
320 pciclk = txx9_cpu_clock * 2 / 11; break;
321 case TX4938_CCFG_PCIDIVMODE_8:
322 pciclk = txx9_cpu_clock / 8; break;
323 case TX4938_CCFG_PCIDIVMODE_9:
324 pciclk = txx9_cpu_clock / 9; break;
325 case TX4938_CCFG_PCIDIVMODE_10:
326 pciclk = txx9_cpu_clock / 10; break;
327 case TX4938_CCFG_PCIDIVMODE_11:
328 pciclk = txx9_cpu_clock / 11; break;
329 }
330 printk("Internal(%dMHz)", pciclk / 1000000);
331 } else {
332 printk("External");
333 pciclk = -1;
334 }
335 printk("\n");
336 return pciclk;
337 }
338
339 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
340 {
341 pcicptrs[ch] = pcicptr;
342 }
343
344 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
345 {
346 return pcicptrs[ch];
347 }
348
349 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
350 int top_bus, int busnr, int devfn)
351 {
352 static struct pci_dev dev;
353 static struct pci_bus bus;
354
355 dev.sysdata = bus.sysdata = hose;
356 dev.devfn = devfn;
357 bus.number = busnr;
358 bus.ops = hose->pci_ops;
359 bus.parent = NULL;
360 dev.bus = &bus;
361
362 return &dev;
363 }
364
365 #define EARLY_PCI_OP(rw, size, type) \
366 static int early_##rw##_config_##size(struct pci_controller *hose, \
367 int top_bus, int bus, int devfn, int offset, type value) \
368 { \
369 return pci_##rw##_config_##size( \
370 fake_pci_dev(hose, top_bus, bus, devfn), \
371 offset, value); \
372 }
373
374 EARLY_PCI_OP(read, word, u16 *)
375
376 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
377 {
378 u32 pci_devfn;
379 unsigned short vid;
380 int devfn_start = 0;
381 int devfn_stop = 0xff;
382 int cap66 = -1;
383 u16 stat;
384
385 printk("PCI: Checking 66MHz capabilities...\n");
386
387 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
388 if (early_read_config_word(hose, top_bus, current_bus,
389 pci_devfn, PCI_VENDOR_ID,
390 &vid) != PCIBIOS_SUCCESSFUL)
391 continue;
392
393 if (vid == 0xffff) continue;
394
395 /* check 66MHz capability */
396 if (cap66 < 0)
397 cap66 = 1;
398 if (cap66) {
399 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
400 PCI_STATUS, &stat);
401 if (!(stat & PCI_STATUS_66MHZ)) {
402 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
403 current_bus, pci_devfn);
404 cap66 = 0;
405 break;
406 }
407 }
408 }
409 return cap66 > 0;
410 }
411
412 int __init
413 tx4938_pciclk66_setup(void)
414 {
415 int pciclk;
416
417 /* Assert M66EN */
418 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
419 /* Double PCICLK (if possible) */
420 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
421 unsigned int pcidivmode =
422 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
423 switch (pcidivmode) {
424 case TX4938_CCFG_PCIDIVMODE_8:
425 case TX4938_CCFG_PCIDIVMODE_4:
426 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
427 pciclk = txx9_cpu_clock / 4;
428 break;
429 case TX4938_CCFG_PCIDIVMODE_9:
430 case TX4938_CCFG_PCIDIVMODE_4_5:
431 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
432 pciclk = txx9_cpu_clock * 2 / 9;
433 break;
434 case TX4938_CCFG_PCIDIVMODE_10:
435 case TX4938_CCFG_PCIDIVMODE_5:
436 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
437 pciclk = txx9_cpu_clock / 5;
438 break;
439 case TX4938_CCFG_PCIDIVMODE_11:
440 case TX4938_CCFG_PCIDIVMODE_5_5:
441 default:
442 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
443 pciclk = txx9_cpu_clock * 2 / 11;
444 break;
445 }
446 tx4938_ccfgptr->ccfg =
447 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
448 | pcidivmode;
449 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
450 (unsigned long)tx4938_ccfgptr->ccfg);
451 } else {
452 pciclk = -1;
453 }
454 return pciclk;
455 }
456
457 extern struct pci_controller tx4938_pci_controller[];
458 static int __init tx4938_pcibios_init(void)
459 {
460 unsigned long mem_base[2];
461 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
462 unsigned long io_base[2];
463 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
464 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
465 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
466
467 PCIBIOS_MIN_IO = 0x00001000UL;
468
469 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
470 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
471
472 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
473 (unsigned short)(tx4938_pcicptr->pciid >> 16),
474 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
475 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
476 extarb ? "External" : "Internal");
477
478 /* setup PCI area */
479 tx4938_pci_controller[0].io_resource->start = io_base[0];
480 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
481 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
482 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
483
484 set_tx4938_pcicptr(0, tx4938_pcicptr);
485
486 register_pci_controller(&tx4938_pci_controller[0]);
487
488 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
489 printk("TX4938_CCFG_PCI66 already configured\n");
490 txboard_pci66_mode = -1; /* already configured */
491 }
492
493 /* Reset PCI Bus */
494 *rbtx4938_pcireset_ptr = 0;
495 /* Reset PCIC */
496 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
497 if (txboard_pci66_mode > 0)
498 tx4938_pciclk66_setup();
499 mdelay(10);
500 /* clear PCIC reset */
501 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
502 *rbtx4938_pcireset_ptr = 1;
503 wbflush();
504 tx4938_report_pcic_status1(tx4938_pcicptr);
505
506 tx4938_report_pciclk();
507 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
508 if (txboard_pci66_mode == 0 &&
509 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
510 /* Reset PCI Bus */
511 *rbtx4938_pcireset_ptr = 0;
512 /* Reset PCIC */
513 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
514 tx4938_pciclk66_setup();
515 mdelay(10);
516 /* clear PCIC reset */
517 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
518 *rbtx4938_pcireset_ptr = 1;
519 wbflush();
520 /* Reinitialize PCIC */
521 tx4938_report_pciclk();
522 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
523 }
524
525 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
526 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
527 /* Reset PCIC1 */
528 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
529 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
530 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
531 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
532 else
533 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
534 mdelay(10);
535 /* clear PCIC1 reset */
536 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
537 tx4938_report_pcic_status1(tx4938_pcic1ptr);
538
539 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
540 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
541 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
542 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
543 printk("%s PCICLK:%dMHz\n",
544 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
545 txx9_gbus_clock /
546 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
547 1000000);
548
549 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
550 tx4938_pci_controller[1].io_resource->start =
551 io_base[1] - io_base[0];
552 tx4938_pci_controller[1].io_resource->end =
553 io_base[1] - io_base[0] + io_size[1] - 1;
554 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
555 tx4938_pci_controller[1].mem_resource->end =
556 mem_base[1] + mem_size[1] - 1;
557 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
558
559 register_pci_controller(&tx4938_pci_controller[1]);
560
561 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
562
563 /* map ioport 0 to PCI I/O space address 0 */
564 set_io_port_base(KSEG1 + io_base[0]);
565
566 return 0;
567 }
568
569 arch_initcall(tx4938_pcibios_init);
570
571 #endif /* CONFIG_PCI */
572
573 /* SPI support */
574
575 /* chip select for SPI devices */
576 #define SEEPROM1_CS 7 /* PIO7 */
577 #define SEEPROM2_CS 0 /* IOC */
578 #define SEEPROM3_CS 1 /* IOC */
579 #define SRTC_CS 2 /* IOC */
580
581 #ifdef CONFIG_PCI
582 static int __init rbtx4938_ethaddr_init(void)
583 {
584 unsigned char dat[17];
585 unsigned char sum;
586 int i;
587
588 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
589 if (spi_eeprom_read(SEEPROM1_CS, 0, dat, sizeof(dat))) {
590 printk(KERN_ERR "seeprom: read error.\n");
591 return -ENODEV;
592 } else {
593 if (strcmp(dat, "MAC") != 0)
594 printk(KERN_WARNING "seeprom: bad signature.\n");
595 for (i = 0, sum = 0; i < sizeof(dat); i++)
596 sum += dat[i];
597 if (sum)
598 printk(KERN_WARNING "seeprom: bad checksum.\n");
599 }
600 for (i = 0; i < 2; i++) {
601 unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i);
602 unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */
603 struct platform_device *pdev;
604 if (!(tx4938_ccfgptr->pcfg &
605 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
606 continue;
607 pdev = platform_device_alloc("tc35815-mac", id);
608 if (!pdev ||
609 platform_device_add_data(pdev, &dat[4 + 6 * i], 6) ||
610 platform_device_add(pdev))
611 platform_device_put(pdev);
612 }
613 return 0;
614 }
615 device_initcall(rbtx4938_ethaddr_init);
616 #endif /* CONFIG_PCI */
617
618 static void __init rbtx4938_spi_setup(void)
619 {
620 /* set SPI_SEL */
621 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
622 /* chip selects for SPI devices */
623 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
624 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
625 }
626
627 static struct resource rbtx4938_fpga_resource;
628
629 static char pcode_str[8];
630 static struct resource tx4938_reg_resource = {
631 .start = TX4938_REG_BASE,
632 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
633 .name = pcode_str,
634 .flags = IORESOURCE_MEM
635 };
636
637 void __init tx4938_board_setup(void)
638 {
639 int i;
640 unsigned long divmode;
641 int cpuclk = 0;
642 unsigned long pcode = TX4938_REV_PCODE();
643
644 ioport_resource.start = 0x1000;
645 ioport_resource.end = 0xffffffff;
646 iomem_resource.start = 0x1000;
647 iomem_resource.end = 0xffffffff; /* expand to 4GB */
648
649 sprintf(pcode_str, "TX%lx", pcode);
650 /* SDRAMC,EBUSC are configured by PROM */
651 for (i = 0; i < 8; i++) {
652 if (!(tx4938_ebuscptr->cr[i] & 0x8))
653 continue; /* disabled */
654 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
655 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
656 }
657
658 /* clocks */
659 if (txx9_master_clock) {
660 /* calculate gbus_clock and cpu_clock from master_clock */
661 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
662 switch (divmode) {
663 case TX4938_CCFG_DIVMODE_8:
664 case TX4938_CCFG_DIVMODE_10:
665 case TX4938_CCFG_DIVMODE_12:
666 case TX4938_CCFG_DIVMODE_16:
667 case TX4938_CCFG_DIVMODE_18:
668 txx9_gbus_clock = txx9_master_clock * 4; break;
669 default:
670 txx9_gbus_clock = txx9_master_clock;
671 }
672 switch (divmode) {
673 case TX4938_CCFG_DIVMODE_2:
674 case TX4938_CCFG_DIVMODE_8:
675 cpuclk = txx9_gbus_clock * 2; break;
676 case TX4938_CCFG_DIVMODE_2_5:
677 case TX4938_CCFG_DIVMODE_10:
678 cpuclk = txx9_gbus_clock * 5 / 2; break;
679 case TX4938_CCFG_DIVMODE_3:
680 case TX4938_CCFG_DIVMODE_12:
681 cpuclk = txx9_gbus_clock * 3; break;
682 case TX4938_CCFG_DIVMODE_4:
683 case TX4938_CCFG_DIVMODE_16:
684 cpuclk = txx9_gbus_clock * 4; break;
685 case TX4938_CCFG_DIVMODE_4_5:
686 case TX4938_CCFG_DIVMODE_18:
687 cpuclk = txx9_gbus_clock * 9 / 2; break;
688 }
689 txx9_cpu_clock = cpuclk;
690 } else {
691 if (txx9_cpu_clock == 0) {
692 txx9_cpu_clock = 300000000; /* 300MHz */
693 }
694 /* calculate gbus_clock and master_clock from cpu_clock */
695 cpuclk = txx9_cpu_clock;
696 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
697 switch (divmode) {
698 case TX4938_CCFG_DIVMODE_2:
699 case TX4938_CCFG_DIVMODE_8:
700 txx9_gbus_clock = cpuclk / 2; break;
701 case TX4938_CCFG_DIVMODE_2_5:
702 case TX4938_CCFG_DIVMODE_10:
703 txx9_gbus_clock = cpuclk * 2 / 5; break;
704 case TX4938_CCFG_DIVMODE_3:
705 case TX4938_CCFG_DIVMODE_12:
706 txx9_gbus_clock = cpuclk / 3; break;
707 case TX4938_CCFG_DIVMODE_4:
708 case TX4938_CCFG_DIVMODE_16:
709 txx9_gbus_clock = cpuclk / 4; break;
710 case TX4938_CCFG_DIVMODE_4_5:
711 case TX4938_CCFG_DIVMODE_18:
712 txx9_gbus_clock = cpuclk * 2 / 9; break;
713 }
714 switch (divmode) {
715 case TX4938_CCFG_DIVMODE_8:
716 case TX4938_CCFG_DIVMODE_10:
717 case TX4938_CCFG_DIVMODE_12:
718 case TX4938_CCFG_DIVMODE_16:
719 case TX4938_CCFG_DIVMODE_18:
720 txx9_master_clock = txx9_gbus_clock / 4; break;
721 default:
722 txx9_master_clock = txx9_gbus_clock;
723 }
724 }
725 /* change default value to udelay/mdelay take reasonable time */
726 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
727
728 /* CCFG */
729 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
730 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
731 /* clear PCIC1 reset */
732 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
733 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
734
735 /* enable Timeout BusError */
736 if (tx4938_ccfg_toeon)
737 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
738
739 /* DMA selection */
740 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
741
742 /* Use external clock for external arbiter */
743 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
744 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
745
746 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
747 pcode_str,
748 cpuclk / 1000000, txx9_master_clock / 1000000,
749 (unsigned long)tx4938_ccfgptr->crir,
750 tx4938_ccfgptr->ccfg,
751 tx4938_ccfgptr->pcfg);
752
753 printk("%s SDRAMC --", pcode_str);
754 for (i = 0; i < 4; i++) {
755 unsigned long long cr = tx4938_sdramcptr->cr[i];
756 unsigned long ram_base, ram_size;
757 if (!((unsigned long)cr & 0x00000400))
758 continue; /* disabled */
759 ram_base = (unsigned long)(cr >> 49) << 21;
760 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
761 if (ram_base >= 0x20000000)
762 continue; /* high memory (ignore) */
763 printk(" CR%d:%016Lx", i, cr);
764 txboard_add_phys_region(ram_base, ram_size);
765 }
766 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
767
768 /* SRAM */
769 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
770 unsigned int size = 0x800;
771 unsigned long base =
772 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
773 txboard_add_phys_region(base, size);
774 }
775
776 /* IRC */
777 /* disable interrupt control */
778 tx4938_ircptr->cer = 0;
779
780 /* TMR */
781 /* disable all timers */
782 for (i = 0; i < TX4938_NR_TMR; i++) {
783 tx4938_tmrptr(i)->tcr = 0x00000020;
784 tx4938_tmrptr(i)->tisr = 0;
785 tx4938_tmrptr(i)->cpra = 0xffffffff;
786 tx4938_tmrptr(i)->itmr = 0;
787 tx4938_tmrptr(i)->ccdr = 0;
788 tx4938_tmrptr(i)->pgmr = 0;
789 }
790
791 /* enable DMA */
792 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
793 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
794
795 /* PIO */
796 tx4938_pioptr->maskcpu = 0;
797 tx4938_pioptr->maskext = 0;
798
799 /* TX4938 internal registers */
800 if (request_resource(&iomem_resource, &tx4938_reg_resource))
801 printk("request resource for internal registers failed\n");
802 }
803
804 #ifdef CONFIG_PCI
805 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
806 {
807 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
808 unsigned long g2pstatus = pcicptr->g2pstatus;
809 unsigned long pcicstatus = pcicptr->pcicstatus;
810 static struct {
811 unsigned long flag;
812 const char *str;
813 } pcistat_tbl[] = {
814 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
815 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
816 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
817 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
818 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
819 { PCI_STATUS_PARITY, "MasterParityError" },
820 }, g2pstat_tbl[] = {
821 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
822 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
823 }, pcicstat_tbl[] = {
824 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
825 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
826 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
827 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
828 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
829 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
830 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
831 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
832 };
833 int i;
834
835 printk("pcistat:%04x(", pcistatus);
836 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
837 if (pcistatus & pcistat_tbl[i].flag)
838 printk("%s ", pcistat_tbl[i].str);
839 printk("), g2pstatus:%08lx(", g2pstatus);
840 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
841 if (g2pstatus & g2pstat_tbl[i].flag)
842 printk("%s ", g2pstat_tbl[i].str);
843 printk("), pcicstatus:%08lx(", pcicstatus);
844 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
845 if (pcicstatus & pcicstat_tbl[i].flag)
846 printk("%s ", pcicstat_tbl[i].str);
847 printk(")\n");
848 }
849
850 void tx4938_report_pcic_status(void)
851 {
852 int i;
853 struct tx4938_pcic_reg *pcicptr;
854 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
855 tx4938_report_pcic_status1(pcicptr);
856 }
857
858 #endif /* CONFIG_PCI */
859
860 /* We use onchip r4k counter or TMR timer as our system wide timer
861 * interrupt running at 100HZ. */
862
863 void __init rbtx4938_time_init(void)
864 {
865 mips_hpt_frequency = txx9_cpu_clock / 2;
866 }
867
868 void __init toshiba_rbtx4938_setup(void)
869 {
870 unsigned long long pcfg;
871 char *argptr;
872
873 iomem_resource.end = 0xffffffff; /* 4GB */
874
875 if (txx9_master_clock == 0)
876 txx9_master_clock = 25000000; /* 25MHz */
877 tx4938_board_setup();
878 /* setup irq stuff */
879 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
880 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
881 /* setup serial stuff */
882 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
883 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
884
885 #ifndef CONFIG_PCI
886 set_io_port_base(RBTX4938_ETHER_BASE);
887 #endif
888
889 #ifdef CONFIG_SERIAL_TXX9
890 {
891 extern int early_serial_txx9_setup(struct uart_port *port);
892 int i;
893 struct uart_port req;
894 for(i = 0; i < 2; i++) {
895 memset(&req, 0, sizeof(req));
896 req.line = i;
897 req.iotype = UPIO_MEM;
898 req.membase = (char *)(0xff1ff300 + i * 0x100);
899 req.mapbase = 0xff1ff300 + i * 0x100;
900 req.irq = 32 + i;
901 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
902 req.uartclk = 50000000;
903 early_serial_txx9_setup(&req);
904 }
905 }
906 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
907 argptr = prom_getcmdline();
908 if (strstr(argptr, "console=") == NULL) {
909 strcat(argptr, " console=ttyS0,38400");
910 }
911 #endif
912 #endif
913
914 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
915 printk("PIOSEL: disabling both ata and nand selection\n");
916 local_irq_disable();
917 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
918 #endif
919
920 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
921 printk("PIOSEL: enabling nand selection\n");
922 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
923 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
924 #endif
925
926 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
927 printk("PIOSEL: enabling ata selection\n");
928 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
929 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
930 #endif
931
932 #ifdef CONFIG_IP_PNP
933 argptr = prom_getcmdline();
934 if (strstr(argptr, "ip=") == NULL) {
935 strcat(argptr, " ip=any");
936 }
937 #endif
938
939
940 #ifdef CONFIG_FB
941 {
942 conswitchp = &dummy_con;
943 }
944 #endif
945
946 rbtx4938_spi_setup();
947 pcfg = tx4938_ccfgptr->pcfg; /* updated */
948 /* fixup piosel */
949 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
950 TX4938_PCFG_ATA_SEL) {
951 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
952 }
953 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
954 TX4938_PCFG_NDF_SEL) {
955 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
956 }
957 else {
958 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
959 }
960
961 rbtx4938_fpga_resource.name = "FPGA Registers";
962 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
963 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
964 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
965 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
966 printk("request resource for fpga failed\n");
967
968 /* disable all OnBoard I/O interrupts */
969 *rbtx4938_imask_ptr = 0;
970
971 _machine_restart = rbtx4938_machine_restart;
972 _machine_halt = rbtx4938_machine_halt;
973 pm_power_off = rbtx4938_machine_power_off;
974
975 *rbtx4938_led_ptr = 0xff;
976 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
977 printk(" DIPSW:%02x,%02x\n",
978 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
979 }
980
981 static int __init rbtx4938_ne_init(void)
982 {
983 struct resource res[] = {
984 {
985 .start = RBTX4938_RTL_8019_BASE,
986 .end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
987 .flags = IORESOURCE_IO,
988 }, {
989 .start = RBTX4938_RTL_8019_IRQ,
990 .flags = IORESOURCE_IRQ,
991 }
992 };
993 struct platform_device *dev =
994 platform_device_register_simple("ne", -1,
995 res, ARRAY_SIZE(res));
996 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
997 }
998 device_initcall(rbtx4938_ne_init);
999
1000 /* GPIO support */
1001
1002 static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
1003
1004 static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
1005 {
1006 u8 val;
1007 unsigned long flags;
1008 gpio -= 16;
1009 spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
1010 val = *rbtx4938_spics_ptr;
1011 if (value)
1012 val |= 1 << gpio;
1013 else
1014 val &= ~(1 << gpio);
1015 *rbtx4938_spics_ptr = val;
1016 mmiowb();
1017 spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
1018 }
1019
1020 static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
1021 {
1022 rbtx4938_spi_gpio_set(gpio, value);
1023 return 0;
1024 }
1025
1026 static DEFINE_SPINLOCK(tx4938_gpio_lock);
1027
1028 static int tx4938_gpio_get(unsigned gpio)
1029 {
1030 return tx4938_pioptr->din & (1 << gpio);
1031 }
1032
1033 static void tx4938_gpio_set_raw(unsigned gpio, int value)
1034 {
1035 u32 val;
1036 val = tx4938_pioptr->dout;
1037 if (value)
1038 val |= 1 << gpio;
1039 else
1040 val &= ~(1 << gpio);
1041 tx4938_pioptr->dout = val;
1042 }
1043
1044 static void tx4938_gpio_set(unsigned gpio, int value)
1045 {
1046 unsigned long flags;
1047 spin_lock_irqsave(&tx4938_gpio_lock, flags);
1048 tx4938_gpio_set_raw(gpio, value);
1049 mmiowb();
1050 spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
1051 }
1052
1053 static int tx4938_gpio_dir_in(unsigned gpio)
1054 {
1055 spin_lock_irq(&tx4938_gpio_lock);
1056 tx4938_pioptr->dir &= ~(1 << gpio);
1057 mmiowb();
1058 spin_unlock_irq(&tx4938_gpio_lock);
1059 return 0;
1060 }
1061
1062 static int tx4938_gpio_dir_out(unsigned int gpio, int value)
1063 {
1064 spin_lock_irq(&tx4938_gpio_lock);
1065 tx4938_gpio_set_raw(gpio, value);
1066 tx4938_pioptr->dir |= 1 << gpio;
1067 mmiowb();
1068 spin_unlock_irq(&tx4938_gpio_lock);
1069 return 0;
1070 }
1071
1072 int gpio_direction_input(unsigned gpio)
1073 {
1074 if (gpio < 16)
1075 return tx4938_gpio_dir_in(gpio);
1076 return -EINVAL;
1077 }
1078
1079 int gpio_direction_output(unsigned gpio, int value)
1080 {
1081 if (gpio < 16)
1082 return tx4938_gpio_dir_out(gpio, value);
1083 if (gpio < 16 + 3)
1084 return rbtx4938_spi_gpio_dir_out(gpio, value);
1085 return -EINVAL;
1086 }
1087
1088 int gpio_get_value(unsigned gpio)
1089 {
1090 if (gpio < 16)
1091 return tx4938_gpio_get(gpio);
1092 return 0;
1093 }
1094
1095 void gpio_set_value(unsigned gpio, int value)
1096 {
1097 if (gpio < 16)
1098 tx4938_gpio_set(gpio, value);
1099 else
1100 rbtx4938_spi_gpio_set(gpio, value);
1101 }
1102
1103 /* SPI support */
1104
1105 static void __init txx9_spi_init(unsigned long base, int irq)
1106 {
1107 struct resource res[] = {
1108 {
1109 .start = base,
1110 .end = base + 0x20 - 1,
1111 .flags = IORESOURCE_MEM,
1112 .parent = &tx4938_reg_resource,
1113 }, {
1114 .start = irq,
1115 .flags = IORESOURCE_IRQ,
1116 },
1117 };
1118 platform_device_register_simple("txx9spi", 0,
1119 res, ARRAY_SIZE(res));
1120 }
1121
1122 static int __init rbtx4938_spi_init(void)
1123 {
1124 struct spi_board_info srtc_info = {
1125 .modalias = "rs5c348",
1126 .max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
1127 .bus_num = 0,
1128 .chip_select = 16 + SRTC_CS,
1129 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
1130 .mode = SPI_MODE_1 | SPI_CS_HIGH,
1131 };
1132 spi_register_board_info(&srtc_info, 1);
1133 spi_eeprom_register(SEEPROM1_CS);
1134 spi_eeprom_register(16 + SEEPROM2_CS);
1135 spi_eeprom_register(16 + SEEPROM3_CS);
1136 txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
1137 return 0;
1138 }
1139 arch_initcall(rbtx4938_spi_init);
1140
1141 /* Minimum CLK support */
1142
1143 struct clk *clk_get(struct device *dev, const char *id)
1144 {
1145 if (!strcmp(id, "spi-baseclk"))
1146 return (struct clk *)(txx9_gbus_clock / 2 / 4);
1147 return ERR_PTR(-ENOENT);
1148 }
1149 EXPORT_SYMBOL(clk_get);
1150
1151 int clk_enable(struct clk *clk)
1152 {
1153 return 0;
1154 }
1155 EXPORT_SYMBOL(clk_enable);
1156
1157 void clk_disable(struct clk *clk)
1158 {
1159 }
1160 EXPORT_SYMBOL(clk_disable);
1161
1162 unsigned long clk_get_rate(struct clk *clk)
1163 {
1164 return (unsigned long)clk;
1165 }
1166 EXPORT_SYMBOL(clk_get_rate);
1167
1168 void clk_put(struct clk *clk)
1169 {
1170 }
1171 EXPORT_SYMBOL(clk_put);
WRT350N Kernel Patches