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[PATCH] ocfs2: zero_user_page conversion
[wrt350n-kernel.git] / arch / ppc / 8260_io / fcc_enet.c
blobcab395da25da533f8947739cf37473f5d4433e0c
1 /*
2 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
3 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is a combination of the 8xx fec and
6 * 8260 SCC Ethernet drivers. This version has some additional
7 * configuration options, which should probably be moved out of
8 * here. This driver currently works for the EST SBC8260,
9 * SBS Diablo/BCM, Embedded Planet RPX6, TQM8260, and others.
10 *
11 * Right now, I am very watseful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets. Since this is a cache coherent processor and CPM,
17 * I could also preallocate SKB's and use them directly on the interface.
18 *
19 * 2004-12 Leo Li (leoli@freescale.com)
20 * - Rework the FCC clock configuration part, make it easier to configure.
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
38 #include <linux/mii.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
41
42 #include <asm/immap_cpm2.h>
43 #include <asm/pgtable.h>
44 #include <asm/mpc8260.h>
45 #include <asm/irq.h>
46 #include <asm/uaccess.h>
47 #include <asm/signal.h>
48
49 /* We can't use the PHY interrupt if we aren't using MDIO. */
50 #if !defined(CONFIG_USE_MDIO)
51 #undef PHY_INTERRUPT
52 #endif
53
54 /* If we have a PHY interrupt, we will advertise both full-duplex and half-
55 * duplex capabilities. If we don't have a PHY interrupt, then we will only
56 * advertise half-duplex capabilities.
57 */
58 #define MII_ADVERTISE_HALF (ADVERTISE_100HALF | ADVERTISE_10HALF | \
59 ADVERTISE_CSMA)
60 #define MII_ADVERTISE_ALL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
61 MII_ADVERTISE_HALF)
62 #ifdef PHY_INTERRUPT
63 #define MII_ADVERTISE_DEFAULT MII_ADVERTISE_ALL
64 #else
65 #define MII_ADVERTISE_DEFAULT MII_ADVERTISE_HALF
66 #endif
67 #include <asm/cpm2.h>
68
69 /* The transmitter timeout
70 */
71 #define TX_TIMEOUT (2*HZ)
72
73 #ifdef CONFIG_USE_MDIO
74 /* Forward declarations of some structures to support different PHYs */
75
76 typedef struct {
77 uint mii_data;
78 void (*funct)(uint mii_reg, struct net_device *dev);
79 } phy_cmd_t;
80
81 typedef struct {
82 uint id;
83 char *name;
84
85 const phy_cmd_t *config;
86 const phy_cmd_t *startup;
87 const phy_cmd_t *ack_int;
88 const phy_cmd_t *shutdown;
89 } phy_info_t;
90
91 /* values for phy_status */
92
93 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
94 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
95 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
96 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
97 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
98 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
99 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
100
101 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
102 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
103 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
104 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
105 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
106 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
107 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
108 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
109 #endif /* CONFIG_USE_MDIO */
110
111 /* The number of Tx and Rx buffers. These are allocated from the page
112 * pool. The code may assume these are power of two, so it is best
113 * to keep them that size.
114 * We don't need to allocate pages for the transmitter. We just use
115 * the skbuffer directly.
116 */
117 #define FCC_ENET_RX_PAGES 16
118 #define FCC_ENET_RX_FRSIZE 2048
119 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
120 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
121 #define TX_RING_SIZE 16 /* Must be power of two */
122 #define TX_RING_MOD_MASK 15 /* for this to work */
123
124 /* The FCC stores dest/src/type, data, and checksum for receive packets.
125 * size includes support for VLAN
126 */
127 #define PKT_MAXBUF_SIZE 1522
128 #define PKT_MINBUF_SIZE 64
129
130 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
131 * size includes support for VLAN
132 */
133 #define PKT_MAXDMA_SIZE 1524
134
135 /* Maximum input buffer size. Must be a multiple of 32.
136 */
137 #define PKT_MAXBLR_SIZE 1536
138
139 static int fcc_enet_open(struct net_device *dev);
140 static int fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
141 static int fcc_enet_rx(struct net_device *dev);
142 static irqreturn_t fcc_enet_interrupt(int irq, void *dev_id);
143 static int fcc_enet_close(struct net_device *dev);
144 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev);
145 /* static void set_multicast_list(struct net_device *dev); */
146 static void fcc_restart(struct net_device *dev, int duplex);
147 static void fcc_stop(struct net_device *dev);
148 static int fcc_enet_set_mac_address(struct net_device *dev, void *addr);
149
150 /* These will be configurable for the FCC choice.
151 * Multiple ports can be configured. There is little choice among the
152 * I/O pins to the PHY, except the clocks. We will need some board
153 * dependent clock selection.
154 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
155 * help show what pins are used for each device.
156 */
157
158 /* Since the CLK setting changes greatly from board to board, I changed
159 * it to a easy way. You just need to specify which CLK number to use.
160 * Note that only limited choices can be make on each port.
161 */
162
163 /* FCC1 Clock Source Configuration. There are board specific.
164 Can only choose from CLK9-12 */
165 #ifdef CONFIG_SBC82xx
166 #define F1_RXCLK 9
167 #define F1_TXCLK 10
168 #elif defined(CONFIG_ADS8272)
169 #define F1_RXCLK 11
170 #define F1_TXCLK 10
171 #else
172 #define F1_RXCLK 12
173 #define F1_TXCLK 11
174 #endif
175
176 /* FCC2 Clock Source Configuration. There are board specific.
177 Can only choose from CLK13-16 */
178 #ifdef CONFIG_ADS8272
179 #define F2_RXCLK 15
180 #define F2_TXCLK 16
181 #else
182 #define F2_RXCLK 13
183 #define F2_TXCLK 14
184 #endif
185
186 /* FCC3 Clock Source Configuration. There are board specific.
187 Can only choose from CLK13-16 */
188 #define F3_RXCLK 15
189 #define F3_TXCLK 16
190
191 /* Automatically generates register configurations */
192 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
193
194 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
195 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
196 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
197 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
198 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
199 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
200
201 #define PC_F1RXCLK PC_CLK(F1_RXCLK)
202 #define PC_F1TXCLK PC_CLK(F1_TXCLK)
203 #define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
204 #define CMX1_CLK_MASK ((uint)0xff000000)
205
206 #define PC_F2RXCLK PC_CLK(F2_RXCLK)
207 #define PC_F2TXCLK PC_CLK(F2_TXCLK)
208 #define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
209 #define CMX2_CLK_MASK ((uint)0x00ff0000)
210
211 #define PC_F3RXCLK PC_CLK(F3_RXCLK)
212 #define PC_F3TXCLK PC_CLK(F3_TXCLK)
213 #define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
214 #define CMX3_CLK_MASK ((uint)0x0000ff00)
215
216
217 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
218 * but there is little variation among the choices.
219 */
220 #define PA1_COL ((uint)0x00000001)
221 #define PA1_CRS ((uint)0x00000002)
222 #define PA1_TXER ((uint)0x00000004)
223 #define PA1_TXEN ((uint)0x00000008)
224 #define PA1_RXDV ((uint)0x00000010)
225 #define PA1_RXER ((uint)0x00000020)
226 #define PA1_TXDAT ((uint)0x00003c00)
227 #define PA1_RXDAT ((uint)0x0003c000)
228 #define PA1_PSORA_BOUT (PA1_RXDAT | PA1_TXDAT)
229 #define PA1_PSORA_BIN (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
230 PA1_RXDV | PA1_RXER)
231 #define PA1_DIRA_BOUT (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
232 #define PA1_DIRA_BIN (PA1_TXDAT | PA1_TXEN | PA1_TXER)
233
234
235 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
236 * but there is little variation among the choices.
237 */
238 #define PB2_TXER ((uint)0x00000001)
239 #define PB2_RXDV ((uint)0x00000002)
240 #define PB2_TXEN ((uint)0x00000004)
241 #define PB2_RXER ((uint)0x00000008)
242 #define PB2_COL ((uint)0x00000010)
243 #define PB2_CRS ((uint)0x00000020)
244 #define PB2_TXDAT ((uint)0x000003c0)
245 #define PB2_RXDAT ((uint)0x00003c00)
246 #define PB2_PSORB_BOUT (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
247 PB2_RXER | PB2_RXDV | PB2_TXER)
248 #define PB2_PSORB_BIN (PB2_TXEN)
249 #define PB2_DIRB_BOUT (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
250 #define PB2_DIRB_BIN (PB2_TXDAT | PB2_TXEN | PB2_TXER)
251
252
253 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
254 * but there is little variation among the choices.
255 */
256 #define PB3_RXDV ((uint)0x00004000)
257 #define PB3_RXER ((uint)0x00008000)
258 #define PB3_TXER ((uint)0x00010000)
259 #define PB3_TXEN ((uint)0x00020000)
260 #define PB3_COL ((uint)0x00040000)
261 #define PB3_CRS ((uint)0x00080000)
262 #ifndef CONFIG_RPX8260
263 #define PB3_TXDAT ((uint)0x0f000000)
264 #define PC3_TXDAT ((uint)0x00000000)
265 #else
266 #define PB3_TXDAT ((uint)0x0f000000)
267 #define PC3_TXDAT 0
268 #endif
269 #define PB3_RXDAT ((uint)0x00f00000)
270 #define PB3_PSORB_BOUT (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
271 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
272 #define PB3_PSORB_BIN (0)
273 #define PB3_DIRB_BOUT (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
274 #define PB3_DIRB_BIN (PB3_TXDAT | PB3_TXEN | PB3_TXER)
275
276 #define PC3_PSORC_BOUT (PC3_TXDAT)
277 #define PC3_PSORC_BIN (0)
278 #define PC3_DIRC_BOUT (0)
279 #define PC3_DIRC_BIN (PC3_TXDAT)
280
281
282 /* MII status/control serial interface.
283 */
284 #if defined(CONFIG_RPX8260)
285 /* The EP8260 doesn't use Port C for MDIO */
286 #define PC_MDIO ((uint)0x00000000)
287 #define PC_MDCK ((uint)0x00000000)
288 #elif defined(CONFIG_TQM8260)
289 /* TQM8260 has MDIO and MDCK on PC30 and PC31 respectively */
290 #define PC_MDIO ((uint)0x00000002)
291 #define PC_MDCK ((uint)0x00000001)
292 #elif defined(CONFIG_ADS8272)
293 #define PC_MDIO ((uint)0x00002000)
294 #define PC_MDCK ((uint)0x00001000)
295 #elif defined(CONFIG_EST8260) || defined(CONFIG_ADS8260) || defined(CONFIG_PQ2FADS)
296 #define PC_MDIO ((uint)0x00400000)
297 #define PC_MDCK ((uint)0x00200000)
298 #else
299 #define PC_MDIO ((uint)0x00000004)
300 #define PC_MDCK ((uint)0x00000020)
301 #endif
302
303 #if defined(CONFIG_USE_MDIO) && (!defined(PC_MDIO) || !defined(PC_MDCK))
304 #error "Must define PC_MDIO and PC_MDCK if using MDIO"
305 #endif
306
307 /* PHY addresses */
308 /* default to dynamic config of phy addresses */
309 #define FCC1_PHY_ADDR 0
310 #ifdef CONFIG_PQ2FADS
311 #define FCC2_PHY_ADDR 0
312 #else
313 #define FCC2_PHY_ADDR 2
314 #endif
315 #define FCC3_PHY_ADDR 3
316
317 /* A table of information for supporting FCCs. This does two things.
318 * First, we know how many FCCs we have and they are always externally
319 * numbered from zero. Second, it holds control register and I/O
320 * information that could be different among board designs.
321 */
322 typedef struct fcc_info {
323 uint fc_fccnum;
324 uint fc_phyaddr;
325 uint fc_cpmblock;
326 uint fc_cpmpage;
327 uint fc_proff;
328 uint fc_interrupt;
329 uint fc_trxclocks;
330 uint fc_clockroute;
331 uint fc_clockmask;
332 uint fc_mdio;
333 uint fc_mdck;
334 } fcc_info_t;
335
336 static fcc_info_t fcc_ports[] = {
337 #ifdef CONFIG_FCC1_ENET
338 { 0, FCC1_PHY_ADDR, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, PROFF_FCC1, SIU_INT_FCC1,
339 (PC_F1RXCLK | PC_F1TXCLK), CMX1_CLK_ROUTE, CMX1_CLK_MASK,
340 PC_MDIO, PC_MDCK },
341 #endif
342 #ifdef CONFIG_FCC2_ENET
343 { 1, FCC2_PHY_ADDR, CPM_CR_FCC2_SBLOCK, CPM_CR_FCC2_PAGE, PROFF_FCC2, SIU_INT_FCC2,
344 (PC_F2RXCLK | PC_F2TXCLK), CMX2_CLK_ROUTE, CMX2_CLK_MASK,
345 PC_MDIO, PC_MDCK },
346 #endif
347 #ifdef CONFIG_FCC3_ENET
348 { 2, FCC3_PHY_ADDR, CPM_CR_FCC3_SBLOCK, CPM_CR_FCC3_PAGE, PROFF_FCC3, SIU_INT_FCC3,
349 (PC_F3RXCLK | PC_F3TXCLK), CMX3_CLK_ROUTE, CMX3_CLK_MASK,
350 PC_MDIO, PC_MDCK },
351 #endif
352 };
353
354 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
355 * tx_bd_base always point to the base of the buffer descriptors. The
356 * cur_rx and cur_tx point to the currently available buffer.
357 * The dirty_tx tracks the current buffer that is being sent by the
358 * controller. The cur_tx and dirty_tx are equal under both completely
359 * empty and completely full conditions. The empty/ready indicator in
360 * the buffer descriptor determines the actual condition.
361 */
362 struct fcc_enet_private {
363 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
364 struct sk_buff* tx_skbuff[TX_RING_SIZE];
365 ushort skb_cur;
366 ushort skb_dirty;
367
368 /* CPM dual port RAM relative addresses.
369 */
370 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
371 cbd_t *tx_bd_base;
372 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
373 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
374 volatile fcc_t *fccp;
375 volatile fcc_enet_t *ep;
376 struct net_device_stats stats;
377 uint tx_free;
378 spinlock_t lock;
379
380 #ifdef CONFIG_USE_MDIO
381 uint phy_id;
382 uint phy_id_done;
383 uint phy_status;
384 phy_info_t *phy;
385 struct work_struct phy_relink;
386 struct work_struct phy_display_config;
387 struct net_device *dev;
388
389 uint sequence_done;
390
391 uint phy_addr;
392 #endif /* CONFIG_USE_MDIO */
393
394 int link;
395 int old_link;
396 int full_duplex;
397
398 fcc_info_t *fip;
399 };
400
401 static void init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
402 volatile cpm2_map_t *immap);
403 static void init_fcc_startup(fcc_info_t *fip, struct net_device *dev);
404 static void init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
405 volatile cpm2_map_t *immap);
406 static void init_fcc_param(fcc_info_t *fip, struct net_device *dev,
407 volatile cpm2_map_t *immap);
408
409 #ifdef CONFIG_USE_MDIO
410 static int mii_queue(struct net_device *dev, int request, void (*func)(uint, struct net_device *));
411 static uint mii_send_receive(fcc_info_t *fip, uint cmd);
412 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c);
413
414 /* Make MII read/write commands for the FCC.
415 */
416 #define mk_mii_read(REG) (0x60020000 | (((REG) & 0x1f) << 18))
417 #define mk_mii_write(REG, VAL) (0x50020000 | (((REG) & 0x1f) << 18) | \
418 ((VAL) & 0xffff))
419 #define mk_mii_end 0
420 #endif /* CONFIG_USE_MDIO */
421
422
423 static int
424 fcc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
425 {
426 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
427 volatile cbd_t *bdp;
428
429 /* Fill in a Tx ring entry */
430 bdp = cep->cur_tx;
431
432 #ifndef final_version
433 if (!cep->tx_free || (bdp->cbd_sc & BD_ENET_TX_READY)) {
434 /* Ooops. All transmit buffers are full. Bail out.
435 * This should not happen, since the tx queue should be stopped.
436 */
437 printk("%s: tx queue full!.\n", dev->name);
438 return 1;
439 }
440 #endif
441
442 /* Clear all of the status flags. */
443 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
444
445 /* If the frame is short, tell CPM to pad it. */
446 if (skb->len <= ETH_ZLEN)
447 bdp->cbd_sc |= BD_ENET_TX_PAD;
448 else
449 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
450
451 /* Set buffer length and buffer pointer. */
452 bdp->cbd_datlen = skb->len;
453 bdp->cbd_bufaddr = __pa(skb->data);
454
455 spin_lock_irq(&cep->lock);
456
457 /* Save skb pointer. */
458 cep->tx_skbuff[cep->skb_cur] = skb;
459
460 cep->stats.tx_bytes += skb->len;
461 cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
462
463 /* Send it on its way. Tell CPM its ready, interrupt when done,
464 * its the last BD of the frame, and to put the CRC on the end.
465 */
466 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
467
468 #if 0
469 /* Errata says don't do this. */
470 cep->fccp->fcc_ftodr = 0x8000;
471 #endif
472 dev->trans_start = jiffies;
473
474 /* If this was the last BD in the ring, start at the beginning again. */
475 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
476 bdp = cep->tx_bd_base;
477 else
478 bdp++;
479
480 if (!--cep->tx_free)
481 netif_stop_queue(dev);
482
483 cep->cur_tx = (cbd_t *)bdp;
484
485 spin_unlock_irq(&cep->lock);
486
487 return 0;
488 }
489
490
491 static void
492 fcc_enet_timeout(struct net_device *dev)
493 {
494 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
495
496 printk("%s: transmit timed out.\n", dev->name);
497 cep->stats.tx_errors++;
498 #ifndef final_version
499 {
500 int i;
501 cbd_t *bdp;
502 printk(" Ring data dump: cur_tx %p tx_free %d cur_rx %p.\n",
503 cep->cur_tx, cep->tx_free,
504 cep->cur_rx);
505 bdp = cep->tx_bd_base;
506 printk(" Tx @base %p :\n", bdp);
507 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
508 printk("%04x %04x %08x\n",
509 bdp->cbd_sc,
510 bdp->cbd_datlen,
511 bdp->cbd_bufaddr);
512 bdp = cep->rx_bd_base;
513 printk(" Rx @base %p :\n", bdp);
514 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
515 printk("%04x %04x %08x\n",
516 bdp->cbd_sc,
517 bdp->cbd_datlen,
518 bdp->cbd_bufaddr);
519 }
520 #endif
521 if (cep->tx_free)
522 netif_wake_queue(dev);
523 }
524
525 /* The interrupt handler. */
526 static irqreturn_t
527 fcc_enet_interrupt(int irq, void * dev_id)
528 {
529 struct net_device *dev = dev_id;
530 volatile struct fcc_enet_private *cep;
531 volatile cbd_t *bdp;
532 ushort int_events;
533 int must_restart;
534
535 cep = (struct fcc_enet_private *)dev->priv;
536
537 /* Get the interrupt events that caused us to be here.
538 */
539 int_events = cep->fccp->fcc_fcce;
540 cep->fccp->fcc_fcce = (int_events & cep->fccp->fcc_fccm);
541 must_restart = 0;
542
543 #ifdef PHY_INTERRUPT
544 /* We have to be careful here to make sure that we aren't
545 * interrupted by a PHY interrupt.
546 */
547 disable_irq_nosync(PHY_INTERRUPT);
548 #endif
549
550 /* Handle receive event in its own function.
551 */
552 if (int_events & FCC_ENET_RXF)
553 fcc_enet_rx(dev_id);
554
555 /* Check for a transmit error. The manual is a little unclear
556 * about this, so the debug code until I get it figured out. It
557 * appears that if TXE is set, then TXB is not set. However,
558 * if carrier sense is lost during frame transmission, the TXE
559 * bit is set, "and continues the buffer transmission normally."
560 * I don't know if "normally" implies TXB is set when the buffer
561 * descriptor is closed.....trial and error :-).
562 */
563
564 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
565 */
566 if (int_events & (FCC_ENET_TXE | FCC_ENET_TXB)) {
567 spin_lock(&cep->lock);
568 bdp = cep->dirty_tx;
569 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
570 if (cep->tx_free == TX_RING_SIZE)
571 break;
572
573 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
574 cep->stats.tx_heartbeat_errors++;
575 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
576 cep->stats.tx_window_errors++;
577 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
578 cep->stats.tx_aborted_errors++;
579 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
580 cep->stats.tx_fifo_errors++;
581 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
582 cep->stats.tx_carrier_errors++;
583
584
585 /* No heartbeat or Lost carrier are not really bad errors.
586 * The others require a restart transmit command.
587 */
588 if (bdp->cbd_sc &
589 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
590 must_restart = 1;
591 cep->stats.tx_errors++;
592 }
593
594 cep->stats.tx_packets++;
595
596 /* Deferred means some collisions occurred during transmit,
597 * but we eventually sent the packet OK.
598 */
599 if (bdp->cbd_sc & BD_ENET_TX_DEF)
600 cep->stats.collisions++;
601
602 /* Free the sk buffer associated with this last transmit. */
603 dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
604 cep->tx_skbuff[cep->skb_dirty] = NULL;
605 cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
606
607 /* Update pointer to next buffer descriptor to be transmitted. */
608 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
609 bdp = cep->tx_bd_base;
610 else
611 bdp++;
612
613 /* I don't know if we can be held off from processing these
614 * interrupts for more than one frame time. I really hope
615 * not. In such a case, we would now want to check the
616 * currently available BD (cur_tx) and determine if any
617 * buffers between the dirty_tx and cur_tx have also been
618 * sent. We would want to process anything in between that
619 * does not have BD_ENET_TX_READY set.
620 */
621
622 /* Since we have freed up a buffer, the ring is no longer
623 * full.
624 */
625 if (!cep->tx_free++) {
626 if (netif_queue_stopped(dev)) {
627 netif_wake_queue(dev);
628 }
629 }
630
631 cep->dirty_tx = (cbd_t *)bdp;
632 }
633
634 if (must_restart) {
635 volatile cpm_cpm2_t *cp;
636
637 /* Some transmit errors cause the transmitter to shut
638 * down. We now issue a restart transmit. Since the
639 * errors close the BD and update the pointers, the restart
640 * _should_ pick up without having to reset any of our
641 * pointers either. Also, To workaround 8260 device erratum
642 * CPM37, we must disable and then re-enable the transmitter
643 * following a Late Collision, Underrun, or Retry Limit error.
644 */
645 cep->fccp->fcc_gfmr &= ~FCC_GFMR_ENT;
646 udelay(10); /* wait a few microseconds just on principle */
647 cep->fccp->fcc_gfmr |= FCC_GFMR_ENT;
648
649 cp = cpmp;
650 cp->cp_cpcr =
651 mk_cr_cmd(cep->fip->fc_cpmpage, cep->fip->fc_cpmblock,
652 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
653 while (cp->cp_cpcr & CPM_CR_FLG);
654 }
655 spin_unlock(&cep->lock);
656 }
657
658 /* Check for receive busy, i.e. packets coming but no place to
659 * put them.
660 */
661 if (int_events & FCC_ENET_BSY) {
662 cep->fccp->fcc_fcce = FCC_ENET_BSY;
663 cep->stats.rx_dropped++;
664 }
665
666 #ifdef PHY_INTERRUPT
667 enable_irq(PHY_INTERRUPT);
668 #endif
669 return IRQ_HANDLED;
670 }
671
672 /* During a receive, the cur_rx points to the current incoming buffer.
673 * When we update through the ring, if the next incoming buffer has
674 * not been given to the system, we just set the empty indicator,
675 * effectively tossing the packet.
676 */
677 static int
678 fcc_enet_rx(struct net_device *dev)
679 {
680 struct fcc_enet_private *cep;
681 volatile cbd_t *bdp;
682 struct sk_buff *skb;
683 ushort pkt_len;
684
685 cep = (struct fcc_enet_private *)dev->priv;
686
687 /* First, grab all of the stats for the incoming packet.
688 * These get messed up if we get called due to a busy condition.
689 */
690 bdp = cep->cur_rx;
691
692 for (;;) {
693 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
694 break;
695
696 #ifndef final_version
697 /* Since we have allocated space to hold a complete frame, both
698 * the first and last indicators should be set.
699 */
700 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
701 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
702 printk("CPM ENET: rcv is not first+last\n");
703 #endif
704
705 /* Frame too long or too short. */
706 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
707 cep->stats.rx_length_errors++;
708 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
709 cep->stats.rx_frame_errors++;
710 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
711 cep->stats.rx_crc_errors++;
712 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
713 cep->stats.rx_crc_errors++;
714 if (bdp->cbd_sc & BD_ENET_RX_CL) /* Late Collision */
715 cep->stats.rx_frame_errors++;
716
717 if (!(bdp->cbd_sc &
718 (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | BD_ENET_RX_CR
719 | BD_ENET_RX_OV | BD_ENET_RX_CL)))
720 {
721 /* Process the incoming frame. */
722 cep->stats.rx_packets++;
723
724 /* Remove the FCS from the packet length. */
725 pkt_len = bdp->cbd_datlen - 4;
726 cep->stats.rx_bytes += pkt_len;
727
728 /* This does 16 byte alignment, much more than we need. */
729 skb = dev_alloc_skb(pkt_len);
730
731 if (skb == NULL) {
732 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
733 cep->stats.rx_dropped++;
734 }
735 else {
736 skb_put(skb,pkt_len); /* Make room */
737 eth_copy_and_sum(skb,
738 (unsigned char *)__va(bdp->cbd_bufaddr),
739 pkt_len, 0);
740 skb->protocol=eth_type_trans(skb,dev);
741 netif_rx(skb);
742 }
743 }
744
745 /* Clear the status flags for this buffer. */
746 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
747
748 /* Mark the buffer empty. */
749 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
750
751 /* Update BD pointer to next entry. */
752 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
753 bdp = cep->rx_bd_base;
754 else
755 bdp++;
756
757 }
758 cep->cur_rx = (cbd_t *)bdp;
759
760 return 0;
761 }
762
763 static int
764 fcc_enet_close(struct net_device *dev)
765 {
766 #ifdef CONFIG_USE_MDIO
767 struct fcc_enet_private *fep = dev->priv;
768 #endif
769
770 netif_stop_queue(dev);
771 fcc_stop(dev);
772 #ifdef CONFIG_USE_MDIO
773 if (fep->phy)
774 mii_do_cmd(dev, fep->phy->shutdown);
775 #endif
776
777 return 0;
778 }
779
780 static struct net_device_stats *fcc_enet_get_stats(struct net_device *dev)
781 {
782 struct fcc_enet_private *cep = (struct fcc_enet_private *)dev->priv;
783
784 return &cep->stats;
785 }
786
787 #ifdef CONFIG_USE_MDIO
788
789 /* NOTE: Most of the following comes from the FEC driver for 860. The
790 * overall structure of MII code has been retained (as it's proved stable
791 * and well-tested), but actual transfer requests are processed "at once"
792 * instead of being queued (there's no interrupt-driven MII transfer
793 * mechanism, one has to toggle the data/clock bits manually).
794 */
795 static int
796 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
797 {
798 struct fcc_enet_private *fep;
799 int retval, tmp;
800
801 /* Add PHY address to register command. */
802 fep = dev->priv;
803 regval |= fep->phy_addr << 23;
804
805 retval = 0;
806
807 tmp = mii_send_receive(fep->fip, regval);
808 if (func)
809 func(tmp, dev);
810
811 return retval;
812 }
813
814 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
815 {
816 int k;
817
818 if(!c)
819 return;
820
821 for(k = 0; (c+k)->mii_data != mk_mii_end; k++)
822 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
823 }
824
825 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
826 {
827 volatile struct fcc_enet_private *fep = dev->priv;
828 uint s = fep->phy_status;
829
830 s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
831
832 if (mii_reg & BMSR_LSTATUS)
833 s |= PHY_STAT_LINK;
834 if (mii_reg & BMSR_RFAULT)
835 s |= PHY_STAT_FAULT;
836 if (mii_reg & BMSR_ANEGCOMPLETE)
837 s |= PHY_STAT_ANC;
838
839 fep->phy_status = s;
840 }
841
842 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
843 {
844 volatile struct fcc_enet_private *fep = dev->priv;
845 uint s = fep->phy_status;
846
847 s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
848
849 if (mii_reg & BMCR_ANENABLE)
850 s |= PHY_CONF_ANE;
851 if (mii_reg & BMCR_LOOPBACK)
852 s |= PHY_CONF_LOOP;
853
854 fep->phy_status = s;
855 }
856
857 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
858 {
859 volatile struct fcc_enet_private *fep = dev->priv;
860 uint s = fep->phy_status;
861
862 s &= ~(PHY_CONF_SPMASK);
863
864 if (mii_reg & ADVERTISE_10HALF)
865 s |= PHY_CONF_10HDX;
866 if (mii_reg & ADVERTISE_10FULL)
867 s |= PHY_CONF_10FDX;
868 if (mii_reg & ADVERTISE_100HALF)
869 s |= PHY_CONF_100HDX;
870 if (mii_reg & ADVERTISE_100FULL)
871 s |= PHY_CONF_100FDX;
872
873 fep->phy_status = s;
874 }
875
876 /* ------------------------------------------------------------------------- */
877 /* Generic PHY support. Should work for all PHYs, but does not support link
878 * change interrupts.
879 */
880 #ifdef CONFIG_FCC_GENERIC_PHY
881
882 static phy_info_t phy_info_generic = {
883 0x00000000, /* 0-->match any PHY */
884 "GENERIC",
885
886 (const phy_cmd_t []) { /* config */
887 /* advertise only half-duplex capabilities */
888 { mk_mii_write(MII_ADVERTISE, MII_ADVERTISE_HALF),
889 mii_parse_anar },
890
891 /* enable auto-negotiation */
892 { mk_mii_write(MII_BMCR, BMCR_ANENABLE), mii_parse_cr },
893 { mk_mii_end, }
894 },
895 (const phy_cmd_t []) { /* startup */
896 /* restart auto-negotiation */
897 { mk_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART),
898 NULL },
899 { mk_mii_end, }
900 },
901 (const phy_cmd_t []) { /* ack_int */
902 /* We don't actually use the ack_int table with a generic
903 * PHY, but putting a reference to mii_parse_sr here keeps
904 * us from getting a compiler warning about unused static
905 * functions in the case where we only compile in generic
906 * PHY support.
907 */
908 { mk_mii_read(MII_BMSR), mii_parse_sr },
909 { mk_mii_end, }
910 },
911 (const phy_cmd_t []) { /* shutdown */
912 { mk_mii_end, }
913 },
914 };
915 #endif /* ifdef CONFIG_FCC_GENERIC_PHY */
916
917 /* ------------------------------------------------------------------------- */
918 /* The Level one LXT970 is used by many boards */
919
920 #ifdef CONFIG_FCC_LXT970
921
922 #define MII_LXT970_MIRROR 16 /* Mirror register */
923 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
924 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
925 #define MII_LXT970_CONFIG 19 /* Configuration Register */
926 #define MII_LXT970_CSR 20 /* Chip Status Register */
927
928 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
929 {
930 volatile struct fcc_enet_private *fep = dev->priv;
931 uint s = fep->phy_status;
932
933 s &= ~(PHY_STAT_SPMASK);
934
935 if (mii_reg & 0x0800) {
936 if (mii_reg & 0x1000)
937 s |= PHY_STAT_100FDX;
938 else
939 s |= PHY_STAT_100HDX;
940 } else {
941 if (mii_reg & 0x1000)
942 s |= PHY_STAT_10FDX;
943 else
944 s |= PHY_STAT_10HDX;
945 }
946
947 fep->phy_status = s;
948 }
949
950 static phy_info_t phy_info_lxt970 = {
951 0x07810000,
952 "LXT970",
953
954 (const phy_cmd_t []) { /* config */
955 #if 0
956 // { mk_mii_write(MII_ADVERTISE, 0x0021), NULL },
957
958 /* Set default operation of 100-TX....for some reason
959 * some of these bits are set on power up, which is wrong.
960 */
961 { mk_mii_write(MII_LXT970_CONFIG, 0), NULL },
962 #endif
963 { mk_mii_read(MII_BMCR), mii_parse_cr },
964 { mk_mii_read(MII_ADVERTISE), mii_parse_anar },
965 { mk_mii_end, }
966 },
967 (const phy_cmd_t []) { /* startup - enable interrupts */
968 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
969 { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */
970 { mk_mii_end, }
971 },
972 (const phy_cmd_t []) { /* ack_int */
973 /* read SR and ISR to acknowledge */
974
975 { mk_mii_read(MII_BMSR), mii_parse_sr },
976 { mk_mii_read(MII_LXT970_ISR), NULL },
977
978 /* find out the current status */
979
980 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
981 { mk_mii_end, }
982 },
983 (const phy_cmd_t []) { /* shutdown - disable interrupts */
984 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
985 { mk_mii_end, }
986 },
987 };
988
989 #endif /* CONFIG_FEC_LXT970 */
990
991 /* ------------------------------------------------------------------------- */
992 /* The Level one LXT971 is used on some of my custom boards */
993
994 #ifdef CONFIG_FCC_LXT971
995
996 /* register definitions for the 971 */
997
998 #define MII_LXT971_PCR 16 /* Port Control Register */
999 #define MII_LXT971_SR2 17 /* Status Register 2 */
1000 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
1001 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
1002 #define MII_LXT971_LCR 20 /* LED Control Register */
1003 #define MII_LXT971_TCR 30 /* Transmit Control Register */
1004
1005 /*
1006 * I had some nice ideas of running the MDIO faster...
1007 * The 971 should support 8MHz and I tried it, but things acted really
1008 * weird, so 2.5 MHz ought to be enough for anyone...
1009 */
1010
1011 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
1012 {
1013 volatile struct fcc_enet_private *fep = dev->priv;
1014 uint s = fep->phy_status;
1015
1016 s &= ~(PHY_STAT_SPMASK);
1017
1018 if (mii_reg & 0x4000) {
1019 if (mii_reg & 0x0200)
1020 s |= PHY_STAT_100FDX;
1021 else
1022 s |= PHY_STAT_100HDX;
1023 } else {
1024 if (mii_reg & 0x0200)
1025 s |= PHY_STAT_10FDX;
1026 else
1027 s |= PHY_STAT_10HDX;
1028 }
1029 if (mii_reg & 0x0008)
1030 s |= PHY_STAT_FAULT;
1031
1032 fep->phy_status = s;
1033 }
1034
1035 static phy_info_t phy_info_lxt971 = {
1036 0x0001378e,
1037 "LXT971",
1038
1039 (const phy_cmd_t []) { /* config */
1040 /* configure link capabilities to advertise */
1041 { mk_mii_write(MII_ADVERTISE, MII_ADVERTISE_DEFAULT),
1042 mii_parse_anar },
1043
1044 /* enable auto-negotiation */
1045 { mk_mii_write(MII_BMCR, BMCR_ANENABLE), mii_parse_cr },
1046 { mk_mii_end, }
1047 },
1048 (const phy_cmd_t []) { /* startup - enable interrupts */
1049 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
1050
1051 /* restart auto-negotiation */
1052 { mk_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART),
1053 NULL },
1054 { mk_mii_end, }
1055 },
1056 (const phy_cmd_t []) { /* ack_int */
1057 /* find out the current status */
1058 { mk_mii_read(MII_BMSR), NULL },
1059 { mk_mii_read(MII_BMSR), mii_parse_sr },
1060 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
1061
1062 /* we only need to read ISR to acknowledge */
1063 { mk_mii_read(MII_LXT971_ISR), NULL },
1064 { mk_mii_end, }
1065 },
1066 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1067 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
1068 { mk_mii_end, }
1069 },
1070 };
1071
1072 #endif /* CONFIG_FCC_LXT971 */
1073
1074 /* ------------------------------------------------------------------------- */
1075 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
1076
1077 #ifdef CONFIG_FCC_QS6612
1078
1079 /* register definitions */
1080
1081 #define MII_QS6612_MCR 17 /* Mode Control Register */
1082 #define MII_QS6612_FTR 27 /* Factory Test Register */
1083 #define MII_QS6612_MCO 28 /* Misc. Control Register */
1084 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
1085 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
1086 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
1087
1088 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1089 {
1090 volatile struct fcc_enet_private *fep = dev->priv;
1091 uint s = fep->phy_status;
1092
1093 s &= ~(PHY_STAT_SPMASK);
1094
1095 switch((mii_reg >> 2) & 7) {
1096 case 1: s |= PHY_STAT_10HDX; break;
1097 case 2: s |= PHY_STAT_100HDX; break;
1098 case 5: s |= PHY_STAT_10FDX; break;
1099 case 6: s |= PHY_STAT_100FDX; break;
1100 }
1101
1102 fep->phy_status = s;
1103 }
1104
1105 static phy_info_t phy_info_qs6612 = {
1106 0x00181440,
1107 "QS6612",
1108
1109 (const phy_cmd_t []) { /* config */
1110 // { mk_mii_write(MII_ADVERTISE, 0x061), NULL }, /* 10 Mbps */
1111
1112 /* The PHY powers up isolated on the RPX,
1113 * so send a command to allow operation.
1114 */
1115
1116 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1117
1118 /* parse cr and anar to get some info */
1119
1120 { mk_mii_read(MII_BMCR), mii_parse_cr },
1121 { mk_mii_read(MII_ADVERTISE), mii_parse_anar },
1122 { mk_mii_end, }
1123 },
1124 (const phy_cmd_t []) { /* startup - enable interrupts */
1125 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1126 { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */
1127 { mk_mii_end, }
1128 },
1129 (const phy_cmd_t []) { /* ack_int */
1130
1131 /* we need to read ISR, SR and ANER to acknowledge */
1132
1133 { mk_mii_read(MII_QS6612_ISR), NULL },
1134 { mk_mii_read(MII_BMSR), mii_parse_sr },
1135 { mk_mii_read(MII_EXPANSION), NULL },
1136
1137 /* read pcr to get info */
1138
1139 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1140 { mk_mii_end, }
1141 },
1142 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1143 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1144 { mk_mii_end, }
1145 },
1146 };
1147
1148
1149 #endif /* CONFIG_FEC_QS6612 */
1150
1151
1152 /* ------------------------------------------------------------------------- */
1153 /* The Davicom DM9131 is used on the HYMOD board */
1154
1155 #ifdef CONFIG_FCC_DM9131
1156
1157 /* register definitions */
1158
1159 #define MII_DM9131_ACR 16 /* Aux. Config Register */
1160 #define MII_DM9131_ACSR 17 /* Aux. Config/Status Register */
1161 #define MII_DM9131_10TCSR 18 /* 10BaseT Config/Status Reg. */
1162 #define MII_DM9131_INTR 21 /* Interrupt Register */
1163 #define MII_DM9131_RECR 22 /* Receive Error Counter Reg. */
1164 #define MII_DM9131_DISCR 23 /* Disconnect Counter Register */
1165
1166 static void mii_parse_dm9131_acsr(uint mii_reg, struct net_device *dev)
1167 {
1168 volatile struct fcc_enet_private *fep = dev->priv;
1169 uint s = fep->phy_status;
1170
1171 s &= ~(PHY_STAT_SPMASK);
1172
1173 switch ((mii_reg >> 12) & 0xf) {
1174 case 1: s |= PHY_STAT_10HDX; break;
1175 case 2: s |= PHY_STAT_10FDX; break;
1176 case 4: s |= PHY_STAT_100HDX; break;
1177 case 8: s |= PHY_STAT_100FDX; break;
1178 }
1179
1180 fep->phy_status = s;
1181 }
1182
1183 static phy_info_t phy_info_dm9131 = {
1184 0x00181b80,
1185 "DM9131",
1186
1187 (const phy_cmd_t []) { /* config */
1188 /* parse cr and anar to get some info */
1189 { mk_mii_read(MII_BMCR), mii_parse_cr },
1190 { mk_mii_read(MII_ADVERTISE), mii_parse_anar },
1191 { mk_mii_end, }
1192 },
1193 (const phy_cmd_t []) { /* startup - enable interrupts */
1194 { mk_mii_write(MII_DM9131_INTR, 0x0002), NULL },
1195 { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */
1196 { mk_mii_end, }
1197 },
1198 (const phy_cmd_t []) { /* ack_int */
1199
1200 /* we need to read INTR, SR and ANER to acknowledge */
1201
1202 { mk_mii_read(MII_DM9131_INTR), NULL },
1203 { mk_mii_read(MII_BMSR), mii_parse_sr },
1204 { mk_mii_read(MII_EXPANSION), NULL },
1205
1206 /* read acsr to get info */
1207
1208 { mk_mii_read(MII_DM9131_ACSR), mii_parse_dm9131_acsr },
1209 { mk_mii_end, }
1210 },
1211 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1212 { mk_mii_write(MII_DM9131_INTR, 0x0f00), NULL },
1213 { mk_mii_end, }
1214 },
1215 };
1216
1217
1218 #endif /* CONFIG_FEC_DM9131 */
1219 #ifdef CONFIG_FCC_DM9161
1220 /* ------------------------------------------------------------------------- */
1221 /* DM9161 Control register values */
1222 #define MIIM_DM9161_CR_STOP 0x0400
1223 #define MIIM_DM9161_CR_RSTAN 0x1200
1224
1225 #define MIIM_DM9161_SCR 0x10
1226 #define MIIM_DM9161_SCR_INIT 0x0610
1227
1228 /* DM9161 Specified Configuration and Status Register */
1229 #define MIIM_DM9161_SCSR 0x11
1230 #define MIIM_DM9161_SCSR_100F 0x8000
1231 #define MIIM_DM9161_SCSR_100H 0x4000
1232 #define MIIM_DM9161_SCSR_10F 0x2000
1233 #define MIIM_DM9161_SCSR_10H 0x1000
1234 /* DM9161 10BT register */
1235 #define MIIM_DM9161_10BTCSR 0x12
1236 #define MIIM_DM9161_10BTCSR_INIT 0x7800
1237 /* DM9161 Interrupt Register */
1238 #define MIIM_DM9161_INTR 0x15
1239 #define MIIM_DM9161_INTR_PEND 0x8000
1240 #define MIIM_DM9161_INTR_DPLX_MASK 0x0800
1241 #define MIIM_DM9161_INTR_SPD_MASK 0x0400
1242 #define MIIM_DM9161_INTR_LINK_MASK 0x0200
1243 #define MIIM_DM9161_INTR_MASK 0x0100
1244 #define MIIM_DM9161_INTR_DPLX_CHANGE 0x0010
1245 #define MIIM_DM9161_INTR_SPD_CHANGE 0x0008
1246 #define MIIM_DM9161_INTR_LINK_CHANGE 0x0004
1247 #define MIIM_DM9161_INTR_INIT 0x0000
1248 #define MIIM_DM9161_INTR_STOP \
1249 (MIIM_DM9161_INTR_DPLX_MASK | MIIM_DM9161_INTR_SPD_MASK \
1250 | MIIM_DM9161_INTR_LINK_MASK | MIIM_DM9161_INTR_MASK)
1251
1252 static void mii_parse_dm9161_sr(uint mii_reg, struct net_device * dev)
1253 {
1254 volatile struct fcc_enet_private *fep = dev->priv;
1255 uint regstat, timeout=0xffff;
1256
1257 while(!(mii_reg & 0x0020) && timeout--)
1258 {
1259 regstat=mk_mii_read(MII_BMSR);
1260 regstat |= fep->phy_addr <<23;
1261 mii_reg = mii_send_receive(fep->fip,regstat);
1262 }
1263
1264 mii_parse_sr(mii_reg, dev);
1265 }
1266
1267 static void mii_parse_dm9161_scsr(uint mii_reg, struct net_device * dev)
1268 {
1269 volatile struct fcc_enet_private *fep = dev->priv;
1270 uint s = fep->phy_status;
1271
1272 s &= ~(PHY_STAT_SPMASK);
1273 switch((mii_reg >>12) & 0xf) {
1274 case 1:
1275 {
1276 s |= PHY_STAT_10HDX;
1277 printk("10BaseT Half Duplex\n");
1278 break;
1279 }
1280 case 2:
1281 {
1282 s |= PHY_STAT_10FDX;
1283 printk("10BaseT Full Duplex\n");
1284 break;
1285 }
1286 case 4:
1287 {
1288 s |= PHY_STAT_100HDX;
1289 printk("100BaseT Half Duplex\n");
1290 break;
1291 }
1292 case 8:
1293 {
1294 s |= PHY_STAT_100FDX;
1295 printk("100BaseT Full Duplex\n");
1296 break;
1297 }
1298 }
1299
1300 fep->phy_status = s;
1301
1302 }
1303
1304 static void mii_dm9161_wait(uint mii_reg, struct net_device *dev)
1305 {
1306 int timeout = HZ;
1307
1308 /* Davicom takes a bit to come up after a reset,
1309 * so wait here for a bit */
1310 schedule_timeout_uninterruptible(timeout);
1311 }
1312
1313 static phy_info_t phy_info_dm9161 = {
1314 0x00181b88,
1315 "Davicom DM9161E",
1316 (const phy_cmd_t[]) { /* config */
1317 { mk_mii_write(MII_BMCR, MIIM_DM9161_CR_STOP), NULL},
1318 /* Do not bypass the scrambler/descrambler */
1319 { mk_mii_write(MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT), NULL},
1320 /* Configure 10BTCSR register */
1321 { mk_mii_write(MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT),NULL},
1322 /* Configure some basic stuff */
1323 { mk_mii_write(MII_BMCR, 0x1000), NULL},
1324 { mk_mii_read(MII_BMCR), mii_parse_cr },
1325 { mk_mii_read(MII_ADVERTISE), mii_parse_anar },
1326 { mk_mii_end,}
1327 },
1328 (const phy_cmd_t[]) { /* startup */
1329 /* Restart Auto Negotiation */
1330 { mk_mii_write(MII_BMCR, MIIM_DM9161_CR_RSTAN), NULL},
1331 /* Status is read once to clear old link state */
1332 { mk_mii_read(MII_BMSR), mii_dm9161_wait},
1333 /* Auto-negotiate */
1334 { mk_mii_read(MII_BMSR), mii_parse_dm9161_sr},
1335 /* Read the status */
1336 { mk_mii_read(MIIM_DM9161_SCSR), mii_parse_dm9161_scsr},
1337 /* Clear any pending interrupts */
1338 { mk_mii_read(MIIM_DM9161_INTR), NULL},
1339 /* Enable Interrupts */
1340 { mk_mii_write(MIIM_DM9161_INTR, MIIM_DM9161_INTR_INIT), NULL},
1341 { mk_mii_end,}
1342 },
1343 (const phy_cmd_t[]) { /* ack_int */
1344 { mk_mii_read(MIIM_DM9161_INTR), NULL},
1345 #if 0
1346 { mk_mii_read(MII_BMSR), NULL},
1347 { mk_mii_read(MII_BMSR), mii_parse_dm9161_sr},
1348 { mk_mii_read(MIIM_DM9161_SCSR), mii_parse_dm9161_scsr},
1349 #endif
1350 { mk_mii_end,}
1351 },
1352 (const phy_cmd_t[]) { /* shutdown */
1353 { mk_mii_read(MIIM_DM9161_INTR),NULL},
1354 { mk_mii_write(MIIM_DM9161_INTR, MIIM_DM9161_INTR_STOP), NULL},
1355 { mk_mii_end,}
1356 },
1357 };
1358 #endif /* CONFIG_FCC_DM9161 */
1359
1360 static phy_info_t *phy_info[] = {
1361
1362 #ifdef CONFIG_FCC_LXT970
1363 &phy_info_lxt970,
1364 #endif /* CONFIG_FEC_LXT970 */
1365
1366 #ifdef CONFIG_FCC_LXT971
1367 &phy_info_lxt971,
1368 #endif /* CONFIG_FEC_LXT971 */
1369
1370 #ifdef CONFIG_FCC_QS6612
1371 &phy_info_qs6612,
1372 #endif /* CONFIG_FEC_QS6612 */
1373
1374 #ifdef CONFIG_FCC_DM9131
1375 &phy_info_dm9131,
1376 #endif /* CONFIG_FEC_DM9131 */
1377
1378 #ifdef CONFIG_FCC_DM9161
1379 &phy_info_dm9161,
1380 #endif /* CONFIG_FCC_DM9161 */
1381
1382 #ifdef CONFIG_FCC_GENERIC_PHY
1383 /* Generic PHY support. This must be the last PHY in the table.
1384 * It will be used to support any PHY that doesn't match a previous
1385 * entry in the table.
1386 */
1387 &phy_info_generic,
1388 #endif /* CONFIG_FCC_GENERIC_PHY */
1389
1390 NULL
1391 };
1392
1393 static void mii_display_status(struct work_struct *work)
1394 {
1395 volatile struct fcc_enet_private *fep =
1396 container_of(work, struct fcc_enet_private, phy_relink);
1397 struct net_device *dev = fep->dev;
1398 uint s = fep->phy_status;
1399
1400 if (!fep->link && !fep->old_link) {
1401 /* Link is still down - don't print anything */
1402 return;
1403 }
1404
1405 printk("%s: status: ", dev->name);
1406
1407 if (!fep->link) {
1408 printk("link down");
1409 } else {
1410 printk("link up");
1411
1412 switch(s & PHY_STAT_SPMASK) {
1413 case PHY_STAT_100FDX: printk(", 100 Mbps Full Duplex"); break;
1414 case PHY_STAT_100HDX: printk(", 100 Mbps Half Duplex"); break;
1415 case PHY_STAT_10FDX: printk(", 10 Mbps Full Duplex"); break;
1416 case PHY_STAT_10HDX: printk(", 10 Mbps Half Duplex"); break;
1417 default:
1418 printk(", Unknown speed/duplex");
1419 }
1420
1421 if (s & PHY_STAT_ANC)
1422 printk(", auto-negotiation complete");
1423 }
1424
1425 if (s & PHY_STAT_FAULT)
1426 printk(", remote fault");
1427
1428 printk(".\n");
1429 }
1430
1431 static void mii_display_config(struct work_struct *work)
1432 {
1433 volatile struct fcc_enet_private *fep =
1434 container_of(work, struct fcc_enet_private,
1435 phy_display_config);
1436 struct net_device *dev = fep->dev;
1437 uint s = fep->phy_status;
1438
1439 printk("%s: config: auto-negotiation ", dev->name);
1440
1441 if (s & PHY_CONF_ANE)
1442 printk("on");
1443 else
1444 printk("off");
1445
1446 if (s & PHY_CONF_100FDX)
1447 printk(", 100FDX");
1448 if (s & PHY_CONF_100HDX)
1449 printk(", 100HDX");
1450 if (s & PHY_CONF_10FDX)
1451 printk(", 10FDX");
1452 if (s & PHY_CONF_10HDX)
1453 printk(", 10HDX");
1454 if (!(s & PHY_CONF_SPMASK))
1455 printk(", No speed/duplex selected?");
1456
1457 if (s & PHY_CONF_LOOP)
1458 printk(", loopback enabled");
1459
1460 printk(".\n");
1461
1462 fep->sequence_done = 1;
1463 }
1464
1465 static void mii_relink(struct net_device *dev)
1466 {
1467 struct fcc_enet_private *fep = dev->priv;
1468 int duplex = 0;
1469
1470 fep->old_link = fep->link;
1471 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1472
1473 #ifdef MDIO_DEBUG
1474 printk(" mii_relink: link=%d\n", fep->link);
1475 #endif
1476
1477 if (fep->link) {
1478 if (fep->phy_status
1479 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1480 duplex = 1;
1481 fcc_restart(dev, duplex);
1482 #ifdef MDIO_DEBUG
1483 printk(" mii_relink: duplex=%d\n", duplex);
1484 #endif
1485 }
1486 }
1487
1488 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1489 {
1490 struct fcc_enet_private *fep = dev->priv;
1491
1492 mii_relink(dev);
1493
1494 schedule_work(&fep->phy_relink);
1495 }
1496
1497 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1498 {
1499 struct fcc_enet_private *fep = dev->priv;
1500
1501 schedule_work(&fep->phy_display_config);
1502 }
1503
1504 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_BMCR), mii_queue_relink },
1505 { mk_mii_end, } };
1506 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_BMCR), mii_queue_config },
1507 { mk_mii_end, } };
1508
1509
1510 /* Read remainder of PHY ID.
1511 */
1512 static void
1513 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1514 {
1515 struct fcc_enet_private *fep;
1516 int i;
1517
1518 fep = dev->priv;
1519 printk("mii_reg: %08x\n", mii_reg);
1520 fep->phy_id |= (mii_reg & 0xffff);
1521
1522 for(i = 0; phy_info[i]; i++)
1523 if((phy_info[i]->id == (fep->phy_id >> 4)) || !phy_info[i]->id)
1524 break;
1525
1526 if(!phy_info[i])
1527 panic("%s: PHY id 0x%08x is not supported!\n",
1528 dev->name, fep->phy_id);
1529
1530 fep->phy = phy_info[i];
1531 fep->phy_id_done = 1;
1532
1533 printk("%s: Phy @ 0x%x, type %s (0x%08x)\n",
1534 dev->name, fep->phy_addr, fep->phy->name, fep->phy_id);
1535 }
1536
1537 /* Scan all of the MII PHY addresses looking for someone to respond
1538 * with a valid ID. This usually happens quickly.
1539 */
1540 static void
1541 mii_discover_phy(uint mii_reg, struct net_device *dev)
1542 {
1543 struct fcc_enet_private *fep;
1544 uint phytype;
1545
1546 fep = dev->priv;
1547
1548 if ((phytype = (mii_reg & 0xffff)) != 0xffff) {
1549
1550 /* Got first part of ID, now get remainder. */
1551 fep->phy_id = phytype << 16;
1552 mii_queue(dev, mk_mii_read(MII_PHYSID2), mii_discover_phy3);
1553 } else {
1554 fep->phy_addr++;
1555 if (fep->phy_addr < 32) {
1556 mii_queue(dev, mk_mii_read(MII_PHYSID1),
1557 mii_discover_phy);
1558 } else {
1559 printk("fec: No PHY device found.\n");
1560 }
1561 }
1562 }
1563 #endif /* CONFIG_USE_MDIO */
1564
1565 #ifdef PHY_INTERRUPT
1566 /* This interrupt occurs when the PHY detects a link change. */
1567 static irqreturn_t
1568 mii_link_interrupt(int irq, void * dev_id)
1569 {
1570 struct net_device *dev = dev_id;
1571 struct fcc_enet_private *fep = dev->priv;
1572 fcc_info_t *fip = fep->fip;
1573
1574 if (fep->phy) {
1575 /* We don't want to be interrupted by an FCC
1576 * interrupt here.
1577 */
1578 disable_irq_nosync(fip->fc_interrupt);
1579
1580 mii_do_cmd(dev, fep->phy->ack_int);
1581 /* restart and display status */
1582 mii_do_cmd(dev, phy_cmd_relink);
1583
1584 enable_irq(fip->fc_interrupt);
1585 }
1586 return IRQ_HANDLED;
1587 }
1588 #endif /* ifdef PHY_INTERRUPT */
1589
1590 #if 0 /* This should be fixed someday */
1591 /* Set or clear the multicast filter for this adaptor.
1592 * Skeleton taken from sunlance driver.
1593 * The CPM Ethernet implementation allows Multicast as well as individual
1594 * MAC address filtering. Some of the drivers check to make sure it is
1595 * a group multicast address, and discard those that are not. I guess I
1596 * will do the same for now, but just remove the test if you want
1597 * individual filtering as well (do the upper net layers want or support
1598 * this kind of feature?).
1599 */
1600 static void
1601 set_multicast_list(struct net_device *dev)
1602 {
1603 struct fcc_enet_private *cep;
1604 struct dev_mc_list *dmi;
1605 u_char *mcptr, *tdptr;
1606 volatile fcc_enet_t *ep;
1607 int i, j;
1608
1609 cep = (struct fcc_enet_private *)dev->priv;
1610
1611 return;
1612 /* Get pointer to FCC area in parameter RAM.
1613 */
1614 ep = (fcc_enet_t *)dev->base_addr;
1615
1616 if (dev->flags&IFF_PROMISC) {
1617
1618 /* Log any net taps. */
1619 printk("%s: Promiscuous mode enabled.\n", dev->name);
1620 cep->fccp->fcc_fpsmr |= FCC_PSMR_PRO;
1621 } else {
1622
1623 cep->fccp->fcc_fpsmr &= ~FCC_PSMR_PRO;
1624
1625 if (dev->flags & IFF_ALLMULTI) {
1626 /* Catch all multicast addresses, so set the
1627 * filter to all 1's.
1628 */
1629 ep->fen_gaddrh = 0xffffffff;
1630 ep->fen_gaddrl = 0xffffffff;
1631 }
1632 else {
1633 /* Clear filter and add the addresses in the list.
1634 */
1635 ep->fen_gaddrh = 0;
1636 ep->fen_gaddrl = 0;
1637
1638 dmi = dev->mc_list;
1639
1640 for (i=0; i<dev->mc_count; i++, dmi = dmi->next) {
1641
1642 /* Only support group multicast for now.
1643 */
1644 if (!(dmi->dmi_addr[0] & 1))
1645 continue;
1646
1647 /* The address in dmi_addr is LSB first,
1648 * and taddr is MSB first. We have to
1649 * copy bytes MSB first from dmi_addr.
1650 */
1651 mcptr = (u_char *)dmi->dmi_addr + 5;
1652 tdptr = (u_char *)&ep->fen_taddrh;
1653 for (j=0; j<6; j++)
1654 *tdptr++ = *mcptr--;
1655
1656 /* Ask CPM to run CRC and set bit in
1657 * filter mask.
1658 */
1659 cpmp->cp_cpcr = mk_cr_cmd(cep->fip->fc_cpmpage,
1660 cep->fip->fc_cpmblock, 0x0c,
1661 CPM_CR_SET_GADDR) | CPM_CR_FLG;
1662 udelay(10);
1663 while (cpmp->cp_cpcr & CPM_CR_FLG);
1664 }
1665 }
1666 }
1667 }
1668 #endif /* if 0 */
1669
1670
1671 /* Set the individual MAC address.
1672 */
1673 int fcc_enet_set_mac_address(struct net_device *dev, void *p)
1674 {
1675 struct sockaddr *addr= (struct sockaddr *) p;
1676 struct fcc_enet_private *cep;
1677 volatile fcc_enet_t *ep;
1678 unsigned char *eap;
1679 int i;
1680
1681 cep = (struct fcc_enet_private *)(dev->priv);
1682 ep = cep->ep;
1683
1684 if (netif_running(dev))
1685 return -EBUSY;
1686
1687 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1688
1689 eap = (unsigned char *) &(ep->fen_paddrh);
1690 for (i=5; i>=0; i--)
1691 *eap++ = addr->sa_data[i];
1692
1693 return 0;
1694 }
1695
1696
1697 /* Initialize the CPM Ethernet on FCC.
1698 */
1699 static int __init fec_enet_init(void)
1700 {
1701 struct net_device *dev;
1702 struct fcc_enet_private *cep;
1703 fcc_info_t *fip;
1704 int i, np, err;
1705 volatile cpm2_map_t *immap;
1706 volatile iop_cpm2_t *io;
1707
1708 immap = (cpm2_map_t *)CPM_MAP_ADDR; /* and to internal registers */
1709 io = &immap->im_ioport;
1710
1711 np = sizeof(fcc_ports) / sizeof(fcc_info_t);
1712 fip = fcc_ports;
1713
1714 while (np-- > 0) {
1715 /* Create an Ethernet device instance.
1716 */
1717 dev = alloc_etherdev(sizeof(*cep));
1718 if (!dev)
1719 return -ENOMEM;
1720
1721 cep = dev->priv;
1722 spin_lock_init(&cep->lock);
1723 cep->fip = fip;
1724
1725 init_fcc_shutdown(fip, cep, immap);
1726 init_fcc_ioports(fip, io, immap);
1727 init_fcc_param(fip, dev, immap);
1728
1729 dev->base_addr = (unsigned long)(cep->ep);
1730
1731 /* The CPM Ethernet specific entries in the device
1732 * structure.
1733 */
1734 dev->open = fcc_enet_open;
1735 dev->hard_start_xmit = fcc_enet_start_xmit;
1736 dev->tx_timeout = fcc_enet_timeout;
1737 dev->watchdog_timeo = TX_TIMEOUT;
1738 dev->stop = fcc_enet_close;
1739 dev->get_stats = fcc_enet_get_stats;
1740 /* dev->set_multicast_list = set_multicast_list; */
1741 dev->set_mac_address = fcc_enet_set_mac_address;
1742
1743 init_fcc_startup(fip, dev);
1744
1745 err = register_netdev(dev);
1746 if (err) {
1747 free_netdev(dev);
1748 return err;
1749 }
1750
1751 printk("%s: FCC ENET Version 0.3, ", dev->name);
1752 for (i=0; i<5; i++)
1753 printk("%02x:", dev->dev_addr[i]);
1754 printk("%02x\n", dev->dev_addr[5]);
1755
1756 #ifdef CONFIG_USE_MDIO
1757 /* Queue up command to detect the PHY and initialize the
1758 * remainder of the interface.
1759 */
1760 cep->phy_id_done = 0;
1761 cep->phy_addr = fip->fc_phyaddr;
1762 mii_queue(dev, mk_mii_read(MII_PHYSID1), mii_discover_phy);
1763 INIT_WORK(&cep->phy_relink, mii_display_status);
1764 INIT_WORK(&cep->phy_display_config, mii_display_config);
1765 cep->dev = dev;
1766 #endif /* CONFIG_USE_MDIO */
1767
1768 fip++;
1769 }
1770
1771 return 0;
1772 }
1773 module_init(fec_enet_init);
1774
1775 /* Make sure the device is shut down during initialization.
1776 */
1777 static void __init
1778 init_fcc_shutdown(fcc_info_t *fip, struct fcc_enet_private *cep,
1779 volatile cpm2_map_t *immap)
1780 {
1781 volatile fcc_enet_t *ep;
1782 volatile fcc_t *fccp;
1783
1784 /* Get pointer to FCC area in parameter RAM.
1785 */
1786 ep = (fcc_enet_t *)(&immap->im_dprambase[fip->fc_proff]);
1787
1788 /* And another to the FCC register area.
1789 */
1790 fccp = (volatile fcc_t *)(&immap->im_fcc[fip->fc_fccnum]);
1791 cep->fccp = fccp; /* Keep the pointers handy */
1792 cep->ep = ep;
1793
1794 /* Disable receive and transmit in case someone left it running.
1795 */
1796 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
1797 }
1798
1799 /* Initialize the I/O pins for the FCC Ethernet.
1800 */
1801 static void __init
1802 init_fcc_ioports(fcc_info_t *fip, volatile iop_cpm2_t *io,
1803 volatile cpm2_map_t *immap)
1804 {
1805
1806 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1807 */
1808 if (fip->fc_proff == PROFF_FCC1) {
1809 /* Configure port A and C pins for FCC1 Ethernet.
1810 */
1811 io->iop_pdira &= ~PA1_DIRA_BOUT;
1812 io->iop_pdira |= PA1_DIRA_BIN;
1813 io->iop_psora &= ~PA1_PSORA_BOUT;
1814 io->iop_psora |= PA1_PSORA_BIN;
1815 io->iop_ppara |= (PA1_DIRA_BOUT | PA1_DIRA_BIN);
1816 }
1817 if (fip->fc_proff == PROFF_FCC2) {
1818 /* Configure port B and C pins for FCC Ethernet.
1819 */
1820 io->iop_pdirb &= ~PB2_DIRB_BOUT;
1821 io->iop_pdirb |= PB2_DIRB_BIN;
1822 io->iop_psorb &= ~PB2_PSORB_BOUT;
1823 io->iop_psorb |= PB2_PSORB_BIN;
1824 io->iop_pparb |= (PB2_DIRB_BOUT | PB2_DIRB_BIN);
1825 }
1826 if (fip->fc_proff == PROFF_FCC3) {
1827 /* Configure port B and C pins for FCC Ethernet.
1828 */
1829 io->iop_pdirb &= ~PB3_DIRB_BOUT;
1830 io->iop_pdirb |= PB3_DIRB_BIN;
1831 io->iop_psorb &= ~PB3_PSORB_BOUT;
1832 io->iop_psorb |= PB3_PSORB_BIN;
1833 io->iop_pparb |= (PB3_DIRB_BOUT | PB3_DIRB_BIN);
1834
1835 io->iop_pdirc &= ~PC3_DIRC_BOUT;
1836 io->iop_pdirc |= PC3_DIRC_BIN;
1837 io->iop_psorc &= ~PC3_PSORC_BOUT;
1838 io->iop_psorc |= PC3_PSORC_BIN;
1839 io->iop_pparc |= (PC3_DIRC_BOUT | PC3_DIRC_BIN);
1840
1841 }
1842
1843 /* Port C has clocks......
1844 */
1845 io->iop_psorc &= ~(fip->fc_trxclocks);
1846 io->iop_pdirc &= ~(fip->fc_trxclocks);
1847 io->iop_pparc |= fip->fc_trxclocks;
1848
1849 #ifdef CONFIG_USE_MDIO
1850 /* ....and the MII serial clock/data.
1851 */
1852 io->iop_pdatc |= (fip->fc_mdio | fip->fc_mdck);
1853 io->iop_podrc &= ~(fip->fc_mdio | fip->fc_mdck);
1854 io->iop_pdirc |= (fip->fc_mdio | fip->fc_mdck);
1855 io->iop_pparc &= ~(fip->fc_mdio | fip->fc_mdck);
1856 #endif /* CONFIG_USE_MDIO */
1857
1858 /* Configure Serial Interface clock routing.
1859 * First, clear all FCC bits to zero,
1860 * then set the ones we want.
1861 */
1862 immap->im_cpmux.cmx_fcr &= ~(fip->fc_clockmask);
1863 immap->im_cpmux.cmx_fcr |= fip->fc_clockroute;
1864 }
1865
1866 static void __init
1867 init_fcc_param(fcc_info_t *fip, struct net_device *dev,
1868 volatile cpm2_map_t *immap)
1869 {
1870 unsigned char *eap;
1871 unsigned long mem_addr;
1872 bd_t *bd;
1873 int i, j;
1874 struct fcc_enet_private *cep;
1875 volatile fcc_enet_t *ep;
1876 volatile cbd_t *bdp;
1877 volatile cpm_cpm2_t *cp;
1878
1879 cep = (struct fcc_enet_private *)(dev->priv);
1880 ep = cep->ep;
1881 cp = cpmp;
1882
1883 bd = (bd_t *)__res;
1884
1885 /* Zero the whole thing.....I must have missed some individually.
1886 * It works when I do this.
1887 */
1888 memset((char *)ep, 0, sizeof(fcc_enet_t));
1889
1890 /* Allocate space for the buffer descriptors from regular memory.
1891 * Initialize base addresses for the buffer descriptors.
1892 */
1893 cep->rx_bd_base = kmalloc(sizeof(cbd_t) * RX_RING_SIZE,
1894 GFP_KERNEL | GFP_DMA);
1895 ep->fen_genfcc.fcc_rbase = __pa(cep->rx_bd_base);
1896 cep->tx_bd_base = kmalloc(sizeof(cbd_t) * TX_RING_SIZE,
1897 GFP_KERNEL | GFP_DMA);
1898 ep->fen_genfcc.fcc_tbase = __pa(cep->tx_bd_base);
1899
1900 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
1901 cep->cur_rx = cep->rx_bd_base;
1902
1903 ep->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1904 ep->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB) << 24;
1905
1906 /* Set maximum bytes per receive buffer.
1907 * It must be a multiple of 32.
1908 */
1909 ep->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE;
1910
1911 /* Allocate space in the reserved FCC area of DPRAM for the
1912 * internal buffers. No one uses this space (yet), so we
1913 * can do this. Later, we will add resource management for
1914 * this area.
1915 */
1916 mem_addr = CPM_FCC_SPECIAL_BASE + (fip->fc_fccnum * 128);
1917 ep->fen_genfcc.fcc_riptr = mem_addr;
1918 ep->fen_genfcc.fcc_tiptr = mem_addr+32;
1919 ep->fen_padptr = mem_addr+64;
1920 memset((char *)(&(immap->im_dprambase[(mem_addr+64)])), 0x88, 32);
1921
1922 ep->fen_genfcc.fcc_rbptr = 0;
1923 ep->fen_genfcc.fcc_tbptr = 0;
1924 ep->fen_genfcc.fcc_rcrc = 0;
1925 ep->fen_genfcc.fcc_tcrc = 0;
1926 ep->fen_genfcc.fcc_res1 = 0;
1927 ep->fen_genfcc.fcc_res2 = 0;
1928
1929 ep->fen_camptr = 0; /* CAM isn't used in this driver */
1930
1931 /* Set CRC preset and mask.
1932 */
1933 ep->fen_cmask = 0xdebb20e3;
1934 ep->fen_cpres = 0xffffffff;
1935
1936 ep->fen_crcec = 0; /* CRC Error counter */
1937 ep->fen_alec = 0; /* alignment error counter */
1938 ep->fen_disfc = 0; /* discard frame counter */
1939 ep->fen_retlim = 15; /* Retry limit threshold */
1940 ep->fen_pper = 0; /* Normal persistence */
1941
1942 /* Clear hash filter tables.
1943 */
1944 ep->fen_gaddrh = 0;
1945 ep->fen_gaddrl = 0;
1946 ep->fen_iaddrh = 0;
1947 ep->fen_iaddrl = 0;
1948
1949 /* Clear the Out-of-sequence TxBD.
1950 */
1951 ep->fen_tfcstat = 0;
1952 ep->fen_tfclen = 0;
1953 ep->fen_tfcptr = 0;
1954
1955 ep->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
1956 ep->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
1957
1958 /* Set Ethernet station address.
1959 *
1960 * This is supplied in the board information structure, so we
1961 * copy that into the controller.
1962 * So, far we have only been given one Ethernet address. We make
1963 * it unique by setting a few bits in the upper byte of the
1964 * non-static part of the address.
1965 */
1966 eap = (unsigned char *)&(ep->fen_paddrh);
1967 for (i=5; i>=0; i--) {
1968
1969 /*
1970 * The EP8260 only uses FCC3, so we can safely give it the real
1971 * MAC address.
1972 */
1973 #ifdef CONFIG_SBC82xx
1974 if (i == 5) {
1975 /* bd->bi_enetaddr holds the SCC0 address; the FCC
1976 devices count up from there */
1977 dev->dev_addr[i] = bd->bi_enetaddr[i] & ~3;
1978 dev->dev_addr[i] += 1 + fip->fc_fccnum;
1979 *eap++ = dev->dev_addr[i];
1980 }
1981 #else
1982 #ifndef CONFIG_RPX8260
1983 if (i == 3) {
1984 dev->dev_addr[i] = bd->bi_enetaddr[i];
1985 dev->dev_addr[i] |= (1 << (7 - fip->fc_fccnum));
1986 *eap++ = dev->dev_addr[i];
1987 } else
1988 #endif
1989 {
1990 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
1991 }
1992 #endif
1993 }
1994
1995 ep->fen_taddrh = 0;
1996 ep->fen_taddrm = 0;
1997 ep->fen_taddrl = 0;
1998
1999 ep->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length */
2000 ep->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length */
2001
2002 /* Clear stat counters, in case we ever enable RMON.
2003 */
2004 ep->fen_octc = 0;
2005 ep->fen_colc = 0;
2006 ep->fen_broc = 0;
2007 ep->fen_mulc = 0;
2008 ep->fen_uspc = 0;
2009 ep->fen_frgc = 0;
2010 ep->fen_ospc = 0;
2011 ep->fen_jbrc = 0;
2012 ep->fen_p64c = 0;
2013 ep->fen_p65c = 0;
2014 ep->fen_p128c = 0;
2015 ep->fen_p256c = 0;
2016 ep->fen_p512c = 0;
2017 ep->fen_p1024c = 0;
2018
2019 ep->fen_rfthr = 0; /* Suggested by manual */
2020 ep->fen_rfcnt = 0;
2021 ep->fen_cftype = 0;
2022
2023 /* Now allocate the host memory pages and initialize the
2024 * buffer descriptors.
2025 */
2026 bdp = cep->tx_bd_base;
2027 for (i=0; i<TX_RING_SIZE; i++) {
2028
2029 /* Initialize the BD for every fragment in the page.
2030 */
2031 bdp->cbd_sc = 0;
2032 bdp->cbd_datlen = 0;
2033 bdp->cbd_bufaddr = 0;
2034 bdp++;
2035 }
2036
2037 /* Set the last buffer to wrap.
2038 */
2039 bdp--;
2040 bdp->cbd_sc |= BD_SC_WRAP;
2041
2042 bdp = cep->rx_bd_base;
2043 for (i=0; i<FCC_ENET_RX_PAGES; i++) {
2044
2045 /* Allocate a page.
2046 */
2047 mem_addr = __get_free_page(GFP_KERNEL);
2048
2049 /* Initialize the BD for every fragment in the page.
2050 */
2051 for (j=0; j<FCC_ENET_RX_FRPPG; j++) {
2052 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
2053 bdp->cbd_datlen = 0;
2054 bdp->cbd_bufaddr = __pa(mem_addr);
2055 mem_addr += FCC_ENET_RX_FRSIZE;
2056 bdp++;
2057 }
2058 }
2059
2060 /* Set the last buffer to wrap.
2061 */
2062 bdp--;
2063 bdp->cbd_sc |= BD_SC_WRAP;
2064
2065 /* Let's re-initialize the channel now. We have to do it later
2066 * than the manual describes because we have just now finished
2067 * the BD initialization.
2068 */
2069 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock, 0x0c,
2070 CPM_CR_INIT_TRX) | CPM_CR_FLG;
2071 while (cp->cp_cpcr & CPM_CR_FLG);
2072
2073 cep->skb_cur = cep->skb_dirty = 0;
2074 }
2075
2076 /* Let 'er rip.
2077 */
2078 static void __init
2079 init_fcc_startup(fcc_info_t *fip, struct net_device *dev)
2080 {
2081 volatile fcc_t *fccp;
2082 struct fcc_enet_private *cep;
2083
2084 cep = (struct fcc_enet_private *)(dev->priv);
2085 fccp = cep->fccp;
2086
2087 #ifdef CONFIG_RPX8260
2088 #ifdef PHY_INTERRUPT
2089 /* Route PHY interrupt to IRQ. The following code only works for
2090 * IRQ1 - IRQ7. It does not work for Port C interrupts.
2091 */
2092 *((volatile u_char *) (RPX_CSR_ADDR + 13)) &= ~BCSR13_FETH_IRQMASK;
2093 *((volatile u_char *) (RPX_CSR_ADDR + 13)) |=
2094 ((PHY_INTERRUPT - SIU_INT_IRQ1 + 1) << 4);
2095 #endif
2096 /* Initialize MDIO pins. */
2097 *((volatile u_char *) (RPX_CSR_ADDR + 4)) &= ~BCSR4_MII_MDC;
2098 *((volatile u_char *) (RPX_CSR_ADDR + 4)) |=
2099 BCSR4_MII_READ | BCSR4_MII_MDIO;
2100 /* Enable external LXT971 PHY. */
2101 *((volatile u_char *) (RPX_CSR_ADDR + 4)) |= BCSR4_EN_PHY;
2102 udelay(1000);
2103 *((volatile u_char *) (RPX_CSR_ADDR+ 4)) |= BCSR4_EN_MII;
2104 udelay(1000);
2105 #endif /* ifdef CONFIG_RPX8260 */
2106
2107 fccp->fcc_fcce = 0xffff; /* Clear any pending events */
2108
2109 /* Leave FCC interrupts masked for now. Will be unmasked by
2110 * fcc_restart().
2111 */
2112 fccp->fcc_fccm = 0;
2113
2114 /* Install our interrupt handler.
2115 */
2116 if (request_irq(fip->fc_interrupt, fcc_enet_interrupt, 0, "fenet",
2117 dev) < 0)
2118 printk("Can't get FCC IRQ %d\n", fip->fc_interrupt);
2119
2120 #ifdef PHY_INTERRUPT
2121 #ifdef CONFIG_ADS8272
2122 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, IRQF_SHARED,
2123 "mii", dev) < 0)
2124 printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT);
2125 #else
2126 /* Make IRQn edge triggered. This does not work if PHY_INTERRUPT is
2127 * on Port C.
2128 */
2129 ((volatile cpm2_map_t *) CPM_MAP_ADDR)->im_intctl.ic_siexr |=
2130 (1 << (14 - (PHY_INTERRUPT - SIU_INT_IRQ1)));
2131
2132 if (request_irq(PHY_INTERRUPT, mii_link_interrupt, 0,
2133 "mii", dev) < 0)
2134 printk(KERN_CRIT "Can't get MII IRQ %d\n", PHY_INTERRUPT);
2135 #endif
2136 #endif /* PHY_INTERRUPT */
2137
2138 /* Set GFMR to enable Ethernet operating mode.
2139 */
2140 fccp->fcc_gfmr = (FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
2141
2142 /* Set sync/delimiters.
2143 */
2144 fccp->fcc_fdsr = 0xd555;
2145
2146 /* Set protocol specific processing mode for Ethernet.
2147 * This has to be adjusted for Full Duplex operation after we can
2148 * determine how to detect that.
2149 */
2150 fccp->fcc_fpsmr = FCC_PSMR_ENCRC;
2151
2152 #ifdef CONFIG_PQ2ADS
2153 /* Enable the PHY. */
2154 *(volatile uint *)(BCSR_ADDR + 4) &= ~BCSR1_FETHIEN;
2155 *(volatile uint *)(BCSR_ADDR + 4) |= BCSR1_FETH_RST;
2156 #endif
2157 #if defined(CONFIG_PQ2ADS) || defined(CONFIG_PQ2FADS)
2158 /* Enable the 2nd PHY. */
2159 *(volatile uint *)(BCSR_ADDR + 12) &= ~BCSR3_FETHIEN2;
2160 *(volatile uint *)(BCSR_ADDR + 12) |= BCSR3_FETH2_RST;
2161 #endif
2162
2163 #if defined(CONFIG_USE_MDIO) || defined(CONFIG_TQM8260)
2164 /* start in full duplex mode, and negotiate speed
2165 */
2166 fcc_restart (dev, 1);
2167 #else
2168 /* start in half duplex mode
2169 */
2170 fcc_restart (dev, 0);
2171 #endif
2172 }
2173
2174 #ifdef CONFIG_USE_MDIO
2175 /* MII command/status interface.
2176 * I'm not going to describe all of the details. You can find the
2177 * protocol definition in many other places, including the data sheet
2178 * of most PHY parts.
2179 * I wonder what "they" were thinking (maybe weren't) when they leave
2180 * the I2C in the CPM but I have to toggle these bits......
2181 */
2182 #ifdef CONFIG_RPX8260
2183 /* The EP8260 has the MDIO pins in a BCSR instead of on Port C
2184 * like most other boards.
2185 */
2186 #define MDIO_ADDR ((volatile u_char *)(RPX_CSR_ADDR + 4))
2187 #define MAKE_MDIO_OUTPUT *MDIO_ADDR &= ~BCSR4_MII_READ
2188 #define MAKE_MDIO_INPUT *MDIO_ADDR |= BCSR4_MII_READ | BCSR4_MII_MDIO
2189 #define OUT_MDIO(bit) \
2190 if (bit) \
2191 *MDIO_ADDR |= BCSR4_MII_MDIO; \
2192 else \
2193 *MDIO_ADDR &= ~BCSR4_MII_MDIO;
2194 #define IN_MDIO (*MDIO_ADDR & BCSR4_MII_MDIO)
2195 #define OUT_MDC(bit) \
2196 if (bit) \
2197 *MDIO_ADDR |= BCSR4_MII_MDC; \
2198 else \
2199 *MDIO_ADDR &= ~BCSR4_MII_MDC;
2200 #else /* ifdef CONFIG_RPX8260 */
2201 /* This is for the usual case where the MDIO pins are on Port C.
2202 */
2203 #define MDIO_ADDR (((volatile cpm2_map_t *)CPM_MAP_ADDR)->im_ioport)
2204 #define MAKE_MDIO_OUTPUT MDIO_ADDR.iop_pdirc |= fip->fc_mdio
2205 #define MAKE_MDIO_INPUT MDIO_ADDR.iop_pdirc &= ~fip->fc_mdio
2206 #define OUT_MDIO(bit) \
2207 if (bit) \
2208 MDIO_ADDR.iop_pdatc |= fip->fc_mdio; \
2209 else \
2210 MDIO_ADDR.iop_pdatc &= ~fip->fc_mdio;
2211 #define IN_MDIO ((MDIO_ADDR.iop_pdatc) & fip->fc_mdio)
2212 #define OUT_MDC(bit) \
2213 if (bit) \
2214 MDIO_ADDR.iop_pdatc |= fip->fc_mdck; \
2215 else \
2216 MDIO_ADDR.iop_pdatc &= ~fip->fc_mdck;
2217 #endif /* ifdef CONFIG_RPX8260 */
2218
2219 static uint
2220 mii_send_receive(fcc_info_t *fip, uint cmd)
2221 {
2222 uint retval;
2223 int read_op, i, off;
2224 const int us = 1;
2225
2226 read_op = ((cmd & 0xf0000000) == 0x60000000);
2227
2228 /* Write preamble
2229 */
2230 OUT_MDIO(1);
2231 MAKE_MDIO_OUTPUT;
2232 OUT_MDIO(1);
2233 for (i = 0; i < 32; i++)
2234 {
2235 udelay(us);
2236 OUT_MDC(1);
2237 udelay(us);
2238 OUT_MDC(0);
2239 }
2240
2241 /* Write data
2242 */
2243 for (i = 0, off = 31; i < (read_op ? 14 : 32); i++, --off)
2244 {
2245 OUT_MDIO((cmd >> off) & 0x00000001);
2246 udelay(us);
2247 OUT_MDC(1);
2248 udelay(us);
2249 OUT_MDC(0);
2250 }
2251
2252 retval = cmd;
2253
2254 if (read_op)
2255 {
2256 retval >>= 16;
2257
2258 MAKE_MDIO_INPUT;
2259 udelay(us);
2260 OUT_MDC(1);
2261 udelay(us);
2262 OUT_MDC(0);
2263
2264 for (i = 0; i < 16; i++)
2265 {
2266 udelay(us);
2267 OUT_MDC(1);
2268 udelay(us);
2269 retval <<= 1;
2270 if (IN_MDIO)
2271 retval++;
2272 OUT_MDC(0);
2273 }
2274 }
2275
2276 MAKE_MDIO_INPUT;
2277 udelay(us);
2278 OUT_MDC(1);
2279 udelay(us);
2280 OUT_MDC(0);
2281
2282 return retval;
2283 }
2284 #endif /* CONFIG_USE_MDIO */
2285
2286 static void
2287 fcc_stop(struct net_device *dev)
2288 {
2289 struct fcc_enet_private *fep= (struct fcc_enet_private *)(dev->priv);
2290 volatile fcc_t *fccp = fep->fccp;
2291 fcc_info_t *fip = fep->fip;
2292 volatile fcc_enet_t *ep = fep->ep;
2293 volatile cpm_cpm2_t *cp = cpmp;
2294 volatile cbd_t *bdp;
2295 int i;
2296
2297 if ((fccp->fcc_gfmr & (FCC_GFMR_ENR | FCC_GFMR_ENT)) == 0)
2298 return; /* already down */
2299
2300 fccp->fcc_fccm = 0;
2301
2302 /* issue the graceful stop tx command */
2303 while (cp->cp_cpcr & CPM_CR_FLG);
2304 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock,
2305 0x0c, CPM_CR_GRA_STOP_TX) | CPM_CR_FLG;
2306 while (cp->cp_cpcr & CPM_CR_FLG);
2307
2308 /* Disable transmit/receive */
2309 fccp->fcc_gfmr &= ~(FCC_GFMR_ENR | FCC_GFMR_ENT);
2310
2311 /* issue the restart tx command */
2312 fccp->fcc_fcce = FCC_ENET_GRA;
2313 while (cp->cp_cpcr & CPM_CR_FLG);
2314 cp->cp_cpcr = mk_cr_cmd(fip->fc_cpmpage, fip->fc_cpmblock,
2315 0x0c, CPM_CR_RESTART_TX) | CPM_CR_FLG;
2316 while (cp->cp_cpcr & CPM_CR_FLG);
2317
2318 /* free tx buffers */
2319 fep->skb_cur = fep->skb_dirty = 0;
2320 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2321 if (fep->tx_skbuff[i] != NULL) {
2322 dev_kfree_skb(fep->tx_skbuff[i]);
2323 fep->tx_skbuff[i] = NULL;
2324 }
2325 }
2326 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2327 fep->tx_free = TX_RING_SIZE;
2328 ep->fen_genfcc.fcc_tbptr = ep->fen_genfcc.fcc_tbase;
2329
2330 /* Initialize the tx buffer descriptors. */
2331 bdp = fep->tx_bd_base;
2332 for (i=0; i<TX_RING_SIZE; i++) {
2333 bdp->cbd_sc = 0;
2334 bdp->cbd_datlen = 0;
2335 bdp->cbd_bufaddr = 0;
2336 bdp++;
2337 }
2338 /* Set the last buffer to wrap. */
2339 bdp--;
2340 bdp->cbd_sc |= BD_SC_WRAP;
2341 }
2342
2343 static void
2344 fcc_restart(struct net_device *dev, int duplex)
2345 {
2346 struct fcc_enet_private *fep = (struct fcc_enet_private *)(dev->priv);
2347 volatile fcc_t *fccp = fep->fccp;
2348
2349 /* stop any transmissions in progress */
2350 fcc_stop(dev);
2351
2352 if (duplex)
2353 fccp->fcc_fpsmr |= FCC_PSMR_FDE | FCC_PSMR_LPB;
2354 else
2355 fccp->fcc_fpsmr &= ~(FCC_PSMR_FDE | FCC_PSMR_LPB);
2356
2357 /* Enable interrupts for transmit error, complete frame
2358 * received, and any transmit buffer we have also set the
2359 * interrupt flag.
2360 */
2361 fccp->fcc_fccm = (FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
2362
2363 /* Enable transmit/receive */
2364 fccp->fcc_gfmr |= FCC_GFMR_ENR | FCC_GFMR_ENT;
2365 }
2366
2367 static int
2368 fcc_enet_open(struct net_device *dev)
2369 {
2370 struct fcc_enet_private *fep = dev->priv;
2371
2372 #ifdef CONFIG_USE_MDIO
2373 fep->sequence_done = 0;
2374 fep->link = 0;
2375
2376 if (fep->phy) {
2377 fcc_restart(dev, 0); /* always start in half-duplex */
2378 mii_do_cmd(dev, fep->phy->ack_int);
2379 mii_do_cmd(dev, fep->phy->config);
2380 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2381 while(!fep->sequence_done)
2382 schedule();
2383
2384 mii_do_cmd(dev, fep->phy->startup);
2385 netif_start_queue(dev);
2386 return 0; /* Success */
2387 }
2388 return -ENODEV; /* No PHY we understand */
2389 #else
2390 fep->link = 1;
2391 fcc_restart(dev, 0); /* always start in half-duplex */
2392 netif_start_queue(dev);
2393 return 0; /* Always succeed */
2394 #endif /* CONFIG_USE_MDIO */
2395 }
2396
WRT350N Kernel Patches