| blob | 944c35c242785b94b66474dd7549fd6284e9635e |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <asm/processor.h>
23 #include <asm/page.h>
24 #include <asm/mmu.h>
25 #include <asm/cache.h>
26 #include <asm/pgtable.h>
27 #include <asm/cputable.h>
28 #include <asm/thread_info.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
32 /* Macro to make the code more readable. */
33 #ifdef CONFIG_8xx_CPU6
34 #define DO_8xx_CPU6(val, reg) \
35 li reg, val; \
36 stw reg, 12(r0); \
37 lwz reg, 12(r0);
38 #else
39 #define DO_8xx_CPU6(val, reg)
40 #endif
41 .text
42 .globl _stext
43 _stext:
44 .text
45 .globl _start
46 _start:
48 /* MPC8xx
49 * This port was done on an MBX board with an 860. Right now I only
50 * support an ELF compressed (zImage) boot from EPPC-Bug because the
51 * code there loads up some registers before calling us:
52 * r3: ptr to board info data
53 * r4: initrd_start or if no initrd then 0
54 * r5: initrd_end - unused if r4 is 0
55 * r6: Start of command line string
56 * r7: End of command line string
57 *
58 * I decided to use conditional compilation instead of checking PVR and
59 * adding more processor specific branches around code I don't need.
60 * Since this is an embedded processor, I also appreciate any memory
61 * savings I can get.
62 *
63 * The MPC8xx does not have any BATs, but it supports large page sizes.
64 * We first initialize the MMU to support 8M byte pages, then load one
65 * entry into each of the instruction and data TLBs to map the first
66 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
67 * the "internal" processor registers before MMU_init is called.
68 *
69 * The TLB code currently contains a major hack. Since I use the condition
70 * code register, I have to save and restore it. I am out of registers, so
71 * I just store it in memory location 0 (the TLB handlers are not reentrant).
72 * To avoid making any decisions, I need to use the "segment" valid bit
73 * in the first level table, but that would require many changes to the
74 * Linux page directory/table functions that I don't want to do right now.
75 *
76 * I used to use SPRG2 for a temporary register in the TLB handler, but it
77 * has since been put to other uses. I now use a hack to save a register
78 * and the CCR at memory location 0.....Someday I'll fix this.....
79 * -- Dan
80 */
81 .globl __start
82 __start:
83 mr r31,r3 /* save parameters */
84 mr r30,r4
85 mr r29,r5
86 mr r28,r6
87 mr r27,r7
89 /* We have to turn on the MMU right away so we get cache modes
90 * set correctly.
91 */
92 bl initial_mmu
94 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
95 * ready to work.
96 */
98 turn_on_mmu:
99 mfmsr r0
100 ori r0,r0,MSR_DR|MSR_IR
101 mtspr SPRN_SRR1,r0
102 lis r0,start_here@h
103 ori r0,r0,start_here@l
104 mtspr SPRN_SRR0,r0
105 SYNC
106 rfi /* enables MMU */
108 /*
109 * Exception entry code. This code runs with address translation
110 * turned off, i.e. using physical addresses.
111 * We assume sprg3 has the physical address of the current
112 * task's thread_struct.
113 */
114 #define EXCEPTION_PROLOG \
115 mtspr SPRN_SPRG0,r10; \
116 mtspr SPRN_SPRG1,r11; \
117 mfcr r10; \
118 EXCEPTION_PROLOG_1; \
119 EXCEPTION_PROLOG_2
121 #define EXCEPTION_PROLOG_1 \
122 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
123 andi. r11,r11,MSR_PR; \
124 tophys(r11,r1); /* use tophys(r1) if kernel */ \
125 beq 1f; \
126 mfspr r11,SPRN_SPRG3; \
127 lwz r11,THREAD_INFO-THREAD(r11); \
128 addi r11,r11,THREAD_SIZE; \
129 tophys(r11,r11); \
130 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
133 #define EXCEPTION_PROLOG_2 \
134 CLR_TOP32(r11); \
135 stw r10,_CCR(r11); /* save registers */ \
136 stw r12,GPR12(r11); \
137 stw r9,GPR9(r11); \
138 mfspr r10,SPRN_SPRG0; \
139 stw r10,GPR10(r11); \
140 mfspr r12,SPRN_SPRG1; \
141 stw r12,GPR11(r11); \
142 mflr r10; \
143 stw r10,_LINK(r11); \
144 mfspr r12,SPRN_SRR0; \
145 mfspr r9,SPRN_SRR1; \
146 stw r1,GPR1(r11); \
147 stw r1,0(r11); \
148 tovirt(r1,r11); /* set new kernel sp */ \
149 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
150 MTMSRD(r10); /* (except for mach check in rtas) */ \
151 stw r0,GPR0(r11); \
152 SAVE_4GPRS(3, r11); \
153 SAVE_2GPRS(7, r11)
155 /*
156 * Note: code which follows this uses cr0.eq (set if from kernel),
157 * r11, r12 (SRR0), and r9 (SRR1).
158 *
159 * Note2: once we have set r1 we are in a position to take exceptions
160 * again, and we could thus set MSR:RI at that point.
161 */
163 /*
164 * Exception vectors.
165 */
166 #define EXCEPTION(n, label, hdlr, xfer) \
167 . = n; \
168 label: \
169 EXCEPTION_PROLOG; \
170 addi r3,r1,STACK_FRAME_OVERHEAD; \
171 xfer(n, hdlr)
173 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
174 li r10,trap; \
175 stw r10,TRAP(r11); \
176 li r10,MSR_KERNEL; \
177 copyee(r10, r9); \
178 bl tfer; \
179 i##n: \
180 .long hdlr; \
181 .long ret
183 #define COPY_EE(d, s) rlwimi d,s,0,16,16
184 #define NOCOPY(d, s)
186 #define EXC_XFER_STD(n, hdlr) \
187 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
188 ret_from_except_full)
190 #define EXC_XFER_LITE(n, hdlr) \
191 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
192 ret_from_except)
194 #define EXC_XFER_EE(n, hdlr) \
195 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
196 ret_from_except_full)
198 #define EXC_XFER_EE_LITE(n, hdlr) \
199 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
200 ret_from_except)
202 /* System reset */
203 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
205 /* Machine check */
206 . = 0x200
207 MachineCheck:
208 EXCEPTION_PROLOG
209 mfspr r4,SPRN_DAR
210 stw r4,_DAR(r11)
211 mfspr r5,SPRN_DSISR
212 stw r5,_DSISR(r11)
213 addi r3,r1,STACK_FRAME_OVERHEAD
214 EXC_XFER_STD(0x200, machine_check_exception)
216 /* Data access exception.
217 * This is "never generated" by the MPC8xx. We jump to it for other
218 * translation errors.
219 */
220 . = 0x300
221 DataAccess:
222 EXCEPTION_PROLOG
223 mfspr r10,SPRN_DSISR
224 stw r10,_DSISR(r11)
225 mr r5,r10
226 mfspr r4,SPRN_DAR
227 EXC_XFER_EE_LITE(0x300, handle_page_fault)
229 /* Instruction access exception.
230 * This is "never generated" by the MPC8xx. We jump to it for other
231 * translation errors.
232 */
233 . = 0x400
234 InstructionAccess:
235 EXCEPTION_PROLOG
236 mr r4,r12
237 mr r5,r9
238 EXC_XFER_EE_LITE(0x400, handle_page_fault)
240 /* External interrupt */
241 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
243 /* Alignment exception */
244 . = 0x600
245 Alignment:
246 EXCEPTION_PROLOG
247 mfspr r4,SPRN_DAR
248 stw r4,_DAR(r11)
249 mfspr r5,SPRN_DSISR
250 stw r5,_DSISR(r11)
251 addi r3,r1,STACK_FRAME_OVERHEAD
252 EXC_XFER_EE(0x600, alignment_exception)
254 /* Program check exception */
255 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
257 /* No FPU on MPC8xx. This exception is not supposed to happen.
258 */
259 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
261 /* Decrementer */
262 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
264 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
265 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
267 /* System call */
268 . = 0xc00
269 SystemCall:
270 EXCEPTION_PROLOG
271 EXC_XFER_EE_LITE(0xc00, DoSyscall)
273 /* Single step - not used on 601 */
274 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
275 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
276 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
278 /* On the MPC8xx, this is a software emulation interrupt. It occurs
279 * for all unimplemented and illegal instructions.
280 */
281 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
283 . = 0x1100
284 /*
285 * For the MPC8xx, this is a software tablewalk to load the instruction
286 * TLB. It is modelled after the example in the Motorola manual. The task
287 * switch loads the M_TWB register with the pointer to the first level table.
288 * If we discover there is no second level table (value is zero) or if there
289 * is an invalid pte, we load that into the TLB, which causes another fault
290 * into the TLB Error interrupt where we can handle such problems.
291 * We have to use the MD_xxx registers for the tablewalk because the
292 * equivalent MI_xxx registers only perform the attribute functions.
293 */
294 InstructionTLBMiss:
295 #ifdef CONFIG_8xx_CPU6
296 stw r3, 8(r0)
297 #endif
298 DO_8xx_CPU6(0x3f80, r3)
299 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
300 mfcr r10
301 stw r10, 0(r0)
302 stw r11, 4(r0)
303 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
304 DO_8xx_CPU6(0x3780, r3)
305 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
306 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
308 /* If we are faulting a kernel address, we have to use the
309 * kernel page tables.
310 */
311 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
312 beq 3f
313 lis r11, swapper_pg_dir@h
314 ori r11, r11, swapper_pg_dir@l
315 rlwimi r10, r11, 0, 2, 19
316 3:
317 lwz r11, 0(r10) /* Get the level 1 entry */
318 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
319 beq 2f /* If zero, don't try to find a pte */
321 /* We have a pte table, so load the MI_TWC with the attributes
322 * for this "segment."
323 */
324 ori r11,r11,1 /* Set valid bit */
325 DO_8xx_CPU6(0x2b80, r3)
326 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
327 DO_8xx_CPU6(0x3b80, r3)
328 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
329 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
330 lwz r10, 0(r11) /* Get the pte */
332 ori r10, r10, _PAGE_ACCESSED
333 stw r10, 0(r11)
335 /* The Linux PTE won't go exactly into the MMU TLB.
336 * Software indicator bits 21, 22 and 28 must be clear.
337 * Software indicator bits 24, 25, 26, and 27 must be
338 * set. All other Linux PTE bits control the behavior
339 * of the MMU.
340 */
341 2: li r11, 0x00f0
342 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
343 DO_8xx_CPU6(0x2d80, r3)
344 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
346 mfspr r10, SPRN_M_TW /* Restore registers */
347 lwz r11, 0(r0)
348 mtcr r11
349 lwz r11, 4(r0)
350 #ifdef CONFIG_8xx_CPU6
351 lwz r3, 8(r0)
352 #endif
353 rfi
355 . = 0x1200
356 DataStoreTLBMiss:
357 stw r3, 8(r0)
358 DO_8xx_CPU6(0x3f80, r3)
359 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
360 mfcr r10
361 stw r10, 0(r0)
362 stw r11, 4(r0)
363 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
365 /* If we are faulting a kernel address, we have to use the
366 * kernel page tables.
367 */
368 andi. r11, r10, 0x0800
369 beq 3f
370 lis r11, swapper_pg_dir@h
371 ori r11, r11, swapper_pg_dir@l
372 rlwimi r10, r11, 0, 2, 19
373 stw r12, 16(r0)
374 b LoadLargeDTLB
375 3:
376 lwz r11, 0(r10) /* Get the level 1 entry */
377 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
378 beq 2f /* If zero, don't try to find a pte */
380 /* We have a pte table, so load fetch the pte from the table.
381 */
382 ori r11, r11, 1 /* Set valid bit in physical L2 page */
383 DO_8xx_CPU6(0x3b80, r3)
384 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
385 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
386 lwz r10, 0(r10) /* Get the pte */
388 /* Insert the Guarded flag into the TWC from the Linux PTE.
389 * It is bit 27 of both the Linux PTE and the TWC (at least
390 * I got that right :-). It will be better when we can put
391 * this into the Linux pgd/pmd and load it in the operation
392 * above.
393 */
394 rlwimi r11, r10, 0, 27, 27
395 DO_8xx_CPU6(0x3b80, r3)
396 mtspr SPRN_MD_TWC, r11
398 mfspr r11, SPRN_MD_TWC /* get the pte address again */
399 ori r10, r10, _PAGE_ACCESSED
400 stw r10, 0(r11)
402 /* The Linux PTE won't go exactly into the MMU TLB.
403 * Software indicator bits 21, 22 and 28 must be clear.
404 * Software indicator bits 24, 25, 26, and 27 must be
405 * set. All other Linux PTE bits control the behavior
406 * of the MMU.
407 */
408 2: li r11, 0x00f0
409 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
410 DO_8xx_CPU6(0x3d80, r3)
411 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
413 mfspr r10, SPRN_M_TW /* Restore registers */
414 lwz r11, 0(r0)
415 mtcr r11
416 lwz r11, 4(r0)
417 lwz r3, 8(r0)
418 rfi
420 /* This is an instruction TLB error on the MPC8xx. This could be due
421 * to many reasons, such as executing guarded memory or illegal instruction
422 * addresses. There is nothing to do but handle a big time error fault.
423 */
424 . = 0x1300
425 InstructionTLBError:
426 b InstructionAccess
428 LoadLargeDTLB:
429 li r12, 0
430 lwz r11, 0(r10) /* Get the level 1 entry */
431 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
432 beq 3f /* If zero, don't try to find a pte */
434 /* We have a pte table, so load fetch the pte from the table.
435 */
436 ori r11, r11, 1 /* Set valid bit in physical L2 page */
437 DO_8xx_CPU6(0x3b80, r3)
438 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
439 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
440 lwz r10, 0(r10) /* Get the pte */
442 /* Insert the Guarded flag into the TWC from the Linux PTE.
443 * It is bit 27 of both the Linux PTE and the TWC (at least
444 * I got that right :-). It will be better when we can put
445 * this into the Linux pgd/pmd and load it in the operation
446 * above.
447 */
448 rlwimi r11, r10, 0, 27, 27
450 rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */
451 mfspr r3, SPRN_MD_EPN
452 rlwinm r3, r3, 0, 0, 9 /* extract virtual address */
453 tophys(r3, r3)
454 cmpw r3, r12 /* only use 8M page if it is a direct
455 kernel mapping */
456 bne 1f
457 ori r11, r11, MD_PS8MEG
458 li r12, 1
459 b 2f
460 1:
461 li r12, 0 /* can't use 8MB TLB, so zero r12. */
462 2:
463 DO_8xx_CPU6(0x3b80, r3)
464 mtspr SPRN_MD_TWC, r11
466 /* The Linux PTE won't go exactly into the MMU TLB.
467 * Software indicator bits 21, 22 and 28 must be clear.
468 * Software indicator bits 24, 25, 26, and 27 must be
469 * set. All other Linux PTE bits control the behavior
470 * of the MMU.
471 */
472 3: li r11, 0x00f0
473 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
474 cmpwi r12, 1
475 bne 4f
476 ori r10, r10, 0x8
478 mfspr r12, SPRN_MD_EPN
479 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
480 ori r3, r3, 0x0fff
481 and r12, r3, r12
482 DO_8xx_CPU6(0x3780, r3)
483 mtspr SPRN_MD_EPN, r12
485 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
486 ori r3, r3, 0x0fff
487 and r10, r3, r10
488 4:
489 DO_8xx_CPU6(0x3d80, r3)
490 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
492 mfspr r10, SPRN_M_TW /* Restore registers */
493 lwz r11, 0(r0)
494 mtcr r11
495 lwz r11, 4(r0)
497 lwz r12, 16(r0)
498 #ifdef CONFIG_8xx_CPU6
499 lwz r3, 8(r0)
500 #endif
501 rfi
503 /* This is the data TLB error on the MPC8xx. This could be due to
504 * many reasons, including a dirty update to a pte. We can catch that
505 * one here, but anything else is an error. First, we track down the
506 * Linux pte. If it is valid, write access is allowed, but the
507 * page dirty bit is not set, we will set it and reload the TLB. For
508 * any other case, we bail out to a higher level function that can
509 * handle it.
510 */
511 . = 0x1400
512 DataTLBError:
513 #ifdef CONFIG_8xx_CPU6
514 stw r3, 8(r0)
515 #endif
516 DO_8xx_CPU6(0x3f80, r3)
517 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
518 mfcr r10
519 stw r10, 0(r0)
520 stw r11, 4(r0)
522 /* First, make sure this was a store operation.
523 */
524 mfspr r10, SPRN_DSISR
525 andis. r11, r10, 0x0200 /* If set, indicates store op */
526 beq 2f
528 /* The EA of a data TLB miss is automatically stored in the MD_EPN
529 * register. The EA of a data TLB error is automatically stored in
530 * the DAR, but not the MD_EPN register. We must copy the 20 most
531 * significant bits of the EA from the DAR to MD_EPN before we
532 * start walking the page tables. We also need to copy the CASID
533 * value from the M_CASID register.
534 * Addendum: The EA of a data TLB error is _supposed_ to be stored
535 * in DAR, but it seems that this doesn't happen in some cases, such
536 * as when the error is due to a dcbi instruction to a page with a
537 * TLB that doesn't have the changed bit set. In such cases, there
538 * does not appear to be any way to recover the EA of the error
539 * since it is neither in DAR nor MD_EPN. As a workaround, the
540 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
541 * are initialized in mapin_ram(). This will avoid the problem,
542 * assuming we only use the dcbi instruction on kernel addresses.
543 */
544 mfspr r10, SPRN_DAR
545 rlwinm r11, r10, 0, 0, 19
546 ori r11, r11, MD_EVALID
547 mfspr r10, SPRN_M_CASID
548 rlwimi r11, r10, 0, 28, 31
549 DO_8xx_CPU6(0x3780, r3)
550 mtspr SPRN_MD_EPN, r11
552 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
554 /* If we are faulting a kernel address, we have to use the
555 * kernel page tables.
556 */
557 andi. r11, r10, 0x0800
558 beq 3f
559 lis r11, swapper_pg_dir@h
560 ori r11, r11, swapper_pg_dir@l
561 rlwimi r10, r11, 0, 2, 19
562 3:
563 lwz r11, 0(r10) /* Get the level 1 entry */
564 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
565 beq 2f /* If zero, bail */
567 /* We have a pte table, so fetch the pte from the table.
568 */
569 ori r11, r11, 1 /* Set valid bit in physical L2 page */
570 DO_8xx_CPU6(0x3b80, r3)
571 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
572 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
573 lwz r10, 0(r11) /* Get the pte */
575 andi. r11, r10, _PAGE_RW /* Is it writeable? */
576 beq 2f /* Bail out if not */
578 /* Update 'changed', among others.
579 */
580 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
581 mfspr r11, SPRN_MD_TWC /* Get pte address again */
582 stw r10, 0(r11) /* and update pte in table */
584 /* The Linux PTE won't go exactly into the MMU TLB.
585 * Software indicator bits 21, 22 and 28 must be clear.
586 * Software indicator bits 24, 25, 26, and 27 must be
587 * set. All other Linux PTE bits control the behavior
588 * of the MMU.
589 */
590 li r11, 0x00f0
591 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
592 DO_8xx_CPU6(0x3d80, r3)
593 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
595 mfspr r10, SPRN_M_TW /* Restore registers */
596 lwz r11, 0(r0)
597 mtcr r11
598 lwz r11, 4(r0)
599 #ifdef CONFIG_8xx_CPU6
600 lwz r3, 8(r0)
601 #endif
602 rfi
603 2:
604 mfspr r10, SPRN_M_TW /* Restore registers */
605 lwz r11, 0(r0)
606 mtcr r11
607 lwz r11, 4(r0)
608 #ifdef CONFIG_8xx_CPU6
609 lwz r3, 8(r0)
610 #endif
611 b DataAccess
613 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
614 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
615 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
616 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
617 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
618 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
619 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
621 /* On the MPC8xx, these next four traps are used for development
622 * support of breakpoints and such. Someday I will get around to
623 * using them.
624 */
625 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
626 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
627 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
628 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
630 . = 0x2000
632 .globl giveup_fpu
633 giveup_fpu:
634 blr
636 /*
637 * This is where the main kernel code starts.
638 */
639 start_here:
640 /* ptr to current */
641 lis r2,init_task@h
642 ori r2,r2,init_task@l
644 /* ptr to phys current thread */
645 tophys(r4,r2)
646 addi r4,r4,THREAD /* init task's THREAD */
647 mtspr SPRN_SPRG3,r4
648 li r3,0
649 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
651 /* stack */
652 lis r1,init_thread_union@ha
653 addi r1,r1,init_thread_union@l
654 li r0,0
655 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
657 bl early_init /* We have to do this with MMU on */
659 /*
660 * Decide what sort of machine this is and initialize the MMU.
661 */
662 mr r3,r31
663 mr r4,r30
664 mr r5,r29
665 mr r6,r28
666 mr r7,r27
667 bl machine_init
668 bl MMU_init
670 /*
671 * Go back to running unmapped so we can load up new values
672 * and change to using our exception vectors.
673 * On the 8xx, all we have to do is invalidate the TLB to clear
674 * the old 8M byte TLB mappings and load the page table base register.
675 */
676 /* The right way to do this would be to track it down through
677 * init's THREAD like the context switch code does, but this is
678 * easier......until someone changes init's static structures.
679 */
680 lis r6, swapper_pg_dir@h
681 ori r6, r6, swapper_pg_dir@l
682 tophys(r6,r6)
683 #ifdef CONFIG_8xx_CPU6
684 lis r4, cpu6_errata_word@h
685 ori r4, r4, cpu6_errata_word@l
686 li r3, 0x3980
687 stw r3, 12(r4)
688 lwz r3, 12(r4)
689 #endif
690 mtspr SPRN_M_TWB, r6
691 lis r4,2f@h
692 ori r4,r4,2f@l
693 tophys(r4,r4)
694 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
695 mtspr SPRN_SRR0,r4
696 mtspr SPRN_SRR1,r3
697 rfi
698 /* Load up the kernel context */
699 2:
700 SYNC /* Force all PTE updates to finish */
701 tlbia /* Clear all TLB entries */
702 sync /* wait for tlbia/tlbie to finish */
703 TLBSYNC /* ... on all CPUs */
705 /* set up the PTE pointers for the Abatron bdiGDB.
706 */
707 tovirt(r6,r6)
708 lis r5, abatron_pteptrs@h
709 ori r5, r5, abatron_pteptrs@l
710 stw r5, 0xf0(r0) /* Must match your Abatron config file */
711 tophys(r5,r5)
712 stw r6, 0(r5)
714 /* Now turn on the MMU for real! */
715 li r4,MSR_KERNEL
716 lis r3,start_kernel@h
717 ori r3,r3,start_kernel@l
718 mtspr SPRN_SRR0,r3
719 mtspr SPRN_SRR1,r4
720 rfi /* enable MMU and jump to start_kernel */
722 /* Set up the initial MMU state so we can do the first level of
723 * kernel initialization. This maps the first 8 MBytes of memory 1:1
724 * virtual to physical. Also, set the cache mode since that is defined
725 * by TLB entries and perform any additional mapping (like of the IMMR).
726 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
727 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
728 * these mappings is mapped by page tables.
729 */
730 initial_mmu:
731 tlbia /* Invalidate all TLB entries */
732 #ifdef CONFIG_PIN_TLB
733 lis r8, MI_RSV4I@h
734 ori r8, r8, 0x1c00
735 #else
736 li r8, 0
737 #endif
738 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
740 #ifdef CONFIG_PIN_TLB
741 lis r10, (MD_RSV4I | MD_RESETVAL)@h
742 ori r10, r10, 0x1c00
743 mr r8, r10
744 #else
745 lis r10, MD_RESETVAL@h
746 #endif
747 #ifndef CONFIG_8xx_COPYBACK
748 oris r10, r10, MD_WTDEF@h
749 #endif
750 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
752 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
753 * we can load the instruction and data TLB registers with the
754 * same values.
755 */
756 lis r8, KERNELBASE@h /* Create vaddr for TLB */
757 ori r8, r8, MI_EVALID /* Mark it valid */
758 mtspr SPRN_MI_EPN, r8
759 mtspr SPRN_MD_EPN, r8
760 li r8, MI_PS8MEG /* Set 8M byte page */
761 ori r8, r8, MI_SVALID /* Make it valid */
762 mtspr SPRN_MI_TWC, r8
763 mtspr SPRN_MD_TWC, r8
764 li r8, MI_BOOTINIT /* Create RPN for address 0 */
765 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
766 mtspr SPRN_MD_RPN, r8
767 lis r8, MI_Kp@h /* Set the protection mode */
768 mtspr SPRN_MI_AP, r8
769 mtspr SPRN_MD_AP, r8
771 /* Map another 8 MByte at the IMMR to get the processor
772 * internal registers (among other things).
773 */
774 #ifdef CONFIG_PIN_TLB
775 addi r10, r10, 0x0100
776 mtspr SPRN_MD_CTR, r10
777 #endif
778 mfspr r9, 638 /* Get current IMMR */
779 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
781 mr r8, r9 /* Create vaddr for TLB */
782 ori r8, r8, MD_EVALID /* Mark it valid */
783 mtspr SPRN_MD_EPN, r8
784 li r8, MD_PS8MEG /* Set 8M byte page */
785 ori r8, r8, MD_SVALID /* Make it valid */
786 mtspr SPRN_MD_TWC, r8
787 mr r8, r9 /* Create paddr for TLB */
788 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
789 mtspr SPRN_MD_RPN, r8
791 #ifdef CONFIG_PIN_TLB
792 /* Map two more 8M kernel data pages.
793 */
794 addi r10, r10, 0x0100
795 mtspr SPRN_MD_CTR, r10
797 lis r8, KERNELBASE@h /* Create vaddr for TLB */
798 addis r8, r8, 0x0080 /* Add 8M */
799 ori r8, r8, MI_EVALID /* Mark it valid */
800 mtspr SPRN_MD_EPN, r8
801 li r9, MI_PS8MEG /* Set 8M byte page */
802 ori r9, r9, MI_SVALID /* Make it valid */
803 mtspr SPRN_MD_TWC, r9
804 li r11, MI_BOOTINIT /* Create RPN for address 0 */
805 addis r11, r11, 0x0080 /* Add 8M */
806 mtspr SPRN_MD_RPN, r11
808 addi r10, r10, 0x0100
809 mtspr SPRN_MD_CTR, r10
811 addis r8, r8, 0x0080 /* Add 8M */
812 mtspr SPRN_MD_EPN, r8
813 mtspr SPRN_MD_TWC, r9
814 addis r11, r11, 0x0080 /* Add 8M */
815 mtspr SPRN_MD_RPN, r11
816 #endif
818 /* Since the cache is enabled according to the information we
819 * just loaded into the TLB, invalidate and enable the caches here.
820 * We should probably check/set other modes....later.
821 */
822 lis r8, IDC_INVALL@h
823 mtspr SPRN_IC_CST, r8
824 mtspr SPRN_DC_CST, r8
825 lis r8, IDC_ENABLE@h
826 mtspr SPRN_IC_CST, r8
827 #ifdef CONFIG_8xx_COPYBACK
828 mtspr SPRN_DC_CST, r8
829 #else
830 /* For a debug option, I left this here to easily enable
831 * the write through cache mode
832 */
833 lis r8, DC_SFWT@h
834 mtspr SPRN_DC_CST, r8
835 lis r8, IDC_ENABLE@h
836 mtspr SPRN_DC_CST, r8
837 #endif
838 blr
841 /*
842 * Set up to use a given MMU context.
843 * r3 is context number, r4 is PGD pointer.
844 *
845 * We place the physical address of the new task page directory loaded
846 * into the MMU base register, and set the ASID compare register with
847 * the new "context."
848 */
849 _GLOBAL(set_context)
851 #ifdef CONFIG_BDI_SWITCH
852 /* Context switch the PTE pointer for the Abatron BDI2000.
853 * The PGDIR is passed as second argument.
854 */
855 lis r5, KERNELBASE@h
856 lwz r5, 0xf0(r5)
857 stw r4, 0x4(r5)
858 #endif
860 #ifdef CONFIG_8xx_CPU6
861 lis r6, cpu6_errata_word@h
862 ori r6, r6, cpu6_errata_word@l
863 tophys (r4, r4)
864 li r7, 0x3980
865 stw r7, 12(r6)
866 lwz r7, 12(r6)
867 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
868 li r7, 0x3380
869 stw r7, 12(r6)
870 lwz r7, 12(r6)
871 mtspr SPRN_M_CASID, r3 /* Update context */
872 #else
873 mtspr SPRN_M_CASID,r3 /* Update context */
874 tophys (r4, r4)
875 mtspr SPRN_M_TWB, r4 /* and pgd */
876 #endif
877 SYNC
878 blr
880 #ifdef CONFIG_8xx_CPU6
881 /* It's here because it is unique to the 8xx.
882 * It is important we get called with interrupts disabled. I used to
883 * do that, but it appears that all code that calls this already had
884 * interrupt disabled.
885 */
886 .globl set_dec_cpu6
887 set_dec_cpu6:
888 lis r7, cpu6_errata_word@h
889 ori r7, r7, cpu6_errata_word@l
890 li r4, 0x2c00
891 stw r4, 8(r7)
892 lwz r4, 8(r7)
893 mtspr 22, r3 /* Update Decrementer */
894 SYNC
895 blr
896 #endif
898 /*
899 * We put a few things here that have to be page-aligned.
900 * This stuff goes at the beginning of the data segment,
901 * which is page-aligned.
902 */
903 .data
904 .globl sdata
905 sdata:
906 .globl empty_zero_page
907 empty_zero_page:
908 .space 4096
910 .globl swapper_pg_dir
911 swapper_pg_dir:
912 .space 4096
914 /*
915 * This space gets a copy of optional info passed to us by the bootstrap
916 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
917 */
918 .globl cmd_line
919 cmd_line:
920 .space 512
922 /* Room for two PTE table poiners, usually the kernel and current user
923 * pointer to their respective root page table (pgdir).
924 */
925 abatron_pteptrs:
926 .space 8
928 #ifdef CONFIG_8xx_CPU6
929 .globl cpu6_errata_word
930 cpu6_errata_word:
931 .space 16
932 #endif