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[PATCH] ocfs2: zero_user_page conversion
[wrt350n-kernel.git] / arch / sparc64 / kernel / pci.c
blob81f4a5ea05f7ab948e307daa1853f53d1b554fbd
1 /* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21
22 #include <asm/uaccess.h>
23 #include <asm/pgtable.h>
24 #include <asm/irq.h>
25 #include <asm/ebus.h>
26 #include <asm/isa.h>
27 #include <asm/prom.h>
28 #include <asm/apb.h>
29
30 #include "pci_impl.h"
31
32 unsigned long pci_memspace_mask = 0xffffffffUL;
33
34 #ifndef CONFIG_PCI
35 /* A "nop" PCI implementation. */
36 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
38 unsigned char *buf)
39 {
40 return 0;
41 }
42 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
43 unsigned long off, unsigned long len,
44 unsigned char *buf)
45 {
46 return 0;
47 }
48 #else
49
50 /* List of all PCI controllers found in the system. */
51 struct pci_pbm_info *pci_pbm_root = NULL;
52
53 /* Each PBM found gets a unique index. */
54 int pci_num_pbms = 0;
55
56 volatile int pci_poke_in_progress;
57 volatile int pci_poke_cpu = -1;
58 volatile int pci_poke_faulted;
59
60 static DEFINE_SPINLOCK(pci_poke_lock);
61
62 void pci_config_read8(u8 *addr, u8 *ret)
63 {
64 unsigned long flags;
65 u8 byte;
66
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
70 pci_poke_faulted = 0;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
73 "membar #Sync"
74 : "=r" (byte)
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
76 : "memory");
77 pci_poke_in_progress = 0;
78 pci_poke_cpu = -1;
79 if (!pci_poke_faulted)
80 *ret = byte;
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
82 }
83
84 void pci_config_read16(u16 *addr, u16 *ret)
85 {
86 unsigned long flags;
87 u16 word;
88
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
92 pci_poke_faulted = 0;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
95 "membar #Sync"
96 : "=r" (word)
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
98 : "memory");
99 pci_poke_in_progress = 0;
100 pci_poke_cpu = -1;
101 if (!pci_poke_faulted)
102 *ret = word;
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
104 }
105
106 void pci_config_read32(u32 *addr, u32 *ret)
107 {
108 unsigned long flags;
109 u32 dword;
110
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
117 "membar #Sync"
118 : "=r" (dword)
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
120 : "memory");
121 pci_poke_in_progress = 0;
122 pci_poke_cpu = -1;
123 if (!pci_poke_faulted)
124 *ret = dword;
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
126 }
127
128 void pci_config_write8(u8 *addr, u8 val)
129 {
130 unsigned long flags;
131
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
138 "membar #Sync"
139 : /* no outputs */
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
141 : "memory");
142 pci_poke_in_progress = 0;
143 pci_poke_cpu = -1;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
145 }
146
147 void pci_config_write16(u16 *addr, u16 val)
148 {
149 unsigned long flags;
150
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
157 "membar #Sync"
158 : /* no outputs */
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
160 : "memory");
161 pci_poke_in_progress = 0;
162 pci_poke_cpu = -1;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
164 }
165
166 void pci_config_write32(u32 *addr, u32 val)
167 {
168 unsigned long flags;
169
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
176 "membar #Sync"
177 : /* no outputs */
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
179 : "memory");
180 pci_poke_in_progress = 0;
181 pci_poke_cpu = -1;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
183 }
184
185 /* Probe for all PCI controllers in the system. */
186 extern void sabre_init(struct device_node *, const char *);
187 extern void psycho_init(struct device_node *, const char *);
188 extern void schizo_init(struct device_node *, const char *);
189 extern void schizo_plus_init(struct device_node *, const char *);
190 extern void tomatillo_init(struct device_node *, const char *);
191 extern void sun4v_pci_init(struct device_node *, const char *);
192 extern void fire_pci_init(struct device_node *, const char *);
193
194 static struct {
195 char *model_name;
196 void (*init)(struct device_node *, const char *);
197 } pci_controller_table[] __initdata = {
198 { "SUNW,sabre", sabre_init },
199 { "pci108e,a000", sabre_init },
200 { "pci108e,a001", sabre_init },
201 { "SUNW,psycho", psycho_init },
202 { "pci108e,8000", psycho_init },
203 { "SUNW,schizo", schizo_init },
204 { "pci108e,8001", schizo_init },
205 { "SUNW,schizo+", schizo_plus_init },
206 { "pci108e,8002", schizo_plus_init },
207 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init },
209 { "SUNW,sun4v-pci", sun4v_pci_init },
210 { "pciex108e,80f0", fire_pci_init },
211 };
212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
213 sizeof(pci_controller_table[0]))
214
215 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
216 {
217 int i;
218
219 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
220 if (!strncmp(model_name,
221 pci_controller_table[i].model_name,
222 namelen)) {
223 pci_controller_table[i].init(dp, model_name);
224 return 1;
225 }
226 }
227
228 return 0;
229 }
230
231 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
232 {
233 int i;
234
235 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
236 if (!strncmp(model_name,
237 pci_controller_table[i].model_name,
238 namelen)) {
239 return 1;
240 }
241 }
242 return 0;
243 }
244
245 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
246 {
247 struct device_node *dp;
248 int count = 0;
249
250 for_each_node_by_name(dp, "pci") {
251 struct property *prop;
252 int len;
253
254 prop = of_find_property(dp, "model", &len);
255 if (!prop)
256 prop = of_find_property(dp, "compatible", &len);
257
258 if (prop) {
259 const char *model = prop->value;
260 int item_len = 0;
261
262 /* Our value may be a multi-valued string in the
263 * case of some compatible properties. For sanity,
264 * only try the first one.
265 */
266 while (model[item_len] && len) {
267 len--;
268 item_len++;
269 }
270
271 if (handler(model, item_len, dp))
272 count++;
273 }
274 }
275
276 return count;
277 }
278
279
280 /* Is there some PCI controller in the system? */
281 int __init pcic_present(void)
282 {
283 return pci_controller_scan(pci_is_controller);
284 }
285
286 const struct pci_iommu_ops *pci_iommu_ops;
287 EXPORT_SYMBOL(pci_iommu_ops);
288
289 extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
290 pci_sun4v_iommu_ops;
291
292 /* Find each controller in the system, attach and initialize
293 * software state structure for each and link into the
294 * pci_pbm_root. Setup the controller enough such
295 * that bus scanning can be done.
296 */
297 static void __init pci_controller_probe(void)
298 {
299 if (tlb_type == hypervisor)
300 pci_iommu_ops = &pci_sun4v_iommu_ops;
301 else
302 pci_iommu_ops = &pci_sun4u_iommu_ops;
303
304 printk("PCI: Probing for controllers.\n");
305
306 pci_controller_scan(pci_controller_init);
307 }
308
309 static int ofpci_verbose;
310
311 static int __init ofpci_debug(char *str)
312 {
313 int val = 0;
314
315 get_option(&str, &val);
316 if (val)
317 ofpci_verbose = 1;
318 return 1;
319 }
320
321 __setup("ofpci_debug=", ofpci_debug);
322
323 static unsigned long pci_parse_of_flags(u32 addr0)
324 {
325 unsigned long flags = 0;
326
327 if (addr0 & 0x02000000) {
328 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
329 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
330 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
331 if (addr0 & 0x40000000)
332 flags |= IORESOURCE_PREFETCH
333 | PCI_BASE_ADDRESS_MEM_PREFETCH;
334 } else if (addr0 & 0x01000000)
335 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
336 return flags;
337 }
338
339 /* The of_device layer has translated all of the assigned-address properties
340 * into physical address resources, we only have to figure out the register
341 * mapping.
342 */
343 static void pci_parse_of_addrs(struct of_device *op,
344 struct device_node *node,
345 struct pci_dev *dev)
346 {
347 struct resource *op_res;
348 const u32 *addrs;
349 int proplen;
350
351 addrs = of_get_property(node, "assigned-addresses", &proplen);
352 if (!addrs)
353 return;
354 if (ofpci_verbose)
355 printk(" parse addresses (%d bytes) @ %p\n",
356 proplen, addrs);
357 op_res = &op->resource[0];
358 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
359 struct resource *res;
360 unsigned long flags;
361 int i;
362
363 flags = pci_parse_of_flags(addrs[0]);
364 if (!flags)
365 continue;
366 i = addrs[0] & 0xff;
367 if (ofpci_verbose)
368 printk(" start: %lx, end: %lx, i: %x\n",
369 op_res->start, op_res->end, i);
370
371 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
372 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
373 } else if (i == dev->rom_base_reg) {
374 res = &dev->resource[PCI_ROM_RESOURCE];
375 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
376 } else {
377 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
378 continue;
379 }
380 res->start = op_res->start;
381 res->end = op_res->end;
382 res->flags = flags;
383 res->name = pci_name(dev);
384 }
385 }
386
387 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
388 struct device_node *node,
389 struct pci_bus *bus, int devfn,
390 int host_controller)
391 {
392 struct dev_archdata *sd;
393 struct pci_dev *dev;
394 const char *type;
395 u32 class;
396
397 dev = alloc_pci_dev();
398 if (!dev)
399 return NULL;
400
401 sd = &dev->dev.archdata;
402 sd->iommu = pbm->iommu;
403 sd->stc = &pbm->stc;
404 sd->host_controller = pbm;
405 sd->prom_node = node;
406 sd->op = of_find_device_by_node(node);
407 sd->msi_num = 0xffffffff;
408
409 type = of_get_property(node, "device_type", NULL);
410 if (type == NULL)
411 type = "";
412
413 if (ofpci_verbose)
414 printk(" create device, devfn: %x, type: %s\n",
415 devfn, type);
416
417 dev->bus = bus;
418 dev->sysdata = node;
419 dev->dev.parent = bus->bridge;
420 dev->dev.bus = &pci_bus_type;
421 dev->devfn = devfn;
422 dev->multifunction = 0; /* maybe a lie? */
423
424 if (host_controller) {
425 dev->vendor = 0x108e;
426 dev->device = 0x8000;
427 dev->subsystem_vendor = 0x0000;
428 dev->subsystem_device = 0x0000;
429 dev->cfg_size = 256;
430 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
431 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
432 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
433 } else {
434 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
435 dev->device = of_getintprop_default(node, "device-id", 0xffff);
436 dev->subsystem_vendor =
437 of_getintprop_default(node, "subsystem-vendor-id", 0);
438 dev->subsystem_device =
439 of_getintprop_default(node, "subsystem-id", 0);
440
441 dev->cfg_size = pci_cfg_space_size(dev);
442
443 /* We can't actually use the firmware value, we have
444 * to read what is in the register right now. One
445 * reason is that in the case of IDE interfaces the
446 * firmware can sample the value before the the IDE
447 * interface is programmed into native mode.
448 */
449 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
450 dev->class = class >> 8;
451
452 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
453 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
454 }
455 if (ofpci_verbose)
456 printk(" class: 0x%x device name: %s\n",
457 dev->class, pci_name(dev));
458
459 /* I have seen IDE devices which will not respond to
460 * the bmdma simplex check reads if bus mastering is
461 * disabled.
462 */
463 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
464 pci_set_master(dev);
465
466 dev->current_state = 4; /* unknown power state */
467 dev->error_state = pci_channel_io_normal;
468
469 if (host_controller) {
470 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
471 dev->rom_base_reg = PCI_ROM_ADDRESS1;
472 dev->irq = PCI_IRQ_NONE;
473 } else {
474 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
475 /* a PCI-PCI bridge */
476 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
477 dev->rom_base_reg = PCI_ROM_ADDRESS1;
478 } else if (!strcmp(type, "cardbus")) {
479 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
480 } else {
481 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
482 dev->rom_base_reg = PCI_ROM_ADDRESS;
483
484 dev->irq = sd->op->irqs[0];
485 if (dev->irq == 0xffffffff)
486 dev->irq = PCI_IRQ_NONE;
487 }
488 }
489 pci_parse_of_addrs(sd->op, node, dev);
490
491 if (ofpci_verbose)
492 printk(" adding to system ...\n");
493
494 pci_device_add(dev, bus);
495
496 return dev;
497 }
498
499 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
500 {
501 u32 idx, first, last;
502
503 first = 8;
504 last = 0;
505 for (idx = 0; idx < 8; idx++) {
506 if ((map & (1 << idx)) != 0) {
507 if (first > idx)
508 first = idx;
509 if (last < idx)
510 last = idx;
511 }
512 }
513
514 *first_p = first;
515 *last_p = last;
516 }
517
518 static void pci_resource_adjust(struct resource *res,
519 struct resource *root)
520 {
521 res->start += root->start;
522 res->end += root->start;
523 }
524
525 /* For PCI bus devices which lack a 'ranges' property we interrogate
526 * the config space values to set the resources, just like the generic
527 * Linux PCI probing code does.
528 */
529 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
530 struct pci_bus *bus,
531 struct pci_pbm_info *pbm)
532 {
533 struct resource *res;
534 u8 io_base_lo, io_limit_lo;
535 u16 mem_base_lo, mem_limit_lo;
536 unsigned long base, limit;
537
538 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
539 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
540 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
541 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
542
543 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
544 u16 io_base_hi, io_limit_hi;
545
546 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
547 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
548 base |= (io_base_hi << 16);
549 limit |= (io_limit_hi << 16);
550 }
551
552 res = bus->resource[0];
553 if (base <= limit) {
554 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
555 if (!res->start)
556 res->start = base;
557 if (!res->end)
558 res->end = limit + 0xfff;
559 pci_resource_adjust(res, &pbm->io_space);
560 }
561
562 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
563 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
564 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
565 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
566
567 res = bus->resource[1];
568 if (base <= limit) {
569 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
570 IORESOURCE_MEM);
571 res->start = base;
572 res->end = limit + 0xfffff;
573 pci_resource_adjust(res, &pbm->mem_space);
574 }
575
576 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
577 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
578 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
579 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
580
581 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
582 u32 mem_base_hi, mem_limit_hi;
583
584 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
585 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
586
587 /*
588 * Some bridges set the base > limit by default, and some
589 * (broken) BIOSes do not initialize them. If we find
590 * this, just assume they are not being used.
591 */
592 if (mem_base_hi <= mem_limit_hi) {
593 base |= ((long) mem_base_hi) << 32;
594 limit |= ((long) mem_limit_hi) << 32;
595 }
596 }
597
598 res = bus->resource[2];
599 if (base <= limit) {
600 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
601 IORESOURCE_MEM | IORESOURCE_PREFETCH);
602 res->start = base;
603 res->end = limit + 0xfffff;
604 pci_resource_adjust(res, &pbm->mem_space);
605 }
606 }
607
608 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
609 * a proper 'ranges' property.
610 */
611 static void __devinit apb_fake_ranges(struct pci_dev *dev,
612 struct pci_bus *bus,
613 struct pci_pbm_info *pbm)
614 {
615 struct resource *res;
616 u32 first, last;
617 u8 map;
618
619 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
620 apb_calc_first_last(map, &first, &last);
621 res = bus->resource[0];
622 res->start = (first << 21);
623 res->end = (last << 21) + ((1 << 21) - 1);
624 res->flags = IORESOURCE_IO;
625 pci_resource_adjust(res, &pbm->io_space);
626
627 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
628 apb_calc_first_last(map, &first, &last);
629 res = bus->resource[1];
630 res->start = (first << 21);
631 res->end = (last << 21) + ((1 << 21) - 1);
632 res->flags = IORESOURCE_MEM;
633 pci_resource_adjust(res, &pbm->mem_space);
634 }
635
636 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
637 struct device_node *node,
638 struct pci_bus *bus);
639
640 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
641
642 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
643 struct device_node *node,
644 struct pci_dev *dev)
645 {
646 struct pci_bus *bus;
647 const u32 *busrange, *ranges;
648 int len, i, simba;
649 struct resource *res;
650 unsigned int flags;
651 u64 size;
652
653 if (ofpci_verbose)
654 printk("of_scan_pci_bridge(%s)\n", node->full_name);
655
656 /* parse bus-range property */
657 busrange = of_get_property(node, "bus-range", &len);
658 if (busrange == NULL || len != 8) {
659 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
660 node->full_name);
661 return;
662 }
663 ranges = of_get_property(node, "ranges", &len);
664 simba = 0;
665 if (ranges == NULL) {
666 const char *model = of_get_property(node, "model", NULL);
667 if (model && !strcmp(model, "SUNW,simba"))
668 simba = 1;
669 }
670
671 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
672 if (!bus) {
673 printk(KERN_ERR "Failed to create pci bus for %s\n",
674 node->full_name);
675 return;
676 }
677
678 bus->primary = dev->bus->number;
679 bus->subordinate = busrange[1];
680 bus->bridge_ctl = 0;
681
682 /* parse ranges property, or cook one up by hand for Simba */
683 /* PCI #address-cells == 3 and #size-cells == 2 always */
684 res = &dev->resource[PCI_BRIDGE_RESOURCES];
685 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
686 res->flags = 0;
687 bus->resource[i] = res;
688 ++res;
689 }
690 if (simba) {
691 apb_fake_ranges(dev, bus, pbm);
692 goto after_ranges;
693 } else if (ranges == NULL) {
694 pci_cfg_fake_ranges(dev, bus, pbm);
695 goto after_ranges;
696 }
697 i = 1;
698 for (; len >= 32; len -= 32, ranges += 8) {
699 struct resource *root;
700
701 flags = pci_parse_of_flags(ranges[0]);
702 size = GET_64BIT(ranges, 6);
703 if (flags == 0 || size == 0)
704 continue;
705 if (flags & IORESOURCE_IO) {
706 res = bus->resource[0];
707 if (res->flags) {
708 printk(KERN_ERR "PCI: ignoring extra I/O range"
709 " for bridge %s\n", node->full_name);
710 continue;
711 }
712 root = &pbm->io_space;
713 } else {
714 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
715 printk(KERN_ERR "PCI: too many memory ranges"
716 " for bridge %s\n", node->full_name);
717 continue;
718 }
719 res = bus->resource[i];
720 ++i;
721 root = &pbm->mem_space;
722 }
723
724 res->start = GET_64BIT(ranges, 1);
725 res->end = res->start + size - 1;
726 res->flags = flags;
727
728 /* Another way to implement this would be to add an of_device
729 * layer routine that can calculate a resource for a given
730 * range property value in a PCI device.
731 */
732 pci_resource_adjust(res, root);
733 }
734 after_ranges:
735 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
736 bus->number);
737 if (ofpci_verbose)
738 printk(" bus name: %s\n", bus->name);
739
740 pci_of_scan_bus(pbm, node, bus);
741 }
742
743 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
744 struct device_node *node,
745 struct pci_bus *bus)
746 {
747 struct device_node *child;
748 const u32 *reg;
749 int reglen, devfn;
750 struct pci_dev *dev;
751
752 if (ofpci_verbose)
753 printk("PCI: scan_bus[%s] bus no %d\n",
754 node->full_name, bus->number);
755
756 child = NULL;
757 while ((child = of_get_next_child(node, child)) != NULL) {
758 if (ofpci_verbose)
759 printk(" * %s\n", child->full_name);
760 reg = of_get_property(child, "reg", &reglen);
761 if (reg == NULL || reglen < 20)
762 continue;
763 devfn = (reg[0] >> 8) & 0xff;
764
765 /* create a new pci_dev for this device */
766 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
767 if (!dev)
768 continue;
769 if (ofpci_verbose)
770 printk("PCI: dev header type: %x\n",
771 dev->hdr_type);
772
773 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
774 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
775 of_scan_pci_bridge(pbm, child, dev);
776 }
777 }
778
779 static ssize_t
780 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
781 {
782 struct pci_dev *pdev;
783 struct device_node *dp;
784
785 pdev = to_pci_dev(dev);
786 dp = pdev->dev.archdata.prom_node;
787
788 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
789 }
790
791 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
792
793 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
794 {
795 struct pci_dev *dev;
796 struct pci_bus *child_bus;
797 int err;
798
799 list_for_each_entry(dev, &bus->devices, bus_list) {
800 /* we don't really care if we can create this file or
801 * not, but we need to assign the result of the call
802 * or the world will fall under alien invasion and
803 * everybody will be frozen on a spaceship ready to be
804 * eaten on alpha centauri by some green and jelly
805 * humanoid.
806 */
807 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
808 }
809 list_for_each_entry(child_bus, &bus->children, node)
810 pci_bus_register_of_sysfs(child_bus);
811 }
812
813 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
814 unsigned int devfn,
815 int where, int size,
816 u32 *value)
817 {
818 static u8 fake_pci_config[] = {
819 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
820 0x00, 0x80, /* Device: 0x8000 (PBM) */
821 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
822 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
823 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
824 0x00, /* Cacheline: 0x00 */
825 0x40, /* Latency: 0x40 */
826 0x00, /* Header-Type: 0x00 normal */
827 };
828
829 *value = 0;
830 if (where >= 0 && where < sizeof(fake_pci_config) &&
831 (where + size) >= 0 &&
832 (where + size) < sizeof(fake_pci_config) &&
833 size <= sizeof(u32)) {
834 while (size--) {
835 *value <<= 8;
836 *value |= fake_pci_config[where + size];
837 }
838 }
839
840 return PCIBIOS_SUCCESSFUL;
841 }
842
843 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
844 unsigned int devfn,
845 int where, int size,
846 u32 value)
847 {
848 return PCIBIOS_SUCCESSFUL;
849 }
850
851 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
852 {
853 struct device_node *node = pbm->prom_node;
854 struct pci_dev *host_pdev;
855 struct pci_bus *bus;
856
857 printk("PCI: Scanning PBM %s\n", node->full_name);
858
859 /* XXX parent device? XXX */
860 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
861 if (!bus) {
862 printk(KERN_ERR "Failed to create bus for %s\n",
863 node->full_name);
864 return NULL;
865 }
866 bus->secondary = pbm->pci_first_busno;
867 bus->subordinate = pbm->pci_last_busno;
868
869 bus->resource[0] = &pbm->io_space;
870 bus->resource[1] = &pbm->mem_space;
871
872 /* Create the dummy host bridge and link it in. */
873 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
874 bus->self = host_pdev;
875
876 pci_of_scan_bus(pbm, node, bus);
877 pci_bus_add_devices(bus);
878 pci_bus_register_of_sysfs(bus);
879
880 return bus;
881 }
882
883 static void __init pci_scan_each_controller_bus(void)
884 {
885 struct pci_pbm_info *pbm;
886
887 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
888 pbm->scan_bus(pbm);
889 }
890
891 extern void power_init(void);
892
893 static int __init pcibios_init(void)
894 {
895 pci_controller_probe();
896 if (pci_pbm_root == NULL)
897 return 0;
898
899 pci_scan_each_controller_bus();
900
901 isa_init();
902 ebus_init();
903 power_init();
904
905 return 0;
906 }
907
908 subsys_initcall(pcibios_init);
909
910 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
911 {
912 struct pci_pbm_info *pbm = pbus->sysdata;
913
914 /* Generic PCI bus probing sets these to point at
915 * &io{port,mem}_resouce which is wrong for us.
916 */
917 pbus->resource[0] = &pbm->io_space;
918 pbus->resource[1] = &pbm->mem_space;
919 }
920
921 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
922 {
923 struct pci_pbm_info *pbm = pdev->bus->sysdata;
924 struct resource *root = NULL;
925
926 if (r->flags & IORESOURCE_IO)
927 root = &pbm->io_space;
928 if (r->flags & IORESOURCE_MEM)
929 root = &pbm->mem_space;
930
931 return root;
932 }
933
934 void pcibios_update_irq(struct pci_dev *pdev, int irq)
935 {
936 }
937
938 void pcibios_align_resource(void *data, struct resource *res,
939 resource_size_t size, resource_size_t align)
940 {
941 }
942
943 int pcibios_enable_device(struct pci_dev *dev, int mask)
944 {
945 u16 cmd, oldcmd;
946 int i;
947
948 pci_read_config_word(dev, PCI_COMMAND, &cmd);
949 oldcmd = cmd;
950
951 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
952 struct resource *res = &dev->resource[i];
953
954 /* Only set up the requested stuff */
955 if (!(mask & (1<<i)))
956 continue;
957
958 if (res->flags & IORESOURCE_IO)
959 cmd |= PCI_COMMAND_IO;
960 if (res->flags & IORESOURCE_MEM)
961 cmd |= PCI_COMMAND_MEMORY;
962 }
963
964 if (cmd != oldcmd) {
965 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
966 pci_name(dev), cmd);
967 /* Enable the appropriate bits in the PCI command register. */
968 pci_write_config_word(dev, PCI_COMMAND, cmd);
969 }
970 return 0;
971 }
972
973 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
974 struct resource *res)
975 {
976 struct pci_pbm_info *pbm = pdev->bus->sysdata;
977 struct resource zero_res, *root;
978
979 zero_res.start = 0;
980 zero_res.end = 0;
981 zero_res.flags = res->flags;
982
983 if (res->flags & IORESOURCE_IO)
984 root = &pbm->io_space;
985 else
986 root = &pbm->mem_space;
987
988 pci_resource_adjust(&zero_res, root);
989
990 region->start = res->start - zero_res.start;
991 region->end = res->end - zero_res.start;
992 }
993 EXPORT_SYMBOL(pcibios_resource_to_bus);
994
995 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
996 struct pci_bus_region *region)
997 {
998 struct pci_pbm_info *pbm = pdev->bus->sysdata;
999 struct resource *root;
1000
1001 res->start = region->start;
1002 res->end = region->end;
1003
1004 if (res->flags & IORESOURCE_IO)
1005 root = &pbm->io_space;
1006 else
1007 root = &pbm->mem_space;
1008
1009 pci_resource_adjust(res, root);
1010 }
1011 EXPORT_SYMBOL(pcibios_bus_to_resource);
1012
1013 char * __devinit pcibios_setup(char *str)
1014 {
1015 return str;
1016 }
1017
1018 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1019
1020 /* If the user uses a host-bridge as the PCI device, he may use
1021 * this to perform a raw mmap() of the I/O or MEM space behind
1022 * that controller.
1023 *
1024 * This can be useful for execution of x86 PCI bios initialization code
1025 * on a PCI card, like the xfree86 int10 stuff does.
1026 */
1027 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1028 enum pci_mmap_state mmap_state)
1029 {
1030 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1031 unsigned long space_size, user_offset, user_size;
1032
1033 if (mmap_state == pci_mmap_io) {
1034 space_size = (pbm->io_space.end -
1035 pbm->io_space.start) + 1;
1036 } else {
1037 space_size = (pbm->mem_space.end -
1038 pbm->mem_space.start) + 1;
1039 }
1040
1041 /* Make sure the request is in range. */
1042 user_offset = vma->vm_pgoff << PAGE_SHIFT;
1043 user_size = vma->vm_end - vma->vm_start;
1044
1045 if (user_offset >= space_size ||
1046 (user_offset + user_size) > space_size)
1047 return -EINVAL;
1048
1049 if (mmap_state == pci_mmap_io) {
1050 vma->vm_pgoff = (pbm->io_space.start +
1051 user_offset) >> PAGE_SHIFT;
1052 } else {
1053 vma->vm_pgoff = (pbm->mem_space.start +
1054 user_offset) >> PAGE_SHIFT;
1055 }
1056
1057 return 0;
1058 }
1059
1060 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
1061 * to the 32-bit pci bus offset for DEV requested by the user.
1062 *
1063 * Basically, the user finds the base address for his device which he wishes
1064 * to mmap. They read the 32-bit value from the config space base register,
1065 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1066 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1067 *
1068 * Returns negative error code on failure, zero on success.
1069 */
1070 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1071 enum pci_mmap_state mmap_state)
1072 {
1073 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
1074 unsigned long user32 = user_offset & pci_memspace_mask;
1075 unsigned long largest_base, this_base, addr32;
1076 int i;
1077
1078 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1079 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
1080
1081 /* Figure out which base address this is for. */
1082 largest_base = 0UL;
1083 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1084 struct resource *rp = &dev->resource[i];
1085
1086 /* Active? */
1087 if (!rp->flags)
1088 continue;
1089
1090 /* Same type? */
1091 if (i == PCI_ROM_RESOURCE) {
1092 if (mmap_state != pci_mmap_mem)
1093 continue;
1094 } else {
1095 if ((mmap_state == pci_mmap_io &&
1096 (rp->flags & IORESOURCE_IO) == 0) ||
1097 (mmap_state == pci_mmap_mem &&
1098 (rp->flags & IORESOURCE_MEM) == 0))
1099 continue;
1100 }
1101
1102 this_base = rp->start;
1103
1104 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1105
1106 if (mmap_state == pci_mmap_io)
1107 addr32 &= 0xffffff;
1108
1109 if (addr32 <= user32 && this_base > largest_base)
1110 largest_base = this_base;
1111 }
1112
1113 if (largest_base == 0UL)
1114 return -EINVAL;
1115
1116 /* Now construct the final physical address. */
1117 if (mmap_state == pci_mmap_io)
1118 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1119 else
1120 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1121
1122 return 0;
1123 }
1124
1125 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1126 * mapping.
1127 */
1128 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1129 enum pci_mmap_state mmap_state)
1130 {
1131 vma->vm_flags |= (VM_IO | VM_RESERVED);
1132 }
1133
1134 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1135 * device mapping.
1136 */
1137 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1138 enum pci_mmap_state mmap_state)
1139 {
1140 /* Our io_remap_pfn_range takes care of this, do nothing. */
1141 }
1142
1143 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1144 * for this architecture. The region in the process to map is described by vm_start
1145 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1146 * The pci device structure is provided so that architectures may make mapping
1147 * decisions on a per-device or per-bus basis.
1148 *
1149 * Returns a negative error code on failure, zero on success.
1150 */
1151 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1152 enum pci_mmap_state mmap_state,
1153 int write_combine)
1154 {
1155 int ret;
1156
1157 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1158 if (ret < 0)
1159 return ret;
1160
1161 __pci_mmap_set_flags(dev, vma, mmap_state);
1162 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1163
1164 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1165 ret = io_remap_pfn_range(vma, vma->vm_start,
1166 vma->vm_pgoff,
1167 vma->vm_end - vma->vm_start,
1168 vma->vm_page_prot);
1169 if (ret)
1170 return ret;
1171
1172 return 0;
1173 }
1174
1175 /* Return the domain nuber for this pci bus */
1176
1177 int pci_domain_nr(struct pci_bus *pbus)
1178 {
1179 struct pci_pbm_info *pbm = pbus->sysdata;
1180 int ret;
1181
1182 if (pbm == NULL || pbm->parent == NULL) {
1183 ret = -ENXIO;
1184 } else {
1185 ret = pbm->index;
1186 }
1187
1188 return ret;
1189 }
1190 EXPORT_SYMBOL(pci_domain_nr);
1191
1192 #ifdef CONFIG_PCI_MSI
1193 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1194 {
1195 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1196 int virt_irq;
1197
1198 if (!pbm->setup_msi_irq)
1199 return -EINVAL;
1200
1201 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1202 }
1203
1204 void arch_teardown_msi_irq(unsigned int virt_irq)
1205 {
1206 struct msi_desc *entry = get_irq_msi(virt_irq);
1207 struct pci_dev *pdev = entry->dev;
1208 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1209
1210 if (!pbm->teardown_msi_irq)
1211 return;
1212
1213 return pbm->teardown_msi_irq(virt_irq, pdev);
1214 }
1215 #endif /* !(CONFIG_PCI_MSI) */
1216
1217 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1218 {
1219 return pdev->dev.archdata.prom_node;
1220 }
1221 EXPORT_SYMBOL(pci_device_to_OF_node);
1222
1223 #endif /* !(CONFIG_PCI) */
WRT350N Kernel Patches