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[PATCH] ocfs2: zero_user_page conversion
[wrt350n-kernel.git] / arch / sparc64 / kernel / pci_psycho.c
blob598393a2df168d1e92910cc9bc2a6866bb933013
1 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/iommu.h>
16 #include <asm/irq.h>
17 #include <asm/starfire.h>
18 #include <asm/prom.h>
19 #include <asm/of_device.h>
20 #include <asm/oplib.h>
21
22 #include "pci_impl.h"
23 #include "iommu_common.h"
24
25 /* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29 #define psycho_read(__reg) \
30 ({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36 })
37 #define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44 /* Misc. PSYCHO PCI controller register offsets and definitions. */
45 #define PSYCHO_CONTROL 0x0010UL
46 #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47 #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48 #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49 #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52 #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53 #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54 #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55 #define PSYCHO_PCIA_CTRL 0x2000UL
56 #define PSYCHO_PCIB_CTRL 0x4000UL
57 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59 #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65 #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69
70 /* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78 #define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89 {
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95 }
96
97 /* PSYCHO error handling support. */
98 enum psycho_error_type {
99 UE_ERR, CE_ERR, PCI_ERR
100 };
101
102 /* Helper function of IOMMU error checking, which checks out
103 * the state of the streaming buffers. The IOMMU lock is
104 * held when this is called.
105 *
106 * For the PCI error case we know which PBM (and thus which
107 * streaming buffer) caused the error, but for the uncorrectable
108 * error case we do not. So we always check both streaming caches.
109 */
110 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
111 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
112 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
113 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
114 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
115 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
116 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
117 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
118 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
119 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
120 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
121 #define PSYCHO_STC_DATA_A 0xb000UL
122 #define PSYCHO_STC_DATA_B 0xc000UL
123 #define PSYCHO_STC_ERR_A 0xb400UL
124 #define PSYCHO_STC_ERR_B 0xc400UL
125 #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
126 #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
127 #define PSYCHO_STC_TAG_A 0xb800UL
128 #define PSYCHO_STC_TAG_B 0xc800UL
129 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
130 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
131 #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
132 #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
133 #define PSYCHO_STC_LINE_A 0xb900UL
134 #define PSYCHO_STC_LINE_B 0xc900UL
135 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
136 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
137 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
138 #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
139 #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
140 #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
141
142 static DEFINE_SPINLOCK(stc_buf_lock);
143 static unsigned long stc_error_buf[128];
144 static unsigned long stc_tag_buf[16];
145 static unsigned long stc_line_buf[16];
146
147 static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
148 int is_pbm_a)
149 {
150 struct strbuf *strbuf = &pbm->stc;
151 unsigned long regbase = pbm->controller_regs;
152 unsigned long err_base, tag_base, line_base;
153 u64 control;
154 int i;
155
156 if (is_pbm_a) {
157 err_base = regbase + PSYCHO_STC_ERR_A;
158 tag_base = regbase + PSYCHO_STC_TAG_A;
159 line_base = regbase + PSYCHO_STC_LINE_A;
160 } else {
161 err_base = regbase + PSYCHO_STC_ERR_B;
162 tag_base = regbase + PSYCHO_STC_TAG_B;
163 line_base = regbase + PSYCHO_STC_LINE_B;
164 }
165
166 spin_lock(&stc_buf_lock);
167
168 /* This is __REALLY__ dangerous. When we put the
169 * streaming buffer into diagnostic mode to probe
170 * it's tags and error status, we _must_ clear all
171 * of the line tag valid bits before re-enabling
172 * the streaming buffer. If any dirty data lives
173 * in the STC when we do this, we will end up
174 * invalidating it before it has a chance to reach
175 * main memory.
176 */
177 control = psycho_read(strbuf->strbuf_control);
178 psycho_write(strbuf->strbuf_control,
179 (control | PSYCHO_STRBUF_CTRL_DENAB));
180 for (i = 0; i < 128; i++) {
181 unsigned long val;
182
183 val = psycho_read(err_base + (i * 8UL));
184 psycho_write(err_base + (i * 8UL), 0UL);
185 stc_error_buf[i] = val;
186 }
187 for (i = 0; i < 16; i++) {
188 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
189 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
190 psycho_write(tag_base + (i * 8UL), 0UL);
191 psycho_write(line_base + (i * 8UL), 0UL);
192 }
193
194 /* OK, state is logged, exit diagnostic mode. */
195 psycho_write(strbuf->strbuf_control, control);
196
197 for (i = 0; i < 16; i++) {
198 int j, saw_error, first, last;
199
200 saw_error = 0;
201 first = i * 8;
202 last = first + 8;
203 for (j = first; j < last; j++) {
204 unsigned long errval = stc_error_buf[j];
205 if (errval != 0) {
206 saw_error++;
207 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
208 pbm->name,
209 j,
210 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
211 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
212 }
213 }
214 if (saw_error != 0) {
215 unsigned long tagval = stc_tag_buf[i];
216 unsigned long lineval = stc_line_buf[i];
217 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
218 pbm->name,
219 i,
220 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
221 (tagval & PSYCHO_STCTAG_VPN),
222 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
223 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
224 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
225 "V(%d)FOFN(%d)]\n",
226 pbm->name,
227 i,
228 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
229 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
230 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
231 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
232 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
233 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
234 }
235 }
236
237 spin_unlock(&stc_buf_lock);
238 }
239
240 static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
241 unsigned long afsr,
242 unsigned long afar,
243 enum psycho_error_type type)
244 {
245 __psycho_check_one_stc(pbm,
246 (pbm == &pbm->parent->pbm_A));
247 }
248
249 /* When an Uncorrectable Error or a PCI Error happens, we
250 * interrogate the IOMMU state to see if it is the cause.
251 */
252 #define PSYCHO_IOMMU_CONTROL 0x0200UL
253 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
254 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
255 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
256 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
257 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
258 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
259 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
260 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
261 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
262 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
263 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
264 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
265 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
266 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
267 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
268 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
269 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
270 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
271 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
272 #define PSYCHO_IOMMU_FLUSH 0x0210UL
273 #define PSYCHO_IOMMU_TAG 0xa580UL
274 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
275 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
276 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
277 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
278 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
279 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
280 #define PSYCHO_IOMMU_DATA 0xa600UL
281 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
282 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
283 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
284 static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
285 unsigned long afsr,
286 unsigned long afar,
287 enum psycho_error_type type)
288 {
289 struct iommu *iommu = pbm->iommu;
290 unsigned long iommu_tag[16];
291 unsigned long iommu_data[16];
292 unsigned long flags;
293 u64 control;
294 int i;
295
296 spin_lock_irqsave(&iommu->lock, flags);
297 control = psycho_read(iommu->iommu_control);
298 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
299 char *type_string;
300
301 /* Clear the error encountered bit. */
302 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
303 psycho_write(iommu->iommu_control, control);
304
305 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
306 case 0:
307 type_string = "Protection Error";
308 break;
309 case 1:
310 type_string = "Invalid Error";
311 break;
312 case 2:
313 type_string = "TimeOut Error";
314 break;
315 case 3:
316 default:
317 type_string = "ECC Error";
318 break;
319 };
320 printk("%s: IOMMU Error, type[%s]\n",
321 pbm->name, type_string);
322
323 /* Put the IOMMU into diagnostic mode and probe
324 * it's TLB for entries with error status.
325 *
326 * It is very possible for another DVMA to occur
327 * while we do this probe, and corrupt the system
328 * further. But we are so screwed at this point
329 * that we are likely to crash hard anyways, so
330 * get as much diagnostic information to the
331 * console as we can.
332 */
333 psycho_write(iommu->iommu_control,
334 control | PSYCHO_IOMMU_CTRL_DENAB);
335 for (i = 0; i < 16; i++) {
336 unsigned long base = pbm->controller_regs;
337
338 iommu_tag[i] =
339 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
340 iommu_data[i] =
341 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
342
343 /* Now clear out the entry. */
344 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
345 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
346 }
347
348 /* Leave diagnostic mode. */
349 psycho_write(iommu->iommu_control, control);
350
351 for (i = 0; i < 16; i++) {
352 unsigned long tag, data;
353
354 tag = iommu_tag[i];
355 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
356 continue;
357
358 data = iommu_data[i];
359 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
360 case 0:
361 type_string = "Protection Error";
362 break;
363 case 1:
364 type_string = "Invalid Error";
365 break;
366 case 2:
367 type_string = "TimeOut Error";
368 break;
369 case 3:
370 default:
371 type_string = "ECC Error";
372 break;
373 };
374 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
375 pbm->name, i, type_string,
376 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
377 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
378 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
379 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
380 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
381 pbm->name, i,
382 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
383 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
384 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
385 }
386 }
387 __psycho_check_stc_error(pbm, afsr, afar, type);
388 spin_unlock_irqrestore(&iommu->lock, flags);
389 }
390
391 /* Uncorrectable Errors. Cause of the error and the address are
392 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
393 * relating to UPA interface transactions.
394 */
395 #define PSYCHO_UE_AFSR 0x0030UL
396 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
397 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
398 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
399 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
400 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
401 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
402 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
403 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
404 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
405 #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
406 #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
407 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
408 #define PSYCHO_UE_AFAR 0x0038UL
409
410 static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
411 {
412 struct pci_pbm_info *pbm = dev_id;
413 struct pci_controller_info *p = pbm->parent;
414 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
415 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
416 unsigned long afsr, afar, error_bits;
417 int reported;
418
419 /* Latch uncorrectable error status. */
420 afar = psycho_read(afar_reg);
421 afsr = psycho_read(afsr_reg);
422
423 /* Clear the primary/secondary error status bits. */
424 error_bits = afsr &
425 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
426 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
427 if (!error_bits)
428 return IRQ_NONE;
429 psycho_write(afsr_reg, error_bits);
430
431 /* Log the error. */
432 printk("%s: Uncorrectable Error, primary error type[%s]\n",
433 pbm->name,
434 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
435 "PIO" :
436 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
437 "DMA Read" :
438 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
439 "DMA Write" : "???")))));
440 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
441 pbm->name,
442 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
443 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
444 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
445 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
446 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
447 printk("%s: UE Secondary errors [", pbm->name);
448 reported = 0;
449 if (afsr & PSYCHO_UEAFSR_SPIO) {
450 reported++;
451 printk("(PIO)");
452 }
453 if (afsr & PSYCHO_UEAFSR_SDRD) {
454 reported++;
455 printk("(DMA Read)");
456 }
457 if (afsr & PSYCHO_UEAFSR_SDWR) {
458 reported++;
459 printk("(DMA Write)");
460 }
461 if (!reported)
462 printk("(none)");
463 printk("]\n");
464
465 /* Interrogate both IOMMUs for error status. */
466 psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR);
467 psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR);
468
469 return IRQ_HANDLED;
470 }
471
472 /* Correctable Errors. */
473 #define PSYCHO_CE_AFSR 0x0040UL
474 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
475 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
476 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
477 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
478 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
479 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
480 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
481 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
482 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
483 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
484 #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
485 #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
486 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
487 #define PSYCHO_CE_AFAR 0x0040UL
488
489 static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
490 {
491 struct pci_pbm_info *pbm = dev_id;
492 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
493 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
494 unsigned long afsr, afar, error_bits;
495 int reported;
496
497 /* Latch error status. */
498 afar = psycho_read(afar_reg);
499 afsr = psycho_read(afsr_reg);
500
501 /* Clear primary/secondary error status bits. */
502 error_bits = afsr &
503 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
504 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
505 if (!error_bits)
506 return IRQ_NONE;
507 psycho_write(afsr_reg, error_bits);
508
509 /* Log the error. */
510 printk("%s: Correctable Error, primary error type[%s]\n",
511 pbm->name,
512 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
513 "PIO" :
514 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
515 "DMA Read" :
516 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
517 "DMA Write" : "???")))));
518
519 /* XXX Use syndrome and afar to print out module string just like
520 * XXX UDB CE trap handler does... -DaveM
521 */
522 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
523 "UPA_MID[%02lx] was_block(%d)\n",
524 pbm->name,
525 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
526 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
527 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
528 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
529 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
530 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
531 printk("%s: CE Secondary errors [", pbm->name);
532 reported = 0;
533 if (afsr & PSYCHO_CEAFSR_SPIO) {
534 reported++;
535 printk("(PIO)");
536 }
537 if (afsr & PSYCHO_CEAFSR_SDRD) {
538 reported++;
539 printk("(DMA Read)");
540 }
541 if (afsr & PSYCHO_CEAFSR_SDWR) {
542 reported++;
543 printk("(DMA Write)");
544 }
545 if (!reported)
546 printk("(none)");
547 printk("]\n");
548
549 return IRQ_HANDLED;
550 }
551
552 /* PCI Errors. They are signalled by the PCI bus module since they
553 * are associated with a specific bus segment.
554 */
555 #define PSYCHO_PCI_AFSR_A 0x2010UL
556 #define PSYCHO_PCI_AFSR_B 0x4010UL
557 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
558 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
559 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
560 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
561 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
562 #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
563 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
564 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
565 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
566 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
567 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
568 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
569 #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
570 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
571 #define PSYCHO_PCI_AFAR_A 0x2018UL
572 #define PSYCHO_PCI_AFAR_B 0x4018UL
573
574 static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
575 {
576 unsigned long csr_reg, csr, csr_error_bits;
577 irqreturn_t ret = IRQ_NONE;
578 u16 stat;
579
580 if (is_pbm_a) {
581 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
582 } else {
583 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
584 }
585 csr = psycho_read(csr_reg);
586 csr_error_bits =
587 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
588 if (csr_error_bits) {
589 /* Clear the errors. */
590 psycho_write(csr_reg, csr);
591
592 /* Log 'em. */
593 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
594 printk("%s: PCI streaming byte hole error asserted.\n",
595 pbm->name);
596 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
597 printk("%s: PCI SERR signal asserted.\n", pbm->name);
598 ret = IRQ_HANDLED;
599 }
600 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
601 if (stat & (PCI_STATUS_PARITY |
602 PCI_STATUS_SIG_TARGET_ABORT |
603 PCI_STATUS_REC_TARGET_ABORT |
604 PCI_STATUS_REC_MASTER_ABORT |
605 PCI_STATUS_SIG_SYSTEM_ERROR)) {
606 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
607 pbm->name, stat);
608 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
609 ret = IRQ_HANDLED;
610 }
611 return ret;
612 }
613
614 static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
615 {
616 struct pci_pbm_info *pbm = dev_id;
617 struct pci_controller_info *p = pbm->parent;
618 unsigned long afsr_reg, afar_reg;
619 unsigned long afsr, afar, error_bits;
620 int is_pbm_a, reported;
621
622 is_pbm_a = (pbm == &pbm->parent->pbm_A);
623 if (is_pbm_a) {
624 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
625 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
626 } else {
627 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
628 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
629 }
630
631 /* Latch error status. */
632 afar = psycho_read(afar_reg);
633 afsr = psycho_read(afsr_reg);
634
635 /* Clear primary/secondary error status bits. */
636 error_bits = afsr &
637 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
638 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
639 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
640 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
641 if (!error_bits)
642 return psycho_pcierr_intr_other(pbm, is_pbm_a);
643 psycho_write(afsr_reg, error_bits);
644
645 /* Log the error. */
646 printk("%s: PCI Error, primary error type[%s]\n",
647 pbm->name,
648 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
649 "Master Abort" :
650 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
651 "Target Abort" :
652 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
653 "Excessive Retries" :
654 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
655 "Parity Error" : "???"))))));
656 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
657 pbm->name,
658 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
659 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
660 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
661 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
662 printk("%s: PCI Secondary errors [", pbm->name);
663 reported = 0;
664 if (afsr & PSYCHO_PCIAFSR_SMA) {
665 reported++;
666 printk("(Master Abort)");
667 }
668 if (afsr & PSYCHO_PCIAFSR_STA) {
669 reported++;
670 printk("(Target Abort)");
671 }
672 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
673 reported++;
674 printk("(Excessive Retries)");
675 }
676 if (afsr & PSYCHO_PCIAFSR_SPERR) {
677 reported++;
678 printk("(Parity Error)");
679 }
680 if (!reported)
681 printk("(none)");
682 printk("]\n");
683
684 /* For the error types shown, scan PBM's PCI bus for devices
685 * which have logged that error type.
686 */
687
688 /* If we see a Target Abort, this could be the result of an
689 * IOMMU translation error of some sort. It is extremely
690 * useful to log this information as usually it indicates
691 * a bug in the IOMMU support code or a PCI device driver.
692 */
693 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
694 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
695 pci_scan_for_target_abort(pbm, pbm->pci_bus);
696 }
697 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
698 pci_scan_for_master_abort(pbm, pbm->pci_bus);
699
700 /* For excessive retries, PSYCHO/PBM will abort the device
701 * and there is no way to specifically check for excessive
702 * retries in the config space status registers. So what
703 * we hope is that we'll catch it via the master/target
704 * abort events.
705 */
706
707 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
708 pci_scan_for_parity_error(pbm, pbm->pci_bus);
709
710 return IRQ_HANDLED;
711 }
712
713 /* XXX What about PowerFail/PowerManagement??? -DaveM */
714 #define PSYCHO_ECC_CTRL 0x0020
715 #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
716 #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
717 #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
718 static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
719 {
720 struct of_device *op = of_find_device_by_node(pbm->prom_node);
721 unsigned long base = pbm->controller_regs;
722 u64 tmp;
723 int err;
724
725 if (!op)
726 return;
727
728 /* Psycho interrupt property order is:
729 * 0: PCIERR INO for this PBM
730 * 1: UE ERR
731 * 2: CE ERR
732 * 3: POWER FAIL
733 * 4: SPARE HARDWARE
734 * 5: POWER MANAGEMENT
735 */
736
737 if (op->num_irqs < 6)
738 return;
739
740 /* We really mean to ignore the return result here. Two
741 * PCI controller share the same interrupt numbers and
742 * drive the same front-end hardware. Whichever of the
743 * two get in here first will register the IRQ handler
744 * the second will just error out since we do not pass in
745 * IRQF_SHARED.
746 */
747 err = request_irq(op->irqs[1], psycho_ue_intr, 0,
748 "PSYCHO_UE", pbm);
749 err = request_irq(op->irqs[2], psycho_ce_intr, 0,
750 "PSYCHO_CE", pbm);
751
752 /* This one, however, ought not to fail. We can just warn
753 * about it since the system can still operate properly even
754 * if this fails.
755 */
756 err = request_irq(op->irqs[0], psycho_pcierr_intr, 0,
757 "PSYCHO_PCIERR", pbm);
758 if (err)
759 printk(KERN_WARNING "%s: Could not register PCIERR, "
760 "err=%d\n", pbm->name, err);
761
762 /* Enable UE and CE interrupts for controller. */
763 psycho_write(base + PSYCHO_ECC_CTRL,
764 (PSYCHO_ECCCTRL_EE |
765 PSYCHO_ECCCTRL_UE |
766 PSYCHO_ECCCTRL_CE));
767
768 /* Enable PCI Error interrupts and clear error
769 * bits for each PBM.
770 */
771 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
772 tmp |= (PSYCHO_PCICTRL_SERR |
773 PSYCHO_PCICTRL_SBH_ERR |
774 PSYCHO_PCICTRL_EEN);
775 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
776 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
777
778 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
779 tmp |= (PSYCHO_PCICTRL_SERR |
780 PSYCHO_PCICTRL_SBH_ERR |
781 PSYCHO_PCICTRL_EEN);
782 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
783 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
784 }
785
786 /* PSYCHO boot time probing and initialization. */
787 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
788 {
789 u8 *addr;
790
791 /* Set cache-line size to 64 bytes, this is actually
792 * a nop but I do it for completeness.
793 */
794 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
795 0, PCI_CACHE_LINE_SIZE);
796 pci_config_write8(addr, 64 / sizeof(u32));
797
798 /* Set PBM latency timer to 64 PCI clocks. */
799 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
800 0, PCI_LATENCY_TIMER);
801 pci_config_write8(addr, 64);
802 }
803
804 static void psycho_scan_bus(struct pci_pbm_info *pbm)
805 {
806 pbm_config_busmastering(pbm);
807 pbm->is_66mhz_capable = 0;
808 pbm->pci_bus = pci_scan_one_pbm(pbm);
809
810 /* After the PCI bus scan is complete, we can register
811 * the error interrupt handlers.
812 */
813 psycho_register_error_handlers(pbm);
814 }
815
816 static void psycho_iommu_init(struct pci_pbm_info *pbm)
817 {
818 struct iommu *iommu = pbm->iommu;
819 unsigned long i;
820 u64 control;
821
822 /* Register addresses. */
823 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
824 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
825 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
826 /* PSYCHO's IOMMU lacks ctx flushing. */
827 iommu->iommu_ctxflush = 0;
828
829 /* We use the main control register of PSYCHO as the write
830 * completion register.
831 */
832 iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;
833
834 /*
835 * Invalidate TLB Entries.
836 */
837 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
838 control |= PSYCHO_IOMMU_CTRL_DENAB;
839 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
840 for(i = 0; i < 16; i++) {
841 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
842 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
843 }
844
845 /* Leave diag mode enabled for full-flushing done
846 * in pci_iommu.c
847 */
848 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
849
850 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,
851 __pa(iommu->page_table));
852
853 control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
854 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
855 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
856 psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
857
858 /* If necessary, hook us up for starfire IRQ translations. */
859 if (this_is_starfire)
860 starfire_hookup(pbm->portid);
861 }
862
863 #define PSYCHO_IRQ_RETRY 0x1a00UL
864 #define PSYCHO_PCIA_DIAG 0x2020UL
865 #define PSYCHO_PCIB_DIAG 0x4020UL
866 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
867 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
868 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
869 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
870 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
871 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
872 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
873 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
874
875 static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
876 {
877 u64 tmp;
878
879 psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);
880
881 /* Enable arbiter for all PCI slots. */
882 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);
883 tmp |= PSYCHO_PCICTRL_AEN;
884 psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);
885
886 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);
887 tmp |= PSYCHO_PCICTRL_AEN;
888 psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);
889
890 /* Disable DMA write / PIO read synchronization on
891 * both PCI bus segments.
892 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
893 */
894 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);
895 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
896 psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);
897
898 tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);
899 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
900 psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);
901 }
902
903 static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
904 int is_pbm_a)
905 {
906 unsigned long base = pbm->controller_regs;
907 u64 control;
908
909 if (is_pbm_a) {
910 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
911 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
912 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
913 } else {
914 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
915 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
916 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
917 }
918 /* PSYCHO's streaming buffer lacks ctx flushing. */
919 pbm->stc.strbuf_ctxflush = 0;
920 pbm->stc.strbuf_ctxmatch_base = 0;
921
922 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
923 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
924 + 63UL)
925 & ~63UL);
926 pbm->stc.strbuf_flushflag_pa = (unsigned long)
927 __pa(pbm->stc.strbuf_flushflag);
928
929 /* Enable the streaming buffer. We have to be careful
930 * just in case OBP left it with LRU locking enabled.
931 *
932 * It is possible to control if PBM will be rerun on
933 * line misses. Currently I just retain whatever setting
934 * OBP left us with. All checks so far show it having
935 * a value of zero.
936 */
937 #undef PSYCHO_STRBUF_RERUN_ENABLE
938 #undef PSYCHO_STRBUF_RERUN_DISABLE
939 control = psycho_read(pbm->stc.strbuf_control);
940 control |= PSYCHO_STRBUF_CTRL_ENAB;
941 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
942 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
943 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
944 #else
945 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
946 control |= PSYCHO_STRBUF_CTRL_RRDIS;
947 #endif
948 #endif
949 psycho_write(pbm->stc.strbuf_control, control);
950
951 pbm->stc.strbuf_enabled = 1;
952 }
953
954 #define PSYCHO_IOSPACE_A 0x002000000UL
955 #define PSYCHO_IOSPACE_B 0x002010000UL
956 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
957 #define PSYCHO_MEMSPACE_A 0x100000000UL
958 #define PSYCHO_MEMSPACE_B 0x180000000UL
959 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
960
961 static void psycho_pbm_init(struct pci_controller_info *p,
962 struct device_node *dp, int is_pbm_a)
963 {
964 struct property *prop;
965 struct pci_pbm_info *pbm;
966
967 if (is_pbm_a)
968 pbm = &p->pbm_A;
969 else
970 pbm = &p->pbm_B;
971
972 pbm->next = pci_pbm_root;
973 pci_pbm_root = pbm;
974
975 pbm->scan_bus = psycho_scan_bus;
976 pbm->pci_ops = &sun4u_pci_ops;
977 pbm->config_space_reg_bits = 8;
978
979 pbm->index = pci_num_pbms++;
980
981 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
982 pbm->chip_version = 0;
983 prop = of_find_property(dp, "version#", NULL);
984 if (prop)
985 pbm->chip_version = *(int *) prop->value;
986 pbm->chip_revision = 0;
987 prop = of_find_property(dp, "module-revision#", NULL);
988 if (prop)
989 pbm->chip_revision = *(int *) prop->value;
990
991 pbm->parent = p;
992 pbm->prom_node = dp;
993 pbm->name = dp->full_name;
994
995 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
996 pbm->name,
997 pbm->chip_version, pbm->chip_revision);
998
999 pci_determine_mem_io_space(pbm);
1000
1001 pci_get_pbm_props(pbm);
1002
1003 psycho_pbm_strbuf_init(pbm, is_pbm_a);
1004 }
1005
1006 #define PSYCHO_CONFIGSPACE 0x001000000UL
1007
1008 void psycho_init(struct device_node *dp, char *model_name)
1009 {
1010 struct linux_prom64_registers *pr_regs;
1011 struct pci_controller_info *p;
1012 struct pci_pbm_info *pbm;
1013 struct iommu *iommu;
1014 struct property *prop;
1015 u32 upa_portid;
1016 int is_pbm_a;
1017
1018 upa_portid = 0xff;
1019 prop = of_find_property(dp, "upa-portid", NULL);
1020 if (prop)
1021 upa_portid = *(u32 *) prop->value;
1022
1023 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1024 struct pci_controller_info *p = pbm->parent;
1025
1026 if (p->pbm_A.portid == upa_portid) {
1027 is_pbm_a = (p->pbm_A.prom_node == NULL);
1028 psycho_pbm_init(p, dp, is_pbm_a);
1029 return;
1030 }
1031 }
1032
1033 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1034 if (!p) {
1035 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1036 prom_halt();
1037 }
1038 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1039 if (!iommu) {
1040 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1041 prom_halt();
1042 }
1043 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1044
1045 p->pbm_A.portid = upa_portid;
1046 p->pbm_B.portid = upa_portid;
1047
1048 prop = of_find_property(dp, "reg", NULL);
1049 pr_regs = prop->value;
1050
1051 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1052 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1053
1054 p->pbm_A.config_space = p->pbm_B.config_space =
1055 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1056
1057 /*
1058 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1059 * we need to adjust our MEM space mask.
1060 */
1061 pci_memspace_mask = 0x7fffffffUL;
1062
1063 psycho_controller_hwinit(&p->pbm_A);
1064
1065 psycho_iommu_init(&p->pbm_A);
1066
1067 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1068 psycho_pbm_init(p, dp, is_pbm_a);
1069 }
WRT350N Kernel Patches