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[PATCH] ocfs2: zero_user_page conversion
[wrt350n-kernel.git] / arch / sparc64 / mm / init.c
blob3010227fe24313ccddc630068c9503aa77b7c409
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27
28 #include <asm/head.h>
29 #include <asm/system.h>
30 #include <asm/page.h>
31 #include <asm/pgalloc.h>
32 #include <asm/pgtable.h>
33 #include <asm/oplib.h>
34 #include <asm/iommu.h>
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/dma.h>
40 #include <asm/starfire.h>
41 #include <asm/tlb.h>
42 #include <asm/spitfire.h>
43 #include <asm/sections.h>
44 #include <asm/tsb.h>
45 #include <asm/hypervisor.h>
46 #include <asm/prom.h>
47 #include <asm/sstate.h>
48 #include <asm/mdesc.h>
49
50 #define MAX_PHYS_ADDRESS (1UL << 42UL)
51 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
52 #define KPTE_BITMAP_BYTES \
53 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS 32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
75 static int pavail_ents __initdata;
76 static int pavail_rescan_ents __initdata;
77
78 static int cmp_p64(const void *a, const void *b)
79 {
80 const struct linux_prom64_registers *x = a, *y = b;
81
82 if (x->phys_addr > y->phys_addr)
83 return 1;
84 if (x->phys_addr < y->phys_addr)
85 return -1;
86 return 0;
87 }
88
89 static void __init read_obp_memory(const char *property,
90 struct linux_prom64_registers *regs,
91 int *num_ents)
92 {
93 int node = prom_finddevice("/memory");
94 int prop_size = prom_getproplen(node, property);
95 int ents, ret, i;
96
97 ents = prop_size / sizeof(struct linux_prom64_registers);
98 if (ents > MAX_BANKS) {
99 prom_printf("The machine has more %s property entries than "
100 "this kernel can support (%d).\n",
101 property, MAX_BANKS);
102 prom_halt();
103 }
104
105 ret = prom_getproperty(node, property, (char *) regs, prop_size);
106 if (ret == -1) {
107 prom_printf("Couldn't get %s property from /memory.\n");
108 prom_halt();
109 }
110
111 /* Sanitize what we got from the firmware, by page aligning
112 * everything.
113 */
114 for (i = 0; i < ents; i++) {
115 unsigned long base, size;
116
117 base = regs[i].phys_addr;
118 size = regs[i].reg_size;
119
120 size &= PAGE_MASK;
121 if (base & ~PAGE_MASK) {
122 unsigned long new_base = PAGE_ALIGN(base);
123
124 size -= new_base - base;
125 if ((long) size < 0L)
126 size = 0UL;
127 base = new_base;
128 }
129 if (size == 0UL) {
130 /* If it is empty, simply get rid of it.
131 * This simplifies the logic of the other
132 * functions that process these arrays.
133 */
134 memmove(&regs[i], &regs[i + 1],
135 (ents - i - 1) * sizeof(regs[0]));
136 i--;
137 ents--;
138 continue;
139 }
140 regs[i].phys_addr = base;
141 regs[i].reg_size = size;
142 }
143
144 *num_ents = ents;
145
146 sort(regs, ents, sizeof(struct linux_prom64_registers),
147 cmp_p64, NULL);
148 }
149
150 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
151
152 /* Kernel physical address base and size in bytes. */
153 unsigned long kern_base __read_mostly;
154 unsigned long kern_size __read_mostly;
155
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64;
158 extern unsigned int sparc_ramdisk_image;
159 extern unsigned int sparc_ramdisk_size;
160
161 struct page *mem_map_zero __read_mostly;
162
163 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
164
165 unsigned long sparc64_kern_pri_context __read_mostly;
166 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
167 unsigned long sparc64_kern_sec_context __read_mostly;
168
169 int bigkernel = 0;
170
171 #ifdef CONFIG_DEBUG_DCFLUSH
172 atomic_t dcpage_flushes = ATOMIC_INIT(0);
173 #ifdef CONFIG_SMP
174 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
175 #endif
176 #endif
177
178 inline void flush_dcache_page_impl(struct page *page)
179 {
180 BUG_ON(tlb_type == hypervisor);
181 #ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes);
183 #endif
184
185 #ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page),
187 ((tlb_type == spitfire) &&
188 page_mapping(page) != NULL));
189 #else
190 if (page_mapping(page) != NULL &&
191 tlb_type == spitfire)
192 __flush_icache_page(__pa(page_address(page)));
193 #endif
194 }
195
196 #define PG_dcache_dirty PG_arch_1
197 #define PG_dcache_cpu_shift 32UL
198 #define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
200
201 #define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
203
204 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
205 {
206 unsigned long mask = this_cpu;
207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
218 "membar #StoreLoad | #StoreStore\n\t"
219 "bne,pn %%xcc, 1b\n\t"
220 " nop"
221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224 }
225
226 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "membar #StoreLoad | #StoreStore\n\t"
241 "bne,pn %%xcc, 1b\n\t"
242 " nop\n"
243 "2:"
244 : /* no outputs */
245 : "r" (cpu), "r" (mask), "r" (&page->flags),
246 "i" (PG_dcache_cpu_mask),
247 "i" (PG_dcache_cpu_shift)
248 : "g1", "g7");
249 }
250
251 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
252 {
253 unsigned long tsb_addr = (unsigned long) ent;
254
255 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
256 tsb_addr = __pa(tsb_addr);
257
258 __tsb_insert(tsb_addr, tag, pte);
259 }
260
261 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
262 unsigned long _PAGE_SZBITS __read_mostly;
263
264 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
265 {
266 struct mm_struct *mm;
267 struct tsb *tsb;
268 unsigned long tag, flags;
269 unsigned long tsb_index, tsb_hash_shift;
270
271 if (tlb_type != hypervisor) {
272 unsigned long pfn = pte_pfn(pte);
273 unsigned long pg_flags;
274 struct page *page;
275
276 if (pfn_valid(pfn) &&
277 (page = pfn_to_page(pfn), page_mapping(page)) &&
278 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
279 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
280 PG_dcache_cpu_mask);
281 int this_cpu = get_cpu();
282
283 /* This is just to optimize away some function calls
284 * in the SMP case.
285 */
286 if (cpu == this_cpu)
287 flush_dcache_page_impl(page);
288 else
289 smp_flush_dcache_page_impl(page, cpu);
290
291 clear_dcache_dirty_cpu(page, cpu);
292
293 put_cpu();
294 }
295 }
296
297 mm = vma->vm_mm;
298
299 tsb_index = MM_TSB_BASE;
300 tsb_hash_shift = PAGE_SHIFT;
301
302 spin_lock_irqsave(&mm->context.lock, flags);
303
304 #ifdef CONFIG_HUGETLB_PAGE
305 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
306 if ((tlb_type == hypervisor &&
307 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
308 (tlb_type != hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
310 tsb_index = MM_TSB_HUGE;
311 tsb_hash_shift = HPAGE_SHIFT;
312 }
313 }
314 #endif
315
316 tsb = mm->context.tsb_block[tsb_index].tsb;
317 tsb += ((address >> tsb_hash_shift) &
318 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
319 tag = (address >> 22UL);
320 tsb_insert(tsb, tag, pte_val(pte));
321
322 spin_unlock_irqrestore(&mm->context.lock, flags);
323 }
324
325 void flush_dcache_page(struct page *page)
326 {
327 struct address_space *mapping;
328 int this_cpu;
329
330 if (tlb_type == hypervisor)
331 return;
332
333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
336 */
337 if (page == ZERO_PAGE(0))
338 return;
339
340 this_cpu = get_cpu();
341
342 mapping = page_mapping(page);
343 if (mapping && !mapping_mapped(mapping)) {
344 int dirty = test_bit(PG_dcache_dirty, &page->flags);
345 if (dirty) {
346 int dirty_cpu = dcache_dirty_cpu(page);
347
348 if (dirty_cpu == this_cpu)
349 goto out;
350 smp_flush_dcache_page_impl(page, dirty_cpu);
351 }
352 set_dcache_dirty(page, this_cpu);
353 } else {
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
358 */
359 flush_dcache_page_impl(page);
360 }
361
362 out:
363 put_cpu();
364 }
365
366 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
367 {
368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
369 if (tlb_type == spitfire) {
370 unsigned long kaddr;
371
372 /* This code only runs on Spitfire cpus so this is
373 * why we can assume _PAGE_PADDR_4U.
374 */
375 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
376 unsigned long paddr, mask = _PAGE_PADDR_4U;
377
378 if (kaddr >= PAGE_OFFSET)
379 paddr = kaddr & mask;
380 else {
381 pgd_t *pgdp = pgd_offset_k(kaddr);
382 pud_t *pudp = pud_offset(pgdp, kaddr);
383 pmd_t *pmdp = pmd_offset(pudp, kaddr);
384 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
385
386 paddr = pte_val(*ptep) & mask;
387 }
388 __flush_icache_page(paddr);
389 }
390 }
391 }
392
393 void show_mem(void)
394 {
395 unsigned long total = 0, reserved = 0;
396 unsigned long shared = 0, cached = 0;
397 pg_data_t *pgdat;
398
399 printk(KERN_INFO "Mem-info:\n");
400 show_free_areas();
401 printk(KERN_INFO "Free swap: %6ldkB\n",
402 nr_swap_pages << (PAGE_SHIFT-10));
403 for_each_online_pgdat(pgdat) {
404 unsigned long i, flags;
405
406 pgdat_resize_lock(pgdat, &flags);
407 for (i = 0; i < pgdat->node_spanned_pages; i++) {
408 struct page *page = pgdat_page_nr(pgdat, i);
409 total++;
410 if (PageReserved(page))
411 reserved++;
412 else if (PageSwapCache(page))
413 cached++;
414 else if (page_count(page))
415 shared += page_count(page) - 1;
416 }
417 pgdat_resize_unlock(pgdat, &flags);
418 }
419
420 printk(KERN_INFO "%lu pages of RAM\n", total);
421 printk(KERN_INFO "%lu reserved pages\n", reserved);
422 printk(KERN_INFO "%lu pages shared\n", shared);
423 printk(KERN_INFO "%lu pages swap cached\n", cached);
424
425 printk(KERN_INFO "%lu pages dirty\n",
426 global_page_state(NR_FILE_DIRTY));
427 printk(KERN_INFO "%lu pages writeback\n",
428 global_page_state(NR_WRITEBACK));
429 printk(KERN_INFO "%lu pages mapped\n",
430 global_page_state(NR_FILE_MAPPED));
431 printk(KERN_INFO "%lu pages slab\n",
432 global_page_state(NR_SLAB_RECLAIMABLE) +
433 global_page_state(NR_SLAB_UNRECLAIMABLE));
434 printk(KERN_INFO "%lu pages pagetables\n",
435 global_page_state(NR_PAGETABLE));
436 }
437
438 void mmu_info(struct seq_file *m)
439 {
440 if (tlb_type == cheetah)
441 seq_printf(m, "MMU Type\t: Cheetah\n");
442 else if (tlb_type == cheetah_plus)
443 seq_printf(m, "MMU Type\t: Cheetah+\n");
444 else if (tlb_type == spitfire)
445 seq_printf(m, "MMU Type\t: Spitfire\n");
446 else if (tlb_type == hypervisor)
447 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
448 else
449 seq_printf(m, "MMU Type\t: ???\n");
450
451 #ifdef CONFIG_DEBUG_DCFLUSH
452 seq_printf(m, "DCPageFlushes\t: %d\n",
453 atomic_read(&dcpage_flushes));
454 #ifdef CONFIG_SMP
455 seq_printf(m, "DCPageFlushesXC\t: %d\n",
456 atomic_read(&dcpage_flushes_xcall));
457 #endif /* CONFIG_SMP */
458 #endif /* CONFIG_DEBUG_DCFLUSH */
459 }
460
461 struct linux_prom_translation {
462 unsigned long virt;
463 unsigned long size;
464 unsigned long data;
465 };
466
467 /* Exported for kernel TLB miss handling in ktlb.S */
468 struct linux_prom_translation prom_trans[512] __read_mostly;
469 unsigned int prom_trans_ents __read_mostly;
470
471 /* Exported for SMP bootup purposes. */
472 unsigned long kern_locked_tte_data;
473
474 /* The obp translations are saved based on 8k pagesize, since obp can
475 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
476 * HI_OBP_ADDRESS range are handled in ktlb.S.
477 */
478 static inline int in_obp_range(unsigned long vaddr)
479 {
480 return (vaddr >= LOW_OBP_ADDRESS &&
481 vaddr < HI_OBP_ADDRESS);
482 }
483
484 static int cmp_ptrans(const void *a, const void *b)
485 {
486 const struct linux_prom_translation *x = a, *y = b;
487
488 if (x->virt > y->virt)
489 return 1;
490 if (x->virt < y->virt)
491 return -1;
492 return 0;
493 }
494
495 /* Read OBP translations property into 'prom_trans[]'. */
496 static void __init read_obp_translations(void)
497 {
498 int n, node, ents, first, last, i;
499
500 node = prom_finddevice("/virtual-memory");
501 n = prom_getproplen(node, "translations");
502 if (unlikely(n == 0 || n == -1)) {
503 prom_printf("prom_mappings: Couldn't get size.\n");
504 prom_halt();
505 }
506 if (unlikely(n > sizeof(prom_trans))) {
507 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
508 prom_halt();
509 }
510
511 if ((n = prom_getproperty(node, "translations",
512 (char *)&prom_trans[0],
513 sizeof(prom_trans))) == -1) {
514 prom_printf("prom_mappings: Couldn't get property.\n");
515 prom_halt();
516 }
517
518 n = n / sizeof(struct linux_prom_translation);
519
520 ents = n;
521
522 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
523 cmp_ptrans, NULL);
524
525 /* Now kick out all the non-OBP entries. */
526 for (i = 0; i < ents; i++) {
527 if (in_obp_range(prom_trans[i].virt))
528 break;
529 }
530 first = i;
531 for (; i < ents; i++) {
532 if (!in_obp_range(prom_trans[i].virt))
533 break;
534 }
535 last = i;
536
537 for (i = 0; i < (last - first); i++) {
538 struct linux_prom_translation *src = &prom_trans[i + first];
539 struct linux_prom_translation *dest = &prom_trans[i];
540
541 *dest = *src;
542 }
543 for (; i < ents; i++) {
544 struct linux_prom_translation *dest = &prom_trans[i];
545 dest->virt = dest->size = dest->data = 0x0UL;
546 }
547
548 prom_trans_ents = last - first;
549
550 if (tlb_type == spitfire) {
551 /* Clear diag TTE bits. */
552 for (i = 0; i < prom_trans_ents; i++)
553 prom_trans[i].data &= ~0x0003fe0000000000UL;
554 }
555 }
556
557 static void __init hypervisor_tlb_lock(unsigned long vaddr,
558 unsigned long pte,
559 unsigned long mmu)
560 {
561 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
562
563 if (ret != 0) {
564 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
565 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
566 prom_halt();
567 }
568 }
569
570 static unsigned long kern_large_tte(unsigned long paddr);
571
572 static void __init remap_kernel(void)
573 {
574 unsigned long phys_page, tte_vaddr, tte_data;
575 int tlb_ent = sparc64_highest_locked_tlbent();
576
577 tte_vaddr = (unsigned long) KERNBASE;
578 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
579 tte_data = kern_large_tte(phys_page);
580
581 kern_locked_tte_data = tte_data;
582
583 /* Now lock us into the TLBs via Hypervisor or OBP. */
584 if (tlb_type == hypervisor) {
585 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
586 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
587 if (bigkernel) {
588 tte_vaddr += 0x400000;
589 tte_data += 0x400000;
590 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
591 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
592 }
593 } else {
594 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
595 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
596 if (bigkernel) {
597 tlb_ent -= 1;
598 prom_dtlb_load(tlb_ent,
599 tte_data + 0x400000,
600 tte_vaddr + 0x400000);
601 prom_itlb_load(tlb_ent,
602 tte_data + 0x400000,
603 tte_vaddr + 0x400000);
604 }
605 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
606 }
607 if (tlb_type == cheetah_plus) {
608 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
609 CTX_CHEETAH_PLUS_NUC);
610 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
611 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
612 }
613 }
614
615
616 static void __init inherit_prom_mappings(void)
617 {
618 read_obp_translations();
619
620 /* Now fixup OBP's idea about where we really are mapped. */
621 prom_printf("Remapping the kernel... ");
622 remap_kernel();
623 prom_printf("done.\n");
624 }
625
626 void prom_world(int enter)
627 {
628 if (!enter)
629 set_fs((mm_segment_t) { get_thread_current_ds() });
630
631 __asm__ __volatile__("flushw");
632 }
633
634 #ifdef DCACHE_ALIASING_POSSIBLE
635 void __flush_dcache_range(unsigned long start, unsigned long end)
636 {
637 unsigned long va;
638
639 if (tlb_type == spitfire) {
640 int n = 0;
641
642 for (va = start; va < end; va += 32) {
643 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
644 if (++n >= 512)
645 break;
646 }
647 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
648 start = __pa(start);
649 end = __pa(end);
650 for (va = start; va < end; va += 32)
651 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
652 "membar #Sync"
653 : /* no outputs */
654 : "r" (va),
655 "i" (ASI_DCACHE_INVALIDATE));
656 }
657 }
658 #endif /* DCACHE_ALIASING_POSSIBLE */
659
660 /* get_new_mmu_context() uses "cache + 1". */
661 DEFINE_SPINLOCK(ctx_alloc_lock);
662 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
663 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
664 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
665 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
666
667 /* Caller does TLB context flushing on local CPU if necessary.
668 * The caller also ensures that CTX_VALID(mm->context) is false.
669 *
670 * We must be careful about boundary cases so that we never
671 * let the user have CTX 0 (nucleus) or we ever use a CTX
672 * version of zero (and thus NO_CONTEXT would not be caught
673 * by version mis-match tests in mmu_context.h).
674 *
675 * Always invoked with interrupts disabled.
676 */
677 void get_new_mmu_context(struct mm_struct *mm)
678 {
679 unsigned long ctx, new_ctx;
680 unsigned long orig_pgsz_bits;
681 unsigned long flags;
682 int new_version;
683
684 spin_lock_irqsave(&ctx_alloc_lock, flags);
685 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
686 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
687 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
688 new_version = 0;
689 if (new_ctx >= (1 << CTX_NR_BITS)) {
690 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
691 if (new_ctx >= ctx) {
692 int i;
693 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
694 CTX_FIRST_VERSION;
695 if (new_ctx == 1)
696 new_ctx = CTX_FIRST_VERSION;
697
698 /* Don't call memset, for 16 entries that's just
699 * plain silly...
700 */
701 mmu_context_bmap[0] = 3;
702 mmu_context_bmap[1] = 0;
703 mmu_context_bmap[2] = 0;
704 mmu_context_bmap[3] = 0;
705 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
706 mmu_context_bmap[i + 0] = 0;
707 mmu_context_bmap[i + 1] = 0;
708 mmu_context_bmap[i + 2] = 0;
709 mmu_context_bmap[i + 3] = 0;
710 }
711 new_version = 1;
712 goto out;
713 }
714 }
715 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
716 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
717 out:
718 tlb_context_cache = new_ctx;
719 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
720 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
721
722 if (unlikely(new_version))
723 smp_new_mmu_context_version();
724 }
725
726 /* Find a free area for the bootmem map, avoiding the kernel image
727 * and the initial ramdisk.
728 */
729 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
730 unsigned long end_pfn)
731 {
732 unsigned long avoid_start, avoid_end, bootmap_size;
733 int i;
734
735 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
736 bootmap_size <<= PAGE_SHIFT;
737
738 avoid_start = avoid_end = 0;
739 #ifdef CONFIG_BLK_DEV_INITRD
740 avoid_start = initrd_start;
741 avoid_end = PAGE_ALIGN(initrd_end);
742 #endif
743
744 #ifdef CONFIG_DEBUG_BOOTMEM
745 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
746 kern_base, PAGE_ALIGN(kern_base + kern_size),
747 avoid_start, avoid_end);
748 #endif
749 for (i = 0; i < pavail_ents; i++) {
750 unsigned long start, end;
751
752 start = pavail[i].phys_addr;
753 end = start + pavail[i].reg_size;
754
755 while (start < end) {
756 if (start >= kern_base &&
757 start < PAGE_ALIGN(kern_base + kern_size)) {
758 start = PAGE_ALIGN(kern_base + kern_size);
759 continue;
760 }
761 if (start >= avoid_start && start < avoid_end) {
762 start = avoid_end;
763 continue;
764 }
765
766 if ((end - start) < bootmap_size)
767 break;
768
769 if (start < kern_base &&
770 (start + bootmap_size) > kern_base) {
771 start = PAGE_ALIGN(kern_base + kern_size);
772 continue;
773 }
774
775 if (start < avoid_start &&
776 (start + bootmap_size) > avoid_start) {
777 start = avoid_end;
778 continue;
779 }
780
781 /* OK, it doesn't overlap anything, use it. */
782 #ifdef CONFIG_DEBUG_BOOTMEM
783 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
784 start >> PAGE_SHIFT, start);
785 #endif
786 return start >> PAGE_SHIFT;
787 }
788 }
789
790 prom_printf("Cannot find free area for bootmap, aborting.\n");
791 prom_halt();
792 }
793
794 static void __init trim_pavail(unsigned long *cur_size_p,
795 unsigned long *end_of_phys_p)
796 {
797 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
798 unsigned long avoid_start, avoid_end;
799 int i;
800
801 to_trim = PAGE_ALIGN(to_trim);
802
803 avoid_start = avoid_end = 0;
804 #ifdef CONFIG_BLK_DEV_INITRD
805 avoid_start = initrd_start;
806 avoid_end = PAGE_ALIGN(initrd_end);
807 #endif
808
809 /* Trim some pavail[] entries in order to satisfy the
810 * requested "mem=xxx" kernel command line specification.
811 *
812 * We must not trim off the kernel image area nor the
813 * initial ramdisk range (if any). Also, we must not trim
814 * any pavail[] entry down to zero in order to preserve
815 * the invariant that all pavail[] entries have a non-zero
816 * size which is assumed by all of the code in here.
817 */
818 for (i = 0; i < pavail_ents; i++) {
819 unsigned long start, end, kern_end;
820 unsigned long trim_low, trim_high, n;
821
822 kern_end = PAGE_ALIGN(kern_base + kern_size);
823
824 trim_low = start = pavail[i].phys_addr;
825 trim_high = end = start + pavail[i].reg_size;
826
827 if (kern_base >= start &&
828 kern_base < end) {
829 trim_low = kern_base;
830 if (kern_end >= end)
831 continue;
832 }
833 if (kern_end >= start &&
834 kern_end < end) {
835 trim_high = kern_end;
836 }
837 if (avoid_start &&
838 avoid_start >= start &&
839 avoid_start < end) {
840 if (trim_low > avoid_start)
841 trim_low = avoid_start;
842 if (avoid_end >= end)
843 continue;
844 }
845 if (avoid_end &&
846 avoid_end >= start &&
847 avoid_end < end) {
848 if (trim_high < avoid_end)
849 trim_high = avoid_end;
850 }
851
852 if (trim_high <= trim_low)
853 continue;
854
855 if (trim_low == start && trim_high == end) {
856 /* Whole chunk is available for trimming.
857 * Trim all except one page, in order to keep
858 * entry non-empty.
859 */
860 n = (end - start) - PAGE_SIZE;
861 if (n > to_trim)
862 n = to_trim;
863
864 if (n) {
865 pavail[i].phys_addr += n;
866 pavail[i].reg_size -= n;
867 to_trim -= n;
868 }
869 } else {
870 n = (trim_low - start);
871 if (n > to_trim)
872 n = to_trim;
873
874 if (n) {
875 pavail[i].phys_addr += n;
876 pavail[i].reg_size -= n;
877 to_trim -= n;
878 }
879 if (to_trim) {
880 n = end - trim_high;
881 if (n > to_trim)
882 n = to_trim;
883 if (n) {
884 pavail[i].reg_size -= n;
885 to_trim -= n;
886 }
887 }
888 }
889
890 if (!to_trim)
891 break;
892 }
893
894 /* Recalculate. */
895 *cur_size_p = 0UL;
896 for (i = 0; i < pavail_ents; i++) {
897 *end_of_phys_p = pavail[i].phys_addr +
898 pavail[i].reg_size;
899 *cur_size_p += pavail[i].reg_size;
900 }
901 }
902
903 /* About pages_avail, this is the value we will use to calculate
904 * the zholes_size[] argument given to free_area_init_node(). The
905 * page allocator uses this to calculate nr_kernel_pages,
906 * nr_all_pages and zone->present_pages. On NUMA it is used
907 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
908 *
909 * So this number should really be set to what the page allocator
910 * actually ends up with. This means:
911 * 1) It should include bootmem map pages, we'll release those.
912 * 2) It should not include the kernel image, except for the
913 * __init sections which we will also release.
914 * 3) It should include the initrd image, since we'll release
915 * that too.
916 */
917 static unsigned long __init bootmem_init(unsigned long *pages_avail,
918 unsigned long phys_base)
919 {
920 unsigned long bootmap_size, end_pfn;
921 unsigned long end_of_phys_memory = 0UL;
922 unsigned long bootmap_pfn, bytes_avail, size;
923 int i;
924
925 #ifdef CONFIG_DEBUG_BOOTMEM
926 prom_printf("bootmem_init: Scan pavail, ");
927 #endif
928
929 bytes_avail = 0UL;
930 for (i = 0; i < pavail_ents; i++) {
931 end_of_phys_memory = pavail[i].phys_addr +
932 pavail[i].reg_size;
933 bytes_avail += pavail[i].reg_size;
934 }
935
936 /* Determine the location of the initial ramdisk before trying
937 * to honor the "mem=xxx" command line argument. We must know
938 * where the kernel image and the ramdisk image are so that we
939 * do not trim those two areas from the physical memory map.
940 */
941
942 #ifdef CONFIG_BLK_DEV_INITRD
943 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
944 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
945 unsigned long ramdisk_image = sparc_ramdisk_image ?
946 sparc_ramdisk_image : sparc_ramdisk_image64;
947 ramdisk_image -= KERNBASE;
948 initrd_start = ramdisk_image + phys_base;
949 initrd_end = initrd_start + sparc_ramdisk_size;
950 if (initrd_end > end_of_phys_memory) {
951 printk(KERN_CRIT "initrd extends beyond end of memory "
952 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
953 initrd_end, end_of_phys_memory);
954 initrd_start = 0;
955 initrd_end = 0;
956 }
957 }
958 #endif
959
960 if (cmdline_memory_size &&
961 bytes_avail > cmdline_memory_size)
962 trim_pavail(&bytes_avail,
963 &end_of_phys_memory);
964
965 *pages_avail = bytes_avail >> PAGE_SHIFT;
966
967 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
968
969 /* Initialize the boot-time allocator. */
970 max_pfn = max_low_pfn = end_pfn;
971 min_low_pfn = (phys_base >> PAGE_SHIFT);
972
973 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
974
975 #ifdef CONFIG_DEBUG_BOOTMEM
976 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
977 min_low_pfn, bootmap_pfn, max_low_pfn);
978 #endif
979 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
980 min_low_pfn, end_pfn);
981
982 /* Now register the available physical memory with the
983 * allocator.
984 */
985 for (i = 0; i < pavail_ents; i++) {
986 #ifdef CONFIG_DEBUG_BOOTMEM
987 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
988 i, pavail[i].phys_addr, pavail[i].reg_size);
989 #endif
990 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
991 }
992
993 #ifdef CONFIG_BLK_DEV_INITRD
994 if (initrd_start) {
995 size = initrd_end - initrd_start;
996
997 /* Reserve the initrd image area. */
998 #ifdef CONFIG_DEBUG_BOOTMEM
999 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1000 initrd_start, initrd_end);
1001 #endif
1002 reserve_bootmem(initrd_start, size);
1003
1004 initrd_start += PAGE_OFFSET;
1005 initrd_end += PAGE_OFFSET;
1006 }
1007 #endif
1008 /* Reserve the kernel text/data/bss. */
1009 #ifdef CONFIG_DEBUG_BOOTMEM
1010 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1011 #endif
1012 reserve_bootmem(kern_base, kern_size);
1013 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1014
1015 /* Add back in the initmem pages. */
1016 size = ((unsigned long)(__init_end) & PAGE_MASK) -
1017 PAGE_ALIGN((unsigned long)__init_begin);
1018 *pages_avail += size >> PAGE_SHIFT;
1019
1020 /* Reserve the bootmem map. We do not account for it
1021 * in pages_avail because we will release that memory
1022 * in free_all_bootmem.
1023 */
1024 size = bootmap_size;
1025 #ifdef CONFIG_DEBUG_BOOTMEM
1026 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1027 (bootmap_pfn << PAGE_SHIFT), size);
1028 #endif
1029 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1030
1031 for (i = 0; i < pavail_ents; i++) {
1032 unsigned long start_pfn, end_pfn;
1033
1034 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1035 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1036 #ifdef CONFIG_DEBUG_BOOTMEM
1037 prom_printf("memory_present(0, %lx, %lx)\n",
1038 start_pfn, end_pfn);
1039 #endif
1040 memory_present(0, start_pfn, end_pfn);
1041 }
1042
1043 sparse_init();
1044
1045 return end_pfn;
1046 }
1047
1048 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1049 static int pall_ents __initdata;
1050
1051 #ifdef CONFIG_DEBUG_PAGEALLOC
1052 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1053 {
1054 unsigned long vstart = PAGE_OFFSET + pstart;
1055 unsigned long vend = PAGE_OFFSET + pend;
1056 unsigned long alloc_bytes = 0UL;
1057
1058 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1059 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1060 vstart, vend);
1061 prom_halt();
1062 }
1063
1064 while (vstart < vend) {
1065 unsigned long this_end, paddr = __pa(vstart);
1066 pgd_t *pgd = pgd_offset_k(vstart);
1067 pud_t *pud;
1068 pmd_t *pmd;
1069 pte_t *pte;
1070
1071 pud = pud_offset(pgd, vstart);
1072 if (pud_none(*pud)) {
1073 pmd_t *new;
1074
1075 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1076 alloc_bytes += PAGE_SIZE;
1077 pud_populate(&init_mm, pud, new);
1078 }
1079
1080 pmd = pmd_offset(pud, vstart);
1081 if (!pmd_present(*pmd)) {
1082 pte_t *new;
1083
1084 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1085 alloc_bytes += PAGE_SIZE;
1086 pmd_populate_kernel(&init_mm, pmd, new);
1087 }
1088
1089 pte = pte_offset_kernel(pmd, vstart);
1090 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1091 if (this_end > vend)
1092 this_end = vend;
1093
1094 while (vstart < this_end) {
1095 pte_val(*pte) = (paddr | pgprot_val(prot));
1096
1097 vstart += PAGE_SIZE;
1098 paddr += PAGE_SIZE;
1099 pte++;
1100 }
1101 }
1102
1103 return alloc_bytes;
1104 }
1105
1106 extern unsigned int kvmap_linear_patch[1];
1107 #endif /* CONFIG_DEBUG_PAGEALLOC */
1108
1109 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1110 {
1111 const unsigned long shift_256MB = 28;
1112 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1113 const unsigned long size_256MB = (1UL << shift_256MB);
1114
1115 while (start < end) {
1116 long remains;
1117
1118 remains = end - start;
1119 if (remains < size_256MB)
1120 break;
1121
1122 if (start & mask_256MB) {
1123 start = (start + size_256MB) & ~mask_256MB;
1124 continue;
1125 }
1126
1127 while (remains >= size_256MB) {
1128 unsigned long index = start >> shift_256MB;
1129
1130 __set_bit(index, kpte_linear_bitmap);
1131
1132 start += size_256MB;
1133 remains -= size_256MB;
1134 }
1135 }
1136 }
1137
1138 static void __init kernel_physical_mapping_init(void)
1139 {
1140 unsigned long i;
1141 #ifdef CONFIG_DEBUG_PAGEALLOC
1142 unsigned long mem_alloced = 0UL;
1143 #endif
1144
1145 read_obp_memory("reg", &pall[0], &pall_ents);
1146
1147 for (i = 0; i < pall_ents; i++) {
1148 unsigned long phys_start, phys_end;
1149
1150 phys_start = pall[i].phys_addr;
1151 phys_end = phys_start + pall[i].reg_size;
1152
1153 mark_kpte_bitmap(phys_start, phys_end);
1154
1155 #ifdef CONFIG_DEBUG_PAGEALLOC
1156 mem_alloced += kernel_map_range(phys_start, phys_end,
1157 PAGE_KERNEL);
1158 #endif
1159 }
1160
1161 #ifdef CONFIG_DEBUG_PAGEALLOC
1162 printk("Allocated %ld bytes for kernel page tables.\n",
1163 mem_alloced);
1164
1165 kvmap_linear_patch[0] = 0x01000000; /* nop */
1166 flushi(&kvmap_linear_patch[0]);
1167
1168 __flush_tlb_all();
1169 #endif
1170 }
1171
1172 #ifdef CONFIG_DEBUG_PAGEALLOC
1173 void kernel_map_pages(struct page *page, int numpages, int enable)
1174 {
1175 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1176 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1177
1178 kernel_map_range(phys_start, phys_end,
1179 (enable ? PAGE_KERNEL : __pgprot(0)));
1180
1181 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1182 PAGE_OFFSET + phys_end);
1183
1184 /* we should perform an IPI and flush all tlbs,
1185 * but that can deadlock->flush only current cpu.
1186 */
1187 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1188 PAGE_OFFSET + phys_end);
1189 }
1190 #endif
1191
1192 unsigned long __init find_ecache_flush_span(unsigned long size)
1193 {
1194 int i;
1195
1196 for (i = 0; i < pavail_ents; i++) {
1197 if (pavail[i].reg_size >= size)
1198 return pavail[i].phys_addr;
1199 }
1200
1201 return ~0UL;
1202 }
1203
1204 static void __init tsb_phys_patch(void)
1205 {
1206 struct tsb_ldquad_phys_patch_entry *pquad;
1207 struct tsb_phys_patch_entry *p;
1208
1209 pquad = &__tsb_ldquad_phys_patch;
1210 while (pquad < &__tsb_ldquad_phys_patch_end) {
1211 unsigned long addr = pquad->addr;
1212
1213 if (tlb_type == hypervisor)
1214 *(unsigned int *) addr = pquad->sun4v_insn;
1215 else
1216 *(unsigned int *) addr = pquad->sun4u_insn;
1217 wmb();
1218 __asm__ __volatile__("flush %0"
1219 : /* no outputs */
1220 : "r" (addr));
1221
1222 pquad++;
1223 }
1224
1225 p = &__tsb_phys_patch;
1226 while (p < &__tsb_phys_patch_end) {
1227 unsigned long addr = p->addr;
1228
1229 *(unsigned int *) addr = p->insn;
1230 wmb();
1231 __asm__ __volatile__("flush %0"
1232 : /* no outputs */
1233 : "r" (addr));
1234
1235 p++;
1236 }
1237 }
1238
1239 /* Don't mark as init, we give this to the Hypervisor. */
1240 #ifndef CONFIG_DEBUG_PAGEALLOC
1241 #define NUM_KTSB_DESCR 2
1242 #else
1243 #define NUM_KTSB_DESCR 1
1244 #endif
1245 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1246 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1247
1248 static void __init sun4v_ktsb_init(void)
1249 {
1250 unsigned long ktsb_pa;
1251
1252 /* First KTSB for PAGE_SIZE mappings. */
1253 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1254
1255 switch (PAGE_SIZE) {
1256 case 8 * 1024:
1257 default:
1258 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1259 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1260 break;
1261
1262 case 64 * 1024:
1263 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1264 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1265 break;
1266
1267 case 512 * 1024:
1268 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1269 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1270 break;
1271
1272 case 4 * 1024 * 1024:
1273 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1274 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1275 break;
1276 };
1277
1278 ktsb_descr[0].assoc = 1;
1279 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1280 ktsb_descr[0].ctx_idx = 0;
1281 ktsb_descr[0].tsb_base = ktsb_pa;
1282 ktsb_descr[0].resv = 0;
1283
1284 #ifndef CONFIG_DEBUG_PAGEALLOC
1285 /* Second KTSB for 4MB/256MB mappings. */
1286 ktsb_pa = (kern_base +
1287 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1288
1289 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1290 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1291 HV_PGSZ_MASK_256MB);
1292 ktsb_descr[1].assoc = 1;
1293 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1294 ktsb_descr[1].ctx_idx = 0;
1295 ktsb_descr[1].tsb_base = ktsb_pa;
1296 ktsb_descr[1].resv = 0;
1297 #endif
1298 }
1299
1300 void __cpuinit sun4v_ktsb_register(void)
1301 {
1302 unsigned long pa, ret;
1303
1304 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1305
1306 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1307 if (ret != 0) {
1308 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1309 "errors with %lx\n", pa, ret);
1310 prom_halt();
1311 }
1312 }
1313
1314 /* paging_init() sets up the page tables */
1315
1316 extern void cheetah_ecache_flush_init(void);
1317 extern void sun4v_patch_tlb_handlers(void);
1318
1319 extern void cpu_probe(void);
1320 extern void central_probe(void);
1321
1322 static unsigned long last_valid_pfn;
1323 pgd_t swapper_pg_dir[2048];
1324
1325 static void sun4u_pgprot_init(void);
1326 static void sun4v_pgprot_init(void);
1327
1328 void __init paging_init(void)
1329 {
1330 unsigned long end_pfn, pages_avail, shift, phys_base;
1331 unsigned long real_end, i;
1332
1333 /* These build time checkes make sure that the dcache_dirty_cpu()
1334 * page->flags usage will work.
1335 *
1336 * When a page gets marked as dcache-dirty, we store the
1337 * cpu number starting at bit 32 in the page->flags. Also,
1338 * functions like clear_dcache_dirty_cpu use the cpu mask
1339 * in 13-bit signed-immediate instruction fields.
1340 */
1341 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1342 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1343 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1344 BUILD_BUG_ON(NR_CPUS > 4096);
1345
1346 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1347 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1348
1349 sstate_booting();
1350
1351 /* Invalidate both kernel TSBs. */
1352 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1353 #ifndef CONFIG_DEBUG_PAGEALLOC
1354 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1355 #endif
1356
1357 if (tlb_type == hypervisor)
1358 sun4v_pgprot_init();
1359 else
1360 sun4u_pgprot_init();
1361
1362 if (tlb_type == cheetah_plus ||
1363 tlb_type == hypervisor)
1364 tsb_phys_patch();
1365
1366 if (tlb_type == hypervisor) {
1367 sun4v_patch_tlb_handlers();
1368 sun4v_ktsb_init();
1369 }
1370
1371 /* Find available physical memory... */
1372 read_obp_memory("available", &pavail[0], &pavail_ents);
1373
1374 phys_base = 0xffffffffffffffffUL;
1375 for (i = 0; i < pavail_ents; i++)
1376 phys_base = min(phys_base, pavail[i].phys_addr);
1377
1378 set_bit(0, mmu_context_bmap);
1379
1380 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1381
1382 real_end = (unsigned long)_end;
1383 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1384 bigkernel = 1;
1385 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1386 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1387 prom_halt();
1388 }
1389
1390 /* Set kernel pgd to upper alias so physical page computations
1391 * work.
1392 */
1393 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1394
1395 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1396
1397 /* Now can init the kernel/bad page tables. */
1398 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1399 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1400
1401 inherit_prom_mappings();
1402
1403 /* Ok, we can use our TLB miss and window trap handlers safely. */
1404 setup_tba();
1405
1406 __flush_tlb_all();
1407
1408 if (tlb_type == hypervisor)
1409 sun4v_ktsb_register();
1410
1411 /* Setup bootmem... */
1412 pages_avail = 0;
1413 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1414
1415 max_mapnr = last_valid_pfn;
1416
1417 kernel_physical_mapping_init();
1418
1419 real_setup_per_cpu_areas();
1420
1421 prom_build_devicetree();
1422
1423 if (tlb_type == hypervisor)
1424 sun4v_mdesc_init();
1425
1426 {
1427 unsigned long zones_size[MAX_NR_ZONES];
1428 unsigned long zholes_size[MAX_NR_ZONES];
1429 int znum;
1430
1431 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1432 zones_size[znum] = zholes_size[znum] = 0;
1433
1434 zones_size[ZONE_NORMAL] = end_pfn;
1435 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1436
1437 free_area_init_node(0, &contig_page_data, zones_size,
1438 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1439 zholes_size);
1440 }
1441
1442 prom_printf("Booting Linux...\n");
1443
1444 central_probe();
1445 cpu_probe();
1446 }
1447
1448 static void __init taint_real_pages(void)
1449 {
1450 int i;
1451
1452 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1453
1454 /* Find changes discovered in the physmem available rescan and
1455 * reserve the lost portions in the bootmem maps.
1456 */
1457 for (i = 0; i < pavail_ents; i++) {
1458 unsigned long old_start, old_end;
1459
1460 old_start = pavail[i].phys_addr;
1461 old_end = old_start +
1462 pavail[i].reg_size;
1463 while (old_start < old_end) {
1464 int n;
1465
1466 for (n = 0; n < pavail_rescan_ents; n++) {
1467 unsigned long new_start, new_end;
1468
1469 new_start = pavail_rescan[n].phys_addr;
1470 new_end = new_start +
1471 pavail_rescan[n].reg_size;
1472
1473 if (new_start <= old_start &&
1474 new_end >= (old_start + PAGE_SIZE)) {
1475 set_bit(old_start >> 22,
1476 sparc64_valid_addr_bitmap);
1477 goto do_next_page;
1478 }
1479 }
1480 reserve_bootmem(old_start, PAGE_SIZE);
1481
1482 do_next_page:
1483 old_start += PAGE_SIZE;
1484 }
1485 }
1486 }
1487
1488 int __init page_in_phys_avail(unsigned long paddr)
1489 {
1490 int i;
1491
1492 paddr &= PAGE_MASK;
1493
1494 for (i = 0; i < pavail_rescan_ents; i++) {
1495 unsigned long start, end;
1496
1497 start = pavail_rescan[i].phys_addr;
1498 end = start + pavail_rescan[i].reg_size;
1499
1500 if (paddr >= start && paddr < end)
1501 return 1;
1502 }
1503 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1504 return 1;
1505 #ifdef CONFIG_BLK_DEV_INITRD
1506 if (paddr >= __pa(initrd_start) &&
1507 paddr < __pa(PAGE_ALIGN(initrd_end)))
1508 return 1;
1509 #endif
1510
1511 return 0;
1512 }
1513
1514 void __init mem_init(void)
1515 {
1516 unsigned long codepages, datapages, initpages;
1517 unsigned long addr, last;
1518 int i;
1519
1520 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1521 i += 1;
1522 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1523 if (sparc64_valid_addr_bitmap == NULL) {
1524 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1525 prom_halt();
1526 }
1527 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1528
1529 addr = PAGE_OFFSET + kern_base;
1530 last = PAGE_ALIGN(kern_size) + addr;
1531 while (addr < last) {
1532 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1533 addr += PAGE_SIZE;
1534 }
1535
1536 taint_real_pages();
1537
1538 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1539
1540 #ifdef CONFIG_DEBUG_BOOTMEM
1541 prom_printf("mem_init: Calling free_all_bootmem().\n");
1542 #endif
1543
1544 /* We subtract one to account for the mem_map_zero page
1545 * allocated below.
1546 */
1547 totalram_pages = num_physpages = free_all_bootmem() - 1;
1548
1549 /*
1550 * Set up the zero page, mark it reserved, so that page count
1551 * is not manipulated when freeing the page from user ptes.
1552 */
1553 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1554 if (mem_map_zero == NULL) {
1555 prom_printf("paging_init: Cannot alloc zero page.\n");
1556 prom_halt();
1557 }
1558 SetPageReserved(mem_map_zero);
1559
1560 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1561 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1562 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1563 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1564 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1565 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1566
1567 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1568 nr_free_pages() << (PAGE_SHIFT-10),
1569 codepages << (PAGE_SHIFT-10),
1570 datapages << (PAGE_SHIFT-10),
1571 initpages << (PAGE_SHIFT-10),
1572 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1573
1574 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1575 cheetah_ecache_flush_init();
1576 }
1577
1578 void free_initmem(void)
1579 {
1580 unsigned long addr, initend;
1581
1582 /*
1583 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1584 */
1585 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1586 initend = (unsigned long)(__init_end) & PAGE_MASK;
1587 for (; addr < initend; addr += PAGE_SIZE) {
1588 unsigned long page;
1589 struct page *p;
1590
1591 page = (addr +
1592 ((unsigned long) __va(kern_base)) -
1593 ((unsigned long) KERNBASE));
1594 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1595 p = virt_to_page(page);
1596
1597 ClearPageReserved(p);
1598 init_page_count(p);
1599 __free_page(p);
1600 num_physpages++;
1601 totalram_pages++;
1602 }
1603 }
1604
1605 #ifdef CONFIG_BLK_DEV_INITRD
1606 void free_initrd_mem(unsigned long start, unsigned long end)
1607 {
1608 if (start < end)
1609 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1610 for (; start < end; start += PAGE_SIZE) {
1611 struct page *p = virt_to_page(start);
1612
1613 ClearPageReserved(p);
1614 init_page_count(p);
1615 __free_page(p);
1616 num_physpages++;
1617 totalram_pages++;
1618 }
1619 }
1620 #endif
1621
1622 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1623 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1624 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1625 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1626 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1627 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1628
1629 pgprot_t PAGE_KERNEL __read_mostly;
1630 EXPORT_SYMBOL(PAGE_KERNEL);
1631
1632 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1633 pgprot_t PAGE_COPY __read_mostly;
1634
1635 pgprot_t PAGE_SHARED __read_mostly;
1636 EXPORT_SYMBOL(PAGE_SHARED);
1637
1638 pgprot_t PAGE_EXEC __read_mostly;
1639 unsigned long pg_iobits __read_mostly;
1640
1641 unsigned long _PAGE_IE __read_mostly;
1642 EXPORT_SYMBOL(_PAGE_IE);
1643
1644 unsigned long _PAGE_E __read_mostly;
1645 EXPORT_SYMBOL(_PAGE_E);
1646
1647 unsigned long _PAGE_CACHE __read_mostly;
1648 EXPORT_SYMBOL(_PAGE_CACHE);
1649
1650 static void prot_init_common(unsigned long page_none,
1651 unsigned long page_shared,
1652 unsigned long page_copy,
1653 unsigned long page_readonly,
1654 unsigned long page_exec_bit)
1655 {
1656 PAGE_COPY = __pgprot(page_copy);
1657 PAGE_SHARED = __pgprot(page_shared);
1658
1659 protection_map[0x0] = __pgprot(page_none);
1660 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1661 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1662 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1663 protection_map[0x4] = __pgprot(page_readonly);
1664 protection_map[0x5] = __pgprot(page_readonly);
1665 protection_map[0x6] = __pgprot(page_copy);
1666 protection_map[0x7] = __pgprot(page_copy);
1667 protection_map[0x8] = __pgprot(page_none);
1668 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1669 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1670 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1671 protection_map[0xc] = __pgprot(page_readonly);
1672 protection_map[0xd] = __pgprot(page_readonly);
1673 protection_map[0xe] = __pgprot(page_shared);
1674 protection_map[0xf] = __pgprot(page_shared);
1675 }
1676
1677 static void __init sun4u_pgprot_init(void)
1678 {
1679 unsigned long page_none, page_shared, page_copy, page_readonly;
1680 unsigned long page_exec_bit;
1681
1682 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1683 _PAGE_CACHE_4U | _PAGE_P_4U |
1684 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1685 _PAGE_EXEC_4U);
1686 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1687 _PAGE_CACHE_4U | _PAGE_P_4U |
1688 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1689 _PAGE_EXEC_4U | _PAGE_L_4U);
1690 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1691
1692 _PAGE_IE = _PAGE_IE_4U;
1693 _PAGE_E = _PAGE_E_4U;
1694 _PAGE_CACHE = _PAGE_CACHE_4U;
1695
1696 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1697 __ACCESS_BITS_4U | _PAGE_E_4U);
1698
1699 #ifdef CONFIG_DEBUG_PAGEALLOC
1700 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1701 0xfffff80000000000;
1702 #else
1703 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1704 0xfffff80000000000;
1705 #endif
1706 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1707 _PAGE_P_4U | _PAGE_W_4U);
1708
1709 /* XXX Should use 256MB on Panther. XXX */
1710 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1711
1712 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1713 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1714 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1715 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1716
1717
1718 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1719 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1720 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1721 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1722 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1723 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1724 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1725
1726 page_exec_bit = _PAGE_EXEC_4U;
1727
1728 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1729 page_exec_bit);
1730 }
1731
1732 static void __init sun4v_pgprot_init(void)
1733 {
1734 unsigned long page_none, page_shared, page_copy, page_readonly;
1735 unsigned long page_exec_bit;
1736
1737 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1738 _PAGE_CACHE_4V | _PAGE_P_4V |
1739 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1740 _PAGE_EXEC_4V);
1741 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1742 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1743
1744 _PAGE_IE = _PAGE_IE_4V;
1745 _PAGE_E = _PAGE_E_4V;
1746 _PAGE_CACHE = _PAGE_CACHE_4V;
1747
1748 #ifdef CONFIG_DEBUG_PAGEALLOC
1749 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1750 0xfffff80000000000;
1751 #else
1752 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1753 0xfffff80000000000;
1754 #endif
1755 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1756 _PAGE_P_4V | _PAGE_W_4V);
1757
1758 #ifdef CONFIG_DEBUG_PAGEALLOC
1759 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1760 0xfffff80000000000;
1761 #else
1762 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1763 0xfffff80000000000;
1764 #endif
1765 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1766 _PAGE_P_4V | _PAGE_W_4V);
1767
1768 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1769 __ACCESS_BITS_4V | _PAGE_E_4V);
1770
1771 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1772 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1773 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1774 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1775 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1776
1777 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1778 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1779 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1780 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1781 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1782 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1783 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1784
1785 page_exec_bit = _PAGE_EXEC_4V;
1786
1787 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1788 page_exec_bit);
1789 }
1790
1791 unsigned long pte_sz_bits(unsigned long sz)
1792 {
1793 if (tlb_type == hypervisor) {
1794 switch (sz) {
1795 case 8 * 1024:
1796 default:
1797 return _PAGE_SZ8K_4V;
1798 case 64 * 1024:
1799 return _PAGE_SZ64K_4V;
1800 case 512 * 1024:
1801 return _PAGE_SZ512K_4V;
1802 case 4 * 1024 * 1024:
1803 return _PAGE_SZ4MB_4V;
1804 };
1805 } else {
1806 switch (sz) {
1807 case 8 * 1024:
1808 default:
1809 return _PAGE_SZ8K_4U;
1810 case 64 * 1024:
1811 return _PAGE_SZ64K_4U;
1812 case 512 * 1024:
1813 return _PAGE_SZ512K_4U;
1814 case 4 * 1024 * 1024:
1815 return _PAGE_SZ4MB_4U;
1816 };
1817 }
1818 }
1819
1820 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1821 {
1822 pte_t pte;
1823
1824 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1825 pte_val(pte) |= (((unsigned long)space) << 32);
1826 pte_val(pte) |= pte_sz_bits(page_size);
1827
1828 return pte;
1829 }
1830
1831 static unsigned long kern_large_tte(unsigned long paddr)
1832 {
1833 unsigned long val;
1834
1835 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1836 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1837 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1838 if (tlb_type == hypervisor)
1839 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1840 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1841 _PAGE_EXEC_4V | _PAGE_W_4V);
1842
1843 return val | paddr;
1844 }
1845
1846 /* If not locked, zap it. */
1847 void __flush_tlb_all(void)
1848 {
1849 unsigned long pstate;
1850 int i;
1851
1852 __asm__ __volatile__("flushw\n\t"
1853 "rdpr %%pstate, %0\n\t"
1854 "wrpr %0, %1, %%pstate"
1855 : "=r" (pstate)
1856 : "i" (PSTATE_IE));
1857 if (tlb_type == spitfire) {
1858 for (i = 0; i < 64; i++) {
1859 /* Spitfire Errata #32 workaround */
1860 /* NOTE: Always runs on spitfire, so no
1861 * cheetah+ page size encodings.
1862 */
1863 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1864 "flush %%g6"
1865 : /* No outputs */
1866 : "r" (0),
1867 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1868
1869 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1870 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1871 "membar #Sync"
1872 : /* no outputs */
1873 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1874 spitfire_put_dtlb_data(i, 0x0UL);
1875 }
1876
1877 /* Spitfire Errata #32 workaround */
1878 /* NOTE: Always runs on spitfire, so no
1879 * cheetah+ page size encodings.
1880 */
1881 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1882 "flush %%g6"
1883 : /* No outputs */
1884 : "r" (0),
1885 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1886
1887 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1888 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1889 "membar #Sync"
1890 : /* no outputs */
1891 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1892 spitfire_put_itlb_data(i, 0x0UL);
1893 }
1894 }
1895 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1896 cheetah_flush_dtlb_all();
1897 cheetah_flush_itlb_all();
1898 }
1899 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1900 : : "r" (pstate));
1901 }
1902
1903 #ifdef CONFIG_MEMORY_HOTPLUG
1904
1905 void online_page(struct page *page)
1906 {
1907 ClearPageReserved(page);
1908 init_page_count(page);
1909 __free_page(page);
1910 totalram_pages++;
1911 num_physpages++;
1912 }
1913
1914 int remove_memory(u64 start, u64 size)
1915 {
1916 return -EINVAL;
1917 }
1918
1919 #endif /* CONFIG_MEMORY_HOTPLUG */
WRT350N Kernel Patches