arch/arm/mach-at91/at91cap9.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/arch/at91cap9.h>
  20 #include <asm/arch/at91_pmc.h>
  21 #include <asm/arch/at91_rstc.h>
  22
  23 #include "generic.h"
  24 #include "clock.h"
  25
  26 static struct map_desc at91cap9_io_desc[] __initdata = {
  27         {
  28                 .virtual        = AT91_VA_BASE_SYS,
  29                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  30                 .length         = SZ_16K,
  31                 .type           = MT_DEVICE,
  32         }, {
  33                 .virtual        = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
  34                 .pfn            = __phys_to_pfn(AT91CAP9_SRAM_BASE),
  35                 .length         = AT91CAP9_SRAM_SIZE,
  36                 .type           = MT_DEVICE,
  37         },
  38 };
  39
  40 /* --------------------------------------------------------------------
  41  *  Clocks
  42  * -------------------------------------------------------------------- */
  43
  44 /*
  45  * The peripheral clocks.
  46  */
  47 static struct clk pioABCD_clk = {
  48         .name           = "pioABCD_clk",
  49         .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
  50         .type           = CLK_TYPE_PERIPHERAL,
  51 };
  52 static struct clk mpb0_clk = {
  53         .name           = "mpb0_clk",
  54         .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk mpb1_clk = {
  58         .name           = "mpb1_clk",
  59         .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62 static struct clk mpb2_clk = {
  63         .name           = "mpb2_clk",
  64         .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
  65         .type           = CLK_TYPE_PERIPHERAL,
  66 };
  67 static struct clk mpb3_clk = {
  68         .name           = "mpb3_clk",
  69         .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
  70         .type           = CLK_TYPE_PERIPHERAL,
  71 };
  72 static struct clk mpb4_clk = {
  73         .name           = "mpb4_clk",
  74         .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk usart0_clk = {
  78         .name           = "usart0_clk",
  79         .pmc_mask       = 1 << AT91CAP9_ID_US0,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk usart1_clk = {
  83         .name           = "usart1_clk",
  84         .pmc_mask       = 1 << AT91CAP9_ID_US1,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk usart2_clk = {
  88         .name           = "usart2_clk",
  89         .pmc_mask       = 1 << AT91CAP9_ID_US2,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk mmc0_clk = {
  93         .name           = "mci0_clk",
  94         .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk mmc1_clk = {
  98         .name           = "mci1_clk",
  99         .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk can_clk = {
 103         .name           = "can_clk",
 104         .pmc_mask       = 1 << AT91CAP9_ID_CAN,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk twi_clk = {
 108         .name           = "twi_clk",
 109         .pmc_mask       = 1 << AT91CAP9_ID_TWI,
 110         .type           = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk spi0_clk = {
 113         .name           = "spi0_clk",
 114         .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
 115         .type           = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk spi1_clk = {
 118         .name           = "spi1_clk",
 119         .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk ssc0_clk = {
 123         .name           = "ssc0_clk",
 124         .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk ssc1_clk = {
 128         .name           = "ssc1_clk",
 129         .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132 static struct clk ac97_clk = {
 133         .name           = "ac97_clk",
 134         .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
 135         .type           = CLK_TYPE_PERIPHERAL,
 136 };
 137 static struct clk tcb_clk = {
 138         .name           = "tcb_clk",
 139         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
 140         .type           = CLK_TYPE_PERIPHERAL,
 141 };
 142 static struct clk pwmc_clk = {
 143         .name           = "pwmc_clk",
 144         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
 145         .type           = CLK_TYPE_PERIPHERAL,
 146 };
 147 static struct clk macb_clk = {
 148         .name           = "macb_clk",
 149         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
 150         .type           = CLK_TYPE_PERIPHERAL,
 151 };
 152 static struct clk aestdes_clk = {
 153         .name           = "aestdes_clk",
 154         .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
 155         .type           = CLK_TYPE_PERIPHERAL,
 156 };
 157 static struct clk adc_clk = {
 158         .name           = "adc_clk",
 159         .pmc_mask       = 1 << AT91CAP9_ID_ADC,
 160         .type           = CLK_TYPE_PERIPHERAL,
 161 };
 162 static struct clk isi_clk = {
 163         .name           = "isi_clk",
 164         .pmc_mask       = 1 << AT91CAP9_ID_ISI,
 165         .type           = CLK_TYPE_PERIPHERAL,
 166 };
 167 static struct clk lcdc_clk = {
 168         .name           = "lcdc_clk",
 169         .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
 170         .type           = CLK_TYPE_PERIPHERAL,
 171 };
 172 static struct clk dma_clk = {
 173         .name           = "dma_clk",
 174         .pmc_mask       = 1 << AT91CAP9_ID_DMA,
 175         .type           = CLK_TYPE_PERIPHERAL,
 176 };
 177 static struct clk udphs_clk = {
 178         .name           = "udphs_clk",
 179         .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
 180         .type           = CLK_TYPE_PERIPHERAL,
 181 };
 182 static struct clk ohci_clk = {
 183         .name           = "ohci_clk",
 184         .pmc_mask       = 1 << AT91CAP9_ID_UHP,
 185         .type           = CLK_TYPE_PERIPHERAL,
 186 };
 187
 188 static struct clk *periph_clocks[] __initdata = {
 189         &pioABCD_clk,
 190         &mpb0_clk,
 191         &mpb1_clk,
 192         &mpb2_clk,
 193         &mpb3_clk,
 194         &mpb4_clk,
 195         &usart0_clk,
 196         &usart1_clk,
 197         &usart2_clk,
 198         &mmc0_clk,
 199         &mmc1_clk,
 200         &can_clk,
 201         &twi_clk,
 202         &spi0_clk,
 203         &spi1_clk,
 204         &ssc0_clk,
 205         &ssc1_clk,
 206         &ac97_clk,
 207         &tcb_clk,
 208         &pwmc_clk,
 209         &macb_clk,
 210         &aestdes_clk,
 211         &adc_clk,
 212         &isi_clk,
 213         &lcdc_clk,
 214         &dma_clk,
 215         &udphs_clk,
 216         &ohci_clk,
 217         // irq0 .. irq1
 218 };
 219
 220 /*
 221  * The four programmable clocks.
 222  * You must configure pin multiplexing to bring these signals out.
 223  */
 224 static struct clk pck0 = {
 225         .name           = "pck0",
 226         .pmc_mask       = AT91_PMC_PCK0,
 227         .type           = CLK_TYPE_PROGRAMMABLE,
 228         .id             = 0,
 229 };
 230 static struct clk pck1 = {
 231         .name           = "pck1",
 232         .pmc_mask       = AT91_PMC_PCK1,
 233         .type           = CLK_TYPE_PROGRAMMABLE,
 234         .id             = 1,
 235 };
 236 static struct clk pck2 = {
 237         .name           = "pck2",
 238         .pmc_mask       = AT91_PMC_PCK2,
 239         .type           = CLK_TYPE_PROGRAMMABLE,
 240         .id             = 2,
 241 };
 242 static struct clk pck3 = {
 243         .name           = "pck3",
 244         .pmc_mask       = AT91_PMC_PCK3,
 245         .type           = CLK_TYPE_PROGRAMMABLE,
 246         .id             = 3,
 247 };
 248
 249 static void __init at91cap9_register_clocks(void)
 250 {
 251         int i;
 252
 253         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 254                 clk_register(periph_clocks[i]);
 255
 256         clk_register(&pck0);
 257         clk_register(&pck1);
 258         clk_register(&pck2);
 259         clk_register(&pck3);
 260 }
 261
 262 /* --------------------------------------------------------------------
 263  *  GPIO
 264  * -------------------------------------------------------------------- */
 265
 266 static struct at91_gpio_bank at91cap9_gpio[] = {
 267         {
 268                 .id             = AT91CAP9_ID_PIOABCD,
 269                 .offset         = AT91_PIOA,
 270                 .clock          = &pioABCD_clk,
 271         }, {
 272                 .id             = AT91CAP9_ID_PIOABCD,
 273                 .offset         = AT91_PIOB,
 274                 .clock          = &pioABCD_clk,
 275         }, {
 276                 .id             = AT91CAP9_ID_PIOABCD,
 277                 .offset         = AT91_PIOC,
 278                 .clock          = &pioABCD_clk,
 279         }, {
 280                 .id             = AT91CAP9_ID_PIOABCD,
 281                 .offset         = AT91_PIOD,
 282                 .clock          = &pioABCD_clk,
 283         }
 284 };
 285
 286 static void at91cap9_reset(void)
 287 {
 288         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 289 }
 290
 291 /* --------------------------------------------------------------------
 292  *  AT91CAP9 processor initialization
 293  * -------------------------------------------------------------------- */
 294
 295 void __init at91cap9_initialize(unsigned long main_clock)
 296 {
 297         /* Map peripherals */
 298         iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
 299
 300         at91_arch_reset = at91cap9_reset;
 301         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 302
 303         /* Init clock subsystem */
 304         at91_clock_init(main_clock);
 305
 306         /* Register the processor-specific clocks */
 307         at91cap9_register_clocks();
 308
 309         /* Register GPIO subsystem */
 310         at91_gpio_init(at91cap9_gpio, 4);
 311 }
 312
 313 /* --------------------------------------------------------------------
 314  *  Interrupt initialization
 315  * -------------------------------------------------------------------- */
 316
 317 /*
 318  * The default interrupt priority levels (0 = lowest, 7 = highest).
 319  */
 320 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 321         7,      /* Advanced Interrupt Controller (FIQ) */
 322         7,      /* System Peripherals */
 323         1,      /* Parallel IO Controller A, B, C and D */
 324         0,      /* MP Block Peripheral 0 */
 325         0,      /* MP Block Peripheral 1 */
 326         0,      /* MP Block Peripheral 2 */
 327         0,      /* MP Block Peripheral 3 */
 328         0,      /* MP Block Peripheral 4 */
 329         5,      /* USART 0 */
 330         5,      /* USART 1 */
 331         5,      /* USART 2 */
 332         0,      /* Multimedia Card Interface 0 */
 333         0,      /* Multimedia Card Interface 1 */
 334         3,      /* CAN */
 335         6,      /* Two-Wire Interface */
 336         5,      /* Serial Peripheral Interface 0 */
 337         5,      /* Serial Peripheral Interface 1 */
 338         4,      /* Serial Synchronous Controller 0 */
 339         4,      /* Serial Synchronous Controller 1 */
 340         5,      /* AC97 Controller */
 341         0,      /* Timer Counter 0, 1 and 2 */
 342         0,      /* Pulse Width Modulation Controller */
 343         3,      /* Ethernet */
 344         0,      /* Advanced Encryption Standard, Triple DES*/
 345         0,      /* Analog-to-Digital Converter */
 346         0,      /* Image Sensor Interface */
 347         3,      /* LCD Controller */
 348         0,      /* DMA Controller */
 349         2,      /* USB Device Port */
 350         2,      /* USB Host port */
 351         0,      /* Advanced Interrupt Controller (IRQ0) */
 352         0,      /* Advanced Interrupt Controller (IRQ1) */
 353 };
 354
 355 void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 356 {
 357         if (!priority)
 358                 priority = at91cap9_default_irq_priority;
 359
 360         /* Initialize the AIC interrupt controller */
 361         at91_aic_init(priority);
 362
 363         /* Enable GPIO interrupts */
 364         at91_gpio_irq_setup();
 365 }