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x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / arm / mach-at91 / at91sam9260_devices.c
blob105f8403860bbd648842bf2e1479b165262d38fb
1 /*
2 * arch/arm/mach-at91/at91sam9260_devices.c
3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <asm/arch/board.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/at91sam9260.h>
22 #include <asm/arch/at91sam926x_mc.h>
23 #include <asm/arch/at91sam9260_matrix.h>
24
25 #include "generic.h"
26
27
28 /* --------------------------------------------------------------------
29 * USB Host
30 * -------------------------------------------------------------------- */
31
32 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
33 static u64 ohci_dmamask = DMA_BIT_MASK(32);
34 static struct at91_usbh_data usbh_data;
35
36 static struct resource usbh_resources[] = {
37 [0] = {
38 .start = AT91SAM9260_UHP_BASE,
39 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
40 .flags = IORESOURCE_MEM,
41 },
42 [1] = {
43 .start = AT91SAM9260_ID_UHP,
44 .end = AT91SAM9260_ID_UHP,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 static struct platform_device at91_usbh_device = {
50 .name = "at91_ohci",
51 .id = -1,
52 .dev = {
53 .dma_mask = &ohci_dmamask,
54 .coherent_dma_mask = DMA_BIT_MASK(32),
55 .platform_data = &usbh_data,
56 },
57 .resource = usbh_resources,
58 .num_resources = ARRAY_SIZE(usbh_resources),
59 };
60
61 void __init at91_add_device_usbh(struct at91_usbh_data *data)
62 {
63 if (!data)
64 return;
65
66 usbh_data = *data;
67 platform_device_register(&at91_usbh_device);
68 }
69 #else
70 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
71 #endif
72
73
74 /* --------------------------------------------------------------------
75 * USB Device (Gadget)
76 * -------------------------------------------------------------------- */
77
78 #ifdef CONFIG_USB_GADGET_AT91
79 static struct at91_udc_data udc_data;
80
81 static struct resource udc_resources[] = {
82 [0] = {
83 .start = AT91SAM9260_BASE_UDP,
84 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 [1] = {
88 .start = AT91SAM9260_ID_UDP,
89 .end = AT91SAM9260_ID_UDP,
90 .flags = IORESOURCE_IRQ,
91 },
92 };
93
94 static struct platform_device at91_udc_device = {
95 .name = "at91_udc",
96 .id = -1,
97 .dev = {
98 .platform_data = &udc_data,
99 },
100 .resource = udc_resources,
101 .num_resources = ARRAY_SIZE(udc_resources),
102 };
103
104 void __init at91_add_device_udc(struct at91_udc_data *data)
105 {
106 if (!data)
107 return;
108
109 if (data->vbus_pin) {
110 at91_set_gpio_input(data->vbus_pin, 0);
111 at91_set_deglitch(data->vbus_pin, 1);
112 }
113
114 /* Pullup pin is handled internally by USB device peripheral */
115
116 udc_data = *data;
117 platform_device_register(&at91_udc_device);
118 }
119 #else
120 void __init at91_add_device_udc(struct at91_udc_data *data) {}
121 #endif
122
123
124 /* --------------------------------------------------------------------
125 * Ethernet
126 * -------------------------------------------------------------------- */
127
128 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
129 static u64 eth_dmamask = DMA_BIT_MASK(32);
130 static struct at91_eth_data eth_data;
131
132 static struct resource eth_resources[] = {
133 [0] = {
134 .start = AT91SAM9260_BASE_EMAC,
135 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = AT91SAM9260_ID_EMAC,
140 .end = AT91SAM9260_ID_EMAC,
141 .flags = IORESOURCE_IRQ,
142 },
143 };
144
145 static struct platform_device at91sam9260_eth_device = {
146 .name = "macb",
147 .id = -1,
148 .dev = {
149 .dma_mask = &eth_dmamask,
150 .coherent_dma_mask = DMA_BIT_MASK(32),
151 .platform_data = &eth_data,
152 },
153 .resource = eth_resources,
154 .num_resources = ARRAY_SIZE(eth_resources),
155 };
156
157 void __init at91_add_device_eth(struct at91_eth_data *data)
158 {
159 if (!data)
160 return;
161
162 if (data->phy_irq_pin) {
163 at91_set_gpio_input(data->phy_irq_pin, 0);
164 at91_set_deglitch(data->phy_irq_pin, 1);
165 }
166
167 /* Pins used for MII and RMII */
168 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
169 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
170 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
171 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
172 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
173 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
174 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
175 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
176 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
177 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
178
179 if (!data->is_rmii) {
180 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
181 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
182 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
183 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
184 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
185 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
186 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
187 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
188 }
189
190 eth_data = *data;
191 platform_device_register(&at91sam9260_eth_device);
192 }
193 #else
194 void __init at91_add_device_eth(struct at91_eth_data *data) {}
195 #endif
196
197
198 /* --------------------------------------------------------------------
199 * MMC / SD
200 * -------------------------------------------------------------------- */
201
202 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
203 static u64 mmc_dmamask = DMA_BIT_MASK(32);
204 static struct at91_mmc_data mmc_data;
205
206 static struct resource mmc_resources[] = {
207 [0] = {
208 .start = AT91SAM9260_BASE_MCI,
209 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = AT91SAM9260_ID_MCI,
214 .end = AT91SAM9260_ID_MCI,
215 .flags = IORESOURCE_IRQ,
216 },
217 };
218
219 static struct platform_device at91sam9260_mmc_device = {
220 .name = "at91_mci",
221 .id = -1,
222 .dev = {
223 .dma_mask = &mmc_dmamask,
224 .coherent_dma_mask = DMA_BIT_MASK(32),
225 .platform_data = &mmc_data,
226 },
227 .resource = mmc_resources,
228 .num_resources = ARRAY_SIZE(mmc_resources),
229 };
230
231 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
232 {
233 if (!data)
234 return;
235
236 /* input/irq */
237 if (data->det_pin) {
238 at91_set_gpio_input(data->det_pin, 1);
239 at91_set_deglitch(data->det_pin, 1);
240 }
241 if (data->wp_pin)
242 at91_set_gpio_input(data->wp_pin, 1);
243 if (data->vcc_pin)
244 at91_set_gpio_output(data->vcc_pin, 0);
245
246 /* CLK */
247 at91_set_A_periph(AT91_PIN_PA8, 0);
248
249 if (data->slot_b) {
250 /* CMD */
251 at91_set_B_periph(AT91_PIN_PA1, 1);
252
253 /* DAT0, maybe DAT1..DAT3 */
254 at91_set_B_periph(AT91_PIN_PA0, 1);
255 if (data->wire4) {
256 at91_set_B_periph(AT91_PIN_PA5, 1);
257 at91_set_B_periph(AT91_PIN_PA4, 1);
258 at91_set_B_periph(AT91_PIN_PA3, 1);
259 }
260 } else {
261 /* CMD */
262 at91_set_A_periph(AT91_PIN_PA7, 1);
263
264 /* DAT0, maybe DAT1..DAT3 */
265 at91_set_A_periph(AT91_PIN_PA6, 1);
266 if (data->wire4) {
267 at91_set_A_periph(AT91_PIN_PA9, 1);
268 at91_set_A_periph(AT91_PIN_PA10, 1);
269 at91_set_A_periph(AT91_PIN_PA11, 1);
270 }
271 }
272
273 mmc_data = *data;
274 platform_device_register(&at91sam9260_mmc_device);
275 }
276 #else
277 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
278 #endif
279
280
281 /* --------------------------------------------------------------------
282 * NAND / SmartMedia
283 * -------------------------------------------------------------------- */
284
285 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
286 static struct at91_nand_data nand_data;
287
288 #define NAND_BASE AT91_CHIPSELECT_3
289
290 static struct resource nand_resources[] = {
291 {
292 .start = NAND_BASE,
293 .end = NAND_BASE + SZ_256M - 1,
294 .flags = IORESOURCE_MEM,
295 }
296 };
297
298 static struct platform_device at91sam9260_nand_device = {
299 .name = "at91_nand",
300 .id = -1,
301 .dev = {
302 .platform_data = &nand_data,
303 },
304 .resource = nand_resources,
305 .num_resources = ARRAY_SIZE(nand_resources),
306 };
307
308 void __init at91_add_device_nand(struct at91_nand_data *data)
309 {
310 unsigned long csa, mode;
311
312 if (!data)
313 return;
314
315 csa = at91_sys_read(AT91_MATRIX_EBICSA);
316 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
317
318 /* set the bus interface characteristics */
319 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
320 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
321
322 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
323 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
324
325 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
326
327 if (data->bus_width_16)
328 mode = AT91_SMC_DBW_16;
329 else
330 mode = AT91_SMC_DBW_8;
331 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
332
333 /* enable pin */
334 if (data->enable_pin)
335 at91_set_gpio_output(data->enable_pin, 1);
336
337 /* ready/busy pin */
338 if (data->rdy_pin)
339 at91_set_gpio_input(data->rdy_pin, 1);
340
341 /* card detect pin */
342 if (data->det_pin)
343 at91_set_gpio_input(data->det_pin, 1);
344
345 nand_data = *data;
346 platform_device_register(&at91sam9260_nand_device);
347 }
348 #else
349 void __init at91_add_device_nand(struct at91_nand_data *data) {}
350 #endif
351
352
353 /* --------------------------------------------------------------------
354 * TWI (i2c)
355 * -------------------------------------------------------------------- */
356
357 /*
358 * Prefer the GPIO code since the TWI controller isn't robust
359 * (gets overruns and underruns under load) and can only issue
360 * repeated STARTs in one scenario (the driver doesn't yet handle them).
361 */
362
363 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
364
365 static struct i2c_gpio_platform_data pdata = {
366 .sda_pin = AT91_PIN_PA23,
367 .sda_is_open_drain = 1,
368 .scl_pin = AT91_PIN_PA24,
369 .scl_is_open_drain = 1,
370 .udelay = 2, /* ~100 kHz */
371 };
372
373 static struct platform_device at91sam9260_twi_device = {
374 .name = "i2c-gpio",
375 .id = -1,
376 .dev.platform_data = &pdata,
377 };
378
379 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
380 {
381 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
382 at91_set_multi_drive(AT91_PIN_PA23, 1);
383
384 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
385 at91_set_multi_drive(AT91_PIN_PA24, 1);
386
387 i2c_register_board_info(0, devices, nr_devices);
388 platform_device_register(&at91sam9260_twi_device);
389 }
390
391 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
392
393 static struct resource twi_resources[] = {
394 [0] = {
395 .start = AT91SAM9260_BASE_TWI,
396 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
397 .flags = IORESOURCE_MEM,
398 },
399 [1] = {
400 .start = AT91SAM9260_ID_TWI,
401 .end = AT91SAM9260_ID_TWI,
402 .flags = IORESOURCE_IRQ,
403 },
404 };
405
406 static struct platform_device at91sam9260_twi_device = {
407 .name = "at91_i2c",
408 .id = -1,
409 .resource = twi_resources,
410 .num_resources = ARRAY_SIZE(twi_resources),
411 };
412
413 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
414 {
415 /* pins used for TWI interface */
416 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
417 at91_set_multi_drive(AT91_PIN_PA23, 1);
418
419 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
420 at91_set_multi_drive(AT91_PIN_PA24, 1);
421
422 i2c_register_board_info(0, devices, nr_devices);
423 platform_device_register(&at91sam9260_twi_device);
424 }
425 #else
426 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
427 #endif
428
429
430 /* --------------------------------------------------------------------
431 * SPI
432 * -------------------------------------------------------------------- */
433
434 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
435 static u64 spi_dmamask = DMA_BIT_MASK(32);
436
437 static struct resource spi0_resources[] = {
438 [0] = {
439 .start = AT91SAM9260_BASE_SPI0,
440 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 [1] = {
444 .start = AT91SAM9260_ID_SPI0,
445 .end = AT91SAM9260_ID_SPI0,
446 .flags = IORESOURCE_IRQ,
447 },
448 };
449
450 static struct platform_device at91sam9260_spi0_device = {
451 .name = "atmel_spi",
452 .id = 0,
453 .dev = {
454 .dma_mask = &spi_dmamask,
455 .coherent_dma_mask = DMA_BIT_MASK(32),
456 },
457 .resource = spi0_resources,
458 .num_resources = ARRAY_SIZE(spi0_resources),
459 };
460
461 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
462
463 static struct resource spi1_resources[] = {
464 [0] = {
465 .start = AT91SAM9260_BASE_SPI1,
466 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
467 .flags = IORESOURCE_MEM,
468 },
469 [1] = {
470 .start = AT91SAM9260_ID_SPI1,
471 .end = AT91SAM9260_ID_SPI1,
472 .flags = IORESOURCE_IRQ,
473 },
474 };
475
476 static struct platform_device at91sam9260_spi1_device = {
477 .name = "atmel_spi",
478 .id = 1,
479 .dev = {
480 .dma_mask = &spi_dmamask,
481 .coherent_dma_mask = DMA_BIT_MASK(32),
482 },
483 .resource = spi1_resources,
484 .num_resources = ARRAY_SIZE(spi1_resources),
485 };
486
487 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
488
489 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
490 {
491 int i;
492 unsigned long cs_pin;
493 short enable_spi0 = 0;
494 short enable_spi1 = 0;
495
496 /* Choose SPI chip-selects */
497 for (i = 0; i < nr_devices; i++) {
498 if (devices[i].controller_data)
499 cs_pin = (unsigned long) devices[i].controller_data;
500 else if (devices[i].bus_num == 0)
501 cs_pin = spi0_standard_cs[devices[i].chip_select];
502 else
503 cs_pin = spi1_standard_cs[devices[i].chip_select];
504
505 if (devices[i].bus_num == 0)
506 enable_spi0 = 1;
507 else
508 enable_spi1 = 1;
509
510 /* enable chip-select pin */
511 at91_set_gpio_output(cs_pin, 1);
512
513 /* pass chip-select pin to driver */
514 devices[i].controller_data = (void *) cs_pin;
515 }
516
517 spi_register_board_info(devices, nr_devices);
518
519 /* Configure SPI bus(es) */
520 if (enable_spi0) {
521 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
522 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
523 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
524
525 at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
526 platform_device_register(&at91sam9260_spi0_device);
527 }
528 if (enable_spi1) {
529 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
530 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
531 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
532
533 at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
534 platform_device_register(&at91sam9260_spi1_device);
535 }
536 }
537 #else
538 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
539 #endif
540
541
542 /* --------------------------------------------------------------------
543 * RTT
544 * -------------------------------------------------------------------- */
545
546 static struct resource rtt_resources[] = {
547 {
548 .start = AT91_BASE_SYS + AT91_RTT,
549 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
550 .flags = IORESOURCE_MEM,
551 }
552 };
553
554 static struct platform_device at91sam9260_rtt_device = {
555 .name = "at91_rtt",
556 .id = -1,
557 .resource = rtt_resources,
558 .num_resources = ARRAY_SIZE(rtt_resources),
559 };
560
561 static void __init at91_add_device_rtt(void)
562 {
563 platform_device_register(&at91sam9260_rtt_device);
564 }
565
566
567 /* --------------------------------------------------------------------
568 * Watchdog
569 * -------------------------------------------------------------------- */
570
571 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
572 static struct platform_device at91sam9260_wdt_device = {
573 .name = "at91_wdt",
574 .id = -1,
575 .num_resources = 0,
576 };
577
578 static void __init at91_add_device_watchdog(void)
579 {
580 platform_device_register(&at91sam9260_wdt_device);
581 }
582 #else
583 static void __init at91_add_device_watchdog(void) {}
584 #endif
585
586
587 /* --------------------------------------------------------------------
588 * SSC -- Synchronous Serial Controller
589 * -------------------------------------------------------------------- */
590
591 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
592 static u64 ssc_dmamask = DMA_BIT_MASK(32);
593
594 static struct resource ssc_resources[] = {
595 [0] = {
596 .start = AT91SAM9260_BASE_SSC,
597 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
598 .flags = IORESOURCE_MEM,
599 },
600 [1] = {
601 .start = AT91SAM9260_ID_SSC,
602 .end = AT91SAM9260_ID_SSC,
603 .flags = IORESOURCE_IRQ,
604 },
605 };
606
607 static struct platform_device at91sam9260_ssc_device = {
608 .name = "ssc",
609 .id = 0,
610 .dev = {
611 .dma_mask = &ssc_dmamask,
612 .coherent_dma_mask = DMA_BIT_MASK(32),
613 },
614 .resource = ssc_resources,
615 .num_resources = ARRAY_SIZE(ssc_resources),
616 };
617
618 static inline void configure_ssc_pins(unsigned pins)
619 {
620 if (pins & ATMEL_SSC_TF)
621 at91_set_A_periph(AT91_PIN_PB17, 1);
622 if (pins & ATMEL_SSC_TK)
623 at91_set_A_periph(AT91_PIN_PB16, 1);
624 if (pins & ATMEL_SSC_TD)
625 at91_set_A_periph(AT91_PIN_PB18, 1);
626 if (pins & ATMEL_SSC_RD)
627 at91_set_A_periph(AT91_PIN_PB19, 1);
628 if (pins & ATMEL_SSC_RK)
629 at91_set_A_periph(AT91_PIN_PB20, 1);
630 if (pins & ATMEL_SSC_RF)
631 at91_set_A_periph(AT91_PIN_PB21, 1);
632 }
633
634 /*
635 * SSC controllers are accessed through library code, instead of any
636 * kind of all-singing/all-dancing driver. For example one could be
637 * used by a particular I2S audio codec's driver, while another one
638 * on the same system might be used by a custom data capture driver.
639 */
640 void __init at91_add_device_ssc(unsigned id, unsigned pins)
641 {
642 struct platform_device *pdev;
643
644 /*
645 * NOTE: caller is responsible for passing information matching
646 * "pins" to whatever will be using each particular controller.
647 */
648 switch (id) {
649 case AT91SAM9260_ID_SSC:
650 pdev = &at91sam9260_ssc_device;
651 configure_ssc_pins(pins);
652 at91_clock_associate("ssc_clk", &pdev->dev, "pclk");
653 break;
654 default:
655 return;
656 }
657
658 platform_device_register(pdev);
659 }
660
661 #else
662 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
663 #endif
664
665
666 /* --------------------------------------------------------------------
667 * UART
668 * -------------------------------------------------------------------- */
669 #if defined(CONFIG_SERIAL_ATMEL)
670 static struct resource dbgu_resources[] = {
671 [0] = {
672 .start = AT91_VA_BASE_SYS + AT91_DBGU,
673 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
674 .flags = IORESOURCE_MEM,
675 },
676 [1] = {
677 .start = AT91_ID_SYS,
678 .end = AT91_ID_SYS,
679 .flags = IORESOURCE_IRQ,
680 },
681 };
682
683 static struct atmel_uart_data dbgu_data = {
684 .use_dma_tx = 0,
685 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
686 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
687 };
688
689 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
690
691 static struct platform_device at91sam9260_dbgu_device = {
692 .name = "atmel_usart",
693 .id = 0,
694 .dev = {
695 .dma_mask = &dbgu_dmamask,
696 .coherent_dma_mask = DMA_BIT_MASK(32),
697 .platform_data = &dbgu_data,
698 },
699 .resource = dbgu_resources,
700 .num_resources = ARRAY_SIZE(dbgu_resources),
701 };
702
703 static inline void configure_dbgu_pins(void)
704 {
705 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
706 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
707 }
708
709 static struct resource uart0_resources[] = {
710 [0] = {
711 .start = AT91SAM9260_BASE_US0,
712 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
713 .flags = IORESOURCE_MEM,
714 },
715 [1] = {
716 .start = AT91SAM9260_ID_US0,
717 .end = AT91SAM9260_ID_US0,
718 .flags = IORESOURCE_IRQ,
719 },
720 };
721
722 static struct atmel_uart_data uart0_data = {
723 .use_dma_tx = 1,
724 .use_dma_rx = 1,
725 };
726
727 static u64 uart0_dmamask = DMA_BIT_MASK(32);
728
729 static struct platform_device at91sam9260_uart0_device = {
730 .name = "atmel_usart",
731 .id = 1,
732 .dev = {
733 .dma_mask = &uart0_dmamask,
734 .coherent_dma_mask = DMA_BIT_MASK(32),
735 .platform_data = &uart0_data,
736 },
737 .resource = uart0_resources,
738 .num_resources = ARRAY_SIZE(uart0_resources),
739 };
740
741 static inline void configure_usart0_pins(unsigned pins)
742 {
743 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
744 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
745
746 if (pins & ATMEL_UART_RTS)
747 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
748 if (pins & ATMEL_UART_CTS)
749 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
750 if (pins & ATMEL_UART_DTR)
751 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
752 if (pins & ATMEL_UART_DSR)
753 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
754 if (pins & ATMEL_UART_DCD)
755 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
756 if (pins & ATMEL_UART_RI)
757 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
758 }
759
760 static struct resource uart1_resources[] = {
761 [0] = {
762 .start = AT91SAM9260_BASE_US1,
763 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
764 .flags = IORESOURCE_MEM,
765 },
766 [1] = {
767 .start = AT91SAM9260_ID_US1,
768 .end = AT91SAM9260_ID_US1,
769 .flags = IORESOURCE_IRQ,
770 },
771 };
772
773 static struct atmel_uart_data uart1_data = {
774 .use_dma_tx = 1,
775 .use_dma_rx = 1,
776 };
777
778 static u64 uart1_dmamask = DMA_BIT_MASK(32);
779
780 static struct platform_device at91sam9260_uart1_device = {
781 .name = "atmel_usart",
782 .id = 2,
783 .dev = {
784 .dma_mask = &uart1_dmamask,
785 .coherent_dma_mask = DMA_BIT_MASK(32),
786 .platform_data = &uart1_data,
787 },
788 .resource = uart1_resources,
789 .num_resources = ARRAY_SIZE(uart1_resources),
790 };
791
792 static inline void configure_usart1_pins(unsigned pins)
793 {
794 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
795 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
796
797 if (pins & ATMEL_UART_RTS)
798 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
799 if (pins & ATMEL_UART_CTS)
800 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
801 }
802
803 static struct resource uart2_resources[] = {
804 [0] = {
805 .start = AT91SAM9260_BASE_US2,
806 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 [1] = {
810 .start = AT91SAM9260_ID_US2,
811 .end = AT91SAM9260_ID_US2,
812 .flags = IORESOURCE_IRQ,
813 },
814 };
815
816 static struct atmel_uart_data uart2_data = {
817 .use_dma_tx = 1,
818 .use_dma_rx = 1,
819 };
820
821 static u64 uart2_dmamask = DMA_BIT_MASK(32);
822
823 static struct platform_device at91sam9260_uart2_device = {
824 .name = "atmel_usart",
825 .id = 3,
826 .dev = {
827 .dma_mask = &uart2_dmamask,
828 .coherent_dma_mask = DMA_BIT_MASK(32),
829 .platform_data = &uart2_data,
830 },
831 .resource = uart2_resources,
832 .num_resources = ARRAY_SIZE(uart2_resources),
833 };
834
835 static inline void configure_usart2_pins(unsigned pins)
836 {
837 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
838 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
839
840 if (pins & ATMEL_UART_RTS)
841 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
842 if (pins & ATMEL_UART_CTS)
843 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
844 }
845
846 static struct resource uart3_resources[] = {
847 [0] = {
848 .start = AT91SAM9260_BASE_US3,
849 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
850 .flags = IORESOURCE_MEM,
851 },
852 [1] = {
853 .start = AT91SAM9260_ID_US3,
854 .end = AT91SAM9260_ID_US3,
855 .flags = IORESOURCE_IRQ,
856 },
857 };
858
859 static struct atmel_uart_data uart3_data = {
860 .use_dma_tx = 1,
861 .use_dma_rx = 1,
862 };
863
864 static u64 uart3_dmamask = DMA_BIT_MASK(32);
865
866 static struct platform_device at91sam9260_uart3_device = {
867 .name = "atmel_usart",
868 .id = 4,
869 .dev = {
870 .dma_mask = &uart3_dmamask,
871 .coherent_dma_mask = DMA_BIT_MASK(32),
872 .platform_data = &uart3_data,
873 },
874 .resource = uart3_resources,
875 .num_resources = ARRAY_SIZE(uart3_resources),
876 };
877
878 static inline void configure_usart3_pins(unsigned pins)
879 {
880 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
881 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
882
883 if (pins & ATMEL_UART_RTS)
884 at91_set_B_periph(AT91_PIN_PC8, 0); /* RTS3 */
885 if (pins & ATMEL_UART_CTS)
886 at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
887 }
888
889 static struct resource uart4_resources[] = {
890 [0] = {
891 .start = AT91SAM9260_BASE_US4,
892 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
893 .flags = IORESOURCE_MEM,
894 },
895 [1] = {
896 .start = AT91SAM9260_ID_US4,
897 .end = AT91SAM9260_ID_US4,
898 .flags = IORESOURCE_IRQ,
899 },
900 };
901
902 static struct atmel_uart_data uart4_data = {
903 .use_dma_tx = 1,
904 .use_dma_rx = 1,
905 };
906
907 static u64 uart4_dmamask = DMA_BIT_MASK(32);
908
909 static struct platform_device at91sam9260_uart4_device = {
910 .name = "atmel_usart",
911 .id = 5,
912 .dev = {
913 .dma_mask = &uart4_dmamask,
914 .coherent_dma_mask = DMA_BIT_MASK(32),
915 .platform_data = &uart4_data,
916 },
917 .resource = uart4_resources,
918 .num_resources = ARRAY_SIZE(uart4_resources),
919 };
920
921 static inline void configure_usart4_pins(void)
922 {
923 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
924 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
925 }
926
927 static struct resource uart5_resources[] = {
928 [0] = {
929 .start = AT91SAM9260_BASE_US5,
930 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
931 .flags = IORESOURCE_MEM,
932 },
933 [1] = {
934 .start = AT91SAM9260_ID_US5,
935 .end = AT91SAM9260_ID_US5,
936 .flags = IORESOURCE_IRQ,
937 },
938 };
939
940 static struct atmel_uart_data uart5_data = {
941 .use_dma_tx = 1,
942 .use_dma_rx = 1,
943 };
944
945 static u64 uart5_dmamask = DMA_BIT_MASK(32);
946
947 static struct platform_device at91sam9260_uart5_device = {
948 .name = "atmel_usart",
949 .id = 6,
950 .dev = {
951 .dma_mask = &uart5_dmamask,
952 .coherent_dma_mask = DMA_BIT_MASK(32),
953 .platform_data = &uart5_data,
954 },
955 .resource = uart5_resources,
956 .num_resources = ARRAY_SIZE(uart5_resources),
957 };
958
959 static inline void configure_usart5_pins(void)
960 {
961 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
962 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
963 }
964
965 static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
966 struct platform_device *atmel_default_console_device; /* the serial console device */
967
968 void __init __deprecated at91_init_serial(struct at91_uart_config *config)
969 {
970 int i;
971
972 /* Fill in list of supported UARTs */
973 for (i = 0; i < config->nr_tty; i++) {
974 switch (config->tty_map[i]) {
975 case 0:
976 configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
977 at91_uarts[i] = &at91sam9260_uart0_device;
978 at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
979 break;
980 case 1:
981 configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
982 at91_uarts[i] = &at91sam9260_uart1_device;
983 at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
984 break;
985 case 2:
986 configure_usart2_pins(0);
987 at91_uarts[i] = &at91sam9260_uart2_device;
988 at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
989 break;
990 case 3:
991 configure_usart3_pins(0);
992 at91_uarts[i] = &at91sam9260_uart3_device;
993 at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
994 break;
995 case 4:
996 configure_usart4_pins();
997 at91_uarts[i] = &at91sam9260_uart4_device;
998 at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
999 break;
1000 case 5:
1001 configure_usart5_pins();
1002 at91_uarts[i] = &at91sam9260_uart5_device;
1003 at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
1004 break;
1005 case 6:
1006 configure_dbgu_pins();
1007 at91_uarts[i] = &at91sam9260_dbgu_device;
1008 at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
1009 break;
1010 default:
1011 continue;
1012 }
1013 at91_uarts[i]->id = i; /* update ID number to mapped ID */
1014 }
1015
1016 /* Set serial console device */
1017 if (config->console_tty < ATMEL_MAX_UART)
1018 atmel_default_console_device = at91_uarts[config->console_tty];
1019 if (!atmel_default_console_device)
1020 printk(KERN_INFO "AT91: No default serial console defined.\n");
1021 }
1022
1023 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1024 {
1025 struct platform_device *pdev;
1026
1027 switch (id) {
1028 case 0: /* DBGU */
1029 pdev = &at91sam9260_dbgu_device;
1030 configure_dbgu_pins();
1031 at91_clock_associate("mck", &pdev->dev, "usart");
1032 break;
1033 case AT91SAM9260_ID_US0:
1034 pdev = &at91sam9260_uart0_device;
1035 configure_usart0_pins(pins);
1036 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1037 break;
1038 case AT91SAM9260_ID_US1:
1039 pdev = &at91sam9260_uart1_device;
1040 configure_usart1_pins(pins);
1041 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1042 break;
1043 case AT91SAM9260_ID_US2:
1044 pdev = &at91sam9260_uart2_device;
1045 configure_usart2_pins(pins);
1046 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1047 break;
1048 case AT91SAM9260_ID_US3:
1049 pdev = &at91sam9260_uart3_device;
1050 configure_usart3_pins(pins);
1051 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1052 break;
1053 case AT91SAM9260_ID_US4:
1054 pdev = &at91sam9260_uart4_device;
1055 configure_usart4_pins();
1056 at91_clock_associate("usart4_clk", &pdev->dev, "usart");
1057 break;
1058 case AT91SAM9260_ID_US5:
1059 pdev = &at91sam9260_uart5_device;
1060 configure_usart5_pins();
1061 at91_clock_associate("usart5_clk", &pdev->dev, "usart");
1062 break;
1063 default:
1064 return;
1065 }
1066 pdev->id = portnr; /* update to mapped ID */
1067
1068 if (portnr < ATMEL_MAX_UART)
1069 at91_uarts[portnr] = pdev;
1070 }
1071
1072 void __init at91_set_serial_console(unsigned portnr)
1073 {
1074 if (portnr < ATMEL_MAX_UART)
1075 atmel_default_console_device = at91_uarts[portnr];
1076 if (!atmel_default_console_device)
1077 printk(KERN_INFO "AT91: No default serial console defined.\n");
1078 }
1079
1080 void __init at91_add_device_serial(void)
1081 {
1082 int i;
1083
1084 for (i = 0; i < ATMEL_MAX_UART; i++) {
1085 if (at91_uarts[i])
1086 platform_device_register(at91_uarts[i]);
1087 }
1088 }
1089 #else
1090 void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1091 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1092 void __init at91_set_serial_console(unsigned portnr) {}
1093 void __init at91_add_device_serial(void) {}
1094 #endif
1095
1096
1097 /* -------------------------------------------------------------------- */
1098 /*
1099 * These devices are always present and don't need any board-specific
1100 * setup.
1101 */
1102 static int __init at91_add_standard_devices(void)
1103 {
1104 at91_add_device_rtt();
1105 at91_add_device_watchdog();
1106 return 0;
1107 }
1108
1109 arch_initcall(at91_add_standard_devices);
WRT350N Kernel Patches