x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / arm / mach-pxa / devices.c
blob50ff453ad3707453051ce1703bed2a519a7c4df4
1 #include <linux/module.h>
2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <linux/platform_device.h>
5 #include <linux/dma-mapping.h>
7 #include <asm/arch/gpio.h>
8 #include <asm/arch/udc.h>
9 #include <asm/arch/pxafb.h>
10 #include <asm/arch/mmc.h>
11 #include <asm/arch/irda.h>
12 #include <asm/arch/i2c.h>
14 #include "devices.h"
16 void __init pxa_register_device(struct platform_device *dev, void *data)
18 int ret;
20 dev->dev.platform_data = data;
22 ret = platform_device_register(dev);
23 if (ret)
24 dev_err(&dev->dev, "unable to register device: %d\n", ret);
27 static struct resource pxamci_resources[] = {
28 [0] = {
29 .start = 0x41100000,
30 .end = 0x41100fff,
31 .flags = IORESOURCE_MEM,
33 [1] = {
34 .start = IRQ_MMC,
35 .end = IRQ_MMC,
36 .flags = IORESOURCE_IRQ,
38 [2] = {
39 .start = 21,
40 .end = 21,
41 .flags = IORESOURCE_DMA,
43 [3] = {
44 .start = 22,
45 .end = 22,
46 .flags = IORESOURCE_DMA,
50 static u64 pxamci_dmamask = 0xffffffffUL;
52 struct platform_device pxa_device_mci = {
53 .name = "pxa2xx-mci",
54 .id = 0,
55 .dev = {
56 .dma_mask = &pxamci_dmamask,
57 .coherent_dma_mask = 0xffffffff,
59 .num_resources = ARRAY_SIZE(pxamci_resources),
60 .resource = pxamci_resources,
63 void __init pxa_set_mci_info(struct pxamci_platform_data *info)
65 pxa_register_device(&pxa_device_mci, info);
69 static struct pxa2xx_udc_mach_info pxa_udc_info;
71 void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
73 memcpy(&pxa_udc_info, info, sizeof *info);
76 static struct resource pxa2xx_udc_resources[] = {
77 [0] = {
78 .start = 0x40600000,
79 .end = 0x4060ffff,
80 .flags = IORESOURCE_MEM,
82 [1] = {
83 .start = IRQ_USB,
84 .end = IRQ_USB,
85 .flags = IORESOURCE_IRQ,
89 static u64 udc_dma_mask = ~(u32)0;
91 struct platform_device pxa_device_udc = {
92 .name = "pxa2xx-udc",
93 .id = -1,
94 .resource = pxa2xx_udc_resources,
95 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
96 .dev = {
97 .platform_data = &pxa_udc_info,
98 .dma_mask = &udc_dma_mask,
102 static struct resource pxafb_resources[] = {
103 [0] = {
104 .start = 0x44000000,
105 .end = 0x4400ffff,
106 .flags = IORESOURCE_MEM,
108 [1] = {
109 .start = IRQ_LCD,
110 .end = IRQ_LCD,
111 .flags = IORESOURCE_IRQ,
115 static u64 fb_dma_mask = ~(u64)0;
117 struct platform_device pxa_device_fb = {
118 .name = "pxa2xx-fb",
119 .id = -1,
120 .dev = {
121 .dma_mask = &fb_dma_mask,
122 .coherent_dma_mask = 0xffffffff,
124 .num_resources = ARRAY_SIZE(pxafb_resources),
125 .resource = pxafb_resources,
128 void __init set_pxa_fb_info(struct pxafb_mach_info *info)
130 pxa_register_device(&pxa_device_fb, info);
133 void __init set_pxa_fb_parent(struct device *parent_dev)
135 pxa_device_fb.dev.parent = parent_dev;
138 static struct resource pxa_resource_ffuart[] = {
140 .start = __PREG(FFUART),
141 .end = __PREG(FFUART) + 35,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = IRQ_FFUART,
145 .end = IRQ_FFUART,
146 .flags = IORESOURCE_IRQ,
150 struct platform_device pxa_device_ffuart= {
151 .name = "pxa2xx-uart",
152 .id = 0,
153 .resource = pxa_resource_ffuart,
154 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
157 static struct resource pxa_resource_btuart[] = {
159 .start = __PREG(BTUART),
160 .end = __PREG(BTUART) + 35,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = IRQ_BTUART,
164 .end = IRQ_BTUART,
165 .flags = IORESOURCE_IRQ,
169 struct platform_device pxa_device_btuart = {
170 .name = "pxa2xx-uart",
171 .id = 1,
172 .resource = pxa_resource_btuart,
173 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
176 static struct resource pxa_resource_stuart[] = {
178 .start = __PREG(STUART),
179 .end = __PREG(STUART) + 35,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = IRQ_STUART,
183 .end = IRQ_STUART,
184 .flags = IORESOURCE_IRQ,
188 struct platform_device pxa_device_stuart = {
189 .name = "pxa2xx-uart",
190 .id = 2,
191 .resource = pxa_resource_stuart,
192 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
195 static struct resource pxa_resource_hwuart[] = {
197 .start = __PREG(HWUART),
198 .end = __PREG(HWUART) + 47,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = IRQ_HWUART,
202 .end = IRQ_HWUART,
203 .flags = IORESOURCE_IRQ,
207 struct platform_device pxa_device_hwuart = {
208 .name = "pxa2xx-uart",
209 .id = 3,
210 .resource = pxa_resource_hwuart,
211 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
214 static struct resource pxai2c_resources[] = {
216 .start = 0x40301680,
217 .end = 0x403016a3,
218 .flags = IORESOURCE_MEM,
219 }, {
220 .start = IRQ_I2C,
221 .end = IRQ_I2C,
222 .flags = IORESOURCE_IRQ,
226 struct platform_device pxa_device_i2c = {
227 .name = "pxa2xx-i2c",
228 .id = 0,
229 .resource = pxai2c_resources,
230 .num_resources = ARRAY_SIZE(pxai2c_resources),
233 void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
235 pxa_register_device(&pxa_device_i2c, info);
238 static struct resource pxai2s_resources[] = {
240 .start = 0x40400000,
241 .end = 0x40400083,
242 .flags = IORESOURCE_MEM,
243 }, {
244 .start = IRQ_I2S,
245 .end = IRQ_I2S,
246 .flags = IORESOURCE_IRQ,
250 struct platform_device pxa_device_i2s = {
251 .name = "pxa2xx-i2s",
252 .id = -1,
253 .resource = pxai2s_resources,
254 .num_resources = ARRAY_SIZE(pxai2s_resources),
257 static u64 pxaficp_dmamask = ~(u32)0;
259 struct platform_device pxa_device_ficp = {
260 .name = "pxa2xx-ir",
261 .id = -1,
262 .dev = {
263 .dma_mask = &pxaficp_dmamask,
264 .coherent_dma_mask = 0xffffffff,
268 void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
270 pxa_register_device(&pxa_device_ficp, info);
273 struct platform_device pxa_device_rtc = {
274 .name = "sa1100-rtc",
275 .id = -1,
278 #ifdef CONFIG_PXA25x
280 static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
282 static struct resource pxa25x_resource_ssp[] = {
283 [0] = {
284 .start = 0x41000000,
285 .end = 0x4100001f,
286 .flags = IORESOURCE_MEM,
288 [1] = {
289 .start = IRQ_SSP,
290 .end = IRQ_SSP,
291 .flags = IORESOURCE_IRQ,
293 [2] = {
294 /* DRCMR for RX */
295 .start = 13,
296 .end = 13,
297 .flags = IORESOURCE_DMA,
299 [3] = {
300 /* DRCMR for TX */
301 .start = 14,
302 .end = 14,
303 .flags = IORESOURCE_DMA,
307 struct platform_device pxa25x_device_ssp = {
308 .name = "pxa25x-ssp",
309 .id = 0,
310 .dev = {
311 .dma_mask = &pxa25x_ssp_dma_mask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
314 .resource = pxa25x_resource_ssp,
315 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
318 static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
320 static struct resource pxa25x_resource_nssp[] = {
321 [0] = {
322 .start = 0x41400000,
323 .end = 0x4140002f,
324 .flags = IORESOURCE_MEM,
326 [1] = {
327 .start = IRQ_NSSP,
328 .end = IRQ_NSSP,
329 .flags = IORESOURCE_IRQ,
331 [2] = {
332 /* DRCMR for RX */
333 .start = 15,
334 .end = 15,
335 .flags = IORESOURCE_DMA,
337 [3] = {
338 /* DRCMR for TX */
339 .start = 16,
340 .end = 16,
341 .flags = IORESOURCE_DMA,
345 struct platform_device pxa25x_device_nssp = {
346 .name = "pxa25x-nssp",
347 .id = 1,
348 .dev = {
349 .dma_mask = &pxa25x_nssp_dma_mask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
352 .resource = pxa25x_resource_nssp,
353 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
356 static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
358 static struct resource pxa25x_resource_assp[] = {
359 [0] = {
360 .start = 0x41500000,
361 .end = 0x4150002f,
362 .flags = IORESOURCE_MEM,
364 [1] = {
365 .start = IRQ_ASSP,
366 .end = IRQ_ASSP,
367 .flags = IORESOURCE_IRQ,
369 [2] = {
370 /* DRCMR for RX */
371 .start = 23,
372 .end = 23,
373 .flags = IORESOURCE_DMA,
375 [3] = {
376 /* DRCMR for TX */
377 .start = 24,
378 .end = 24,
379 .flags = IORESOURCE_DMA,
383 struct platform_device pxa25x_device_assp = {
384 /* ASSP is basically equivalent to NSSP */
385 .name = "pxa25x-nssp",
386 .id = 2,
387 .dev = {
388 .dma_mask = &pxa25x_assp_dma_mask,
389 .coherent_dma_mask = DMA_BIT_MASK(32),
391 .resource = pxa25x_resource_assp,
392 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
394 #endif /* CONFIG_PXA25x */
396 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
398 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
400 static struct resource pxa27x_resource_ohci[] = {
401 [0] = {
402 .start = 0x4C000000,
403 .end = 0x4C00ff6f,
404 .flags = IORESOURCE_MEM,
406 [1] = {
407 .start = IRQ_USBH1,
408 .end = IRQ_USBH1,
409 .flags = IORESOURCE_IRQ,
413 struct platform_device pxa27x_device_ohci = {
414 .name = "pxa27x-ohci",
415 .id = -1,
416 .dev = {
417 .dma_mask = &pxa27x_ohci_dma_mask,
418 .coherent_dma_mask = DMA_BIT_MASK(32),
420 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
421 .resource = pxa27x_resource_ohci,
424 void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
426 pxa_register_device(&pxa27x_device_ohci, info);
429 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
431 static struct resource pxa27x_resource_ssp1[] = {
432 [0] = {
433 .start = 0x41000000,
434 .end = 0x4100003f,
435 .flags = IORESOURCE_MEM,
437 [1] = {
438 .start = IRQ_SSP,
439 .end = IRQ_SSP,
440 .flags = IORESOURCE_IRQ,
442 [2] = {
443 /* DRCMR for RX */
444 .start = 13,
445 .end = 13,
446 .flags = IORESOURCE_DMA,
448 [3] = {
449 /* DRCMR for TX */
450 .start = 14,
451 .end = 14,
452 .flags = IORESOURCE_DMA,
456 struct platform_device pxa27x_device_ssp1 = {
457 .name = "pxa27x-ssp",
458 .id = 0,
459 .dev = {
460 .dma_mask = &pxa27x_ssp1_dma_mask,
461 .coherent_dma_mask = DMA_BIT_MASK(32),
463 .resource = pxa27x_resource_ssp1,
464 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
467 static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
469 static struct resource pxa27x_resource_ssp2[] = {
470 [0] = {
471 .start = 0x41700000,
472 .end = 0x4170003f,
473 .flags = IORESOURCE_MEM,
475 [1] = {
476 .start = IRQ_SSP2,
477 .end = IRQ_SSP2,
478 .flags = IORESOURCE_IRQ,
480 [2] = {
481 /* DRCMR for RX */
482 .start = 15,
483 .end = 15,
484 .flags = IORESOURCE_DMA,
486 [3] = {
487 /* DRCMR for TX */
488 .start = 16,
489 .end = 16,
490 .flags = IORESOURCE_DMA,
494 struct platform_device pxa27x_device_ssp2 = {
495 .name = "pxa27x-ssp",
496 .id = 1,
497 .dev = {
498 .dma_mask = &pxa27x_ssp2_dma_mask,
499 .coherent_dma_mask = DMA_BIT_MASK(32),
501 .resource = pxa27x_resource_ssp2,
502 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
505 static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
507 static struct resource pxa27x_resource_ssp3[] = {
508 [0] = {
509 .start = 0x41900000,
510 .end = 0x4190003f,
511 .flags = IORESOURCE_MEM,
513 [1] = {
514 .start = IRQ_SSP3,
515 .end = IRQ_SSP3,
516 .flags = IORESOURCE_IRQ,
518 [2] = {
519 /* DRCMR for RX */
520 .start = 66,
521 .end = 66,
522 .flags = IORESOURCE_DMA,
524 [3] = {
525 /* DRCMR for TX */
526 .start = 67,
527 .end = 67,
528 .flags = IORESOURCE_DMA,
532 struct platform_device pxa27x_device_ssp3 = {
533 .name = "pxa27x-ssp",
534 .id = 2,
535 .dev = {
536 .dma_mask = &pxa27x_ssp3_dma_mask,
537 .coherent_dma_mask = DMA_BIT_MASK(32),
539 .resource = pxa27x_resource_ssp3,
540 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
542 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
544 #ifdef CONFIG_PXA3xx
545 static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
547 static struct resource pxa3xx_resource_ssp4[] = {
548 [0] = {
549 .start = 0x41a00000,
550 .end = 0x41a0003f,
551 .flags = IORESOURCE_MEM,
553 [1] = {
554 .start = IRQ_SSP4,
555 .end = IRQ_SSP4,
556 .flags = IORESOURCE_IRQ,
558 [2] = {
559 /* DRCMR for RX */
560 .start = 2,
561 .end = 2,
562 .flags = IORESOURCE_DMA,
564 [3] = {
565 /* DRCMR for TX */
566 .start = 3,
567 .end = 3,
568 .flags = IORESOURCE_DMA,
572 struct platform_device pxa3xx_device_ssp4 = {
573 /* PXA3xx SSP is basically equivalent to PXA27x */
574 .name = "pxa27x-ssp",
575 .id = 3,
576 .dev = {
577 .dma_mask = &pxa3xx_ssp4_dma_mask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
580 .resource = pxa3xx_resource_ssp4,
581 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
584 static struct resource pxa3xx_resources_mci2[] = {
585 [0] = {
586 .start = 0x42000000,
587 .end = 0x42000fff,
588 .flags = IORESOURCE_MEM,
590 [1] = {
591 .start = IRQ_MMC2,
592 .end = IRQ_MMC2,
593 .flags = IORESOURCE_IRQ,
595 [2] = {
596 .start = 93,
597 .end = 93,
598 .flags = IORESOURCE_DMA,
600 [3] = {
601 .start = 94,
602 .end = 94,
603 .flags = IORESOURCE_DMA,
607 struct platform_device pxa3xx_device_mci2 = {
608 .name = "pxa2xx-mci",
609 .id = 1,
610 .dev = {
611 .dma_mask = &pxamci_dmamask,
612 .coherent_dma_mask = 0xffffffff,
614 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
615 .resource = pxa3xx_resources_mci2,
618 void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
620 pxa_register_device(&pxa3xx_device_mci2, info);
623 static struct resource pxa3xx_resources_mci3[] = {
624 [0] = {
625 .start = 0x42500000,
626 .end = 0x42500fff,
627 .flags = IORESOURCE_MEM,
629 [1] = {
630 .start = IRQ_MMC3,
631 .end = IRQ_MMC3,
632 .flags = IORESOURCE_IRQ,
634 [2] = {
635 .start = 100,
636 .end = 100,
637 .flags = IORESOURCE_DMA,
639 [3] = {
640 .start = 101,
641 .end = 101,
642 .flags = IORESOURCE_DMA,
646 struct platform_device pxa3xx_device_mci3 = {
647 .name = "pxa2xx-mci",
648 .id = 2,
649 .dev = {
650 .dma_mask = &pxamci_dmamask,
651 .coherent_dma_mask = 0xffffffff,
653 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
654 .resource = pxa3xx_resources_mci3,
657 void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
659 pxa_register_device(&pxa3xx_device_mci3, info);
662 #endif /* CONFIG_PXA3xx */