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x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / arm / mach-pxa / lpd270.c
blobafa62ffe3ad5d0ccb1e8a31cec66a57937d432f5
1 /*
2 * linux/arch/arm/mach-pxa/lpd270.c
3 *
4 * Support for the LogicPD PXA270 Card Engine.
5 * Derived from the mainstone code, which carries these notices:
6 *
7 * Author: Nicolas Pitre
8 * Created: Nov 05, 2002
9 * Copyright: MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/sysdev.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/bitops.h>
22 #include <linux/fb.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26
27 #include <asm/types.h>
28 #include <asm/setup.h>
29 #include <asm/memory.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware.h>
32 #include <asm/irq.h>
33 #include <asm/sizes.h>
34
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach/flash.h>
39
40 #include <asm/arch/pxa-regs.h>
41 #include <asm/arch/pxa2xx-regs.h>
42 #include <asm/arch/lpd270.h>
43 #include <asm/arch/audio.h>
44 #include <asm/arch/pxafb.h>
45 #include <asm/arch/mmc.h>
46 #include <asm/arch/irda.h>
47 #include <asm/arch/ohci.h>
48
49 #include "generic.h"
50 #include "devices.h"
51
52
53 static unsigned int lpd270_irq_enabled;
54
55 static void lpd270_mask_irq(unsigned int irq)
56 {
57 int lpd270_irq = irq - LPD270_IRQ(0);
58
59 __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
60
61 lpd270_irq_enabled &= ~(1 << lpd270_irq);
62 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
63 }
64
65 static void lpd270_unmask_irq(unsigned int irq)
66 {
67 int lpd270_irq = irq - LPD270_IRQ(0);
68
69 lpd270_irq_enabled |= 1 << lpd270_irq;
70 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
71 }
72
73 static struct irq_chip lpd270_irq_chip = {
74 .name = "CPLD",
75 .ack = lpd270_mask_irq,
76 .mask = lpd270_mask_irq,
77 .unmask = lpd270_unmask_irq,
78 };
79
80 static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
81 {
82 unsigned long pending;
83
84 pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
85 do {
86 GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
87 if (likely(pending)) {
88 irq = LPD270_IRQ(0) + __ffs(pending);
89 desc = irq_desc + irq;
90 desc_handle_irq(irq, desc);
91
92 pending = __raw_readw(LPD270_INT_STATUS) &
93 lpd270_irq_enabled;
94 }
95 } while (pending);
96 }
97
98 static void __init lpd270_init_irq(void)
99 {
100 int irq;
101
102 pxa27x_init_irq();
103
104 __raw_writew(0, LPD270_INT_MASK);
105 __raw_writew(0, LPD270_INT_STATUS);
106
107 /* setup extra LogicPD PXA270 irqs */
108 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
109 set_irq_chip(irq, &lpd270_irq_chip);
110 set_irq_handler(irq, handle_level_irq);
111 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
112 }
113 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
114 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
115 }
116
117
118 #ifdef CONFIG_PM
119 static int lpd270_irq_resume(struct sys_device *dev)
120 {
121 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
122 return 0;
123 }
124
125 static struct sysdev_class lpd270_irq_sysclass = {
126 .name = "cpld_irq",
127 .resume = lpd270_irq_resume,
128 };
129
130 static struct sys_device lpd270_irq_device = {
131 .cls = &lpd270_irq_sysclass,
132 };
133
134 static int __init lpd270_irq_device_init(void)
135 {
136 int ret = sysdev_class_register(&lpd270_irq_sysclass);
137 if (ret == 0)
138 ret = sysdev_register(&lpd270_irq_device);
139 return ret;
140 }
141
142 device_initcall(lpd270_irq_device_init);
143 #endif
144
145
146 static struct resource smc91x_resources[] = {
147 [0] = {
148 .start = LPD270_ETH_PHYS,
149 .end = (LPD270_ETH_PHYS + 0xfffff),
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = {
153 .start = LPD270_ETHERNET_IRQ,
154 .end = LPD270_ETHERNET_IRQ,
155 .flags = IORESOURCE_IRQ,
156 },
157 };
158
159 static struct platform_device smc91x_device = {
160 .name = "smc91x",
161 .id = 0,
162 .num_resources = ARRAY_SIZE(smc91x_resources),
163 .resource = smc91x_resources,
164 };
165
166 static struct platform_device lpd270_audio_device = {
167 .name = "pxa2xx-ac97",
168 .id = -1,
169 };
170
171 static struct resource lpd270_flash_resources[] = {
172 [0] = {
173 .start = PXA_CS0_PHYS,
174 .end = PXA_CS0_PHYS + SZ_64M - 1,
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .start = PXA_CS1_PHYS,
179 .end = PXA_CS1_PHYS + SZ_64M - 1,
180 .flags = IORESOURCE_MEM,
181 },
182 };
183
184 static struct mtd_partition lpd270_flash0_partitions[] = {
185 {
186 .name = "Bootloader",
187 .size = 0x00040000,
188 .offset = 0,
189 .mask_flags = MTD_WRITEABLE /* force read-only */
190 }, {
191 .name = "Kernel",
192 .size = 0x00400000,
193 .offset = 0x00040000,
194 }, {
195 .name = "Filesystem",
196 .size = MTDPART_SIZ_FULL,
197 .offset = 0x00440000
198 },
199 };
200
201 static struct flash_platform_data lpd270_flash_data[2] = {
202 {
203 .name = "processor-flash",
204 .map_name = "cfi_probe",
205 .parts = lpd270_flash0_partitions,
206 .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
207 }, {
208 .name = "mainboard-flash",
209 .map_name = "cfi_probe",
210 .parts = NULL,
211 .nr_parts = 0,
212 }
213 };
214
215 static struct platform_device lpd270_flash_device[2] = {
216 {
217 .name = "pxa2xx-flash",
218 .id = 0,
219 .dev = {
220 .platform_data = &lpd270_flash_data[0],
221 },
222 .resource = &lpd270_flash_resources[0],
223 .num_resources = 1,
224 }, {
225 .name = "pxa2xx-flash",
226 .id = 1,
227 .dev = {
228 .platform_data = &lpd270_flash_data[1],
229 },
230 .resource = &lpd270_flash_resources[1],
231 .num_resources = 1,
232 },
233 };
234
235 static void lpd270_backlight_power(int on)
236 {
237 if (on) {
238 pxa_gpio_mode(GPIO16_PWM0_MD);
239 pxa_set_cken(CKEN_PWM0, 1);
240 PWM_CTRL0 = 0;
241 PWM_PWDUTY0 = 0x3ff;
242 PWM_PERVAL0 = 0x3ff;
243 } else {
244 PWM_CTRL0 = 0;
245 PWM_PWDUTY0 = 0x0;
246 PWM_PERVAL0 = 0x3FF;
247 pxa_set_cken(CKEN_PWM0, 0);
248 }
249 }
250
251 /* 5.7" TFT QVGA (LoLo display number 1) */
252 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
253 .pixclock = 150000,
254 .xres = 320,
255 .yres = 240,
256 .bpp = 16,
257 .hsync_len = 0x14,
258 .left_margin = 0x28,
259 .right_margin = 0x0a,
260 .vsync_len = 0x02,
261 .upper_margin = 0x08,
262 .lower_margin = 0x14,
263 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
264 };
265
266 static struct pxafb_mach_info sharp_lq057q3dc02 = {
267 .modes = &sharp_lq057q3dc02_mode,
268 .num_modes = 1,
269 .lccr0 = 0x07800080,
270 .lccr3 = 0x00400000,
271 .pxafb_backlight_power = lpd270_backlight_power,
272 };
273
274 /* 12.1" TFT SVGA (LoLo display number 2) */
275 static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
276 .pixclock = 50000,
277 .xres = 800,
278 .yres = 600,
279 .bpp = 16,
280 .hsync_len = 0x05,
281 .left_margin = 0x52,
282 .right_margin = 0x05,
283 .vsync_len = 0x04,
284 .upper_margin = 0x14,
285 .lower_margin = 0x0a,
286 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
287 };
288
289 static struct pxafb_mach_info sharp_lq121s1dg31 = {
290 .modes = &sharp_lq121s1dg31_mode,
291 .num_modes = 1,
292 .lccr0 = 0x07800080,
293 .lccr3 = 0x00400000,
294 .pxafb_backlight_power = lpd270_backlight_power,
295 };
296
297 /* 3.6" TFT QVGA (LoLo display number 3) */
298 static struct pxafb_mode_info sharp_lq036q1da01_mode = {
299 .pixclock = 150000,
300 .xres = 320,
301 .yres = 240,
302 .bpp = 16,
303 .hsync_len = 0x0e,
304 .left_margin = 0x04,
305 .right_margin = 0x0a,
306 .vsync_len = 0x03,
307 .upper_margin = 0x03,
308 .lower_margin = 0x03,
309 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
310 };
311
312 static struct pxafb_mach_info sharp_lq036q1da01 = {
313 .modes = &sharp_lq036q1da01_mode,
314 .num_modes = 1,
315 .lccr0 = 0x07800080,
316 .lccr3 = 0x00400000,
317 .pxafb_backlight_power = lpd270_backlight_power,
318 };
319
320 /* 6.4" TFT VGA (LoLo display number 5) */
321 static struct pxafb_mode_info sharp_lq64d343_mode = {
322 .pixclock = 25000,
323 .xres = 640,
324 .yres = 480,
325 .bpp = 16,
326 .hsync_len = 0x31,
327 .left_margin = 0x89,
328 .right_margin = 0x19,
329 .vsync_len = 0x12,
330 .upper_margin = 0x22,
331 .lower_margin = 0x00,
332 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
333 };
334
335 static struct pxafb_mach_info sharp_lq64d343 = {
336 .modes = &sharp_lq64d343_mode,
337 .num_modes = 1,
338 .lccr0 = 0x07800080,
339 .lccr3 = 0x00400000,
340 .pxafb_backlight_power = lpd270_backlight_power,
341 };
342
343 /* 10.4" TFT VGA (LoLo display number 7) */
344 static struct pxafb_mode_info sharp_lq10d368_mode = {
345 .pixclock = 25000,
346 .xres = 640,
347 .yres = 480,
348 .bpp = 16,
349 .hsync_len = 0x31,
350 .left_margin = 0x89,
351 .right_margin = 0x19,
352 .vsync_len = 0x12,
353 .upper_margin = 0x22,
354 .lower_margin = 0x00,
355 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
356 };
357
358 static struct pxafb_mach_info sharp_lq10d368 = {
359 .modes = &sharp_lq10d368_mode,
360 .num_modes = 1,
361 .lccr0 = 0x07800080,
362 .lccr3 = 0x00400000,
363 .pxafb_backlight_power = lpd270_backlight_power,
364 };
365
366 /* 3.5" TFT QVGA (LoLo display number 8) */
367 static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
368 .pixclock = 150000,
369 .xres = 240,
370 .yres = 320,
371 .bpp = 16,
372 .hsync_len = 0x0e,
373 .left_margin = 0x0a,
374 .right_margin = 0x0a,
375 .vsync_len = 0x03,
376 .upper_margin = 0x05,
377 .lower_margin = 0x14,
378 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
379 };
380
381 static struct pxafb_mach_info sharp_lq035q7db02_20 = {
382 .modes = &sharp_lq035q7db02_20_mode,
383 .num_modes = 1,
384 .lccr0 = 0x07800080,
385 .lccr3 = 0x00400000,
386 .pxafb_backlight_power = lpd270_backlight_power,
387 };
388
389 static struct pxafb_mach_info *lpd270_lcd_to_use;
390
391 static int __init lpd270_set_lcd(char *str)
392 {
393 if (!strnicmp(str, "lq057q3dc02", 11)) {
394 lpd270_lcd_to_use = &sharp_lq057q3dc02;
395 } else if (!strnicmp(str, "lq121s1dg31", 11)) {
396 lpd270_lcd_to_use = &sharp_lq121s1dg31;
397 } else if (!strnicmp(str, "lq036q1da01", 11)) {
398 lpd270_lcd_to_use = &sharp_lq036q1da01;
399 } else if (!strnicmp(str, "lq64d343", 8)) {
400 lpd270_lcd_to_use = &sharp_lq64d343;
401 } else if (!strnicmp(str, "lq10d368", 8)) {
402 lpd270_lcd_to_use = &sharp_lq10d368;
403 } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
404 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
405 } else {
406 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
407 }
408
409 return 1;
410 }
411
412 __setup("lcd=", lpd270_set_lcd);
413
414 static struct platform_device *platform_devices[] __initdata = {
415 &smc91x_device,
416 &lpd270_audio_device,
417 &lpd270_flash_device[0],
418 &lpd270_flash_device[1],
419 };
420
421 static int lpd270_ohci_init(struct device *dev)
422 {
423 /* setup Port1 GPIO pin. */
424 pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
425 pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
426
427 /* Set the Power Control Polarity Low and Power Sense
428 Polarity Low to active low. */
429 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
430 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
431
432 return 0;
433 }
434
435 static struct pxaohci_platform_data lpd270_ohci_platform_data = {
436 .port_mode = PMM_PERPORT_MODE,
437 .init = lpd270_ohci_init,
438 };
439
440 static void __init lpd270_init(void)
441 {
442 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
443 lpd270_flash_data[1].width = 4;
444
445 /*
446 * System bus arbiter setting:
447 * - Core_Park
448 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
449 */
450 ARB_CNTRL = ARB_CORE_PARK | 0x234;
451
452 /*
453 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
454 */
455 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
456
457 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
458
459 if (lpd270_lcd_to_use != NULL)
460 set_pxa_fb_info(lpd270_lcd_to_use);
461
462 pxa_set_ohci_info(&lpd270_ohci_platform_data);
463 }
464
465
466 static struct map_desc lpd270_io_desc[] __initdata = {
467 {
468 .virtual = LPD270_CPLD_VIRT,
469 .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
470 .length = LPD270_CPLD_SIZE,
471 .type = MT_DEVICE,
472 },
473 };
474
475 static void __init lpd270_map_io(void)
476 {
477 pxa_map_io();
478 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
479
480 /* initialize sleep mode regs (wake-up sources, etc) */
481 PGSR0 = 0x00008800;
482 PGSR1 = 0x00000002;
483 PGSR2 = 0x0001FC00;
484 PGSR3 = 0x00001F81;
485 PWER = 0xC0000002;
486 PRER = 0x00000002;
487 PFER = 0x00000002;
488
489 /* for use I SRAM as framebuffer. */
490 PSLR |= 0x00000F04;
491 PCFR = 0x00000066;
492 }
493
494 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
495 /* Maintainer: Peter Barada */
496 .phys_io = 0x40000000,
497 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
498 .boot_params = 0xa0000100,
499 .map_io = lpd270_map_io,
500 .init_irq = lpd270_init_irq,
501 .timer = &pxa_timer,
502 .init_machine = lpd270_init,
503 MACHINE_END
WRT350N Kernel Patches