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x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / arm / mach-versatile / core.c
bloba7dd09436cbcb6b484515e120101688adef64a49
1 /*
2 * linux/arch/arm/mach-versatile/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31
32 #include <asm/cnt32_to_63.h>
33 #include <asm/system.h>
34 #include <asm/hardware.h>
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 #include <asm/leds.h>
38 #include <asm/hardware/arm_timer.h>
39 #include <asm/hardware/icst307.h>
40 #include <asm/hardware/vic.h>
41 #include <asm/mach-types.h>
42
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/time.h>
47 #include <asm/mach/map.h>
48 #include <asm/mach/mmc.h>
49
50 #include "core.h"
51 #include "clock.h"
52
53 /*
54 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
55 * is the (PA >> 12).
56 *
57 * Setup a VA for the Versatile Vectored Interrupt Controller.
58 */
59 #define __io_address(n) __io(IO_ADDRESS(n))
60 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
61 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
62
63 static void sic_mask_irq(unsigned int irq)
64 {
65 irq -= IRQ_SIC_START;
66 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
67 }
68
69 static void sic_unmask_irq(unsigned int irq)
70 {
71 irq -= IRQ_SIC_START;
72 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
73 }
74
75 static struct irq_chip sic_chip = {
76 .name = "SIC",
77 .ack = sic_mask_irq,
78 .mask = sic_mask_irq,
79 .unmask = sic_unmask_irq,
80 };
81
82 static void
83 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
84 {
85 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
86
87 if (status == 0) {
88 do_bad_IRQ(irq, desc);
89 return;
90 }
91
92 do {
93 irq = ffs(status) - 1;
94 status &= ~(1 << irq);
95
96 irq += IRQ_SIC_START;
97
98 desc = irq_desc + irq;
99 desc_handle_irq(irq, desc);
100 } while (status);
101 }
102
103 #if 1
104 #define IRQ_MMCI0A IRQ_VICSOURCE22
105 #define IRQ_AACI IRQ_VICSOURCE24
106 #define IRQ_ETH IRQ_VICSOURCE25
107 #define PIC_MASK 0xFFD00000
108 #else
109 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
110 #define IRQ_AACI IRQ_SIC_AACI
111 #define IRQ_ETH IRQ_SIC_ETH
112 #define PIC_MASK 0
113 #endif
114
115 void __init versatile_init_irq(void)
116 {
117 unsigned int i;
118
119 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
120
121 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
122
123 /* Do second interrupt controller */
124 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
125
126 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
127 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
128 set_irq_chip(i, &sic_chip);
129 set_irq_handler(i, handle_level_irq);
130 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
131 }
132 }
133
134 /*
135 * Interrupts on secondary controller from 0 to 8 are routed to
136 * source 31 on PIC.
137 * Interrupts from 21 to 31 are routed directly to the VIC on
138 * the corresponding number on primary controller. This is controlled
139 * by setting PIC_ENABLEx.
140 */
141 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
142 }
143
144 static struct map_desc versatile_io_desc[] __initdata = {
145 {
146 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
147 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
148 .length = SZ_4K,
149 .type = MT_DEVICE
150 }, {
151 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
152 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
153 .length = SZ_4K,
154 .type = MT_DEVICE
155 }, {
156 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
157 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
158 .length = SZ_4K,
159 .type = MT_DEVICE
160 }, {
161 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
162 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
163 .length = SZ_4K * 9,
164 .type = MT_DEVICE
165 },
166 #ifdef CONFIG_MACH_VERSATILE_AB
167 {
168 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE),
169 .pfn = __phys_to_pfn(VERSATILE_GPIO0_BASE),
170 .length = SZ_4K,
171 .type = MT_DEVICE
172 }, {
173 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
174 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
175 .length = SZ_64M,
176 .type = MT_DEVICE
177 },
178 #endif
179 #ifdef CONFIG_DEBUG_LL
180 {
181 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
182 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
183 .length = SZ_4K,
184 .type = MT_DEVICE
185 },
186 #endif
187 #ifdef CONFIG_PCI
188 {
189 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
190 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
191 .length = SZ_4K,
192 .type = MT_DEVICE
193 }, {
194 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
195 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
196 .length = VERSATILE_PCI_BASE_SIZE,
197 .type = MT_DEVICE
198 }, {
199 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
200 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
201 .length = VERSATILE_PCI_CFG_BASE_SIZE,
202 .type = MT_DEVICE
203 },
204 #if 0
205 {
206 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0,
207 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
208 .length = SZ_16M,
209 .type = MT_DEVICE
210 }, {
211 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1,
212 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
213 .length = SZ_16M,
214 .type = MT_DEVICE
215 }, {
216 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2,
217 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
218 .length = SZ_16M,
219 .type = MT_DEVICE
220 },
221 #endif
222 #endif
223 };
224
225 void __init versatile_map_io(void)
226 {
227 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
228 }
229
230 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
231
232 /*
233 * This is the Versatile sched_clock implementation. This has
234 * a resolution of 41.7ns, and a maximum value of about 35583 days.
235 *
236 * The return value is guaranteed to be monotonic in that range as
237 * long as there is always less than 89 seconds between successive
238 * calls to this function.
239 */
240 unsigned long long sched_clock(void)
241 {
242 unsigned long long v = cnt32_to_63(readl(VERSATILE_REFCOUNTER));
243
244 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
245 v *= 125<<1;
246 do_div(v, 3<<1);
247
248 return v;
249 }
250
251
252 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
253
254 static int versatile_flash_init(void)
255 {
256 u32 val;
257
258 val = __raw_readl(VERSATILE_FLASHCTRL);
259 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
260 __raw_writel(val, VERSATILE_FLASHCTRL);
261
262 return 0;
263 }
264
265 static void versatile_flash_exit(void)
266 {
267 u32 val;
268
269 val = __raw_readl(VERSATILE_FLASHCTRL);
270 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
271 __raw_writel(val, VERSATILE_FLASHCTRL);
272 }
273
274 static void versatile_flash_set_vpp(int on)
275 {
276 u32 val;
277
278 val = __raw_readl(VERSATILE_FLASHCTRL);
279 if (on)
280 val |= VERSATILE_FLASHPROG_FLVPPEN;
281 else
282 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
283 __raw_writel(val, VERSATILE_FLASHCTRL);
284 }
285
286 static struct flash_platform_data versatile_flash_data = {
287 .map_name = "cfi_probe",
288 .width = 4,
289 .init = versatile_flash_init,
290 .exit = versatile_flash_exit,
291 .set_vpp = versatile_flash_set_vpp,
292 };
293
294 static struct resource versatile_flash_resource = {
295 .start = VERSATILE_FLASH_BASE,
296 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
297 .flags = IORESOURCE_MEM,
298 };
299
300 static struct platform_device versatile_flash_device = {
301 .name = "armflash",
302 .id = 0,
303 .dev = {
304 .platform_data = &versatile_flash_data,
305 },
306 .num_resources = 1,
307 .resource = &versatile_flash_resource,
308 };
309
310 static struct resource smc91x_resources[] = {
311 [0] = {
312 .start = VERSATILE_ETH_BASE,
313 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 .start = IRQ_ETH,
318 .end = IRQ_ETH,
319 .flags = IORESOURCE_IRQ,
320 },
321 };
322
323 static struct platform_device smc91x_device = {
324 .name = "smc91x",
325 .id = 0,
326 .num_resources = ARRAY_SIZE(smc91x_resources),
327 .resource = smc91x_resources,
328 };
329
330 static struct resource versatile_i2c_resource = {
331 .start = VERSATILE_I2C_BASE,
332 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
333 .flags = IORESOURCE_MEM,
334 };
335
336 static struct platform_device versatile_i2c_device = {
337 .name = "versatile-i2c",
338 .id = -1,
339 .num_resources = 1,
340 .resource = &versatile_i2c_resource,
341 };
342
343 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
344
345 unsigned int mmc_status(struct device *dev)
346 {
347 struct amba_device *adev = container_of(dev, struct amba_device, dev);
348 u32 mask;
349
350 if (adev->res.start == VERSATILE_MMCI0_BASE)
351 mask = 1;
352 else
353 mask = 2;
354
355 return readl(VERSATILE_SYSMCI) & mask;
356 }
357
358 static struct mmc_platform_data mmc0_plat_data = {
359 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
360 .status = mmc_status,
361 };
362
363 /*
364 * Clock handling
365 */
366 static const struct icst307_params versatile_oscvco_params = {
367 .ref = 24000,
368 .vco_max = 200000,
369 .vd_min = 4 + 8,
370 .vd_max = 511 + 8,
371 .rd_min = 1 + 2,
372 .rd_max = 127 + 2,
373 };
374
375 static void versatile_oscvco_set(struct clk *clk, struct icst307_vco vco)
376 {
377 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
378 void __iomem *sys_osc = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
379 u32 val;
380
381 val = readl(sys_osc) & ~0x7ffff;
382 val |= vco.v | (vco.r << 9) | (vco.s << 16);
383
384 writel(0xa05f, sys_lock);
385 writel(val, sys_osc);
386 writel(0, sys_lock);
387 }
388
389 static struct clk versatile_clcd_clk = {
390 .name = "CLCDCLK",
391 .params = &versatile_oscvco_params,
392 .setvco = versatile_oscvco_set,
393 };
394
395 /*
396 * CLCD support.
397 */
398 #define SYS_CLCD_MODE_MASK (3 << 0)
399 #define SYS_CLCD_MODE_888 (0 << 0)
400 #define SYS_CLCD_MODE_5551 (1 << 0)
401 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
402 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
403 #define SYS_CLCD_NLCDIOON (1 << 2)
404 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
405 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
406 #define SYS_CLCD_ID_MASK (0x1f << 8)
407 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
408 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
409 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
410 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
411 #define SYS_CLCD_ID_VGA (0x1f << 8)
412
413 static struct clcd_panel vga = {
414 .mode = {
415 .name = "VGA",
416 .refresh = 60,
417 .xres = 640,
418 .yres = 480,
419 .pixclock = 39721,
420 .left_margin = 40,
421 .right_margin = 24,
422 .upper_margin = 32,
423 .lower_margin = 11,
424 .hsync_len = 96,
425 .vsync_len = 2,
426 .sync = 0,
427 .vmode = FB_VMODE_NONINTERLACED,
428 },
429 .width = -1,
430 .height = -1,
431 .tim2 = TIM2_BCD | TIM2_IPC,
432 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
433 .bpp = 16,
434 };
435
436 static struct clcd_panel sanyo_3_8_in = {
437 .mode = {
438 .name = "Sanyo QVGA",
439 .refresh = 116,
440 .xres = 320,
441 .yres = 240,
442 .pixclock = 100000,
443 .left_margin = 6,
444 .right_margin = 6,
445 .upper_margin = 5,
446 .lower_margin = 5,
447 .hsync_len = 6,
448 .vsync_len = 6,
449 .sync = 0,
450 .vmode = FB_VMODE_NONINTERLACED,
451 },
452 .width = -1,
453 .height = -1,
454 .tim2 = TIM2_BCD,
455 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
456 .bpp = 16,
457 };
458
459 static struct clcd_panel sanyo_2_5_in = {
460 .mode = {
461 .name = "Sanyo QVGA Portrait",
462 .refresh = 116,
463 .xres = 240,
464 .yres = 320,
465 .pixclock = 100000,
466 .left_margin = 20,
467 .right_margin = 10,
468 .upper_margin = 2,
469 .lower_margin = 2,
470 .hsync_len = 10,
471 .vsync_len = 2,
472 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
473 .vmode = FB_VMODE_NONINTERLACED,
474 },
475 .width = -1,
476 .height = -1,
477 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
478 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
479 .bpp = 16,
480 };
481
482 static struct clcd_panel epson_2_2_in = {
483 .mode = {
484 .name = "Epson QCIF",
485 .refresh = 390,
486 .xres = 176,
487 .yres = 220,
488 .pixclock = 62500,
489 .left_margin = 3,
490 .right_margin = 2,
491 .upper_margin = 1,
492 .lower_margin = 0,
493 .hsync_len = 3,
494 .vsync_len = 2,
495 .sync = 0,
496 .vmode = FB_VMODE_NONINTERLACED,
497 },
498 .width = -1,
499 .height = -1,
500 .tim2 = TIM2_BCD | TIM2_IPC,
501 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
502 .bpp = 16,
503 };
504
505 /*
506 * Detect which LCD panel is connected, and return the appropriate
507 * clcd_panel structure. Note: we do not have any information on
508 * the required timings for the 8.4in panel, so we presently assume
509 * VGA timings.
510 */
511 static struct clcd_panel *versatile_clcd_panel(void)
512 {
513 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
514 struct clcd_panel *panel = &vga;
515 u32 val;
516
517 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
518 if (val == SYS_CLCD_ID_SANYO_3_8)
519 panel = &sanyo_3_8_in;
520 else if (val == SYS_CLCD_ID_SANYO_2_5)
521 panel = &sanyo_2_5_in;
522 else if (val == SYS_CLCD_ID_EPSON_2_2)
523 panel = &epson_2_2_in;
524 else if (val == SYS_CLCD_ID_VGA)
525 panel = &vga;
526 else {
527 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
528 val);
529 panel = &vga;
530 }
531
532 return panel;
533 }
534
535 /*
536 * Disable all display connectors on the interface module.
537 */
538 static void versatile_clcd_disable(struct clcd_fb *fb)
539 {
540 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
541 u32 val;
542
543 val = readl(sys_clcd);
544 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
545 writel(val, sys_clcd);
546
547 #ifdef CONFIG_MACH_VERSATILE_AB
548 /*
549 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
550 */
551 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
552 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
553 unsigned long ctrl;
554
555 ctrl = readl(versatile_ib2_ctrl);
556 ctrl &= ~0x01;
557 writel(ctrl, versatile_ib2_ctrl);
558 }
559 #endif
560 }
561
562 /*
563 * Enable the relevant connector on the interface module.
564 */
565 static void versatile_clcd_enable(struct clcd_fb *fb)
566 {
567 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
568 u32 val;
569
570 val = readl(sys_clcd);
571 val &= ~SYS_CLCD_MODE_MASK;
572
573 switch (fb->fb.var.green.length) {
574 case 5:
575 val |= SYS_CLCD_MODE_5551;
576 break;
577 case 6:
578 val |= SYS_CLCD_MODE_565_RLSB;
579 break;
580 case 8:
581 val |= SYS_CLCD_MODE_888;
582 break;
583 }
584
585 /*
586 * Set the MUX
587 */
588 writel(val, sys_clcd);
589
590 /*
591 * And now enable the PSUs
592 */
593 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
594 writel(val, sys_clcd);
595
596 #ifdef CONFIG_MACH_VERSATILE_AB
597 /*
598 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
599 */
600 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) {
601 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
602 unsigned long ctrl;
603
604 ctrl = readl(versatile_ib2_ctrl);
605 ctrl |= 0x01;
606 writel(ctrl, versatile_ib2_ctrl);
607 }
608 #endif
609 }
610
611 static unsigned long framesize = SZ_1M;
612
613 static int versatile_clcd_setup(struct clcd_fb *fb)
614 {
615 dma_addr_t dma;
616
617 fb->panel = versatile_clcd_panel();
618
619 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
620 &dma, GFP_KERNEL);
621 if (!fb->fb.screen_base) {
622 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
623 return -ENOMEM;
624 }
625
626 fb->fb.fix.smem_start = dma;
627 fb->fb.fix.smem_len = framesize;
628
629 return 0;
630 }
631
632 static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
633 {
634 return dma_mmap_writecombine(&fb->dev->dev, vma,
635 fb->fb.screen_base,
636 fb->fb.fix.smem_start,
637 fb->fb.fix.smem_len);
638 }
639
640 static void versatile_clcd_remove(struct clcd_fb *fb)
641 {
642 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
643 fb->fb.screen_base, fb->fb.fix.smem_start);
644 }
645
646 static struct clcd_board clcd_plat_data = {
647 .name = "Versatile",
648 .check = clcdfb_check,
649 .decode = clcdfb_decode,
650 .disable = versatile_clcd_disable,
651 .enable = versatile_clcd_enable,
652 .setup = versatile_clcd_setup,
653 .mmap = versatile_clcd_mmap,
654 .remove = versatile_clcd_remove,
655 };
656
657 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
658 #define AACI_DMA { 0x80, 0x81 }
659 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
660 #define MMCI0_DMA { 0x84, 0 }
661 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
662 #define KMI0_DMA { 0, 0 }
663 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
664 #define KMI1_DMA { 0, 0 }
665
666 /*
667 * These devices are connected directly to the multi-layer AHB switch
668 */
669 #define SMC_IRQ { NO_IRQ, NO_IRQ }
670 #define SMC_DMA { 0, 0 }
671 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
672 #define MPMC_DMA { 0, 0 }
673 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
674 #define CLCD_DMA { 0, 0 }
675 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
676 #define DMAC_DMA { 0, 0 }
677
678 /*
679 * These devices are connected via the core APB bridge
680 */
681 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
682 #define SCTL_DMA { 0, 0 }
683 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
684 #define WATCHDOG_DMA { 0, 0 }
685 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
686 #define GPIO0_DMA { 0, 0 }
687 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
688 #define GPIO1_DMA { 0, 0 }
689 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
690 #define RTC_DMA { 0, 0 }
691
692 /*
693 * These devices are connected via the DMA APB bridge
694 */
695 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
696 #define SCI_DMA { 7, 6 }
697 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
698 #define UART0_DMA { 15, 14 }
699 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
700 #define UART1_DMA { 13, 12 }
701 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
702 #define UART2_DMA { 11, 10 }
703 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
704 #define SSP_DMA { 9, 8 }
705
706 /* FPGA Primecells */
707 AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
708 AMBA_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
709 AMBA_DEVICE(kmi0, "fpga:06", KMI0, NULL);
710 AMBA_DEVICE(kmi1, "fpga:07", KMI1, NULL);
711
712 /* DevChip Primecells */
713 AMBA_DEVICE(smc, "dev:00", SMC, NULL);
714 AMBA_DEVICE(mpmc, "dev:10", MPMC, NULL);
715 AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
716 AMBA_DEVICE(dmac, "dev:30", DMAC, NULL);
717 AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL);
718 AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
719 AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL);
720 AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL);
721 AMBA_DEVICE(rtc, "dev:e8", RTC, NULL);
722 AMBA_DEVICE(sci0, "dev:f0", SCI, NULL);
723 AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
724 AMBA_DEVICE(uart1, "dev:f2", UART1, NULL);
725 AMBA_DEVICE(uart2, "dev:f3", UART2, NULL);
726 AMBA_DEVICE(ssp0, "dev:f4", SSP, NULL);
727
728 static struct amba_device *amba_devs[] __initdata = {
729 &dmac_device,
730 &uart0_device,
731 &uart1_device,
732 &uart2_device,
733 &smc_device,
734 &mpmc_device,
735 &clcd_device,
736 &sctl_device,
737 &wdog_device,
738 &gpio0_device,
739 &gpio1_device,
740 &rtc_device,
741 &sci0_device,
742 &ssp0_device,
743 &aaci_device,
744 &mmc0_device,
745 &kmi0_device,
746 &kmi1_device,
747 };
748
749 #ifdef CONFIG_LEDS
750 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
751
752 static void versatile_leds_event(led_event_t ledevt)
753 {
754 unsigned long flags;
755 u32 val;
756
757 local_irq_save(flags);
758 val = readl(VA_LEDS_BASE);
759
760 switch (ledevt) {
761 case led_idle_start:
762 val = val & ~VERSATILE_SYS_LED0;
763 break;
764
765 case led_idle_end:
766 val = val | VERSATILE_SYS_LED0;
767 break;
768
769 case led_timer:
770 val = val ^ VERSATILE_SYS_LED1;
771 break;
772
773 case led_halted:
774 val = 0;
775 break;
776
777 default:
778 break;
779 }
780
781 writel(val, VA_LEDS_BASE);
782 local_irq_restore(flags);
783 }
784 #endif /* CONFIG_LEDS */
785
786 void __init versatile_init(void)
787 {
788 int i;
789
790 clk_register(&versatile_clcd_clk);
791
792 platform_device_register(&versatile_flash_device);
793 platform_device_register(&versatile_i2c_device);
794 platform_device_register(&smc91x_device);
795
796 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
797 struct amba_device *d = amba_devs[i];
798 amba_device_register(d, &iomem_resource);
799 }
800
801 #ifdef CONFIG_LEDS
802 leds_event = versatile_leds_event;
803 #endif
804 }
805
806 /*
807 * Where is the timer (VA)?
808 */
809 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
810 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
811 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
812 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
813 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
814
815 /*
816 * How long is the timer interval?
817 */
818 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
819 #if TIMER_INTERVAL >= 0x100000
820 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
821 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
822 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
823 #elif TIMER_INTERVAL >= 0x10000
824 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
825 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
826 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
827 #else
828 #define TIMER_RELOAD (TIMER_INTERVAL)
829 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
830 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
831 #endif
832
833 static void timer_set_mode(enum clock_event_mode mode,
834 struct clock_event_device *clk)
835 {
836 unsigned long ctrl;
837
838 switch(mode) {
839 case CLOCK_EVT_MODE_PERIODIC:
840 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
841
842 ctrl = TIMER_CTRL_PERIODIC;
843 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
844 break;
845 case CLOCK_EVT_MODE_ONESHOT:
846 /* period set, and timer enabled in 'next_event' hook */
847 ctrl = TIMER_CTRL_ONESHOT;
848 ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
849 break;
850 case CLOCK_EVT_MODE_UNUSED:
851 case CLOCK_EVT_MODE_SHUTDOWN:
852 default:
853 ctrl = 0;
854 }
855
856 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
857 }
858
859 static int timer_set_next_event(unsigned long evt,
860 struct clock_event_device *unused)
861 {
862 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
863
864 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
865 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
866
867 return 0;
868 }
869
870 static struct clock_event_device timer0_clockevent = {
871 .name = "timer0",
872 .shift = 32,
873 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
874 .set_mode = timer_set_mode,
875 .set_next_event = timer_set_next_event,
876 };
877
878 /*
879 * IRQ handler for the timer
880 */
881 static irqreturn_t versatile_timer_interrupt(int irq, void *dev_id)
882 {
883 struct clock_event_device *evt = &timer0_clockevent;
884
885 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
886
887 evt->event_handler(evt);
888
889 return IRQ_HANDLED;
890 }
891
892 static struct irqaction versatile_timer_irq = {
893 .name = "Versatile Timer Tick",
894 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
895 .handler = versatile_timer_interrupt,
896 };
897
898 static cycle_t versatile_get_cycles(void)
899 {
900 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
901 }
902
903 static struct clocksource clocksource_versatile = {
904 .name = "timer3",
905 .rating = 200,
906 .read = versatile_get_cycles,
907 .mask = CLOCKSOURCE_MASK(32),
908 .shift = 20,
909 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
910 };
911
912 static int __init versatile_clocksource_init(void)
913 {
914 /* setup timer3 as free-running clocksource */
915 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
916 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
917 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
918 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
919 TIMER3_VA_BASE + TIMER_CTRL);
920
921 clocksource_versatile.mult =
922 clocksource_khz2mult(1000, clocksource_versatile.shift);
923 clocksource_register(&clocksource_versatile);
924
925 return 0;
926 }
927
928 /*
929 * Set up timer interrupt, and return the current time in seconds.
930 */
931 static void __init versatile_timer_init(void)
932 {
933 u32 val;
934
935 /*
936 * set clock frequency:
937 * VERSATILE_REFCLK is 32KHz
938 * VERSATILE_TIMCLK is 1MHz
939 */
940 val = readl(__io_address(VERSATILE_SCTL_BASE));
941 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
942 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
943 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
944 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
945 __io_address(VERSATILE_SCTL_BASE));
946
947 /*
948 * Initialise to a known state (all timers off)
949 */
950 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
951 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
952 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
953 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
954
955 /*
956 * Make irqs happen for the system timer
957 */
958 setup_irq(IRQ_TIMERINT0_1, &versatile_timer_irq);
959
960 versatile_clocksource_init();
961
962 timer0_clockevent.mult =
963 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
964 timer0_clockevent.max_delta_ns =
965 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
966 timer0_clockevent.min_delta_ns =
967 clockevent_delta2ns(0xf, &timer0_clockevent);
968
969 timer0_clockevent.cpumask = cpumask_of_cpu(0);
970 clockevents_register_device(&timer0_clockevent);
971 }
972
973 struct sys_timer versatile_timer = {
974 .init = versatile_timer_init,
975 };
976
WRT350N Kernel Patches