x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / mips / au1000 / common / time.c
blobf113b512d7b166b81c9b32ece83516693cf72123
1 /*
3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/init.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/sched.h>
39 #include <linux/spinlock.h>
40 #include <linux/hardirq.h>
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
44 #include <asm/time.h>
45 #include <asm/div64.h>
46 #include <asm/mach-au1x00/au1000.h>
48 #include <linux/mc146818rtc.h>
49 #include <linux/timex.h>
51 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
52 static unsigned long r4k_cur; /* What counter should be at next timer irq */
53 int no_au1xxx_32khz;
54 extern int allow_au1k_wait; /* default off for CP0 Counter */
56 #ifdef CONFIG_PM
57 #if HZ < 100 || HZ > 1000
58 #error "unsupported HZ value! Must be in [100,1000]"
59 #endif
60 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
61 extern void startup_match20_interrupt(irq_handler_t handler);
62 static unsigned long last_pc0, last_match20;
63 #endif
65 static DEFINE_SPINLOCK(time_lock);
67 unsigned long wtimer;
69 #ifdef CONFIG_PM
70 static irqreturn_t counter0_irq(int irq, void *dev_id)
72 unsigned long pc0;
73 int time_elapsed;
74 static int jiffie_drift = 0;
76 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
77 /* should never happen! */
78 printk(KERN_WARNING "counter 0 w status error\n");
79 return IRQ_NONE;
82 pc0 = au_readl(SYS_TOYREAD);
83 if (pc0 < last_match20) {
84 /* counter overflowed */
85 time_elapsed = (0xffffffff - last_match20) + pc0;
87 else {
88 time_elapsed = pc0 - last_match20;
91 while (time_elapsed > 0) {
92 do_timer(1);
93 #ifndef CONFIG_SMP
94 update_process_times(user_mode(get_irq_regs()));
95 #endif
96 time_elapsed -= MATCH20_INC;
97 last_match20 += MATCH20_INC;
98 jiffie_drift++;
101 last_pc0 = pc0;
102 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
103 au_sync();
105 /* our counter ticks at 10.009765625 ms/tick, we we're running
106 * almost 10uS too slow per tick.
109 if (jiffie_drift >= 999) {
110 jiffie_drift -= 999;
111 do_timer(1); /* increment jiffies by one */
112 #ifndef CONFIG_SMP
113 update_process_times(user_mode(get_irq_regs()));
114 #endif
117 return IRQ_HANDLED;
120 struct irqaction counter0_action = {
121 .handler = counter0_irq,
122 .flags = IRQF_DISABLED,
123 .name = "alchemy-toy",
124 .dev_id = NULL,
127 /* When we wakeup from sleep, we have to "catch up" on all of the
128 * timer ticks we have missed.
130 void
131 wakeup_counter0_adjust(void)
133 unsigned long pc0;
134 int time_elapsed;
136 pc0 = au_readl(SYS_TOYREAD);
137 if (pc0 < last_match20) {
138 /* counter overflowed */
139 time_elapsed = (0xffffffff - last_match20) + pc0;
141 else {
142 time_elapsed = pc0 - last_match20;
145 while (time_elapsed > 0) {
146 time_elapsed -= MATCH20_INC;
147 last_match20 += MATCH20_INC;
150 last_pc0 = pc0;
151 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
152 au_sync();
156 /* This is just for debugging to set the timer for a sleep delay.
158 void
159 wakeup_counter0_set(int ticks)
161 unsigned long pc0;
163 pc0 = au_readl(SYS_TOYREAD);
164 last_pc0 = pc0;
165 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
166 au_sync();
168 #endif
170 /* I haven't found anyone that doesn't use a 12 MHz source clock,
171 * but just in case.....
173 #define AU1000_SRC_CLK 12000000
176 * We read the real processor speed from the PLL. This is important
177 * because it is more accurate than computing it from the 32KHz
178 * counter, if it exists. If we don't have an accurate processor
179 * speed, all of the peripherals that derive their clocks based on
180 * this advertised speed will introduce error and sometimes not work
181 * properly. This function is futher convoluted to still allow configurations
182 * to do that in case they have really, really old silicon with a
183 * write-only PLL register, that we need the 32KHz when power management
184 * "wait" is enabled, and we need to detect if the 32KHz isn't present
185 * but requested......got it? :-) -- Dan
187 unsigned long cal_r4koff(void)
189 unsigned long cpu_speed;
190 unsigned long flags;
191 unsigned long counter;
193 spin_lock_irqsave(&time_lock, flags);
195 /* Power management cares if we don't have a 32KHz counter.
197 no_au1xxx_32khz = 0;
198 counter = au_readl(SYS_COUNTER_CNTRL);
199 if (counter & SYS_CNTRL_E0) {
200 int trim_divide = 16;
202 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
204 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
205 /* RTC now ticks at 32.768/16 kHz */
206 au_writel(trim_divide-1, SYS_RTCTRIM);
207 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
209 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
210 au_writel(0, SYS_TOYWRITE);
211 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
213 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
214 AU1000_SRC_CLK;
216 else {
217 /* The 32KHz oscillator isn't running, so assume there
218 * isn't one and grab the processor speed from the PLL.
219 * NOTE: some old silicon doesn't allow reading the PLL.
221 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
222 no_au1xxx_32khz = 1;
224 mips_hpt_frequency = cpu_speed;
225 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
226 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
227 spin_unlock_irqrestore(&time_lock, flags);
228 return (cpu_speed / HZ);
231 void __init plat_time_init(void)
233 unsigned int est_freq;
235 printk("calculating r4koff... ");
236 r4k_offset = cal_r4koff();
237 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
239 //est_freq = 2*r4k_offset*HZ;
240 est_freq = r4k_offset*HZ;
241 est_freq += 5000; /* round */
242 est_freq -= est_freq%10000;
243 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
244 (est_freq%1000000)*100/1000000);
245 set_au1x00_speed(est_freq);
246 set_au1x00_lcd_clock(); // program the LCD clock
248 r4k_cur = (read_c0_count() + r4k_offset);
249 write_c0_compare(r4k_cur);
251 #ifdef CONFIG_PM
253 * setup counter 0, since it keeps ticking after a
254 * 'wait' instruction has been executed. The CP0 timer and
255 * counter 1 do NOT continue running after 'wait'
257 * It's too early to call request_irq() here, so we handle
258 * counter 0 interrupt as a special irq and it doesn't show
259 * up under /proc/interrupts.
261 * Check to ensure we really have a 32KHz oscillator before
262 * we do this.
264 if (no_au1xxx_32khz) {
265 printk("WARNING: no 32KHz clock found.\n");
267 /* Ensure we get CPO_COUNTER interrupts. */
268 set_c0_status(IE_IRQ5);
270 else {
271 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
272 au_writel(0, SYS_TOYWRITE);
273 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
275 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
276 au_writel(~0, SYS_WAKESRC);
277 au_sync();
278 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
280 /* setup match20 to interrupt once every HZ */
281 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
282 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
283 au_sync();
284 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
285 setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
287 /* We can use the real 'wait' instruction.
289 allow_au1k_wait = 1;
292 #endif