x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / mips / sgi-ip22 / ip22-nvram.c
blob0177566475d4cd42ae3a68d2eb1c73a4c39789c9
1 /*
2 * ip22-nvram.c: NVRAM and serial EEPROM handling.
4 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
5 */
6 #include <linux/module.h>
8 #include <asm/sgi/hpc3.h>
9 #include <asm/sgi/ip22.h>
11 /* Control opcode for serial eeprom */
12 #define EEPROM_READ 0xc000 /* serial memory read */
13 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
14 #define EEPROM_WRITE 0xa000 /* serial memory write */
15 #define EEPROM_WRALL 0x8800 /* write all registers */
16 #define EEPROM_WDS 0x8000 /* disable all programming */
17 #define EEPROM_PRREAD 0xc000 /* read protect register */
18 #define EEPROM_PREN 0x9800 /* enable protect register mode */
19 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
20 #define EEPROM_PRWRITE 0xa000 /* write protect register */
21 #define EEPROM_PRDS 0x8000 /* disable protect register, forever */
23 #define EEPROM_EPROT 0x01 /* Protect register enable */
24 #define EEPROM_CSEL 0x02 /* Chip select */
25 #define EEPROM_ECLK 0x04 /* EEPROM clock */
26 #define EEPROM_DATO 0x08 /* Data out */
27 #define EEPROM_DATI 0x10 /* Data in */
29 /* We need to use these functions early... */
30 #define delay() ({ \
31 int x; \
32 for (x=0; x<100000; x++) __asm__ __volatile__(""); })
34 #define eeprom_cs_on(ptr) ({ \
35 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
36 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
38 delay(); \
39 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
43 #define eeprom_cs_off(ptr) ({ \
44 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
46 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
49 #define BITS_IN_COMMAND 11
51 * clock in the nvram command and the register number. For the
52 * national semiconductor nv ram chip the op code is 3 bits and
53 * the address is 6/8 bits.
55 static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg)
57 unsigned short ser_cmd;
58 int i;
60 ser_cmd = cmd | (reg << (16 - BITS_IN_COMMAND));
61 for (i = 0; i < BITS_IN_COMMAND; i++) {
62 if (ser_cmd & (1<<15)) /* if high order bit set */
63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl);
64 else
65 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
66 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
67 delay();
68 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
69 delay();
70 ser_cmd <<= 1;
72 /* see data sheet timing diagram */
73 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl);
76 unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg)
78 unsigned short res = 0;
79 int i;
81 __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl);
82 eeprom_cs_on(ctrl);
83 eeprom_cmd(ctrl, EEPROM_READ, reg);
85 /* clock the data ouf of serial mem */
86 for (i = 0; i < 16; i++) {
87 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl);
88 delay();
89 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl);
90 delay();
91 res <<= 1;
92 if (__raw_readl(ctrl) & EEPROM_DATI)
93 res |= 1;
96 eeprom_cs_off(ctrl);
98 return res;
101 EXPORT_SYMBOL(ip22_eeprom_read);
104 * Read specified register from main NVRAM
106 unsigned short ip22_nvram_read(int reg)
108 if (ip22_is_fullhouse())
109 /* IP22 (Indigo2 aka FullHouse) stores env variables into
110 * 93CS56 Microwire Bus EEPROM 2048 Bit (128x16) */
111 return ip22_eeprom_read(&hpc3c0->eeprom, reg);
112 else {
113 unsigned short tmp;
114 /* IP24 (Indy aka Guiness) uses DS1386 8K version */
115 reg <<= 1;
116 tmp = hpc3c0->bbram[reg++] & 0xff;
117 return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff);
121 EXPORT_SYMBOL(ip22_nvram_read);