arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c

   1 /*
   2  * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
   3  *
   4  * Initialize for ALi M1535+(included M5229 and M5237).
   5  *
   6  * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
   7  *         Alex Sapkov <asapkov@ru.mvista.com>
   8  *
   9  * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
  10  * the terms of the GNU General Public License version 2. This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  *
  14  * Support for NEC-CMBVR4133 in 2.6
  15  * Author: Manish Lachwani (mlachwani@mvista.com)
  16  */
  17 #include <linux/init.h>
  18 #include <linux/types.h>
  19 #include <linux/serial.h>
  20
  21 #include <asm/vr41xx/cmbvr4133.h>
  22 #include <linux/pci.h>
  23 #include <asm/io.h>
  24
  25 #define CONFIG_PORT(port)       ((port) ? 0x3f0 : 0x370)
  26 #define DATA_PORT(port)         ((port) ? 0x3f1 : 0x371)
  27 #define INDEX_PORT(port)        CONFIG_PORT(port)
  28
  29 #define ENTER_CONFIG_MODE(port)                         \
  30         do {                                            \
  31                 outb_p(0x51, CONFIG_PORT(port));        \
  32                 outb_p(0x23, CONFIG_PORT(port));        \
  33         } while(0)
  34
  35 #define SELECT_LOGICAL_DEVICE(port, dev_no)             \
  36         do {                                            \
  37                 outb_p(0x07, INDEX_PORT(port));         \
  38                 outb_p((dev_no), DATA_PORT(port));      \
  39         } while(0)
  40
  41 #define WRITE_CONFIG_DATA(port, index, data)            \
  42         do {                                            \
  43                 outb_p((index), INDEX_PORT(port));      \
  44                 outb_p((data), DATA_PORT(port));        \
  45         } while(0)
  46
  47 #define EXIT_CONFIG_MODE(port)  outb(0xbb, CONFIG_PORT(port))
  48
  49 #define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
  50 #define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
  51
  52 #ifdef CONFIG_BLK_DEV_FD
  53
  54 void __devinit ali_m1535plus_fdc_init(int port)
  55 {
  56         ENTER_CONFIG_MODE(port);
  57         SELECT_LOGICAL_DEVICE(port, 0);         /* FDC */
  58         WRITE_CONFIG_DATA(port, 0x30, 0x01);    /* FDC: enable */
  59         WRITE_CONFIG_DATA(port, 0x60, 0x03);    /* I/O port base: 0x3f0 */
  60         WRITE_CONFIG_DATA(port, 0x61, 0xf0);
  61         WRITE_CONFIG_DATA(port, 0x70, 0x06);    /* IRQ: 6 */
  62         WRITE_CONFIG_DATA(port, 0x74, 0x02);    /* DMA: channel 2 */
  63         WRITE_CONFIG_DATA(port, 0xf0, 0x08);
  64         WRITE_CONFIG_DATA(port, 0xf1, 0x00);
  65         WRITE_CONFIG_DATA(port, 0xf2, 0xff);
  66         WRITE_CONFIG_DATA(port, 0xf4, 0x00);
  67         EXIT_CONFIG_MODE(port);
  68 }
  69
  70 #endif
  71
  72 void __devinit ali_m1535plus_parport_init(int port)
  73 {
  74         ENTER_CONFIG_MODE(port);
  75         SELECT_LOGICAL_DEVICE(port, 3);         /* Parallel Port */
  76         WRITE_CONFIG_DATA(port, 0x30, 0x01);
  77         WRITE_CONFIG_DATA(port, 0x60, 0x03);    /* I/O port base: 0x378 */
  78         WRITE_CONFIG_DATA(port, 0x61, 0x78);
  79         WRITE_CONFIG_DATA(port, 0x70, 0x07);    /* IRQ: 7 */
  80         WRITE_CONFIG_DATA(port, 0x74, 0x04);    /* DMA: None */
  81         WRITE_CONFIG_DATA(port, 0xf0, 0x8c);    /* IRQ polarity: Active Low */
  82         WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
  83         EXIT_CONFIG_MODE(port);
  84 }
  85
  86 void __devinit ali_m1535plus_keyboard_init(int port)
  87 {
  88         ENTER_CONFIG_MODE(port);
  89         SELECT_LOGICAL_DEVICE(port, 7);         /* KEYBOARD */
  90         WRITE_CONFIG_DATA(port, 0x30, 0x01);    /* KEYBOARD: eable */
  91         WRITE_CONFIG_DATA(port, 0x70, 0x01);    /* IRQ: 1 */
  92         WRITE_CONFIG_DATA(port, 0x72, 0x0c);    /* PS/2 Mouse IRQ: 12 */
  93         WRITE_CONFIG_DATA(port, 0xf0, 0x00);
  94         EXIT_CONFIG_MODE(port);
  95 }
  96
  97 void __devinit ali_m1535plus_hotkey_init(int port)
  98 {
  99         ENTER_CONFIG_MODE(port);
 100         SELECT_LOGICAL_DEVICE(port, 0xc);       /* HOTKEY */
 101         WRITE_CONFIG_DATA(port, 0x30, 0x00);
 102         WRITE_CONFIG_DATA(port, 0xf0, 0x35);
 103         WRITE_CONFIG_DATA(port, 0xf1, 0x14);
 104         WRITE_CONFIG_DATA(port, 0xf2, 0x11);
 105         WRITE_CONFIG_DATA(port, 0xf3, 0x71);
 106         WRITE_CONFIG_DATA(port, 0xf5, 0x05);
 107         EXIT_CONFIG_MODE(port);
 108 }
 109
 110 void ali_m1535plus_init(struct pci_dev *dev)
 111 {
 112         pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
 113         pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
 114         pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
 115         pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
 116         pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
 117         pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
 118         pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
 119
 120         /* IRQ routing */
 121         pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
 122         pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
 123         pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
 124         pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
 125
 126         pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
 127         pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
 128         pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
 129         pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
 130
 131         pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
 132         pci_write_config_byte(dev, 0x5a, 0x00);
 133         pci_write_config_byte(dev, 0x5b, 0x00);
 134         pci_write_config_word(dev, 0x5c, 0x0000);
 135         pci_write_config_byte(dev, 0x5e, 0x00);
 136         pci_write_config_byte(dev, 0x5f, 0x00);
 137         pci_write_config_word(dev, 0x60, 0x0000);
 138
 139         pci_write_config_byte(dev, 0x6c, 0x00);
 140         pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
 141         pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
 142
 143         pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
 144         pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
 145         pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
 146         pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
 147
 148         /*
 149          * IRQ setup ALi M5237 USB Host Controller
 150          * IRQ: 9
 151          */
 152         pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
 153
 154         pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15  */
 155         pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
 156         pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
 157         pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
 158         pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
 159         pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
 160         pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
 161         pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
 162
 163 #ifdef CONFIG_BLK_DEV_FD
 164         ali_m1535plus_fdc_init(1);
 165 #endif
 166
 167         ali_m1535plus_keyboard_init(1);
 168         ali_m1535plus_hotkey_init(1);
 169 }
 170
 171 static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
 172 {
 173         u32 data;
 174         int shift;
 175
 176         writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
 177         data = readl(PCI_CONFIG_DATA);
 178
 179         shift = (reg & 3) << 3;
 180         data &= ~(0xff << shift);
 181         data |= (((u32)val) << shift);
 182
 183         writel(data, PCI_CONFIG_DATA);
 184 }
 185
 186 static inline u8 ali_config_readb(u8 reg, int devfn)
 187 {
 188         u32 data;
 189
 190         writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
 191         data = readl(PCI_CONFIG_DATA);
 192
 193         return (u8)(data >> ((reg & 3) << 3));
 194 }
 195
 196 static inline u16 ali_config_readw(u8 reg, int devfn)
 197 {
 198         u32 data;
 199
 200         writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
 201         data = readl(PCI_CONFIG_DATA);
 202
 203         return (u16)(data >> ((reg & 2) << 3));
 204 }
 205
 206 int vr4133_rockhopper = 0;
 207 void __init ali_m5229_preinit(void)
 208 {
 209         if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
 210             ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
 211                 printk(KERN_INFO "Found an NEC Rockhopper \n");
 212                 vr4133_rockhopper = 1;
 213                 /*
 214                  * Enable ALi M5229 IDE Controller (both channels)
 215                  * IDSEL: A27
 216                  */
 217                 ali_config_writeb(0x58, 0x4c, 16);
 218         }
 219 }
 220
 221 void __init ali_m5229_init(struct pci_dev *dev)
 222 {
 223         /*
 224          * Enable Primary/Secondary Channel Cable Detect 40-Pin
 225          */
 226         pci_write_config_word(dev, 0x4a, 0xc023);
 227
 228         /*
 229          * Set only the 3rd byteis for the master IDE's cycle and
 230          * enable Internal IDE Function
 231          */
 232         pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
 233
 234         pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
 235         pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
 236         pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
 237         pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
 238         pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
 239         pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
 240         pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
 241         pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
 242         pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
 243         pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
 244         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
 245         pci_write_config_word(dev, PCI_COMMAND,
 246                                    PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
 247                                    PCI_COMMAND_IO);
 248 }
 249