arch/powerpc/platforms/8xx/m8xx_setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   6  *  Further modified for generic 8xx by Dan.
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/init.h>
  17 #include <linux/time.h>
  18 #include <linux/rtc.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/mpc8xx.h>
  22 #include <asm/8xx_immap.h>
  23 #include <asm/prom.h>
  24 #include <asm/fs_pd.h>
  25 #include <mm/mmu_decl.h>
  26
  27 #include <sysdev/mpc8xx_pic.h>
  28 #include <sysdev/commproc.h>
  29
  30 #ifdef CONFIG_PCMCIA_M8XX
  31 struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
  32 #endif
  33
  34 void m8xx_calibrate_decr(void);
  35 extern int cpm_pic_init(void);
  36 extern int cpm_get_irq(void);
  37
  38 /* A place holder for time base interrupts, if they are ever enabled. */
  39 static irqreturn_t timebase_interrupt(int irq, void *dev)
  40 {
  41         printk ("timebase_interrupt()\n");
  42
  43         return IRQ_HANDLED;
  44 }
  45
  46 static struct irqaction tbint_irqaction = {
  47         .handler = timebase_interrupt,
  48         .mask = CPU_MASK_NONE,
  49         .name = "tbint",
  50 };
  51
  52 /* per-board overridable init_internal_rtc() function. */
  53 void __init __attribute__ ((weak))
  54 init_internal_rtc(void)
  55 {
  56         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
  57
  58         /* Disable the RTC one second and alarm interrupts. */
  59         clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
  60
  61         /* Enable the RTC */
  62         setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
  63         immr_unmap(sys_tmr);
  64 }
  65
  66 static int __init get_freq(char *name, unsigned long *val)
  67 {
  68         struct device_node *cpu;
  69         const unsigned int *fp;
  70         int found = 0;
  71
  72         /* The cpu node should have timebase and clock frequency properties */
  73         cpu = of_find_node_by_type(NULL, "cpu");
  74
  75         if (cpu) {
  76                 fp = of_get_property(cpu, name, NULL);
  77                 if (fp) {
  78                         found = 1;
  79                         *val = *fp;
  80                 }
  81
  82                 of_node_put(cpu);
  83         }
  84
  85         return found;
  86 }
  87
  88 /* The decrementer counts at the system (internal) clock frequency divided by
  89  * sixteen, or external oscillator divided by four.  We force the processor
  90  * to use system clock divided by sixteen.
  91  */
  92 void __init mpc8xx_calibrate_decr(void)
  93 {
  94         struct device_node *cpu;
  95         cark8xx_t __iomem *clk_r1;
  96         car8xx_t __iomem *clk_r2;
  97         sitk8xx_t __iomem *sys_tmr1;
  98         sit8xx_t __iomem *sys_tmr2;
  99         int irq, virq;
 100
 101         clk_r1 = immr_map(im_clkrstk);
 102
 103         /* Unlock the SCCR. */
 104         out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
 105         out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
 106         immr_unmap(clk_r1);
 107
 108         /* Force all 8xx processors to use divide by 16 processor clock. */
 109         clk_r2 = immr_map(im_clkrst);
 110         setbits32(&clk_r2->car_sccr, 0x02000000);
 111         immr_unmap(clk_r2);
 112
 113         /* Processor frequency is MHz.
 114          */
 115         ppc_tb_freq = 50000000;
 116         if (!get_freq("bus-frequency", &ppc_tb_freq)) {
 117                 printk(KERN_ERR "WARNING: Estimating decrementer frequency "
 118                                 "(not found)\n");
 119         }
 120         ppc_tb_freq /= 16;
 121         ppc_proc_freq = 50000000;
 122         if (!get_freq("clock-frequency", &ppc_proc_freq))
 123                 printk(KERN_ERR "WARNING: Estimating processor frequency"
 124                                 "(not found)\n");
 125
 126         printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
 127
 128         /* Perform some more timer/timebase initialization.  This used
 129          * to be done elsewhere, but other changes caused it to get
 130          * called more than once....that is a bad thing.
 131          *
 132          * First, unlock all of the registers we are going to modify.
 133          * To protect them from corruption during power down, registers
 134          * that are maintained by keep alive power are "locked".  To
 135          * modify these registers we have to write the key value to
 136          * the key location associated with the register.
 137          * Some boards power up with these unlocked, while others
 138          * are locked.  Writing anything (including the unlock code?)
 139          * to the unlocked registers will lock them again.  So, here
 140          * we guarantee the registers are locked, then we unlock them
 141          * for our use.
 142          */
 143         sys_tmr1 = immr_map(im_sitk);
 144         out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
 145         out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
 146         out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
 147         out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
 148         out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
 149         out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
 150         immr_unmap(sys_tmr1);
 151
 152         init_internal_rtc();
 153
 154         /* Enabling the decrementer also enables the timebase interrupts
 155          * (or from the other point of view, to get decrementer interrupts
 156          * we have to enable the timebase).  The decrementer interrupt
 157          * is wired into the vector table, nothing to do here for that.
 158          */
 159         cpu = of_find_node_by_type(NULL, "cpu");
 160         virq= irq_of_parse_and_map(cpu, 0);
 161         irq = irq_map[virq].hwirq;
 162
 163         sys_tmr2 = immr_map(im_sit);
 164         out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
 165                                         (TBSCR_TBF | TBSCR_TBE));
 166         immr_unmap(sys_tmr2);
 167
 168         if (setup_irq(virq, &tbint_irqaction))
 169                 panic("Could not allocate timer IRQ!");
 170 }
 171
 172 /* The RTC on the MPC8xx is an internal register.
 173  * We want to protect this during power down, so we need to unlock,
 174  * modify, and re-lock.
 175  */
 176
 177 int mpc8xx_set_rtc_time(struct rtc_time *tm)
 178 {
 179         sitk8xx_t __iomem *sys_tmr1;
 180         sit8xx_t __iomem *sys_tmr2;
 181         int time;
 182
 183         sys_tmr1 = immr_map(im_sitk);
 184         sys_tmr2 = immr_map(im_sit);
 185         time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
 186                       tm->tm_hour, tm->tm_min, tm->tm_sec);
 187
 188         out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
 189         out_be32(&sys_tmr2->sit_rtc, time);
 190         out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
 191
 192         immr_unmap(sys_tmr2);
 193         immr_unmap(sys_tmr1);
 194         return 0;
 195 }
 196
 197 void mpc8xx_get_rtc_time(struct rtc_time *tm)
 198 {
 199         unsigned long data;
 200         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
 201
 202         /* Get time from the RTC. */
 203         data = in_be32(&sys_tmr->sit_rtc);
 204         to_tm(data, tm);
 205         tm->tm_year -= 1900;
 206         tm->tm_mon -= 1;
 207         immr_unmap(sys_tmr);
 208         return;
 209 }
 210
 211 void mpc8xx_restart(char *cmd)
 212 {
 213         car8xx_t __iomem *clk_r = immr_map(im_clkrst);
 214
 215
 216         local_irq_disable();
 217
 218         setbits32(&clk_r->car_plprcr, 0x00000080);
 219         /* Clear the ME bit in MSR to cause checkstop on machine check
 220         */
 221         mtmsr(mfmsr() & ~0x1000);
 222
 223         in_8(&clk_r->res[0]);
 224         panic("Restart failed\n");
 225 }
 226
 227 static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
 228 {
 229         int cascade_irq;
 230
 231         if ((cascade_irq = cpm_get_irq()) >= 0) {
 232                 struct irq_desc *cdesc = irq_desc + cascade_irq;
 233
 234                 generic_handle_irq(cascade_irq);
 235                 cdesc->chip->eoi(cascade_irq);
 236         }
 237         desc->chip->eoi(irq);
 238 }
 239
 240 /* Initialize the internal interrupt controller.  The number of
 241  * interrupts supported can vary with the processor type, and the
 242  * 82xx family can have up to 64.
 243  * External interrupts can be either edge or level triggered, and
 244  * need to be initialized by the appropriate driver.
 245  */
 246 void __init m8xx_pic_init(void)
 247 {
 248         int irq;
 249
 250         if (mpc8xx_pic_init()) {
 251                 printk(KERN_ERR "Failed interrupt 8xx controller  initialization\n");
 252                 return;
 253         }
 254
 255         irq = cpm_pic_init();
 256         if (irq != NO_IRQ)
 257                 set_irq_chained_handler(irq, cpm_cascade);
 258 }