x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / arch / sh / drivers / pci / pci.c
blob49b435c3a57a382302f97e8977954ee510c0aab3
1 /*
2 * arch/sh/drivers/pci/pci.c
4 * Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org>
5 * Copyright (c) 2004 - 2006 Paul Mundt <lethal@linux-sh.org>
7 * These functions are collected here to reduce duplication of common
8 * code amongst the many platform-specific PCI support code files.
10 * These routines require the following board-specific routines:
11 * void pcibios_fixup_irqs();
13 * See include/asm-sh/pci.h for more information.
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <asm/io.h>
24 static inline u8 bridge_swizzle(u8 pin, u8 slot)
26 return (((pin - 1) + slot) % 4) + 1;
29 static u8 __init simple_swizzle(struct pci_dev *dev, u8 *pinp)
31 u8 pin = *pinp;
33 while (dev->bus->parent) {
34 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
35 /* Move up the chain of bridges. */
36 dev = dev->bus->self;
38 *pinp = pin;
40 /* The slot is the slot of the last bridge. */
41 return PCI_SLOT(dev->devfn);
44 static int __init pcibios_init(void)
46 struct pci_channel *p;
47 struct pci_bus *bus;
48 int busno;
50 #ifdef CONFIG_PCI_AUTO
51 /* assign resources */
52 busno = 0;
53 for (p = board_pci_channels; p->pci_ops != NULL; p++)
54 busno = pciauto_assign_resources(busno, p) + 1;
55 #endif
57 /* scan the buses */
58 busno = 0;
59 for (p = board_pci_channels; p->pci_ops != NULL; p++) {
60 bus = pci_scan_bus(busno, p->pci_ops, p);
61 busno = bus->subordinate + 1;
64 pci_fixup_irqs(simple_swizzle, pcibios_map_platform_irq);
66 return 0;
68 subsys_initcall(pcibios_init);
71 * Called after each bus is probed, but before its children
72 * are examined.
74 void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus)
76 pci_read_bridge_bases(bus);
79 void
80 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
81 struct resource *res, int resource)
83 u32 new, check;
84 int reg;
86 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
87 if (resource < 6) {
88 reg = PCI_BASE_ADDRESS_0 + 4*resource;
89 } else if (resource == PCI_ROM_RESOURCE) {
90 res->flags |= IORESOURCE_ROM_ENABLE;
91 new |= PCI_ROM_ADDRESS_ENABLE;
92 reg = dev->rom_base_reg;
93 } else {
95 * Somebody might have asked allocation of a non-standard
96 * resource
98 return;
101 pci_write_config_dword(dev, reg, new);
102 pci_read_config_dword(dev, reg, &check);
103 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ?
104 PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
105 printk(KERN_ERR "PCI: Error while updating region "
106 "%s/%d (%08x != %08x)\n", pci_name(dev), resource,
107 new, check);
111 void pcibios_align_resource(void *data, struct resource *res,
112 resource_size_t size, resource_size_t align)
113 __attribute__ ((weak));
116 * We need to avoid collisions with `mirrored' VGA ports
117 * and other strange ISA hardware, so we always want the
118 * addresses to be allocated in the 0x000-0x0ff region
119 * modulo 0x400.
121 void pcibios_align_resource(void *data, struct resource *res,
122 resource_size_t size, resource_size_t align)
124 if (res->flags & IORESOURCE_IO) {
125 resource_size_t start = res->start;
127 if (start & 0x300) {
128 start = (start + 0x3ff) & ~0x3ff;
129 res->start = start;
134 int pcibios_enable_device(struct pci_dev *dev, int mask)
136 u16 cmd, old_cmd;
137 int idx;
138 struct resource *r;
140 pci_read_config_word(dev, PCI_COMMAND, &cmd);
141 old_cmd = cmd;
142 for(idx=0; idx<6; idx++) {
143 if (!(mask & (1 << idx)))
144 continue;
145 r = &dev->resource[idx];
146 if (!r->start && r->end) {
147 printk(KERN_ERR "PCI: Device %s not available because "
148 "of resource collisions\n", pci_name(dev));
149 return -EINVAL;
151 if (r->flags & IORESOURCE_IO)
152 cmd |= PCI_COMMAND_IO;
153 if (r->flags & IORESOURCE_MEM)
154 cmd |= PCI_COMMAND_MEMORY;
156 if (dev->resource[PCI_ROM_RESOURCE].start)
157 cmd |= PCI_COMMAND_MEMORY;
158 if (cmd != old_cmd) {
159 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
160 pci_name(dev), old_cmd, cmd);
161 pci_write_config_word(dev, PCI_COMMAND, cmd);
163 return 0;
167 * If we set up a device for bus mastering, we need to check and set
168 * the latency timer as it may not be properly set.
170 unsigned int pcibios_max_latency = 255;
172 void pcibios_set_master(struct pci_dev *dev)
174 u8 lat;
175 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
176 if (lat < 16)
177 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
178 else if (lat > pcibios_max_latency)
179 lat = pcibios_max_latency;
180 else
181 return;
182 printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
183 pci_name(dev), lat);
184 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
187 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
189 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
192 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
194 unsigned long start = pci_resource_start(dev, bar);
195 unsigned long len = pci_resource_len(dev, bar);
196 unsigned long flags = pci_resource_flags(dev, bar);
198 if (unlikely(!len || !start))
199 return NULL;
200 if (maxlen && len > maxlen)
201 len = maxlen;
204 * Presently the IORESOURCE_MEM case is a bit special, most
205 * SH7751 style PCI controllers have PCI memory at a fixed
206 * location in the address space where no remapping is desired
207 * (typically at 0xfd000000, but is_pci_memaddr() will know
208 * best). With the IORESOURCE_MEM case more care has to be taken
209 * to inhibit page table mapping for legacy cores, but this is
210 * punted off to __ioremap().
211 * -- PFM.
213 if (flags & IORESOURCE_IO)
214 return ioport_map(start, len);
215 if (flags & IORESOURCE_MEM)
216 return ioremap(start, len);
218 return NULL;
220 EXPORT_SYMBOL(pci_iomap);
222 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
224 iounmap(addr);
226 EXPORT_SYMBOL(pci_iounmap);