?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: cpa self-test, WARN_ON()
[wrt350n-kernel.git] / drivers / ata / ata_piix.c
bloba65c8ae5c461136bae02ccf766030d1c3ecb20e4
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94 #include <linux/dmi.h>
95
96 #define DRV_NAME "ata_piix"
97 #define DRV_VERSION "2.12"
98
99 enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
103 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
108
109 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_80C_PRI = (1 << 5) | (1 << 4),
117 PIIX_80C_SEC = (1 << 7) | (1 << 6),
118
119 /* constants for mapping table */
120 P0 = 0, /* port 0 */
121 P1 = 1, /* port 1 */
122 P2 = 2, /* port 2 */
123 P3 = 3, /* port 3 */
124 IDE = -1, /* IDE */
125 NA = -2, /* not avaliable */
126 RV = -3, /* reserved */
127
128 PIIX_AHCI_DEVICE = 6,
129
130 /* host->flags bits */
131 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
132 };
133
134 enum piix_controller_ids {
135 /* controller IDs */
136 piix_pata_mwdma, /* PIIX3 MWDMA only */
137 piix_pata_33, /* PIIX4 at 33Mhz */
138 ich_pata_33, /* ICH up to UDMA 33 only */
139 ich_pata_66, /* ICH up to 66 Mhz */
140 ich_pata_100, /* ICH up to UDMA 100 */
141 ich5_sata,
142 ich6_sata,
143 ich6_sata_ahci,
144 ich6m_sata_ahci,
145 ich8_sata_ahci,
146 ich8_2port_sata,
147 ich8m_apple_sata_ahci, /* locks up on second port enable */
148 tolapai_sata_ahci,
149 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
150 };
151
152 struct piix_map_db {
153 const u32 mask;
154 const u16 port_enable;
155 const int map[][4];
156 };
157
158 struct piix_host_priv {
159 const int *map;
160 void __iomem *sidpr;
161 };
162
163 static int piix_init_one(struct pci_dev *pdev,
164 const struct pci_device_id *ent);
165 static void piix_pata_error_handler(struct ata_port *ap);
166 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
167 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
168 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
169 static int ich_pata_cable_detect(struct ata_port *ap);
170 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
171 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val);
172 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val);
173 static void piix_sidpr_error_handler(struct ata_port *ap);
174 #ifdef CONFIG_PM
175 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
176 static int piix_pci_device_resume(struct pci_dev *pdev);
177 #endif
178
179 static unsigned int in_module_init = 1;
180
181 static const struct pci_device_id piix_pci_tbl[] = {
182 /* Intel PIIX3 for the 430HX etc */
183 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
184 /* VMware ICH4 */
185 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
186 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
187 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
188 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
189 /* Intel PIIX4 */
190 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
191 /* Intel PIIX4 */
192 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
193 /* Intel PIIX */
194 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
195 /* Intel ICH (i810, i815, i840) UDMA 66*/
196 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
197 /* Intel ICH0 : UDMA 33*/
198 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
199 /* Intel ICH2M */
200 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
202 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* Intel ICH3M */
204 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* Intel ICH3 (E7500/1) UDMA 100 */
206 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
208 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH5 */
211 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 /* C-ICH (i810E2) */
213 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
214 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
215 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
216 /* ICH6 (and 6) (i915) UDMA 100 */
217 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
218 /* ICH7/7-R (i945, i975) UDMA 100*/
219 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
220 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* ICH8 Mobile PATA Controller */
222 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
223
224 /* NOTE: The following PCI ids must be kept in sync with the
225 * list in drivers/pci/quirks.c.
226 */
227
228 /* 82801EB (ICH5) */
229 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
230 /* 82801EB (ICH5) */
231 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
232 /* 6300ESB (ICH5 variant with broken PCS present bits) */
233 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
234 /* 6300ESB pretending RAID */
235 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
236 /* 82801FB/FW (ICH6/ICH6W) */
237 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* 82801FR/FRW (ICH6R/ICH6RW) */
239 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
240 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
241 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
242 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
243 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
244 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
245 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
246 /* Enterprise Southbridge 2 (631xESB/632xESB) */
247 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
248 /* SATA Controller 1 IDE (ICH8) */
249 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
250 /* SATA Controller 2 IDE (ICH8) */
251 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* Mobile SATA Controller IDE (ICH8M) */
253 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
254 /* Mobile SATA Controller IDE (ICH8M), Apple */
255 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
256 /* SATA Controller IDE (ICH9) */
257 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
258 /* SATA Controller IDE (ICH9) */
259 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
260 /* SATA Controller IDE (ICH9) */
261 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
262 /* SATA Controller IDE (ICH9M) */
263 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* SATA Controller IDE (ICH9M) */
265 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH9M) */
267 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
268 /* SATA Controller IDE (Tolapai) */
269 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
270
271 { } /* terminate list */
272 };
273
274 static struct pci_driver piix_pci_driver = {
275 .name = DRV_NAME,
276 .id_table = piix_pci_tbl,
277 .probe = piix_init_one,
278 .remove = ata_pci_remove_one,
279 #ifdef CONFIG_PM
280 .suspend = piix_pci_device_suspend,
281 .resume = piix_pci_device_resume,
282 #endif
283 };
284
285 static struct scsi_host_template piix_sht = {
286 .module = THIS_MODULE,
287 .name = DRV_NAME,
288 .ioctl = ata_scsi_ioctl,
289 .queuecommand = ata_scsi_queuecmd,
290 .can_queue = ATA_DEF_QUEUE,
291 .this_id = ATA_SHT_THIS_ID,
292 .sg_tablesize = LIBATA_MAX_PRD,
293 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
294 .emulated = ATA_SHT_EMULATED,
295 .use_clustering = ATA_SHT_USE_CLUSTERING,
296 .proc_name = DRV_NAME,
297 .dma_boundary = ATA_DMA_BOUNDARY,
298 .slave_configure = ata_scsi_slave_config,
299 .slave_destroy = ata_scsi_slave_destroy,
300 .bios_param = ata_std_bios_param,
301 };
302
303 static const struct ata_port_operations piix_pata_ops = {
304 .set_piomode = piix_set_piomode,
305 .set_dmamode = piix_set_dmamode,
306 .mode_filter = ata_pci_default_filter,
307
308 .tf_load = ata_tf_load,
309 .tf_read = ata_tf_read,
310 .check_status = ata_check_status,
311 .exec_command = ata_exec_command,
312 .dev_select = ata_std_dev_select,
313
314 .bmdma_setup = ata_bmdma_setup,
315 .bmdma_start = ata_bmdma_start,
316 .bmdma_stop = ata_bmdma_stop,
317 .bmdma_status = ata_bmdma_status,
318 .qc_prep = ata_qc_prep,
319 .qc_issue = ata_qc_issue_prot,
320 .data_xfer = ata_data_xfer,
321
322 .freeze = ata_bmdma_freeze,
323 .thaw = ata_bmdma_thaw,
324 .error_handler = piix_pata_error_handler,
325 .post_internal_cmd = ata_bmdma_post_internal_cmd,
326 .cable_detect = ata_cable_40wire,
327
328 .irq_clear = ata_bmdma_irq_clear,
329 .irq_on = ata_irq_on,
330
331 .port_start = ata_port_start,
332 };
333
334 static const struct ata_port_operations ich_pata_ops = {
335 .set_piomode = piix_set_piomode,
336 .set_dmamode = ich_set_dmamode,
337 .mode_filter = ata_pci_default_filter,
338
339 .tf_load = ata_tf_load,
340 .tf_read = ata_tf_read,
341 .check_status = ata_check_status,
342 .exec_command = ata_exec_command,
343 .dev_select = ata_std_dev_select,
344
345 .bmdma_setup = ata_bmdma_setup,
346 .bmdma_start = ata_bmdma_start,
347 .bmdma_stop = ata_bmdma_stop,
348 .bmdma_status = ata_bmdma_status,
349 .qc_prep = ata_qc_prep,
350 .qc_issue = ata_qc_issue_prot,
351 .data_xfer = ata_data_xfer,
352
353 .freeze = ata_bmdma_freeze,
354 .thaw = ata_bmdma_thaw,
355 .error_handler = piix_pata_error_handler,
356 .post_internal_cmd = ata_bmdma_post_internal_cmd,
357 .cable_detect = ich_pata_cable_detect,
358
359 .irq_clear = ata_bmdma_irq_clear,
360 .irq_on = ata_irq_on,
361
362 .port_start = ata_port_start,
363 };
364
365 static const struct ata_port_operations piix_sata_ops = {
366 .tf_load = ata_tf_load,
367 .tf_read = ata_tf_read,
368 .check_status = ata_check_status,
369 .exec_command = ata_exec_command,
370 .dev_select = ata_std_dev_select,
371
372 .bmdma_setup = ata_bmdma_setup,
373 .bmdma_start = ata_bmdma_start,
374 .bmdma_stop = ata_bmdma_stop,
375 .bmdma_status = ata_bmdma_status,
376 .qc_prep = ata_qc_prep,
377 .qc_issue = ata_qc_issue_prot,
378 .data_xfer = ata_data_xfer,
379
380 .freeze = ata_bmdma_freeze,
381 .thaw = ata_bmdma_thaw,
382 .error_handler = ata_bmdma_error_handler,
383 .post_internal_cmd = ata_bmdma_post_internal_cmd,
384
385 .irq_clear = ata_bmdma_irq_clear,
386 .irq_on = ata_irq_on,
387
388 .port_start = ata_port_start,
389 };
390
391 static const struct ata_port_operations piix_vmw_ops = {
392 .set_piomode = piix_set_piomode,
393 .set_dmamode = piix_set_dmamode,
394 .mode_filter = ata_pci_default_filter,
395
396 .tf_load = ata_tf_load,
397 .tf_read = ata_tf_read,
398 .check_status = ata_check_status,
399 .exec_command = ata_exec_command,
400 .dev_select = ata_std_dev_select,
401
402 .bmdma_setup = ata_bmdma_setup,
403 .bmdma_start = ata_bmdma_start,
404 .bmdma_stop = ata_bmdma_stop,
405 .bmdma_status = piix_vmw_bmdma_status,
406 .qc_prep = ata_qc_prep,
407 .qc_issue = ata_qc_issue_prot,
408 .data_xfer = ata_data_xfer,
409
410 .freeze = ata_bmdma_freeze,
411 .thaw = ata_bmdma_thaw,
412 .error_handler = piix_pata_error_handler,
413 .post_internal_cmd = ata_bmdma_post_internal_cmd,
414 .cable_detect = ata_cable_40wire,
415
416 .irq_handler = ata_interrupt,
417 .irq_clear = ata_bmdma_irq_clear,
418 .irq_on = ata_irq_on,
419
420 .port_start = ata_port_start,
421 };
422
423 static const struct ata_port_operations piix_sidpr_sata_ops = {
424 .tf_load = ata_tf_load,
425 .tf_read = ata_tf_read,
426 .check_status = ata_check_status,
427 .exec_command = ata_exec_command,
428 .dev_select = ata_std_dev_select,
429
430 .bmdma_setup = ata_bmdma_setup,
431 .bmdma_start = ata_bmdma_start,
432 .bmdma_stop = ata_bmdma_stop,
433 .bmdma_status = ata_bmdma_status,
434 .qc_prep = ata_qc_prep,
435 .qc_issue = ata_qc_issue_prot,
436 .data_xfer = ata_data_xfer,
437
438 .scr_read = piix_sidpr_scr_read,
439 .scr_write = piix_sidpr_scr_write,
440
441 .freeze = ata_bmdma_freeze,
442 .thaw = ata_bmdma_thaw,
443 .error_handler = piix_sidpr_error_handler,
444 .post_internal_cmd = ata_bmdma_post_internal_cmd,
445
446 .irq_clear = ata_bmdma_irq_clear,
447 .irq_on = ata_irq_on,
448
449 .port_start = ata_port_start,
450 };
451
452 static const struct piix_map_db ich5_map_db = {
453 .mask = 0x7,
454 .port_enable = 0x3,
455 .map = {
456 /* PM PS SM SS MAP */
457 { P0, NA, P1, NA }, /* 000b */
458 { P1, NA, P0, NA }, /* 001b */
459 { RV, RV, RV, RV },
460 { RV, RV, RV, RV },
461 { P0, P1, IDE, IDE }, /* 100b */
462 { P1, P0, IDE, IDE }, /* 101b */
463 { IDE, IDE, P0, P1 }, /* 110b */
464 { IDE, IDE, P1, P0 }, /* 111b */
465 },
466 };
467
468 static const struct piix_map_db ich6_map_db = {
469 .mask = 0x3,
470 .port_enable = 0xf,
471 .map = {
472 /* PM PS SM SS MAP */
473 { P0, P2, P1, P3 }, /* 00b */
474 { IDE, IDE, P1, P3 }, /* 01b */
475 { P0, P2, IDE, IDE }, /* 10b */
476 { RV, RV, RV, RV },
477 },
478 };
479
480 static const struct piix_map_db ich6m_map_db = {
481 .mask = 0x3,
482 .port_enable = 0x5,
483
484 /* Map 01b isn't specified in the doc but some notebooks use
485 * it anyway. MAP 01b have been spotted on both ICH6M and
486 * ICH7M.
487 */
488 .map = {
489 /* PM PS SM SS MAP */
490 { P0, P2, NA, NA }, /* 00b */
491 { IDE, IDE, P1, P3 }, /* 01b */
492 { P0, P2, IDE, IDE }, /* 10b */
493 { RV, RV, RV, RV },
494 },
495 };
496
497 static const struct piix_map_db ich8_map_db = {
498 .mask = 0x3,
499 .port_enable = 0xf,
500 .map = {
501 /* PM PS SM SS MAP */
502 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
503 { RV, RV, RV, RV },
504 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
505 { RV, RV, RV, RV },
506 },
507 };
508
509 static const struct piix_map_db ich8_2port_map_db = {
510 .mask = 0x3,
511 .port_enable = 0x3,
512 .map = {
513 /* PM PS SM SS MAP */
514 { P0, NA, P1, NA }, /* 00b */
515 { RV, RV, RV, RV }, /* 01b */
516 { RV, RV, RV, RV }, /* 10b */
517 { RV, RV, RV, RV },
518 },
519 };
520
521 static const struct piix_map_db ich8m_apple_map_db = {
522 .mask = 0x3,
523 .port_enable = 0x1,
524 .map = {
525 /* PM PS SM SS MAP */
526 { P0, NA, NA, NA }, /* 00b */
527 { RV, RV, RV, RV },
528 { P0, P2, IDE, IDE }, /* 10b */
529 { RV, RV, RV, RV },
530 },
531 };
532
533 static const struct piix_map_db tolapai_map_db = {
534 .mask = 0x3,
535 .port_enable = 0x3,
536 .map = {
537 /* PM PS SM SS MAP */
538 { P0, NA, P1, NA }, /* 00b */
539 { RV, RV, RV, RV }, /* 01b */
540 { RV, RV, RV, RV }, /* 10b */
541 { RV, RV, RV, RV },
542 },
543 };
544
545 static const struct piix_map_db *piix_map_db_table[] = {
546 [ich5_sata] = &ich5_map_db,
547 [ich6_sata] = &ich6_map_db,
548 [ich6_sata_ahci] = &ich6_map_db,
549 [ich6m_sata_ahci] = &ich6m_map_db,
550 [ich8_sata_ahci] = &ich8_map_db,
551 [ich8_2port_sata] = &ich8_2port_map_db,
552 [ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
553 [tolapai_sata_ahci] = &tolapai_map_db,
554 };
555
556 static struct ata_port_info piix_port_info[] = {
557 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
558 {
559 .flags = PIIX_PATA_FLAGS,
560 .pio_mask = 0x1f, /* pio0-4 */
561 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
562 .port_ops = &piix_pata_ops,
563 },
564
565 [piix_pata_33] = /* PIIX4 at 33MHz */
566 {
567 .flags = PIIX_PATA_FLAGS,
568 .pio_mask = 0x1f, /* pio0-4 */
569 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
570 .udma_mask = ATA_UDMA_MASK_40C,
571 .port_ops = &piix_pata_ops,
572 },
573
574 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
575 {
576 .flags = PIIX_PATA_FLAGS,
577 .pio_mask = 0x1f, /* pio 0-4 */
578 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
579 .udma_mask = ATA_UDMA2, /* UDMA33 */
580 .port_ops = &ich_pata_ops,
581 },
582
583 [ich_pata_66] = /* ICH controllers up to 66MHz */
584 {
585 .flags = PIIX_PATA_FLAGS,
586 .pio_mask = 0x1f, /* pio 0-4 */
587 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
588 .udma_mask = ATA_UDMA4,
589 .port_ops = &ich_pata_ops,
590 },
591
592 [ich_pata_100] =
593 {
594 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
595 .pio_mask = 0x1f, /* pio0-4 */
596 .mwdma_mask = 0x06, /* mwdma1-2 */
597 .udma_mask = ATA_UDMA5, /* udma0-5 */
598 .port_ops = &ich_pata_ops,
599 },
600
601 [ich5_sata] =
602 {
603 .flags = PIIX_SATA_FLAGS,
604 .pio_mask = 0x1f, /* pio0-4 */
605 .mwdma_mask = 0x07, /* mwdma0-2 */
606 .udma_mask = ATA_UDMA6,
607 .port_ops = &piix_sata_ops,
608 },
609
610 [ich6_sata] =
611 {
612 .flags = PIIX_SATA_FLAGS,
613 .pio_mask = 0x1f, /* pio0-4 */
614 .mwdma_mask = 0x07, /* mwdma0-2 */
615 .udma_mask = ATA_UDMA6,
616 .port_ops = &piix_sata_ops,
617 },
618
619 [ich6_sata_ahci] =
620 {
621 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
622 .pio_mask = 0x1f, /* pio0-4 */
623 .mwdma_mask = 0x07, /* mwdma0-2 */
624 .udma_mask = ATA_UDMA6,
625 .port_ops = &piix_sata_ops,
626 },
627
628 [ich6m_sata_ahci] =
629 {
630 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
631 .pio_mask = 0x1f, /* pio0-4 */
632 .mwdma_mask = 0x07, /* mwdma0-2 */
633 .udma_mask = ATA_UDMA6,
634 .port_ops = &piix_sata_ops,
635 },
636
637 [ich8_sata_ahci] =
638 {
639 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
640 PIIX_FLAG_SIDPR,
641 .pio_mask = 0x1f, /* pio0-4 */
642 .mwdma_mask = 0x07, /* mwdma0-2 */
643 .udma_mask = ATA_UDMA6,
644 .port_ops = &piix_sata_ops,
645 },
646
647 [ich8_2port_sata] =
648 {
649 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
650 PIIX_FLAG_SIDPR,
651 .pio_mask = 0x1f, /* pio0-4 */
652 .mwdma_mask = 0x07, /* mwdma0-2 */
653 .udma_mask = ATA_UDMA6,
654 .port_ops = &piix_sata_ops,
655 },
656
657 [tolapai_sata_ahci] =
658 {
659 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI,
660 .pio_mask = 0x1f, /* pio0-4 */
661 .mwdma_mask = 0x07, /* mwdma0-2 */
662 .udma_mask = ATA_UDMA6,
663 .port_ops = &piix_sata_ops,
664 },
665
666 [ich8m_apple_sata_ahci] =
667 {
668 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_AHCI |
669 PIIX_FLAG_SIDPR,
670 .pio_mask = 0x1f, /* pio0-4 */
671 .mwdma_mask = 0x07, /* mwdma0-2 */
672 .udma_mask = ATA_UDMA6,
673 .port_ops = &piix_sata_ops,
674 },
675
676 [piix_pata_vmw] =
677 {
678 .sht = &piix_sht,
679 .flags = PIIX_PATA_FLAGS,
680 .pio_mask = 0x1f, /* pio0-4 */
681 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
682 .udma_mask = ATA_UDMA_MASK_40C,
683 .port_ops = &piix_vmw_ops,
684 },
685
686 };
687
688 static struct pci_bits piix_enable_bits[] = {
689 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
690 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
691 };
692
693 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
694 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
695 MODULE_LICENSE("GPL");
696 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
697 MODULE_VERSION(DRV_VERSION);
698
699 struct ich_laptop {
700 u16 device;
701 u16 subvendor;
702 u16 subdevice;
703 };
704
705 /*
706 * List of laptops that use short cables rather than 80 wire
707 */
708
709 static const struct ich_laptop ich_laptop[] = {
710 /* devid, subvendor, subdev */
711 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
712 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
713 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
714 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
715 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
716 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
717 /* end marker */
718 { 0, }
719 };
720
721 /**
722 * ich_pata_cable_detect - Probe host controller cable detect info
723 * @ap: Port for which cable detect info is desired
724 *
725 * Read 80c cable indicator from ATA PCI device's PCI config
726 * register. This register is normally set by firmware (BIOS).
727 *
728 * LOCKING:
729 * None (inherited from caller).
730 */
731
732 static int ich_pata_cable_detect(struct ata_port *ap)
733 {
734 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
735 const struct ich_laptop *lap = &ich_laptop[0];
736 u8 tmp, mask;
737
738 /* Check for specials - Acer Aspire 5602WLMi */
739 while (lap->device) {
740 if (lap->device == pdev->device &&
741 lap->subvendor == pdev->subsystem_vendor &&
742 lap->subdevice == pdev->subsystem_device)
743 return ATA_CBL_PATA40_SHORT;
744
745 lap++;
746 }
747
748 /* check BIOS cable detect results */
749 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
750 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
751 if ((tmp & mask) == 0)
752 return ATA_CBL_PATA40;
753 return ATA_CBL_PATA80;
754 }
755
756 /**
757 * piix_pata_prereset - prereset for PATA host controller
758 * @link: Target link
759 * @deadline: deadline jiffies for the operation
760 *
761 * LOCKING:
762 * None (inherited from caller).
763 */
764 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
765 {
766 struct ata_port *ap = link->ap;
767 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
768
769 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
770 return -ENOENT;
771 return ata_std_prereset(link, deadline);
772 }
773
774 static void piix_pata_error_handler(struct ata_port *ap)
775 {
776 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
777 ata_std_postreset);
778 }
779
780 /**
781 * piix_set_piomode - Initialize host controller PATA PIO timings
782 * @ap: Port whose timings we are configuring
783 * @adev: um
784 *
785 * Set PIO mode for device, in host controller PCI config space.
786 *
787 * LOCKING:
788 * None (inherited from caller).
789 */
790
791 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
792 {
793 unsigned int pio = adev->pio_mode - XFER_PIO_0;
794 struct pci_dev *dev = to_pci_dev(ap->host->dev);
795 unsigned int is_slave = (adev->devno != 0);
796 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
797 unsigned int slave_port = 0x44;
798 u16 master_data;
799 u8 slave_data;
800 u8 udma_enable;
801 int control = 0;
802
803 /*
804 * See Intel Document 298600-004 for the timing programing rules
805 * for ICH controllers.
806 */
807
808 static const /* ISP RTC */
809 u8 timings[][2] = { { 0, 0 },
810 { 0, 0 },
811 { 1, 0 },
812 { 2, 1 },
813 { 2, 3 }, };
814
815 if (pio >= 2)
816 control |= 1; /* TIME1 enable */
817 if (ata_pio_need_iordy(adev))
818 control |= 2; /* IE enable */
819
820 /* Intel specifies that the PPE functionality is for disk only */
821 if (adev->class == ATA_DEV_ATA)
822 control |= 4; /* PPE enable */
823
824 /* PIO configuration clears DTE unconditionally. It will be
825 * programmed in set_dmamode which is guaranteed to be called
826 * after set_piomode if any DMA mode is available.
827 */
828 pci_read_config_word(dev, master_port, &master_data);
829 if (is_slave) {
830 /* clear TIME1|IE1|PPE1|DTE1 */
831 master_data &= 0xff0f;
832 /* Enable SITRE (seperate slave timing register) */
833 master_data |= 0x4000;
834 /* enable PPE1, IE1 and TIME1 as needed */
835 master_data |= (control << 4);
836 pci_read_config_byte(dev, slave_port, &slave_data);
837 slave_data &= (ap->port_no ? 0x0f : 0xf0);
838 /* Load the timing nibble for this slave */
839 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
840 << (ap->port_no ? 4 : 0);
841 } else {
842 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
843 master_data &= 0xccf0;
844 /* Enable PPE, IE and TIME as appropriate */
845 master_data |= control;
846 /* load ISP and RCT */
847 master_data |=
848 (timings[pio][0] << 12) |
849 (timings[pio][1] << 8);
850 }
851 pci_write_config_word(dev, master_port, master_data);
852 if (is_slave)
853 pci_write_config_byte(dev, slave_port, slave_data);
854
855 /* Ensure the UDMA bit is off - it will be turned back on if
856 UDMA is selected */
857
858 if (ap->udma_mask) {
859 pci_read_config_byte(dev, 0x48, &udma_enable);
860 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
861 pci_write_config_byte(dev, 0x48, udma_enable);
862 }
863 }
864
865 /**
866 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
867 * @ap: Port whose timings we are configuring
868 * @adev: Drive in question
869 * @udma: udma mode, 0 - 6
870 * @isich: set if the chip is an ICH device
871 *
872 * Set UDMA mode for device, in host controller PCI config space.
873 *
874 * LOCKING:
875 * None (inherited from caller).
876 */
877
878 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
879 {
880 struct pci_dev *dev = to_pci_dev(ap->host->dev);
881 u8 master_port = ap->port_no ? 0x42 : 0x40;
882 u16 master_data;
883 u8 speed = adev->dma_mode;
884 int devid = adev->devno + 2 * ap->port_no;
885 u8 udma_enable = 0;
886
887 static const /* ISP RTC */
888 u8 timings[][2] = { { 0, 0 },
889 { 0, 0 },
890 { 1, 0 },
891 { 2, 1 },
892 { 2, 3 }, };
893
894 pci_read_config_word(dev, master_port, &master_data);
895 if (ap->udma_mask)
896 pci_read_config_byte(dev, 0x48, &udma_enable);
897
898 if (speed >= XFER_UDMA_0) {
899 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
900 u16 udma_timing;
901 u16 ideconf;
902 int u_clock, u_speed;
903
904 /*
905 * UDMA is handled by a combination of clock switching and
906 * selection of dividers
907 *
908 * Handy rule: Odd modes are UDMATIMx 01, even are 02
909 * except UDMA0 which is 00
910 */
911 u_speed = min(2 - (udma & 1), udma);
912 if (udma == 5)
913 u_clock = 0x1000; /* 100Mhz */
914 else if (udma > 2)
915 u_clock = 1; /* 66Mhz */
916 else
917 u_clock = 0; /* 33Mhz */
918
919 udma_enable |= (1 << devid);
920
921 /* Load the CT/RP selection */
922 pci_read_config_word(dev, 0x4A, &udma_timing);
923 udma_timing &= ~(3 << (4 * devid));
924 udma_timing |= u_speed << (4 * devid);
925 pci_write_config_word(dev, 0x4A, udma_timing);
926
927 if (isich) {
928 /* Select a 33/66/100Mhz clock */
929 pci_read_config_word(dev, 0x54, &ideconf);
930 ideconf &= ~(0x1001 << devid);
931 ideconf |= u_clock << devid;
932 /* For ICH or later we should set bit 10 for better
933 performance (WR_PingPong_En) */
934 pci_write_config_word(dev, 0x54, ideconf);
935 }
936 } else {
937 /*
938 * MWDMA is driven by the PIO timings. We must also enable
939 * IORDY unconditionally along with TIME1. PPE has already
940 * been set when the PIO timing was set.
941 */
942 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
943 unsigned int control;
944 u8 slave_data;
945 const unsigned int needed_pio[3] = {
946 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
947 };
948 int pio = needed_pio[mwdma] - XFER_PIO_0;
949
950 control = 3; /* IORDY|TIME1 */
951
952 /* If the drive MWDMA is faster than it can do PIO then
953 we must force PIO into PIO0 */
954
955 if (adev->pio_mode < needed_pio[mwdma])
956 /* Enable DMA timing only */
957 control |= 8; /* PIO cycles in PIO0 */
958
959 if (adev->devno) { /* Slave */
960 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
961 master_data |= control << 4;
962 pci_read_config_byte(dev, 0x44, &slave_data);
963 slave_data &= (ap->port_no ? 0x0f : 0xf0);
964 /* Load the matching timing */
965 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
966 pci_write_config_byte(dev, 0x44, slave_data);
967 } else { /* Master */
968 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
969 and master timing bits */
970 master_data |= control;
971 master_data |=
972 (timings[pio][0] << 12) |
973 (timings[pio][1] << 8);
974 }
975
976 if (ap->udma_mask) {
977 udma_enable &= ~(1 << devid);
978 pci_write_config_word(dev, master_port, master_data);
979 }
980 }
981 /* Don't scribble on 0x48 if the controller does not support UDMA */
982 if (ap->udma_mask)
983 pci_write_config_byte(dev, 0x48, udma_enable);
984 }
985
986 /**
987 * piix_set_dmamode - Initialize host controller PATA DMA timings
988 * @ap: Port whose timings we are configuring
989 * @adev: um
990 *
991 * Set MW/UDMA mode for device, in host controller PCI config space.
992 *
993 * LOCKING:
994 * None (inherited from caller).
995 */
996
997 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
998 {
999 do_pata_set_dmamode(ap, adev, 0);
1000 }
1001
1002 /**
1003 * ich_set_dmamode - Initialize host controller PATA DMA timings
1004 * @ap: Port whose timings we are configuring
1005 * @adev: um
1006 *
1007 * Set MW/UDMA mode for device, in host controller PCI config space.
1008 *
1009 * LOCKING:
1010 * None (inherited from caller).
1011 */
1012
1013 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
1014 {
1015 do_pata_set_dmamode(ap, adev, 1);
1016 }
1017
1018 /*
1019 * Serial ATA Index/Data Pair Superset Registers access
1020 *
1021 * Beginning from ICH8, there's a sane way to access SCRs using index
1022 * and data register pair located at BAR5. This creates an
1023 * interesting problem of mapping two SCRs to one port.
1024 *
1025 * Although they have separate SCRs, the master and slave aren't
1026 * independent enough to be treated as separate links - e.g. softreset
1027 * resets both. Also, there's no protocol defined for hard resetting
1028 * singled device sharing the virtual port (no defined way to acquire
1029 * device signature). This is worked around by merging the SCR values
1030 * into one sensible value and requesting follow-up SRST after
1031 * hardreset.
1032 *
1033 * SCR merging is perfomed in nibbles which is the unit contents in
1034 * SCRs are organized. If two values are equal, the value is used.
1035 * When they differ, merge table which lists precedence of possible
1036 * values is consulted and the first match or the last entry when
1037 * nothing matches is used. When there's no merge table for the
1038 * specific nibble, value from the first port is used.
1039 */
1040 static const int piix_sidx_map[] = {
1041 [SCR_STATUS] = 0,
1042 [SCR_ERROR] = 2,
1043 [SCR_CONTROL] = 1,
1044 };
1045
1046 static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg)
1047 {
1048 struct ata_port *ap = dev->link->ap;
1049 struct piix_host_priv *hpriv = ap->host->private_data;
1050
1051 iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg],
1052 hpriv->sidpr + PIIX_SIDPR_IDX);
1053 }
1054
1055 static int piix_sidpr_read(struct ata_device *dev, unsigned int reg)
1056 {
1057 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
1058
1059 piix_sidpr_sel(dev, reg);
1060 return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
1061 }
1062
1063 static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val)
1064 {
1065 struct piix_host_priv *hpriv = dev->link->ap->host->private_data;
1066
1067 piix_sidpr_sel(dev, reg);
1068 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1069 }
1070
1071 u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl)
1072 {
1073 u32 val = 0;
1074 int i, mi;
1075
1076 for (i = 0, mi = 0; i < 32 / 4; i++) {
1077 u8 c0 = (val0 >> (i * 4)) & 0xf;
1078 u8 c1 = (val1 >> (i * 4)) & 0xf;
1079 u8 merged = c0;
1080 const int *cur;
1081
1082 /* if no merge preference, assume the first value */
1083 cur = merge_tbl[mi];
1084 if (!cur)
1085 goto done;
1086 mi++;
1087
1088 /* if two values equal, use it */
1089 if (c0 == c1)
1090 goto done;
1091
1092 /* choose the first match or the last from the merge table */
1093 while (*cur != -1) {
1094 if (c0 == *cur || c1 == *cur)
1095 break;
1096 cur++;
1097 }
1098 if (*cur == -1)
1099 cur--;
1100 merged = *cur;
1101 done:
1102 val |= merged << (i * 4);
1103 }
1104
1105 return val;
1106 }
1107
1108 static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val)
1109 {
1110 const int * const sstatus_merge_tbl[] = {
1111 /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 },
1112 /* SPD */ (const int []){ 2, 1, 0, -1 },
1113 /* IPM */ (const int []){ 6, 2, 1, 0, -1 },
1114 NULL,
1115 };
1116 const int * const scontrol_merge_tbl[] = {
1117 /* DET */ (const int []){ 1, 0, 4, 0, -1 },
1118 /* SPD */ (const int []){ 0, 2, 1, 0, -1 },
1119 /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 },
1120 NULL,
1121 };
1122 u32 v0, v1;
1123
1124 if (reg >= ARRAY_SIZE(piix_sidx_map))
1125 return -EINVAL;
1126
1127 if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) {
1128 *val = piix_sidpr_read(&ap->link.device[0], reg);
1129 return 0;
1130 }
1131
1132 v0 = piix_sidpr_read(&ap->link.device[0], reg);
1133 v1 = piix_sidpr_read(&ap->link.device[1], reg);
1134
1135 switch (reg) {
1136 case SCR_STATUS:
1137 *val = piix_merge_scr(v0, v1, sstatus_merge_tbl);
1138 break;
1139 case SCR_ERROR:
1140 *val = v0 | v1;
1141 break;
1142 case SCR_CONTROL:
1143 *val = piix_merge_scr(v0, v1, scontrol_merge_tbl);
1144 break;
1145 }
1146
1147 return 0;
1148 }
1149
1150 static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val)
1151 {
1152 if (reg >= ARRAY_SIZE(piix_sidx_map))
1153 return -EINVAL;
1154
1155 piix_sidpr_write(&ap->link.device[0], reg, val);
1156
1157 if (ap->flags & ATA_FLAG_SLAVE_POSS)
1158 piix_sidpr_write(&ap->link.device[1], reg, val);
1159
1160 return 0;
1161 }
1162
1163 static int piix_sidpr_hardreset(struct ata_link *link, unsigned int *class,
1164 unsigned long deadline)
1165 {
1166 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1167 int rc;
1168
1169 /* do hardreset */
1170 rc = sata_link_hardreset(link, timing, deadline);
1171 if (rc) {
1172 ata_link_printk(link, KERN_ERR,
1173 "COMRESET failed (errno=%d)\n", rc);
1174 return rc;
1175 }
1176
1177 /* TODO: phy layer with polling, timeouts, etc. */
1178 if (ata_link_offline(link)) {
1179 *class = ATA_DEV_NONE;
1180 return 0;
1181 }
1182
1183 return -EAGAIN;
1184 }
1185
1186 static void piix_sidpr_error_handler(struct ata_port *ap)
1187 {
1188 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1189 piix_sidpr_hardreset, ata_std_postreset);
1190 }
1191
1192 #ifdef CONFIG_PM
1193 static int piix_broken_suspend(void)
1194 {
1195 static const struct dmi_system_id sysids[] = {
1196 {
1197 .ident = "TECRA M3",
1198 .matches = {
1199 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1200 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1201 },
1202 },
1203 {
1204 .ident = "TECRA M3",
1205 .matches = {
1206 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1207 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1208 },
1209 },
1210 {
1211 .ident = "TECRA M4",
1212 .matches = {
1213 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1214 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1215 },
1216 },
1217 {
1218 .ident = "TECRA M5",
1219 .matches = {
1220 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1221 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1222 },
1223 },
1224 {
1225 .ident = "TECRA M6",
1226 .matches = {
1227 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1228 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1229 },
1230 },
1231 {
1232 .ident = "TECRA M7",
1233 .matches = {
1234 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1235 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1236 },
1237 },
1238 {
1239 .ident = "TECRA A8",
1240 .matches = {
1241 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1242 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1243 },
1244 },
1245 {
1246 .ident = "Satellite R20",
1247 .matches = {
1248 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1249 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1250 },
1251 },
1252 {
1253 .ident = "Satellite R25",
1254 .matches = {
1255 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1256 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1257 },
1258 },
1259 {
1260 .ident = "Satellite U200",
1261 .matches = {
1262 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1263 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1264 },
1265 },
1266 {
1267 .ident = "Satellite U200",
1268 .matches = {
1269 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1270 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1271 },
1272 },
1273 {
1274 .ident = "Satellite Pro U200",
1275 .matches = {
1276 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1277 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1278 },
1279 },
1280 {
1281 .ident = "Satellite U205",
1282 .matches = {
1283 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1284 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1285 },
1286 },
1287 {
1288 .ident = "SATELLITE U205",
1289 .matches = {
1290 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1291 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1292 },
1293 },
1294 {
1295 .ident = "Portege M500",
1296 .matches = {
1297 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1298 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1299 },
1300 },
1301
1302 { } /* terminate list */
1303 };
1304 static const char *oemstrs[] = {
1305 "Tecra M3,",
1306 };
1307 int i;
1308
1309 if (dmi_check_system(sysids))
1310 return 1;
1311
1312 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1313 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1314 return 1;
1315
1316 return 0;
1317 }
1318
1319 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1320 {
1321 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1322 unsigned long flags;
1323 int rc = 0;
1324
1325 rc = ata_host_suspend(host, mesg);
1326 if (rc)
1327 return rc;
1328
1329 /* Some braindamaged ACPI suspend implementations expect the
1330 * controller to be awake on entry; otherwise, it burns cpu
1331 * cycles and power trying to do something to the sleeping
1332 * beauty.
1333 */
1334 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
1335 pci_save_state(pdev);
1336
1337 /* mark its power state as "unknown", since we don't
1338 * know if e.g. the BIOS will change its device state
1339 * when we suspend.
1340 */
1341 if (pdev->current_state == PCI_D0)
1342 pdev->current_state = PCI_UNKNOWN;
1343
1344 /* tell resume that it's waking up from broken suspend */
1345 spin_lock_irqsave(&host->lock, flags);
1346 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1347 spin_unlock_irqrestore(&host->lock, flags);
1348 } else
1349 ata_pci_device_do_suspend(pdev, mesg);
1350
1351 return 0;
1352 }
1353
1354 static int piix_pci_device_resume(struct pci_dev *pdev)
1355 {
1356 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1357 unsigned long flags;
1358 int rc;
1359
1360 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1361 spin_lock_irqsave(&host->lock, flags);
1362 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1363 spin_unlock_irqrestore(&host->lock, flags);
1364
1365 pci_set_power_state(pdev, PCI_D0);
1366 pci_restore_state(pdev);
1367
1368 /* PCI device wasn't disabled during suspend. Use
1369 * pci_reenable_device() to avoid affecting the enable
1370 * count.
1371 */
1372 rc = pci_reenable_device(pdev);
1373 if (rc)
1374 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1375 "device after resume (%d)\n", rc);
1376 } else
1377 rc = ata_pci_device_do_resume(pdev);
1378
1379 if (rc == 0)
1380 ata_host_resume(host);
1381
1382 return rc;
1383 }
1384 #endif
1385
1386 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1387 {
1388 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1389 }
1390
1391 #define AHCI_PCI_BAR 5
1392 #define AHCI_GLOBAL_CTL 0x04
1393 #define AHCI_ENABLE (1 << 31)
1394 static int piix_disable_ahci(struct pci_dev *pdev)
1395 {
1396 void __iomem *mmio;
1397 u32 tmp;
1398 int rc = 0;
1399
1400 /* BUG: pci_enable_device has not yet been called. This
1401 * works because this device is usually set up by BIOS.
1402 */
1403
1404 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1405 !pci_resource_len(pdev, AHCI_PCI_BAR))
1406 return 0;
1407
1408 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1409 if (!mmio)
1410 return -ENOMEM;
1411
1412 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1413 if (tmp & AHCI_ENABLE) {
1414 tmp &= ~AHCI_ENABLE;
1415 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1416
1417 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1418 if (tmp & AHCI_ENABLE)
1419 rc = -EIO;
1420 }
1421
1422 pci_iounmap(pdev, mmio);
1423 return rc;
1424 }
1425
1426 /**
1427 * piix_check_450nx_errata - Check for problem 450NX setup
1428 * @ata_dev: the PCI device to check
1429 *
1430 * Check for the present of 450NX errata #19 and errata #25. If
1431 * they are found return an error code so we can turn off DMA
1432 */
1433
1434 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1435 {
1436 struct pci_dev *pdev = NULL;
1437 u16 cfg;
1438 int no_piix_dma = 0;
1439
1440 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1441 /* Look for 450NX PXB. Check for problem configurations
1442 A PCI quirk checks bit 6 already */
1443 pci_read_config_word(pdev, 0x41, &cfg);
1444 /* Only on the original revision: IDE DMA can hang */
1445 if (pdev->revision == 0x00)
1446 no_piix_dma = 1;
1447 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1448 else if (cfg & (1<<14) && pdev->revision < 5)
1449 no_piix_dma = 2;
1450 }
1451 if (no_piix_dma)
1452 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1453 if (no_piix_dma == 2)
1454 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1455 return no_piix_dma;
1456 }
1457
1458 static void __devinit piix_init_pcs(struct ata_host *host,
1459 const struct piix_map_db *map_db)
1460 {
1461 struct pci_dev *pdev = to_pci_dev(host->dev);
1462 u16 pcs, new_pcs;
1463
1464 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1465
1466 new_pcs = pcs | map_db->port_enable;
1467
1468 if (new_pcs != pcs) {
1469 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1470 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1471 msleep(150);
1472 }
1473 }
1474
1475 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1476 struct ata_port_info *pinfo,
1477 const struct piix_map_db *map_db)
1478 {
1479 const int *map;
1480 int i, invalid_map = 0;
1481 u8 map_value;
1482
1483 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1484
1485 map = map_db->map[map_value & map_db->mask];
1486
1487 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1488 for (i = 0; i < 4; i++) {
1489 switch (map[i]) {
1490 case RV:
1491 invalid_map = 1;
1492 printk(" XX");
1493 break;
1494
1495 case NA:
1496 printk(" --");
1497 break;
1498
1499 case IDE:
1500 WARN_ON((i & 1) || map[i + 1] != IDE);
1501 pinfo[i / 2] = piix_port_info[ich_pata_100];
1502 i++;
1503 printk(" IDE IDE");
1504 break;
1505
1506 default:
1507 printk(" P%d", map[i]);
1508 if (i & 1)
1509 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1510 break;
1511 }
1512 }
1513 printk(" ]\n");
1514
1515 if (invalid_map)
1516 dev_printk(KERN_ERR, &pdev->dev,
1517 "invalid MAP value %u\n", map_value);
1518
1519 return map;
1520 }
1521
1522 static void __devinit piix_init_sidpr(struct ata_host *host)
1523 {
1524 struct pci_dev *pdev = to_pci_dev(host->dev);
1525 struct piix_host_priv *hpriv = host->private_data;
1526 int i;
1527
1528 /* check for availability */
1529 for (i = 0; i < 4; i++)
1530 if (hpriv->map[i] == IDE)
1531 return;
1532
1533 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1534 return;
1535
1536 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1537 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1538 return;
1539
1540 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1541 return;
1542
1543 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1544 host->ports[0]->ops = &piix_sidpr_sata_ops;
1545 host->ports[1]->ops = &piix_sidpr_sata_ops;
1546 }
1547
1548 static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1549 {
1550 static const struct dmi_system_id sysids[] = {
1551 {
1552 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1553 * isn't used to boot the system which
1554 * disables the channel.
1555 */
1556 .ident = "M570U",
1557 .matches = {
1558 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1559 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1560 },
1561 },
1562
1563 { } /* terminate list */
1564 };
1565 u32 iocfg;
1566
1567 if (!dmi_check_system(sysids))
1568 return;
1569
1570 /* The datasheet says that bit 18 is NOOP but certain systems
1571 * seem to use it to disable a channel. Clear the bit on the
1572 * affected systems.
1573 */
1574 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1575 if (iocfg & (1 << 18)) {
1576 dev_printk(KERN_INFO, &pdev->dev,
1577 "applying IOCFG bit18 quirk\n");
1578 iocfg &= ~(1 << 18);
1579 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1580 }
1581 }
1582
1583 /**
1584 * piix_init_one - Register PIIX ATA PCI device with kernel services
1585 * @pdev: PCI device to register
1586 * @ent: Entry in piix_pci_tbl matching with @pdev
1587 *
1588 * Called from kernel PCI layer. We probe for combined mode (sigh),
1589 * and then hand over control to libata, for it to do the rest.
1590 *
1591 * LOCKING:
1592 * Inherited from PCI layer (may sleep).
1593 *
1594 * RETURNS:
1595 * Zero on success, or -ERRNO value.
1596 */
1597
1598 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1599 {
1600 static int printed_version;
1601 struct device *dev = &pdev->dev;
1602 struct ata_port_info port_info[2];
1603 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1604 unsigned long port_flags;
1605 struct ata_host *host;
1606 struct piix_host_priv *hpriv;
1607 int rc;
1608
1609 if (!printed_version++)
1610 dev_printk(KERN_DEBUG, &pdev->dev,
1611 "version " DRV_VERSION "\n");
1612
1613 /* no hotplugging support (FIXME) */
1614 if (!in_module_init)
1615 return -ENODEV;
1616
1617 port_info[0] = piix_port_info[ent->driver_data];
1618 port_info[1] = piix_port_info[ent->driver_data];
1619
1620 port_flags = port_info[0].flags;
1621
1622 /* enable device and prepare host */
1623 rc = pcim_enable_device(pdev);
1624 if (rc)
1625 return rc;
1626
1627 /* SATA map init can change port_info, do it before prepping host */
1628 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1629 if (!hpriv)
1630 return -ENOMEM;
1631
1632 if (port_flags & ATA_FLAG_SATA)
1633 hpriv->map = piix_init_sata_map(pdev, port_info,
1634 piix_map_db_table[ent->driver_data]);
1635
1636 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
1637 if (rc)
1638 return rc;
1639 host->private_data = hpriv;
1640
1641 /* initialize controller */
1642 if (port_flags & PIIX_FLAG_AHCI) {
1643 u8 tmp;
1644 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1645 if (tmp == PIIX_AHCI_DEVICE) {
1646 int rc = piix_disable_ahci(pdev);
1647 if (rc)
1648 return rc;
1649 }
1650 }
1651
1652 if (port_flags & ATA_FLAG_SATA) {
1653 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1654 piix_init_sidpr(host);
1655 }
1656
1657 /* apply IOCFG bit18 quirk */
1658 piix_iocfg_bit18_quirk(pdev);
1659
1660 /* On ICH5, some BIOSen disable the interrupt using the
1661 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1662 * On ICH6, this bit has the same effect, but only when
1663 * MSI is disabled (and it is disabled, as we don't use
1664 * message-signalled interrupts currently).
1665 */
1666 if (port_flags & PIIX_FLAG_CHECKINTR)
1667 pci_intx(pdev, 1);
1668
1669 if (piix_check_450nx_errata(pdev)) {
1670 /* This writes into the master table but it does not
1671 really matter for this errata as we will apply it to
1672 all the PIIX devices on the board */
1673 host->ports[0]->mwdma_mask = 0;
1674 host->ports[0]->udma_mask = 0;
1675 host->ports[1]->mwdma_mask = 0;
1676 host->ports[1]->udma_mask = 0;
1677 }
1678
1679 pci_set_master(pdev);
1680 return ata_pci_activate_sff_host(host, ata_interrupt, &piix_sht);
1681 }
1682
1683 static int __init piix_init(void)
1684 {
1685 int rc;
1686
1687 DPRINTK("pci_register_driver\n");
1688 rc = pci_register_driver(&piix_pci_driver);
1689 if (rc)
1690 return rc;
1691
1692 in_module_init = 0;
1693
1694 DPRINTK("done\n");
1695 return 0;
1696 }
1697
1698 static void __exit piix_exit(void)
1699 {
1700 pci_unregister_driver(&piix_pci_driver);
1701 }
1702
1703 module_init(piix_init);
1704 module_exit(piix_exit);
WRT350N Kernel Patches