include/asm-mips/mach-generic/ide.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994-1996  Linus Torvalds & authors
   7  *
   8  * Copied from i386; many of the especially older MIPS or ISA-based platforms
   9  * are basically identical.  Using this file probably implies i8259 PIC
  10  * support in a system but the very least interrupt numbers 0 - 15 need to
  11  * be put aside for legacy devices.
  12  */
  13 #ifndef __ASM_MACH_GENERIC_IDE_H
  14 #define __ASM_MACH_GENERIC_IDE_H
  15
  16 #ifdef __KERNEL__
  17
  18 #include <linux/pci.h>
  19 #include <linux/stddef.h>
  20 #include <asm/processor.h>
  21
  22 #ifndef MAX_HWIFS
  23 # ifdef CONFIG_BLK_DEV_IDEPCI
  24 #define MAX_HWIFS       10
  25 # else
  26 #define MAX_HWIFS       6
  27 # endif
  28 #endif
  29
  30 #define IDE_ARCH_OBSOLETE_DEFAULTS
  31
  32 static __inline__ int ide_probe_legacy(void)
  33 {
  34 #ifdef CONFIG_PCI
  35         struct pci_dev *dev;
  36         /*
  37          * This can be called on the ide_setup() path, super-early in
  38          * boot.  But the down_read() will enable local interrupts,
  39          * which can cause some machines to crash.  So here we detect
  40          * and flag that situation and bail out early.
  41          */
  42         if (no_pci_devices())
  43                 return 0;
  44         dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
  45         if (dev)
  46                 goto found;
  47         dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  48         if (dev)
  49                 goto found;
  50         return 0;
  51 found:
  52         pci_dev_put(dev);
  53         return 1;
  54 #elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
  55         return 1;
  56 #else
  57         return 0;
  58 #endif
  59 }
  60
  61 static __inline__ int ide_default_irq(unsigned long base)
  62 {
  63         switch (base) {
  64                 case 0x1f0: return 14;
  65                 case 0x170: return 15;
  66                 case 0x1e8: return 11;
  67                 case 0x168: return 10;
  68                 case 0x1e0: return 8;
  69                 case 0x160: return 12;
  70                 default:
  71                         return 0;
  72         }
  73 }
  74
  75 static __inline__ unsigned long ide_default_io_base(int index)
  76 {
  77         if (!ide_probe_legacy())
  78                 return 0;
  79         /*
  80          *      If PCI is present then it is not safe to poke around
  81          *      the other legacy IDE ports. Only 0x1f0 and 0x170 are
  82          *      defined compatibility mode ports for PCI. A user can
  83          *      override this using ide= but we must default safe.
  84          */
  85         if (no_pci_devices()) {
  86                 switch (index) {
  87                 case 2: return 0x1e8;
  88                 case 3: return 0x168;
  89                 case 4: return 0x1e0;
  90                 case 5: return 0x160;
  91                 }
  92         }
  93         switch (index) {
  94         case 0: return 0x1f0;
  95         case 1: return 0x170;
  96         default:
  97                 return 0;
  98         }
  99 }
 100
 101 #define IDE_ARCH_OBSOLETE_INIT
 102 #define ide_default_io_ctl(base)        ((base) + 0x206) /* obsolete */
 103
 104 #ifdef CONFIG_BLK_DEV_IDEPCI
 105 #define ide_init_default_irq(base)      (0)
 106 #else
 107 #define ide_init_default_irq(base)      ide_default_irq(base)
 108 #endif
 109
 110 /* MIPS port and memory-mapped I/O string operations.  */
 111 static inline void __ide_flush_prologue(void)
 112 {
 113 #ifdef CONFIG_SMP
 114         if (cpu_has_dc_aliases)
 115                 preempt_disable();
 116 #endif
 117 }
 118
 119 static inline void __ide_flush_epilogue(void)
 120 {
 121 #ifdef CONFIG_SMP
 122         if (cpu_has_dc_aliases)
 123                 preempt_enable();
 124 #endif
 125 }
 126
 127 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
 128 {
 129         if (cpu_has_dc_aliases) {
 130                 unsigned long end = addr + size;
 131
 132                 while (addr < end) {
 133                         local_flush_data_cache_page((void *)addr);
 134                         addr += PAGE_SIZE;
 135                 }
 136         }
 137 }
 138
 139 /*
 140  * insw() and gang might be called with interrupts disabled, so we can't
 141  * send IPIs for flushing due to the potencial of deadlocks, see the comment
 142  * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
 143  * problem by disabling preemption so we know we actually perform the flush
 144  * on the processor that actually has the lines to be flushed which hopefully
 145  * is even better for performance anyway.
 146  */
 147 static inline void __ide_insw(unsigned long port, void *addr,
 148         unsigned int count)
 149 {
 150         __ide_flush_prologue();
 151         insw(port, addr, count);
 152         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 153         __ide_flush_epilogue();
 154 }
 155
 156 static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
 157 {
 158         __ide_flush_prologue();
 159         insl(port, addr, count);
 160         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 161         __ide_flush_epilogue();
 162 }
 163
 164 static inline void __ide_outsw(unsigned long port, const void *addr,
 165         unsigned long count)
 166 {
 167         __ide_flush_prologue();
 168         outsw(port, addr, count);
 169         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 170         __ide_flush_epilogue();
 171 }
 172
 173 static inline void __ide_outsl(unsigned long port, const void *addr,
 174         unsigned long count)
 175 {
 176         __ide_flush_prologue();
 177         outsl(port, addr, count);
 178         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 179         __ide_flush_epilogue();
 180 }
 181
 182 static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
 183 {
 184         __ide_flush_prologue();
 185         readsw(port, addr, count);
 186         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 187         __ide_flush_epilogue();
 188 }
 189
 190 static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
 191 {
 192         __ide_flush_prologue();
 193         readsl(port, addr, count);
 194         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 195         __ide_flush_epilogue();
 196 }
 197
 198 static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
 199 {
 200         __ide_flush_prologue();
 201         writesw(port, addr, count);
 202         __ide_flush_dcache_range((unsigned long)addr, count * 2);
 203         __ide_flush_epilogue();
 204 }
 205
 206 static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
 207 {
 208         __ide_flush_prologue();
 209         writesl(port, addr, count);
 210         __ide_flush_dcache_range((unsigned long)addr, count * 4);
 211         __ide_flush_epilogue();
 212 }
 213
 214 /* ide_insw calls insw, not __ide_insw.  Why? */
 215 #undef insw
 216 #undef insl
 217 #undef outsw
 218 #undef outsl
 219 #define insw(port, addr, count) __ide_insw(port, addr, count)
 220 #define insl(port, addr, count) __ide_insl(port, addr, count)
 221 #define outsw(port, addr, count) __ide_outsw(port, addr, count)
 222 #define outsl(port, addr, count) __ide_outsl(port, addr, count)
 223
 224 #endif /* __KERNEL__ */
 225
 226 #endif /* __ASM_MACH_GENERIC_IDE_H */