arch/x86/kernel/i8259_64.c

   1 #include <linux/linkage.h>
   2 #include <linux/errno.h>
   3 #include <linux/signal.h>
   4 #include <linux/sched.h>
   5 #include <linux/ioport.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/timex.h>
   8 #include <linux/slab.h>
   9 #include <linux/random.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel_stat.h>
  12 #include <linux/sysdev.h>
  13 #include <linux/bitops.h>
  14
  15 #include <asm/acpi.h>
  16 #include <asm/atomic.h>
  17 #include <asm/system.h>
  18 #include <asm/io.h>
  19 #include <asm/hw_irq.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/delay.h>
  22 #include <asm/desc.h>
  23 #include <asm/apic.h>
  24 #include <asm/i8259.h>
  25
  26 /*
  27  * Common place to define all x86 IRQ vectors
  28  *
  29  * This builds up the IRQ handler stubs using some ugly macros in irq.h
  30  *
  31  * These macros create the low-level assembly IRQ routines that save
  32  * register context and call do_IRQ(). do_IRQ() then does all the
  33  * operations that are needed to keep the AT (or SMP IOAPIC)
  34  * interrupt-controller happy.
  35  */
  36
  37 #define BI(x,y) \
  38         BUILD_IRQ(x##y)
  39
  40 #define BUILD_16_IRQS(x) \
  41         BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
  42         BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
  43         BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
  44         BI(x,c) BI(x,d) BI(x,e) BI(x,f)
  45
  46 /*
  47  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  48  * (these are usually mapped to vectors 0x30-0x3f)
  49  */
  50
  51 /*
  52  * The IO-APIC gives us many more interrupt sources. Most of these
  53  * are unused but an SMP system is supposed to have enough memory ...
  54  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  55  * across the spectrum, so we really want to be prepared to get all
  56  * of these. Plus, more powerful systems might have more than 64
  57  * IO-APIC registers.
  58  *
  59  * (these are usually mapped into the 0x30-0xff vector range)
  60  */
  61                                       BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
  62 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
  63 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
  64 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
  65
  66 #undef BUILD_16_IRQS
  67 #undef BI
  68
  69
  70 #define IRQ(x,y) \
  71         IRQ##x##y##_interrupt
  72
  73 #define IRQLIST_16(x) \
  74         IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
  75         IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
  76         IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
  77         IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
  78
  79 /* for the irq vectors */
  80 static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
  81                                           IRQLIST_16(0x2), IRQLIST_16(0x3),
  82         IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
  83         IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
  84         IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
  85 };
  86
  87 #undef IRQ
  88 #undef IRQLIST_16
  89
  90 /*
  91  * This is the 'legacy' 8259A Programmable Interrupt Controller,
  92  * present in the majority of PC/AT boxes.
  93  * plus some generic x86 specific things if generic specifics makes
  94  * any sense at all.
  95  * this file should become arch/i386/kernel/irq.c when the old irq.c
  96  * moves to arch independent land
  97  */
  98
  99 static int i8259A_auto_eoi;
 100 DEFINE_SPINLOCK(i8259A_lock);
 101 static void mask_and_ack_8259A(unsigned int);
 102
 103 static struct irq_chip i8259A_chip = {
 104         .name           = "XT-PIC",
 105         .mask           = disable_8259A_irq,
 106         .disable        = disable_8259A_irq,
 107         .unmask         = enable_8259A_irq,
 108         .mask_ack       = mask_and_ack_8259A,
 109 };
 110
 111 /*
 112  * 8259A PIC functions to handle ISA devices:
 113  */
 114
 115 /*
 116  * This contains the irq mask for both 8259A irq controllers,
 117  */
 118 unsigned int cached_irq_mask = 0xffff;
 119
 120 /*
 121  * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 122  * boards the timer interrupt is not really connected to any IO-APIC pin,
 123  * it's fed to the master 8259A's IR0 line only.
 124  *
 125  * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 126  * this 'mixed mode' IRQ handling costs nothing because it's only used
 127  * at IRQ setup time.
 128  */
 129 unsigned long io_apic_irqs;
 130
 131 void disable_8259A_irq(unsigned int irq)
 132 {
 133         unsigned int mask = 1 << irq;
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&i8259A_lock, flags);
 137         cached_irq_mask |= mask;
 138         if (irq & 8)
 139                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 140         else
 141                 outb(cached_master_mask, PIC_MASTER_IMR);
 142         spin_unlock_irqrestore(&i8259A_lock, flags);
 143 }
 144
 145 void enable_8259A_irq(unsigned int irq)
 146 {
 147         unsigned int mask = ~(1 << irq);
 148         unsigned long flags;
 149
 150         spin_lock_irqsave(&i8259A_lock, flags);
 151         cached_irq_mask &= mask;
 152         if (irq & 8)
 153                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 154         else
 155                 outb(cached_master_mask, PIC_MASTER_IMR);
 156         spin_unlock_irqrestore(&i8259A_lock, flags);
 157 }
 158
 159 int i8259A_irq_pending(unsigned int irq)
 160 {
 161         unsigned int mask = 1<<irq;
 162         unsigned long flags;
 163         int ret;
 164
 165         spin_lock_irqsave(&i8259A_lock, flags);
 166         if (irq < 8)
 167                 ret = inb(PIC_MASTER_CMD) & mask;
 168         else
 169                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
 170         spin_unlock_irqrestore(&i8259A_lock, flags);
 171
 172         return ret;
 173 }
 174
 175 void make_8259A_irq(unsigned int irq)
 176 {
 177         disable_irq_nosync(irq);
 178         io_apic_irqs &= ~(1<<irq);
 179         set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
 180                                       "XT");
 181         enable_irq(irq);
 182 }
 183
 184 /*
 185  * This function assumes to be called rarely. Switching between
 186  * 8259A registers is slow.
 187  * This has to be protected by the irq controller spinlock
 188  * before being called.
 189  */
 190 static inline int i8259A_irq_real(unsigned int irq)
 191 {
 192         int value;
 193         int irqmask = 1<<irq;
 194
 195         if (irq < 8) {
 196                 outb(0x0B,PIC_MASTER_CMD);      /* ISR register */
 197                 value = inb(PIC_MASTER_CMD) & irqmask;
 198                 outb(0x0A,PIC_MASTER_CMD);      /* back to the IRR register */
 199                 return value;
 200         }
 201         outb(0x0B,PIC_SLAVE_CMD);       /* ISR register */
 202         value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
 203         outb(0x0A,PIC_SLAVE_CMD);       /* back to the IRR register */
 204         return value;
 205 }
 206
 207 /*
 208  * Careful! The 8259A is a fragile beast, it pretty
 209  * much _has_ to be done exactly like this (mask it
 210  * first, _then_ send the EOI, and the order of EOI
 211  * to the two 8259s is important!
 212  */
 213 static void mask_and_ack_8259A(unsigned int irq)
 214 {
 215         unsigned int irqmask = 1 << irq;
 216         unsigned long flags;
 217
 218         spin_lock_irqsave(&i8259A_lock, flags);
 219         /*
 220          * Lightweight spurious IRQ detection. We do not want
 221          * to overdo spurious IRQ handling - it's usually a sign
 222          * of hardware problems, so we only do the checks we can
 223          * do without slowing down good hardware unnecessarily.
 224          *
 225          * Note that IRQ7 and IRQ15 (the two spurious IRQs
 226          * usually resulting from the 8259A-1|2 PICs) occur
 227          * even if the IRQ is masked in the 8259A. Thus we
 228          * can check spurious 8259A IRQs without doing the
 229          * quite slow i8259A_irq_real() call for every IRQ.
 230          * This does not cover 100% of spurious interrupts,
 231          * but should be enough to warn the user that there
 232          * is something bad going on ...
 233          */
 234         if (cached_irq_mask & irqmask)
 235                 goto spurious_8259A_irq;
 236         cached_irq_mask |= irqmask;
 237
 238 handle_real_irq:
 239         if (irq & 8) {
 240                 inb(PIC_SLAVE_IMR);     /* DUMMY - (do we need this?) */
 241                 outb(cached_slave_mask, PIC_SLAVE_IMR);
 242                 /* 'Specific EOI' to slave */
 243                 outb(0x60+(irq&7),PIC_SLAVE_CMD);
 244                  /* 'Specific EOI' to master-IRQ2 */
 245                 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
 246         } else {
 247                 inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
 248                 outb(cached_master_mask, PIC_MASTER_IMR);
 249                 /* 'Specific EOI' to master */
 250                 outb(0x60+irq,PIC_MASTER_CMD);
 251         }
 252         spin_unlock_irqrestore(&i8259A_lock, flags);
 253         return;
 254
 255 spurious_8259A_irq:
 256         /*
 257          * this is the slow path - should happen rarely.
 258          */
 259         if (i8259A_irq_real(irq))
 260                 /*
 261                  * oops, the IRQ _is_ in service according to the
 262                  * 8259A - not spurious, go handle it.
 263                  */
 264                 goto handle_real_irq;
 265
 266         {
 267                 static int spurious_irq_mask;
 268                 /*
 269                  * At this point we can be sure the IRQ is spurious,
 270                  * lets ACK and report it. [once per IRQ]
 271                  */
 272                 if (!(spurious_irq_mask & irqmask)) {
 273                         printk(KERN_DEBUG
 274                                "spurious 8259A interrupt: IRQ%d.\n", irq);
 275                         spurious_irq_mask |= irqmask;
 276                 }
 277                 atomic_inc(&irq_err_count);
 278                 /*
 279                  * Theoretically we do not have to handle this IRQ,
 280                  * but in Linux this does not cause problems and is
 281                  * simpler for us.
 282                  */
 283                 goto handle_real_irq;
 284         }
 285 }
 286
 287 static char irq_trigger[2];
 288 /**
 289  * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 290  */
 291 static void restore_ELCR(char *trigger)
 292 {
 293         outb(trigger[0], 0x4d0);
 294         outb(trigger[1], 0x4d1);
 295 }
 296
 297 static void save_ELCR(char *trigger)
 298 {
 299         /* IRQ 0,1,2,8,13 are marked as reserved */
 300         trigger[0] = inb(0x4d0) & 0xF8;
 301         trigger[1] = inb(0x4d1) & 0xDE;
 302 }
 303
 304 static int i8259A_resume(struct sys_device *dev)
 305 {
 306         init_8259A(i8259A_auto_eoi);
 307         restore_ELCR(irq_trigger);
 308         return 0;
 309 }
 310
 311 static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
 312 {
 313         save_ELCR(irq_trigger);
 314         return 0;
 315 }
 316
 317 static int i8259A_shutdown(struct sys_device *dev)
 318 {
 319         /* Put the i8259A into a quiescent state that
 320          * the kernel initialization code can get it
 321          * out of.
 322          */
 323         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 324         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-1 */
 325         return 0;
 326 }
 327
 328 static struct sysdev_class i8259_sysdev_class = {
 329         .name = "i8259",
 330         .suspend = i8259A_suspend,
 331         .resume = i8259A_resume,
 332         .shutdown = i8259A_shutdown,
 333 };
 334
 335 static struct sys_device device_i8259A = {
 336         .id     = 0,
 337         .cls    = &i8259_sysdev_class,
 338 };
 339
 340 static int __init i8259A_init_sysfs(void)
 341 {
 342         int error = sysdev_class_register(&i8259_sysdev_class);
 343         if (!error)
 344                 error = sysdev_register(&device_i8259A);
 345         return error;
 346 }
 347
 348 device_initcall(i8259A_init_sysfs);
 349
 350 void init_8259A(int auto_eoi)
 351 {
 352         unsigned long flags;
 353
 354         i8259A_auto_eoi = auto_eoi;
 355
 356         spin_lock_irqsave(&i8259A_lock, flags);
 357
 358         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
 359         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
 360
 361         /*
 362          * outb_pic - this has to work on a wide range of PC hardware.
 363          */
 364         outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
 365         /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
 366         outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
 367         /* 8259A-1 (the master) has a slave on IR2 */
 368         outb_pic(0x04, PIC_MASTER_IMR);
 369         if (auto_eoi)   /* master does Auto EOI */
 370                 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
 371         else            /* master expects normal EOI */
 372                 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
 373
 374         outb_pic(0x11, PIC_SLAVE_CMD);  /* ICW1: select 8259A-2 init */
 375         /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
 376         outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
 377         /* 8259A-2 is a slave on master's IR2 */
 378         outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
 379         /* (slave's support for AEOI in flat mode is to be investigated) */
 380         outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
 381
 382         if (auto_eoi)
 383                 /*
 384                  * In AEOI mode we just have to mask the interrupt
 385                  * when acking.
 386                  */
 387                 i8259A_chip.mask_ack = disable_8259A_irq;
 388         else
 389                 i8259A_chip.mask_ack = mask_and_ack_8259A;
 390
 391         udelay(100);            /* wait for 8259A to initialize */
 392
 393         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
 394         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 395
 396         spin_unlock_irqrestore(&i8259A_lock, flags);
 397 }
 398
 399
 400
 401
 402 /*
 403  * IRQ2 is cascade interrupt to second interrupt controller
 404  */
 405
 406 static struct irqaction irq2 = {
 407         .handler = no_action,
 408         .mask = CPU_MASK_NONE,
 409         .name = "cascade",
 410 };
 411 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
 412         [0 ... IRQ0_VECTOR - 1] = -1,
 413         [IRQ0_VECTOR] = 0,
 414         [IRQ1_VECTOR] = 1,
 415         [IRQ2_VECTOR] = 2,
 416         [IRQ3_VECTOR] = 3,
 417         [IRQ4_VECTOR] = 4,
 418         [IRQ5_VECTOR] = 5,
 419         [IRQ6_VECTOR] = 6,
 420         [IRQ7_VECTOR] = 7,
 421         [IRQ8_VECTOR] = 8,
 422         [IRQ9_VECTOR] = 9,
 423         [IRQ10_VECTOR] = 10,
 424         [IRQ11_VECTOR] = 11,
 425         [IRQ12_VECTOR] = 12,
 426         [IRQ13_VECTOR] = 13,
 427         [IRQ14_VECTOR] = 14,
 428         [IRQ15_VECTOR] = 15,
 429         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 430 };
 431
 432 void __init init_ISA_irqs (void)
 433 {
 434         int i;
 435
 436         init_bsp_APIC();
 437         init_8259A(0);
 438
 439         for (i = 0; i < NR_IRQS; i++) {
 440                 irq_desc[i].status = IRQ_DISABLED;
 441                 irq_desc[i].action = NULL;
 442                 irq_desc[i].depth = 1;
 443
 444                 if (i < 16) {
 445                         /*
 446                          * 16 old-style INTA-cycle interrupts:
 447                          */
 448                         set_irq_chip_and_handler_name(i, &i8259A_chip,
 449                                                       handle_level_irq, "XT");
 450                 } else {
 451                         /*
 452                          * 'high' PCI IRQs filled in on demand
 453                          */
 454                         irq_desc[i].chip = &no_irq_chip;
 455                 }
 456         }
 457 }
 458
 459 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 460
 461 void __init native_init_IRQ(void)
 462 {
 463         int i;
 464
 465         init_ISA_irqs();
 466         /*
 467          * Cover the whole vector space, no vector can escape
 468          * us. (some of these will be overridden and become
 469          * 'special' SMP interrupts)
 470          */
 471         for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
 472                 int vector = FIRST_EXTERNAL_VECTOR + i;
 473                 if (vector != IA32_SYSCALL_VECTOR)
 474                         set_intr_gate(vector, interrupt[i]);
 475         }
 476
 477 #ifdef CONFIG_SMP
 478         /*
 479          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 480          * IPI, driven by wakeup.
 481          */
 482         set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 483
 484         /* IPIs for invalidation */
 485         set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 486         set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 487         set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 488         set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 489         set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 490         set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 491         set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 492         set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 493
 494         /* IPI for generic function call */
 495         set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 496
 497         /* Low priority IPI to cleanup after moving an irq */
 498         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 499 #endif
 500         set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 501         set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
 502
 503         /* self generated IPI for local APIC timer */
 504         set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 505
 506         /* IPI vectors for APIC spurious and error interrupts */
 507         set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 508         set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 509
 510         if (!acpi_ioapic)
 511                 setup_irq(2, &irq2);
 512 }