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sched: make early bootup sched_clock() use safer
[wrt350n-kernel.git] / drivers / net / igb / igb_main.c
blobbff280eff5e335ec563c732c7b708b567fc60699
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/tcp.h>
35 #include <linux/ipv6.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/if_ether.h>
45
46 #include "igb.h"
47
48 #define DRV_VERSION "1.0.8-k2"
49 char igb_driver_name[] = "igb";
50 char igb_driver_version[] = DRV_VERSION;
51 static const char igb_driver_string[] =
52 "Intel(R) Gigabit Ethernet Network Driver";
53 static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
54
55
56 static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58 };
59
60 static struct pci_device_id igb_pci_tbl[] = {
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
64 /* required last entry */
65 {0, }
66 };
67
68 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
69
70 void igb_reset(struct igb_adapter *);
71 static int igb_setup_all_tx_resources(struct igb_adapter *);
72 static int igb_setup_all_rx_resources(struct igb_adapter *);
73 static void igb_free_all_tx_resources(struct igb_adapter *);
74 static void igb_free_all_rx_resources(struct igb_adapter *);
75 static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *);
76 static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *);
77 void igb_update_stats(struct igb_adapter *);
78 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
79 static void __devexit igb_remove(struct pci_dev *pdev);
80 static int igb_sw_init(struct igb_adapter *);
81 static int igb_open(struct net_device *);
82 static int igb_close(struct net_device *);
83 static void igb_configure_tx(struct igb_adapter *);
84 static void igb_configure_rx(struct igb_adapter *);
85 static void igb_setup_rctl(struct igb_adapter *);
86 static void igb_clean_all_tx_rings(struct igb_adapter *);
87 static void igb_clean_all_rx_rings(struct igb_adapter *);
88 static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *);
89 static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *);
90 static void igb_set_multi(struct net_device *);
91 static void igb_update_phy_info(unsigned long);
92 static void igb_watchdog(unsigned long);
93 static void igb_watchdog_task(struct work_struct *);
94 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
95 struct igb_ring *);
96 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
97 static struct net_device_stats *igb_get_stats(struct net_device *);
98 static int igb_change_mtu(struct net_device *, int);
99 static int igb_set_mac(struct net_device *, void *);
100 static irqreturn_t igb_intr(int irq, void *);
101 static irqreturn_t igb_intr_msi(int irq, void *);
102 static irqreturn_t igb_msix_other(int irq, void *);
103 static irqreturn_t igb_msix_rx(int irq, void *);
104 static irqreturn_t igb_msix_tx(int irq, void *);
105 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
106 static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *);
107 static int igb_clean(struct napi_struct *, int);
108 static bool igb_clean_rx_irq_adv(struct igb_adapter *,
109 struct igb_ring *, int *, int);
110 static void igb_alloc_rx_buffers_adv(struct igb_adapter *,
111 struct igb_ring *, int);
112 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
113 static void igb_tx_timeout(struct net_device *);
114 static void igb_reset_task(struct work_struct *);
115 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
116 static void igb_vlan_rx_add_vid(struct net_device *, u16);
117 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
118 static void igb_restore_vlan(struct igb_adapter *);
119
120 static int igb_suspend(struct pci_dev *, pm_message_t);
121 #ifdef CONFIG_PM
122 static int igb_resume(struct pci_dev *);
123 #endif
124 static void igb_shutdown(struct pci_dev *);
125
126 #ifdef CONFIG_NET_POLL_CONTROLLER
127 /* for netdump / net console */
128 static void igb_netpoll(struct net_device *);
129 #endif
130
131 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
132 pci_channel_state_t);
133 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
134 static void igb_io_resume(struct pci_dev *);
135
136 static struct pci_error_handlers igb_err_handler = {
137 .error_detected = igb_io_error_detected,
138 .slot_reset = igb_io_slot_reset,
139 .resume = igb_io_resume,
140 };
141
142
143 static struct pci_driver igb_driver = {
144 .name = igb_driver_name,
145 .id_table = igb_pci_tbl,
146 .probe = igb_probe,
147 .remove = __devexit_p(igb_remove),
148 #ifdef CONFIG_PM
149 /* Power Managment Hooks */
150 .suspend = igb_suspend,
151 .resume = igb_resume,
152 #endif
153 .shutdown = igb_shutdown,
154 .err_handler = &igb_err_handler
155 };
156
157 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
158 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_VERSION);
161
162 #ifdef DEBUG
163 /**
164 * igb_get_hw_dev_name - return device name string
165 * used by hardware layer to print debugging information
166 **/
167 char *igb_get_hw_dev_name(struct e1000_hw *hw)
168 {
169 struct igb_adapter *adapter = hw->back;
170 return adapter->netdev->name;
171 }
172 #endif
173
174 /**
175 * igb_init_module - Driver Registration Routine
176 *
177 * igb_init_module is the first routine called when the driver is
178 * loaded. All it does is register with the PCI subsystem.
179 **/
180 static int __init igb_init_module(void)
181 {
182 int ret;
183 printk(KERN_INFO "%s - version %s\n",
184 igb_driver_string, igb_driver_version);
185
186 printk(KERN_INFO "%s\n", igb_copyright);
187
188 ret = pci_register_driver(&igb_driver);
189 return ret;
190 }
191
192 module_init(igb_init_module);
193
194 /**
195 * igb_exit_module - Driver Exit Cleanup Routine
196 *
197 * igb_exit_module is called just before the driver is removed
198 * from memory.
199 **/
200 static void __exit igb_exit_module(void)
201 {
202 pci_unregister_driver(&igb_driver);
203 }
204
205 module_exit(igb_exit_module);
206
207 /**
208 * igb_alloc_queues - Allocate memory for all rings
209 * @adapter: board private structure to initialize
210 *
211 * We allocate one ring per queue at run-time since we don't know the
212 * number of queues at compile-time.
213 **/
214 static int igb_alloc_queues(struct igb_adapter *adapter)
215 {
216 int i;
217
218 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
219 sizeof(struct igb_ring), GFP_KERNEL);
220 if (!adapter->tx_ring)
221 return -ENOMEM;
222
223 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
224 sizeof(struct igb_ring), GFP_KERNEL);
225 if (!adapter->rx_ring) {
226 kfree(adapter->tx_ring);
227 return -ENOMEM;
228 }
229
230 for (i = 0; i < adapter->num_rx_queues; i++) {
231 struct igb_ring *ring = &(adapter->rx_ring[i]);
232 ring->adapter = adapter;
233 ring->itr_register = E1000_ITR;
234
235 if (!ring->napi.poll)
236 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
237 adapter->napi.weight /
238 adapter->num_rx_queues);
239 }
240 return 0;
241 }
242
243 #define IGB_N0_QUEUE -1
244 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
245 int tx_queue, int msix_vector)
246 {
247 u32 msixbm = 0;
248 struct e1000_hw *hw = &adapter->hw;
249 /* The 82575 assigns vectors using a bitmask, which matches the
250 bitmask for the EICR/EIMS/EIMC registers. To assign one
251 or more queues to a vector, we write the appropriate bits
252 into the MSIXBM register for that vector. */
253 if (rx_queue > IGB_N0_QUEUE) {
254 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
255 adapter->rx_ring[rx_queue].eims_value = msixbm;
256 }
257 if (tx_queue > IGB_N0_QUEUE) {
258 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
259 adapter->tx_ring[tx_queue].eims_value =
260 E1000_EICR_TX_QUEUE0 << tx_queue;
261 }
262 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
263 }
264
265 /**
266 * igb_configure_msix - Configure MSI-X hardware
267 *
268 * igb_configure_msix sets up the hardware to properly
269 * generate MSI-X interrupts.
270 **/
271 static void igb_configure_msix(struct igb_adapter *adapter)
272 {
273 u32 tmp;
274 int i, vector = 0;
275 struct e1000_hw *hw = &adapter->hw;
276
277 adapter->eims_enable_mask = 0;
278
279 for (i = 0; i < adapter->num_tx_queues; i++) {
280 struct igb_ring *tx_ring = &adapter->tx_ring[i];
281 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
282 adapter->eims_enable_mask |= tx_ring->eims_value;
283 if (tx_ring->itr_val)
284 writel(1000000000 / (tx_ring->itr_val * 256),
285 hw->hw_addr + tx_ring->itr_register);
286 else
287 writel(1, hw->hw_addr + tx_ring->itr_register);
288 }
289
290 for (i = 0; i < adapter->num_rx_queues; i++) {
291 struct igb_ring *rx_ring = &adapter->rx_ring[i];
292 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
293 adapter->eims_enable_mask |= rx_ring->eims_value;
294 if (rx_ring->itr_val)
295 writel(1000000000 / (rx_ring->itr_val * 256),
296 hw->hw_addr + rx_ring->itr_register);
297 else
298 writel(1, hw->hw_addr + rx_ring->itr_register);
299 }
300
301
302 /* set vector for other causes, i.e. link changes */
303 array_wr32(E1000_MSIXBM(0), vector++,
304 E1000_EIMS_OTHER);
305
306 /* disable IAM for ICR interrupt bits */
307 wr32(E1000_IAM, 0);
308
309 tmp = rd32(E1000_CTRL_EXT);
310 /* enable MSI-X PBA support*/
311 tmp |= E1000_CTRL_EXT_PBA_CLR;
312
313 /* Auto-Mask interrupts upon ICR read. */
314 tmp |= E1000_CTRL_EXT_EIAME;
315 tmp |= E1000_CTRL_EXT_IRCA;
316
317 wr32(E1000_CTRL_EXT, tmp);
318 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
319
320 wrfl();
321 }
322
323 /**
324 * igb_request_msix - Initialize MSI-X interrupts
325 *
326 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
327 * kernel.
328 **/
329 static int igb_request_msix(struct igb_adapter *adapter)
330 {
331 struct net_device *netdev = adapter->netdev;
332 int i, err = 0, vector = 0;
333
334 vector = 0;
335
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 struct igb_ring *ring = &(adapter->tx_ring[i]);
338 sprintf(ring->name, "%s-tx%d", netdev->name, i);
339 err = request_irq(adapter->msix_entries[vector].vector,
340 &igb_msix_tx, 0, ring->name,
341 &(adapter->tx_ring[i]));
342 if (err)
343 goto out;
344 ring->itr_register = E1000_EITR(0) + (vector << 2);
345 ring->itr_val = adapter->itr;
346 vector++;
347 }
348 for (i = 0; i < adapter->num_rx_queues; i++) {
349 struct igb_ring *ring = &(adapter->rx_ring[i]);
350 if (strlen(netdev->name) < (IFNAMSIZ - 5))
351 sprintf(ring->name, "%s-rx%d", netdev->name, i);
352 else
353 memcpy(ring->name, netdev->name, IFNAMSIZ);
354 err = request_irq(adapter->msix_entries[vector].vector,
355 &igb_msix_rx, 0, ring->name,
356 &(adapter->rx_ring[i]));
357 if (err)
358 goto out;
359 ring->itr_register = E1000_EITR(0) + (vector << 2);
360 ring->itr_val = adapter->itr;
361 vector++;
362 }
363
364 err = request_irq(adapter->msix_entries[vector].vector,
365 &igb_msix_other, 0, netdev->name, netdev);
366 if (err)
367 goto out;
368
369 adapter->napi.poll = igb_clean_rx_ring_msix;
370 for (i = 0; i < adapter->num_rx_queues; i++)
371 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
372 igb_configure_msix(adapter);
373 return 0;
374 out:
375 return err;
376 }
377
378 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
379 {
380 if (adapter->msix_entries) {
381 pci_disable_msix(adapter->pdev);
382 kfree(adapter->msix_entries);
383 adapter->msix_entries = NULL;
384 } else if (adapter->msi_enabled)
385 pci_disable_msi(adapter->pdev);
386 return;
387 }
388
389
390 /**
391 * igb_set_interrupt_capability - set MSI or MSI-X if supported
392 *
393 * Attempt to configure interrupts using the best available
394 * capabilities of the hardware and kernel.
395 **/
396 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
397 {
398 int err;
399 int numvecs, i;
400
401 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
402 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
403 GFP_KERNEL);
404 if (!adapter->msix_entries)
405 goto msi_only;
406
407 for (i = 0; i < numvecs; i++)
408 adapter->msix_entries[i].entry = i;
409
410 err = pci_enable_msix(adapter->pdev,
411 adapter->msix_entries,
412 numvecs);
413 if (err == 0)
414 return;
415
416 igb_reset_interrupt_capability(adapter);
417
418 /* If we can't do MSI-X, try MSI */
419 msi_only:
420 adapter->num_rx_queues = 1;
421 if (!pci_enable_msi(adapter->pdev))
422 adapter->msi_enabled = 1;
423 return;
424 }
425
426 /**
427 * igb_request_irq - initialize interrupts
428 *
429 * Attempts to configure interrupts using the best available
430 * capabilities of the hardware and kernel.
431 **/
432 static int igb_request_irq(struct igb_adapter *adapter)
433 {
434 struct net_device *netdev = adapter->netdev;
435 struct e1000_hw *hw = &adapter->hw;
436 int err = 0;
437
438 if (adapter->msix_entries) {
439 err = igb_request_msix(adapter);
440 if (!err) {
441 /* enable IAM, auto-mask,
442 * DO NOT USE EIAME or IAME in legacy mode */
443 wr32(E1000_IAM, IMS_ENABLE_MASK);
444 goto request_done;
445 }
446 /* fall back to MSI */
447 igb_reset_interrupt_capability(adapter);
448 if (!pci_enable_msi(adapter->pdev))
449 adapter->msi_enabled = 1;
450 igb_free_all_tx_resources(adapter);
451 igb_free_all_rx_resources(adapter);
452 adapter->num_rx_queues = 1;
453 igb_alloc_queues(adapter);
454 }
455 if (adapter->msi_enabled) {
456 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
457 netdev->name, netdev);
458 if (!err)
459 goto request_done;
460 /* fall back to legacy interrupts */
461 igb_reset_interrupt_capability(adapter);
462 adapter->msi_enabled = 0;
463 }
464
465 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
466 netdev->name, netdev);
467
468 if (err) {
469 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
470 err);
471 goto request_done;
472 }
473
474 /* enable IAM, auto-mask */
475 wr32(E1000_IAM, IMS_ENABLE_MASK);
476
477 request_done:
478 return err;
479 }
480
481 static void igb_free_irq(struct igb_adapter *adapter)
482 {
483 struct net_device *netdev = adapter->netdev;
484
485 if (adapter->msix_entries) {
486 int vector = 0, i;
487
488 for (i = 0; i < adapter->num_tx_queues; i++)
489 free_irq(adapter->msix_entries[vector++].vector,
490 &(adapter->tx_ring[i]));
491 for (i = 0; i < adapter->num_rx_queues; i++)
492 free_irq(adapter->msix_entries[vector++].vector,
493 &(adapter->rx_ring[i]));
494
495 free_irq(adapter->msix_entries[vector++].vector, netdev);
496 return;
497 }
498
499 free_irq(adapter->pdev->irq, netdev);
500 }
501
502 /**
503 * igb_irq_disable - Mask off interrupt generation on the NIC
504 * @adapter: board private structure
505 **/
506 static void igb_irq_disable(struct igb_adapter *adapter)
507 {
508 struct e1000_hw *hw = &adapter->hw;
509
510 if (adapter->msix_entries) {
511 wr32(E1000_EIMC, ~0);
512 wr32(E1000_EIAC, 0);
513 }
514 wr32(E1000_IMC, ~0);
515 wrfl();
516 synchronize_irq(adapter->pdev->irq);
517 }
518
519 /**
520 * igb_irq_enable - Enable default interrupt generation settings
521 * @adapter: board private structure
522 **/
523 static void igb_irq_enable(struct igb_adapter *adapter)
524 {
525 struct e1000_hw *hw = &adapter->hw;
526
527 if (adapter->msix_entries) {
528 wr32(E1000_EIMS,
529 adapter->eims_enable_mask);
530 wr32(E1000_EIAC,
531 adapter->eims_enable_mask);
532 wr32(E1000_IMS, E1000_IMS_LSC);
533 } else
534 wr32(E1000_IMS, IMS_ENABLE_MASK);
535 }
536
537 static void igb_update_mng_vlan(struct igb_adapter *adapter)
538 {
539 struct net_device *netdev = adapter->netdev;
540 u16 vid = adapter->hw.mng_cookie.vlan_id;
541 u16 old_vid = adapter->mng_vlan_id;
542 if (adapter->vlgrp) {
543 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
544 if (adapter->hw.mng_cookie.status &
545 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
546 igb_vlan_rx_add_vid(netdev, vid);
547 adapter->mng_vlan_id = vid;
548 } else
549 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
550
551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
552 (vid != old_vid) &&
553 !vlan_group_get_device(adapter->vlgrp, old_vid))
554 igb_vlan_rx_kill_vid(netdev, old_vid);
555 } else
556 adapter->mng_vlan_id = vid;
557 }
558 }
559
560 /**
561 * igb_release_hw_control - release control of the h/w to f/w
562 * @adapter: address of board private structure
563 *
564 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
565 * For ASF and Pass Through versions of f/w this means that the
566 * driver is no longer loaded.
567 *
568 **/
569 static void igb_release_hw_control(struct igb_adapter *adapter)
570 {
571 struct e1000_hw *hw = &adapter->hw;
572 u32 ctrl_ext;
573
574 /* Let firmware take over control of h/w */
575 ctrl_ext = rd32(E1000_CTRL_EXT);
576 wr32(E1000_CTRL_EXT,
577 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
578 }
579
580
581 /**
582 * igb_get_hw_control - get control of the h/w from f/w
583 * @adapter: address of board private structure
584 *
585 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
586 * For ASF and Pass Through versions of f/w this means that
587 * the driver is loaded.
588 *
589 **/
590 static void igb_get_hw_control(struct igb_adapter *adapter)
591 {
592 struct e1000_hw *hw = &adapter->hw;
593 u32 ctrl_ext;
594
595 /* Let firmware know the driver has taken over */
596 ctrl_ext = rd32(E1000_CTRL_EXT);
597 wr32(E1000_CTRL_EXT,
598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
599 }
600
601 static void igb_init_manageability(struct igb_adapter *adapter)
602 {
603 struct e1000_hw *hw = &adapter->hw;
604
605 if (adapter->en_mng_pt) {
606 u32 manc2h = rd32(E1000_MANC2H);
607 u32 manc = rd32(E1000_MANC);
608
609 /* enable receiving management packets to the host */
610 /* this will probably generate destination unreachable messages
611 * from the host OS, but the packets will be handled on SMBUS */
612 manc |= E1000_MANC_EN_MNG2HOST;
613 #define E1000_MNG2HOST_PORT_623 (1 << 5)
614 #define E1000_MNG2HOST_PORT_664 (1 << 6)
615 manc2h |= E1000_MNG2HOST_PORT_623;
616 manc2h |= E1000_MNG2HOST_PORT_664;
617 wr32(E1000_MANC2H, manc2h);
618
619 wr32(E1000_MANC, manc);
620 }
621 }
622
623 /**
624 * igb_configure - configure the hardware for RX and TX
625 * @adapter: private board structure
626 **/
627 static void igb_configure(struct igb_adapter *adapter)
628 {
629 struct net_device *netdev = adapter->netdev;
630 int i;
631
632 igb_get_hw_control(adapter);
633 igb_set_multi(netdev);
634
635 igb_restore_vlan(adapter);
636 igb_init_manageability(adapter);
637
638 igb_configure_tx(adapter);
639 igb_setup_rctl(adapter);
640 igb_configure_rx(adapter);
641 /* call IGB_DESC_UNUSED which always leaves
642 * at least 1 descriptor unused to make sure
643 * next_to_use != next_to_clean */
644 for (i = 0; i < adapter->num_rx_queues; i++) {
645 struct igb_ring *ring = &adapter->rx_ring[i];
646 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring));
647 }
648
649
650 adapter->tx_queue_len = netdev->tx_queue_len;
651 }
652
653
654 /**
655 * igb_up - Open the interface and prepare it to handle traffic
656 * @adapter: board private structure
657 **/
658
659 int igb_up(struct igb_adapter *adapter)
660 {
661 struct e1000_hw *hw = &adapter->hw;
662 int i;
663
664 /* hardware has been reset, we need to reload some things */
665 igb_configure(adapter);
666
667 clear_bit(__IGB_DOWN, &adapter->state);
668
669 napi_enable(&adapter->napi);
670
671 if (adapter->msix_entries) {
672 for (i = 0; i < adapter->num_rx_queues; i++)
673 napi_enable(&adapter->rx_ring[i].napi);
674 igb_configure_msix(adapter);
675 }
676
677 /* Clear any pending interrupts. */
678 rd32(E1000_ICR);
679 igb_irq_enable(adapter);
680
681 /* Fire a link change interrupt to start the watchdog. */
682 wr32(E1000_ICS, E1000_ICS_LSC);
683 return 0;
684 }
685
686 void igb_down(struct igb_adapter *adapter)
687 {
688 struct e1000_hw *hw = &adapter->hw;
689 struct net_device *netdev = adapter->netdev;
690 u32 tctl, rctl;
691 int i;
692
693 /* signal that we're down so the interrupt handler does not
694 * reschedule our watchdog timer */
695 set_bit(__IGB_DOWN, &adapter->state);
696
697 /* disable receives in the hardware */
698 rctl = rd32(E1000_RCTL);
699 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
700 /* flush and sleep below */
701
702 netif_stop_queue(netdev);
703
704 /* disable transmits in the hardware */
705 tctl = rd32(E1000_TCTL);
706 tctl &= ~E1000_TCTL_EN;
707 wr32(E1000_TCTL, tctl);
708 /* flush both disables and wait for them to finish */
709 wrfl();
710 msleep(10);
711
712 napi_disable(&adapter->napi);
713
714 if (adapter->msix_entries)
715 for (i = 0; i < adapter->num_rx_queues; i++)
716 napi_disable(&adapter->rx_ring[i].napi);
717 igb_irq_disable(adapter);
718
719 del_timer_sync(&adapter->watchdog_timer);
720 del_timer_sync(&adapter->phy_info_timer);
721
722 netdev->tx_queue_len = adapter->tx_queue_len;
723 netif_carrier_off(netdev);
724 adapter->link_speed = 0;
725 adapter->link_duplex = 0;
726
727 igb_reset(adapter);
728 igb_clean_all_tx_rings(adapter);
729 igb_clean_all_rx_rings(adapter);
730 }
731
732 void igb_reinit_locked(struct igb_adapter *adapter)
733 {
734 WARN_ON(in_interrupt());
735 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
736 msleep(1);
737 igb_down(adapter);
738 igb_up(adapter);
739 clear_bit(__IGB_RESETTING, &adapter->state);
740 }
741
742 void igb_reset(struct igb_adapter *adapter)
743 {
744 struct e1000_hw *hw = &adapter->hw;
745 struct e1000_fc_info *fc = &adapter->hw.fc;
746 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
747 u16 hwm;
748
749 /* Repartition Pba for greater than 9k mtu
750 * To take effect CTRL.RST is required.
751 */
752 pba = E1000_PBA_34K;
753
754 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
755 /* adjust PBA for jumbo frames */
756 wr32(E1000_PBA, pba);
757
758 /* To maintain wire speed transmits, the Tx FIFO should be
759 * large enough to accommodate two full transmit packets,
760 * rounded up to the next 1KB and expressed in KB. Likewise,
761 * the Rx FIFO should be large enough to accommodate at least
762 * one full receive packet and is similarly rounded up and
763 * expressed in KB. */
764 pba = rd32(E1000_PBA);
765 /* upper 16 bits has Tx packet buffer allocation size in KB */
766 tx_space = pba >> 16;
767 /* lower 16 bits has Rx packet buffer allocation size in KB */
768 pba &= 0xffff;
769 /* the tx fifo also stores 16 bytes of information about the tx
770 * but don't include ethernet FCS because hardware appends it */
771 min_tx_space = (adapter->max_frame_size +
772 sizeof(struct e1000_tx_desc) -
773 ETH_FCS_LEN) * 2;
774 min_tx_space = ALIGN(min_tx_space, 1024);
775 min_tx_space >>= 10;
776 /* software strips receive CRC, so leave room for it */
777 min_rx_space = adapter->max_frame_size;
778 min_rx_space = ALIGN(min_rx_space, 1024);
779 min_rx_space >>= 10;
780
781 /* If current Tx allocation is less than the min Tx FIFO size,
782 * and the min Tx FIFO size is less than the current Rx FIFO
783 * allocation, take space away from current Rx allocation */
784 if (tx_space < min_tx_space &&
785 ((min_tx_space - tx_space) < pba)) {
786 pba = pba - (min_tx_space - tx_space);
787
788 /* if short on rx space, rx wins and must trump tx
789 * adjustment */
790 if (pba < min_rx_space)
791 pba = min_rx_space;
792 }
793 }
794 wr32(E1000_PBA, pba);
795
796 /* flow control settings */
797 /* The high water mark must be low enough to fit one full frame
798 * (or the size used for early receive) above it in the Rx FIFO.
799 * Set it to the lower of:
800 * - 90% of the Rx FIFO size, or
801 * - the full Rx FIFO size minus one full frame */
802 hwm = min(((pba << 10) * 9 / 10),
803 ((pba << 10) - adapter->max_frame_size));
804
805 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
806 fc->low_water = fc->high_water - 8;
807 fc->pause_time = 0xFFFF;
808 fc->send_xon = 1;
809 fc->type = fc->original_type;
810
811 /* Allow time for pending master requests to run */
812 adapter->hw.mac.ops.reset_hw(&adapter->hw);
813 wr32(E1000_WUC, 0);
814
815 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
816 dev_err(&adapter->pdev->dev, "Hardware Error\n");
817
818 igb_update_mng_vlan(adapter);
819
820 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
821 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
822
823 igb_reset_adaptive(&adapter->hw);
824 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
825 }
826
827 /**
828 * igb_probe - Device Initialization Routine
829 * @pdev: PCI device information struct
830 * @ent: entry in igb_pci_tbl
831 *
832 * Returns 0 on success, negative on failure
833 *
834 * igb_probe initializes an adapter identified by a pci_dev structure.
835 * The OS initialization, configuring of the adapter private structure,
836 * and a hardware reset occur.
837 **/
838 static int __devinit igb_probe(struct pci_dev *pdev,
839 const struct pci_device_id *ent)
840 {
841 struct net_device *netdev;
842 struct igb_adapter *adapter;
843 struct e1000_hw *hw;
844 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
845 unsigned long mmio_start, mmio_len;
846 static int cards_found;
847 int i, err, pci_using_dac;
848 u16 eeprom_data = 0;
849 u16 eeprom_apme_mask = IGB_EEPROM_APME;
850 u32 part_num;
851
852 err = pci_enable_device(pdev);
853 if (err)
854 return err;
855
856 pci_using_dac = 0;
857 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
858 if (!err) {
859 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
860 if (!err)
861 pci_using_dac = 1;
862 } else {
863 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
864 if (err) {
865 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
866 if (err) {
867 dev_err(&pdev->dev, "No usable DMA "
868 "configuration, aborting\n");
869 goto err_dma;
870 }
871 }
872 }
873
874 err = pci_request_regions(pdev, igb_driver_name);
875 if (err)
876 goto err_pci_reg;
877
878 pci_set_master(pdev);
879
880 err = -ENOMEM;
881 netdev = alloc_etherdev(sizeof(struct igb_adapter));
882 if (!netdev)
883 goto err_alloc_etherdev;
884
885 SET_NETDEV_DEV(netdev, &pdev->dev);
886
887 pci_set_drvdata(pdev, netdev);
888 adapter = netdev_priv(netdev);
889 adapter->netdev = netdev;
890 adapter->pdev = pdev;
891 hw = &adapter->hw;
892 hw->back = adapter;
893 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
894
895 mmio_start = pci_resource_start(pdev, 0);
896 mmio_len = pci_resource_len(pdev, 0);
897
898 err = -EIO;
899 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
900 if (!adapter->hw.hw_addr)
901 goto err_ioremap;
902
903 netdev->open = &igb_open;
904 netdev->stop = &igb_close;
905 netdev->get_stats = &igb_get_stats;
906 netdev->set_multicast_list = &igb_set_multi;
907 netdev->set_mac_address = &igb_set_mac;
908 netdev->change_mtu = &igb_change_mtu;
909 netdev->do_ioctl = &igb_ioctl;
910 igb_set_ethtool_ops(netdev);
911 netdev->tx_timeout = &igb_tx_timeout;
912 netdev->watchdog_timeo = 5 * HZ;
913 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
914 netdev->vlan_rx_register = igb_vlan_rx_register;
915 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
916 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
917 #ifdef CONFIG_NET_POLL_CONTROLLER
918 netdev->poll_controller = igb_netpoll;
919 #endif
920 netdev->hard_start_xmit = &igb_xmit_frame_adv;
921
922 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
923
924 netdev->mem_start = mmio_start;
925 netdev->mem_end = mmio_start + mmio_len;
926
927 adapter->bd_number = cards_found;
928
929 /* PCI config space info */
930 hw->vendor_id = pdev->vendor;
931 hw->device_id = pdev->device;
932 hw->revision_id = pdev->revision;
933 hw->subsystem_vendor_id = pdev->subsystem_vendor;
934 hw->subsystem_device_id = pdev->subsystem_device;
935
936 /* setup the private structure */
937 hw->back = adapter;
938 /* Copy the default MAC, PHY and NVM function pointers */
939 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
940 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
941 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
942 /* Initialize skew-specific constants */
943 err = ei->get_invariants(hw);
944 if (err)
945 goto err_hw_init;
946
947 err = igb_sw_init(adapter);
948 if (err)
949 goto err_sw_init;
950
951 igb_get_bus_info_pcie(hw);
952
953 hw->phy.autoneg_wait_to_complete = false;
954 hw->mac.adaptive_ifs = true;
955
956 /* Copper options */
957 if (hw->phy.media_type == e1000_media_type_copper) {
958 hw->phy.mdix = AUTO_ALL_MODES;
959 hw->phy.disable_polarity_correction = false;
960 hw->phy.ms_type = e1000_ms_hw_default;
961 }
962
963 if (igb_check_reset_block(hw))
964 dev_info(&pdev->dev,
965 "PHY reset is blocked due to SOL/IDER session.\n");
966
967 netdev->features = NETIF_F_SG |
968 NETIF_F_HW_CSUM |
969 NETIF_F_HW_VLAN_TX |
970 NETIF_F_HW_VLAN_RX |
971 NETIF_F_HW_VLAN_FILTER;
972
973 netdev->features |= NETIF_F_TSO;
974
975 netdev->features |= NETIF_F_TSO6;
976 if (pci_using_dac)
977 netdev->features |= NETIF_F_HIGHDMA;
978
979 netdev->features |= NETIF_F_LLTX;
980 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
981
982 /* before reading the NVM, reset the controller to put the device in a
983 * known good starting state */
984 hw->mac.ops.reset_hw(hw);
985
986 /* make sure the NVM is good */
987 if (igb_validate_nvm_checksum(hw) < 0) {
988 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
989 err = -EIO;
990 goto err_eeprom;
991 }
992
993 /* copy the MAC address out of the NVM */
994 if (hw->mac.ops.read_mac_addr(hw))
995 dev_err(&pdev->dev, "NVM Read Error\n");
996
997 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
998 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
999
1000 if (!is_valid_ether_addr(netdev->perm_addr)) {
1001 dev_err(&pdev->dev, "Invalid MAC Address\n");
1002 err = -EIO;
1003 goto err_eeprom;
1004 }
1005
1006 init_timer(&adapter->watchdog_timer);
1007 adapter->watchdog_timer.function = &igb_watchdog;
1008 adapter->watchdog_timer.data = (unsigned long) adapter;
1009
1010 init_timer(&adapter->phy_info_timer);
1011 adapter->phy_info_timer.function = &igb_update_phy_info;
1012 adapter->phy_info_timer.data = (unsigned long) adapter;
1013
1014 INIT_WORK(&adapter->reset_task, igb_reset_task);
1015 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1016
1017 /* Initialize link & ring properties that are user-changeable */
1018 adapter->tx_ring->count = 256;
1019 for (i = 0; i < adapter->num_tx_queues; i++)
1020 adapter->tx_ring[i].count = adapter->tx_ring->count;
1021 adapter->rx_ring->count = 256;
1022 for (i = 0; i < adapter->num_rx_queues; i++)
1023 adapter->rx_ring[i].count = adapter->rx_ring->count;
1024
1025 adapter->fc_autoneg = true;
1026 hw->mac.autoneg = true;
1027 hw->phy.autoneg_advertised = 0x2f;
1028
1029 hw->fc.original_type = e1000_fc_default;
1030 hw->fc.type = e1000_fc_default;
1031
1032 adapter->itr_setting = 3;
1033 adapter->itr = IGB_START_ITR;
1034
1035 igb_validate_mdi_setting(hw);
1036
1037 adapter->rx_csum = 1;
1038
1039 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1040 * enable the ACPI Magic Packet filter
1041 */
1042
1043 if (hw->bus.func == 0 ||
1044 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1045 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1046 &eeprom_data);
1047
1048 if (eeprom_data & eeprom_apme_mask)
1049 adapter->eeprom_wol |= E1000_WUFC_MAG;
1050
1051 /* now that we have the eeprom settings, apply the special cases where
1052 * the eeprom may be wrong or the board simply won't support wake on
1053 * lan on a particular port */
1054 switch (pdev->device) {
1055 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1056 adapter->eeprom_wol = 0;
1057 break;
1058 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1059 /* Wake events only supported on port A for dual fiber
1060 * regardless of eeprom setting */
1061 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1062 adapter->eeprom_wol = 0;
1063 break;
1064 }
1065
1066 /* initialize the wol settings based on the eeprom settings */
1067 adapter->wol = adapter->eeprom_wol;
1068
1069 /* reset the hardware with the new settings */
1070 igb_reset(adapter);
1071
1072 /* let the f/w know that the h/w is now under the control of the
1073 * driver. */
1074 igb_get_hw_control(adapter);
1075
1076 /* tell the stack to leave us alone until igb_open() is called */
1077 netif_carrier_off(netdev);
1078 netif_stop_queue(netdev);
1079
1080 strcpy(netdev->name, "eth%d");
1081 err = register_netdev(netdev);
1082 if (err)
1083 goto err_register;
1084
1085 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1086 /* print bus type/speed/width info */
1087 dev_info(&pdev->dev,
1088 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1089 netdev->name,
1090 ((hw->bus.speed == e1000_bus_speed_2500)
1091 ? "2.5Gb/s" : "unknown"),
1092 ((hw->bus.width == e1000_bus_width_pcie_x4)
1093 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1094 ? "Width x1" : "unknown"),
1095 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1096 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1097
1098 igb_read_part_num(hw, &part_num);
1099 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1100 (part_num >> 8), (part_num & 0xff));
1101
1102 dev_info(&pdev->dev,
1103 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1104 adapter->msix_entries ? "MSI-X" :
1105 adapter->msi_enabled ? "MSI" : "legacy",
1106 adapter->num_rx_queues, adapter->num_tx_queues);
1107
1108 cards_found++;
1109 return 0;
1110
1111 err_register:
1112 igb_release_hw_control(adapter);
1113 err_eeprom:
1114 if (!igb_check_reset_block(hw))
1115 hw->phy.ops.reset_phy(hw);
1116
1117 if (hw->flash_address)
1118 iounmap(hw->flash_address);
1119
1120 igb_remove_device(hw);
1121 kfree(adapter->tx_ring);
1122 kfree(adapter->rx_ring);
1123 err_sw_init:
1124 err_hw_init:
1125 iounmap(hw->hw_addr);
1126 err_ioremap:
1127 free_netdev(netdev);
1128 err_alloc_etherdev:
1129 pci_release_regions(pdev);
1130 err_pci_reg:
1131 err_dma:
1132 pci_disable_device(pdev);
1133 return err;
1134 }
1135
1136 /**
1137 * igb_remove - Device Removal Routine
1138 * @pdev: PCI device information struct
1139 *
1140 * igb_remove is called by the PCI subsystem to alert the driver
1141 * that it should release a PCI device. The could be caused by a
1142 * Hot-Plug event, or because the driver is going to be removed from
1143 * memory.
1144 **/
1145 static void __devexit igb_remove(struct pci_dev *pdev)
1146 {
1147 struct net_device *netdev = pci_get_drvdata(pdev);
1148 struct igb_adapter *adapter = netdev_priv(netdev);
1149
1150 /* flush_scheduled work may reschedule our watchdog task, so
1151 * explicitly disable watchdog tasks from being rescheduled */
1152 set_bit(__IGB_DOWN, &adapter->state);
1153 del_timer_sync(&adapter->watchdog_timer);
1154 del_timer_sync(&adapter->phy_info_timer);
1155
1156 flush_scheduled_work();
1157
1158 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1159 * would have already happened in close and is redundant. */
1160 igb_release_hw_control(adapter);
1161
1162 unregister_netdev(netdev);
1163
1164 if (!igb_check_reset_block(&adapter->hw))
1165 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1166
1167 igb_remove_device(&adapter->hw);
1168 igb_reset_interrupt_capability(adapter);
1169
1170 kfree(adapter->tx_ring);
1171 kfree(adapter->rx_ring);
1172
1173 iounmap(adapter->hw.hw_addr);
1174 if (adapter->hw.flash_address)
1175 iounmap(adapter->hw.flash_address);
1176 pci_release_regions(pdev);
1177
1178 free_netdev(netdev);
1179
1180 pci_disable_device(pdev);
1181 }
1182
1183 /**
1184 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1185 * @adapter: board private structure to initialize
1186 *
1187 * igb_sw_init initializes the Adapter private data structure.
1188 * Fields are initialized based on PCI device information and
1189 * OS network device settings (MTU size).
1190 **/
1191 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1192 {
1193 struct e1000_hw *hw = &adapter->hw;
1194 struct net_device *netdev = adapter->netdev;
1195 struct pci_dev *pdev = adapter->pdev;
1196
1197 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1198
1199 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1200 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1201 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1202 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1203
1204 /* Number of supported queues. */
1205 /* Having more queues than CPUs doesn't make sense. */
1206 adapter->num_tx_queues = 1;
1207 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1208
1209 igb_set_interrupt_capability(adapter);
1210
1211 if (igb_alloc_queues(adapter)) {
1212 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1213 return -ENOMEM;
1214 }
1215
1216 /* Explicitly disable IRQ since the NIC can be in any state. */
1217 igb_irq_disable(adapter);
1218
1219 set_bit(__IGB_DOWN, &adapter->state);
1220 return 0;
1221 }
1222
1223 /**
1224 * igb_open - Called when a network interface is made active
1225 * @netdev: network interface device structure
1226 *
1227 * Returns 0 on success, negative value on failure
1228 *
1229 * The open entry point is called when a network interface is made
1230 * active by the system (IFF_UP). At this point all resources needed
1231 * for transmit and receive operations are allocated, the interrupt
1232 * handler is registered with the OS, the watchdog timer is started,
1233 * and the stack is notified that the interface is ready.
1234 **/
1235 static int igb_open(struct net_device *netdev)
1236 {
1237 struct igb_adapter *adapter = netdev_priv(netdev);
1238 struct e1000_hw *hw = &adapter->hw;
1239 int err;
1240 int i;
1241
1242 /* disallow open during test */
1243 if (test_bit(__IGB_TESTING, &adapter->state))
1244 return -EBUSY;
1245
1246 /* allocate transmit descriptors */
1247 err = igb_setup_all_tx_resources(adapter);
1248 if (err)
1249 goto err_setup_tx;
1250
1251 /* allocate receive descriptors */
1252 err = igb_setup_all_rx_resources(adapter);
1253 if (err)
1254 goto err_setup_rx;
1255
1256 /* e1000_power_up_phy(adapter); */
1257
1258 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1259 if ((adapter->hw.mng_cookie.status &
1260 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1261 igb_update_mng_vlan(adapter);
1262
1263 /* before we allocate an interrupt, we must be ready to handle it.
1264 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1265 * as soon as we call pci_request_irq, so we have to setup our
1266 * clean_rx handler before we do so. */
1267 igb_configure(adapter);
1268
1269 err = igb_request_irq(adapter);
1270 if (err)
1271 goto err_req_irq;
1272
1273 /* From here on the code is the same as igb_up() */
1274 clear_bit(__IGB_DOWN, &adapter->state);
1275
1276 napi_enable(&adapter->napi);
1277 if (adapter->msix_entries)
1278 for (i = 0; i < adapter->num_rx_queues; i++)
1279 napi_enable(&adapter->rx_ring[i].napi);
1280
1281 igb_irq_enable(adapter);
1282
1283 /* Clear any pending interrupts. */
1284 rd32(E1000_ICR);
1285 /* Fire a link status change interrupt to start the watchdog. */
1286 wr32(E1000_ICS, E1000_ICS_LSC);
1287
1288 return 0;
1289
1290 err_req_irq:
1291 igb_release_hw_control(adapter);
1292 /* e1000_power_down_phy(adapter); */
1293 igb_free_all_rx_resources(adapter);
1294 err_setup_rx:
1295 igb_free_all_tx_resources(adapter);
1296 err_setup_tx:
1297 igb_reset(adapter);
1298
1299 return err;
1300 }
1301
1302 /**
1303 * igb_close - Disables a network interface
1304 * @netdev: network interface device structure
1305 *
1306 * Returns 0, this is not allowed to fail
1307 *
1308 * The close entry point is called when an interface is de-activated
1309 * by the OS. The hardware is still under the driver's control, but
1310 * needs to be disabled. A global MAC reset is issued to stop the
1311 * hardware, and all transmit and receive resources are freed.
1312 **/
1313 static int igb_close(struct net_device *netdev)
1314 {
1315 struct igb_adapter *adapter = netdev_priv(netdev);
1316
1317 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1318 igb_down(adapter);
1319
1320 igb_free_irq(adapter);
1321
1322 igb_free_all_tx_resources(adapter);
1323 igb_free_all_rx_resources(adapter);
1324
1325 /* kill manageability vlan ID if supported, but not if a vlan with
1326 * the same ID is registered on the host OS (let 8021q kill it) */
1327 if ((adapter->hw.mng_cookie.status &
1328 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1329 !(adapter->vlgrp &&
1330 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1331 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1332
1333 return 0;
1334 }
1335
1336 /**
1337 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1338 * @adapter: board private structure
1339 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1340 *
1341 * Return 0 on success, negative on failure
1342 **/
1343
1344 int igb_setup_tx_resources(struct igb_adapter *adapter,
1345 struct igb_ring *tx_ring)
1346 {
1347 struct pci_dev *pdev = adapter->pdev;
1348 int size;
1349
1350 size = sizeof(struct igb_buffer) * tx_ring->count;
1351 tx_ring->buffer_info = vmalloc(size);
1352 if (!tx_ring->buffer_info)
1353 goto err;
1354 memset(tx_ring->buffer_info, 0, size);
1355
1356 /* round up to nearest 4K */
1357 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1358 + sizeof(u32);
1359 tx_ring->size = ALIGN(tx_ring->size, 4096);
1360
1361 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1362 &tx_ring->dma);
1363
1364 if (!tx_ring->desc)
1365 goto err;
1366
1367 tx_ring->adapter = adapter;
1368 tx_ring->next_to_use = 0;
1369 tx_ring->next_to_clean = 0;
1370 spin_lock_init(&tx_ring->tx_clean_lock);
1371 spin_lock_init(&tx_ring->tx_lock);
1372 return 0;
1373
1374 err:
1375 vfree(tx_ring->buffer_info);
1376 dev_err(&adapter->pdev->dev,
1377 "Unable to allocate memory for the transmit descriptor ring\n");
1378 return -ENOMEM;
1379 }
1380
1381 /**
1382 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1383 * (Descriptors) for all queues
1384 * @adapter: board private structure
1385 *
1386 * Return 0 on success, negative on failure
1387 **/
1388 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1389 {
1390 int i, err = 0;
1391
1392 for (i = 0; i < adapter->num_tx_queues; i++) {
1393 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1394 if (err) {
1395 dev_err(&adapter->pdev->dev,
1396 "Allocation for Tx Queue %u failed\n", i);
1397 for (i--; i >= 0; i--)
1398 igb_free_tx_resources(adapter,
1399 &adapter->tx_ring[i]);
1400 break;
1401 }
1402 }
1403
1404 return err;
1405 }
1406
1407 /**
1408 * igb_configure_tx - Configure transmit Unit after Reset
1409 * @adapter: board private structure
1410 *
1411 * Configure the Tx unit of the MAC after a reset.
1412 **/
1413 static void igb_configure_tx(struct igb_adapter *adapter)
1414 {
1415 u64 tdba, tdwba;
1416 struct e1000_hw *hw = &adapter->hw;
1417 u32 tctl;
1418 u32 txdctl, txctrl;
1419 int i;
1420
1421 for (i = 0; i < adapter->num_tx_queues; i++) {
1422 struct igb_ring *ring = &(adapter->tx_ring[i]);
1423
1424 wr32(E1000_TDLEN(i),
1425 ring->count * sizeof(struct e1000_tx_desc));
1426 tdba = ring->dma;
1427 wr32(E1000_TDBAL(i),
1428 tdba & 0x00000000ffffffffULL);
1429 wr32(E1000_TDBAH(i), tdba >> 32);
1430
1431 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1432 tdwba |= 1; /* enable head wb */
1433 wr32(E1000_TDWBAL(i),
1434 tdwba & 0x00000000ffffffffULL);
1435 wr32(E1000_TDWBAH(i), tdwba >> 32);
1436
1437 ring->head = E1000_TDH(i);
1438 ring->tail = E1000_TDT(i);
1439 writel(0, hw->hw_addr + ring->tail);
1440 writel(0, hw->hw_addr + ring->head);
1441 txdctl = rd32(E1000_TXDCTL(i));
1442 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1443 wr32(E1000_TXDCTL(i), txdctl);
1444
1445 /* Turn off Relaxed Ordering on head write-backs. The
1446 * writebacks MUST be delivered in order or it will
1447 * completely screw up our bookeeping.
1448 */
1449 txctrl = rd32(E1000_DCA_TXCTRL(i));
1450 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1451 wr32(E1000_DCA_TXCTRL(i), txctrl);
1452 }
1453
1454
1455
1456 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1457
1458 /* Program the Transmit Control Register */
1459
1460 tctl = rd32(E1000_TCTL);
1461 tctl &= ~E1000_TCTL_CT;
1462 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1463 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1464
1465 igb_config_collision_dist(hw);
1466
1467 /* Setup Transmit Descriptor Settings for eop descriptor */
1468 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1469
1470 /* Enable transmits */
1471 tctl |= E1000_TCTL_EN;
1472
1473 wr32(E1000_TCTL, tctl);
1474 }
1475
1476 /**
1477 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1478 * @adapter: board private structure
1479 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1480 *
1481 * Returns 0 on success, negative on failure
1482 **/
1483
1484 int igb_setup_rx_resources(struct igb_adapter *adapter,
1485 struct igb_ring *rx_ring)
1486 {
1487 struct pci_dev *pdev = adapter->pdev;
1488 int size, desc_len;
1489
1490 size = sizeof(struct igb_buffer) * rx_ring->count;
1491 rx_ring->buffer_info = vmalloc(size);
1492 if (!rx_ring->buffer_info)
1493 goto err;
1494 memset(rx_ring->buffer_info, 0, size);
1495
1496 desc_len = sizeof(union e1000_adv_rx_desc);
1497
1498 /* Round up to nearest 4K */
1499 rx_ring->size = rx_ring->count * desc_len;
1500 rx_ring->size = ALIGN(rx_ring->size, 4096);
1501
1502 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1503 &rx_ring->dma);
1504
1505 if (!rx_ring->desc)
1506 goto err;
1507
1508 rx_ring->next_to_clean = 0;
1509 rx_ring->next_to_use = 0;
1510 rx_ring->pending_skb = NULL;
1511
1512 rx_ring->adapter = adapter;
1513 /* FIXME: do we want to setup ring->napi->poll here? */
1514 rx_ring->napi.poll = adapter->napi.poll;
1515
1516 return 0;
1517
1518 err:
1519 vfree(rx_ring->buffer_info);
1520 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1521 "the receive descriptor ring\n");
1522 return -ENOMEM;
1523 }
1524
1525 /**
1526 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1527 * (Descriptors) for all queues
1528 * @adapter: board private structure
1529 *
1530 * Return 0 on success, negative on failure
1531 **/
1532 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1533 {
1534 int i, err = 0;
1535
1536 for (i = 0; i < adapter->num_rx_queues; i++) {
1537 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1538 if (err) {
1539 dev_err(&adapter->pdev->dev,
1540 "Allocation for Rx Queue %u failed\n", i);
1541 for (i--; i >= 0; i--)
1542 igb_free_rx_resources(adapter,
1543 &adapter->rx_ring[i]);
1544 break;
1545 }
1546 }
1547
1548 return err;
1549 }
1550
1551 /**
1552 * igb_setup_rctl - configure the receive control registers
1553 * @adapter: Board private structure
1554 **/
1555 static void igb_setup_rctl(struct igb_adapter *adapter)
1556 {
1557 struct e1000_hw *hw = &adapter->hw;
1558 u32 rctl;
1559 u32 srrctl = 0;
1560 int i;
1561
1562 rctl = rd32(E1000_RCTL);
1563
1564 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1565
1566 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1567 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1568 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1569
1570 /* disable the stripping of CRC because it breaks
1571 * BMC firmware connected over SMBUS
1572 rctl |= E1000_RCTL_SECRC;
1573 */
1574
1575 rctl &= ~E1000_RCTL_SBP;
1576
1577 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1578 rctl &= ~E1000_RCTL_LPE;
1579 else
1580 rctl |= E1000_RCTL_LPE;
1581 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1582 /* Setup buffer sizes */
1583 rctl &= ~E1000_RCTL_SZ_4096;
1584 rctl |= E1000_RCTL_BSEX;
1585 switch (adapter->rx_buffer_len) {
1586 case IGB_RXBUFFER_256:
1587 rctl |= E1000_RCTL_SZ_256;
1588 rctl &= ~E1000_RCTL_BSEX;
1589 break;
1590 case IGB_RXBUFFER_512:
1591 rctl |= E1000_RCTL_SZ_512;
1592 rctl &= ~E1000_RCTL_BSEX;
1593 break;
1594 case IGB_RXBUFFER_1024:
1595 rctl |= E1000_RCTL_SZ_1024;
1596 rctl &= ~E1000_RCTL_BSEX;
1597 break;
1598 case IGB_RXBUFFER_2048:
1599 default:
1600 rctl |= E1000_RCTL_SZ_2048;
1601 rctl &= ~E1000_RCTL_BSEX;
1602 break;
1603 case IGB_RXBUFFER_4096:
1604 rctl |= E1000_RCTL_SZ_4096;
1605 break;
1606 case IGB_RXBUFFER_8192:
1607 rctl |= E1000_RCTL_SZ_8192;
1608 break;
1609 case IGB_RXBUFFER_16384:
1610 rctl |= E1000_RCTL_SZ_16384;
1611 break;
1612 }
1613 } else {
1614 rctl &= ~E1000_RCTL_BSEX;
1615 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1616 }
1617
1618 /* 82575 and greater support packet-split where the protocol
1619 * header is placed in skb->data and the packet data is
1620 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1621 * In the case of a non-split, skb->data is linearly filled,
1622 * followed by the page buffers. Therefore, skb->data is
1623 * sized to hold the largest protocol header.
1624 */
1625 /* allocations using alloc_page take too long for regular MTU
1626 * so only enable packet split for jumbo frames */
1627 if (rctl & E1000_RCTL_LPE) {
1628 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1629 srrctl = adapter->rx_ps_hdr_size <<
1630 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1631 /* buffer size is ALWAYS one page */
1632 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1633 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1634 } else {
1635 adapter->rx_ps_hdr_size = 0;
1636 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1637 }
1638
1639 for (i = 0; i < adapter->num_rx_queues; i++)
1640 wr32(E1000_SRRCTL(i), srrctl);
1641
1642 wr32(E1000_RCTL, rctl);
1643 }
1644
1645 /**
1646 * igb_configure_rx - Configure receive Unit after Reset
1647 * @adapter: board private structure
1648 *
1649 * Configure the Rx unit of the MAC after a reset.
1650 **/
1651 static void igb_configure_rx(struct igb_adapter *adapter)
1652 {
1653 u64 rdba;
1654 struct e1000_hw *hw = &adapter->hw;
1655 u32 rctl, rxcsum;
1656 u32 rxdctl;
1657 int i;
1658
1659 /* disable receives while setting up the descriptors */
1660 rctl = rd32(E1000_RCTL);
1661 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1662 wrfl();
1663 mdelay(10);
1664
1665 if (adapter->itr_setting > 3)
1666 wr32(E1000_ITR,
1667 1000000000 / (adapter->itr * 256));
1668
1669 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1670 * the Base and Length of the Rx Descriptor Ring */
1671 for (i = 0; i < adapter->num_rx_queues; i++) {
1672 struct igb_ring *ring = &(adapter->rx_ring[i]);
1673 rdba = ring->dma;
1674 wr32(E1000_RDBAL(i),
1675 rdba & 0x00000000ffffffffULL);
1676 wr32(E1000_RDBAH(i), rdba >> 32);
1677 wr32(E1000_RDLEN(i),
1678 ring->count * sizeof(union e1000_adv_rx_desc));
1679
1680 ring->head = E1000_RDH(i);
1681 ring->tail = E1000_RDT(i);
1682 writel(0, hw->hw_addr + ring->tail);
1683 writel(0, hw->hw_addr + ring->head);
1684
1685 rxdctl = rd32(E1000_RXDCTL(i));
1686 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1687 rxdctl &= 0xFFF00000;
1688 rxdctl |= IGB_RX_PTHRESH;
1689 rxdctl |= IGB_RX_HTHRESH << 8;
1690 rxdctl |= IGB_RX_WTHRESH << 16;
1691 wr32(E1000_RXDCTL(i), rxdctl);
1692 }
1693
1694 if (adapter->num_rx_queues > 1) {
1695 u32 random[10];
1696 u32 mrqc;
1697 u32 j, shift;
1698 union e1000_reta {
1699 u32 dword;
1700 u8 bytes[4];
1701 } reta;
1702
1703 get_random_bytes(&random[0], 40);
1704
1705 shift = 6;
1706 for (j = 0; j < (32 * 4); j++) {
1707 reta.bytes[j & 3] =
1708 (j % adapter->num_rx_queues) << shift;
1709 if ((j & 3) == 3)
1710 writel(reta.dword,
1711 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1712 }
1713 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1714
1715 /* Fill out hash function seeds */
1716 for (j = 0; j < 10; j++)
1717 array_wr32(E1000_RSSRK(0), j, random[j]);
1718
1719 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1720 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1721 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1722 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1723 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1724 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1725 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1726 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1727
1728
1729 wr32(E1000_MRQC, mrqc);
1730
1731 /* Multiqueue and raw packet checksumming are mutually
1732 * exclusive. Note that this not the same as TCP/IP
1733 * checksumming, which works fine. */
1734 rxcsum = rd32(E1000_RXCSUM);
1735 rxcsum |= E1000_RXCSUM_PCSD;
1736 wr32(E1000_RXCSUM, rxcsum);
1737 } else {
1738 /* Enable Receive Checksum Offload for TCP and UDP */
1739 rxcsum = rd32(E1000_RXCSUM);
1740 if (adapter->rx_csum) {
1741 rxcsum |= E1000_RXCSUM_TUOFL;
1742
1743 /* Enable IPv4 payload checksum for UDP fragments
1744 * Must be used in conjunction with packet-split. */
1745 if (adapter->rx_ps_hdr_size)
1746 rxcsum |= E1000_RXCSUM_IPPCSE;
1747 } else {
1748 rxcsum &= ~E1000_RXCSUM_TUOFL;
1749 /* don't need to clear IPPCSE as it defaults to 0 */
1750 }
1751 wr32(E1000_RXCSUM, rxcsum);
1752 }
1753
1754 if (adapter->vlgrp)
1755 wr32(E1000_RLPML,
1756 adapter->max_frame_size + VLAN_TAG_SIZE);
1757 else
1758 wr32(E1000_RLPML, adapter->max_frame_size);
1759
1760 /* Enable Receives */
1761 wr32(E1000_RCTL, rctl);
1762 }
1763
1764 /**
1765 * igb_free_tx_resources - Free Tx Resources per Queue
1766 * @adapter: board private structure
1767 * @tx_ring: Tx descriptor ring for a specific queue
1768 *
1769 * Free all transmit software resources
1770 **/
1771 static void igb_free_tx_resources(struct igb_adapter *adapter,
1772 struct igb_ring *tx_ring)
1773 {
1774 struct pci_dev *pdev = adapter->pdev;
1775
1776 igb_clean_tx_ring(adapter, tx_ring);
1777
1778 vfree(tx_ring->buffer_info);
1779 tx_ring->buffer_info = NULL;
1780
1781 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1782
1783 tx_ring->desc = NULL;
1784 }
1785
1786 /**
1787 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1788 * @adapter: board private structure
1789 *
1790 * Free all transmit software resources
1791 **/
1792 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1793 {
1794 int i;
1795
1796 for (i = 0; i < adapter->num_tx_queues; i++)
1797 igb_free_tx_resources(adapter, &adapter->tx_ring[i]);
1798 }
1799
1800 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1801 struct igb_buffer *buffer_info)
1802 {
1803 if (buffer_info->dma) {
1804 pci_unmap_page(adapter->pdev,
1805 buffer_info->dma,
1806 buffer_info->length,
1807 PCI_DMA_TODEVICE);
1808 buffer_info->dma = 0;
1809 }
1810 if (buffer_info->skb) {
1811 dev_kfree_skb_any(buffer_info->skb);
1812 buffer_info->skb = NULL;
1813 }
1814 buffer_info->time_stamp = 0;
1815 /* buffer_info must be completely set up in the transmit path */
1816 }
1817
1818 /**
1819 * igb_clean_tx_ring - Free Tx Buffers
1820 * @adapter: board private structure
1821 * @tx_ring: ring to be cleaned
1822 **/
1823 static void igb_clean_tx_ring(struct igb_adapter *adapter,
1824 struct igb_ring *tx_ring)
1825 {
1826 struct igb_buffer *buffer_info;
1827 unsigned long size;
1828 unsigned int i;
1829
1830 if (!tx_ring->buffer_info)
1831 return;
1832 /* Free all the Tx ring sk_buffs */
1833
1834 for (i = 0; i < tx_ring->count; i++) {
1835 buffer_info = &tx_ring->buffer_info[i];
1836 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1837 }
1838
1839 size = sizeof(struct igb_buffer) * tx_ring->count;
1840 memset(tx_ring->buffer_info, 0, size);
1841
1842 /* Zero out the descriptor ring */
1843
1844 memset(tx_ring->desc, 0, tx_ring->size);
1845
1846 tx_ring->next_to_use = 0;
1847 tx_ring->next_to_clean = 0;
1848
1849 writel(0, adapter->hw.hw_addr + tx_ring->head);
1850 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1851 }
1852
1853 /**
1854 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1855 * @adapter: board private structure
1856 **/
1857 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1858 {
1859 int i;
1860
1861 for (i = 0; i < adapter->num_tx_queues; i++)
1862 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1863 }
1864
1865 /**
1866 * igb_free_rx_resources - Free Rx Resources
1867 * @adapter: board private structure
1868 * @rx_ring: ring to clean the resources from
1869 *
1870 * Free all receive software resources
1871 **/
1872 static void igb_free_rx_resources(struct igb_adapter *adapter,
1873 struct igb_ring *rx_ring)
1874 {
1875 struct pci_dev *pdev = adapter->pdev;
1876
1877 igb_clean_rx_ring(adapter, rx_ring);
1878
1879 vfree(rx_ring->buffer_info);
1880 rx_ring->buffer_info = NULL;
1881
1882 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1883
1884 rx_ring->desc = NULL;
1885 }
1886
1887 /**
1888 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1889 * @adapter: board private structure
1890 *
1891 * Free all receive software resources
1892 **/
1893 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1894 {
1895 int i;
1896
1897 for (i = 0; i < adapter->num_rx_queues; i++)
1898 igb_free_rx_resources(adapter, &adapter->rx_ring[i]);
1899 }
1900
1901 /**
1902 * igb_clean_rx_ring - Free Rx Buffers per Queue
1903 * @adapter: board private structure
1904 * @rx_ring: ring to free buffers from
1905 **/
1906 static void igb_clean_rx_ring(struct igb_adapter *adapter,
1907 struct igb_ring *rx_ring)
1908 {
1909 struct igb_buffer *buffer_info;
1910 struct pci_dev *pdev = adapter->pdev;
1911 unsigned long size;
1912 unsigned int i;
1913
1914 if (!rx_ring->buffer_info)
1915 return;
1916 /* Free all the Rx ring sk_buffs */
1917 for (i = 0; i < rx_ring->count; i++) {
1918 buffer_info = &rx_ring->buffer_info[i];
1919 if (buffer_info->dma) {
1920 if (adapter->rx_ps_hdr_size)
1921 pci_unmap_single(pdev, buffer_info->dma,
1922 adapter->rx_ps_hdr_size,
1923 PCI_DMA_FROMDEVICE);
1924 else
1925 pci_unmap_single(pdev, buffer_info->dma,
1926 adapter->rx_buffer_len,
1927 PCI_DMA_FROMDEVICE);
1928 buffer_info->dma = 0;
1929 }
1930
1931 if (buffer_info->skb) {
1932 dev_kfree_skb(buffer_info->skb);
1933 buffer_info->skb = NULL;
1934 }
1935 if (buffer_info->page) {
1936 pci_unmap_page(pdev, buffer_info->page_dma,
1937 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1938 put_page(buffer_info->page);
1939 buffer_info->page = NULL;
1940 buffer_info->page_dma = 0;
1941 }
1942 }
1943
1944 /* there also may be some cached data from a chained receive */
1945 if (rx_ring->pending_skb) {
1946 dev_kfree_skb(rx_ring->pending_skb);
1947 rx_ring->pending_skb = NULL;
1948 }
1949
1950 size = sizeof(struct igb_buffer) * rx_ring->count;
1951 memset(rx_ring->buffer_info, 0, size);
1952
1953 /* Zero out the descriptor ring */
1954 memset(rx_ring->desc, 0, rx_ring->size);
1955
1956 rx_ring->next_to_clean = 0;
1957 rx_ring->next_to_use = 0;
1958
1959 writel(0, adapter->hw.hw_addr + rx_ring->head);
1960 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1961 }
1962
1963 /**
1964 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1965 * @adapter: board private structure
1966 **/
1967 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1968 {
1969 int i;
1970
1971 for (i = 0; i < adapter->num_rx_queues; i++)
1972 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1973 }
1974
1975 /**
1976 * igb_set_mac - Change the Ethernet Address of the NIC
1977 * @netdev: network interface device structure
1978 * @p: pointer to an address structure
1979 *
1980 * Returns 0 on success, negative on failure
1981 **/
1982 static int igb_set_mac(struct net_device *netdev, void *p)
1983 {
1984 struct igb_adapter *adapter = netdev_priv(netdev);
1985 struct sockaddr *addr = p;
1986
1987 if (!is_valid_ether_addr(addr->sa_data))
1988 return -EADDRNOTAVAIL;
1989
1990 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1991 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
1992
1993 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1994
1995 return 0;
1996 }
1997
1998 /**
1999 * igb_set_multi - Multicast and Promiscuous mode set
2000 * @netdev: network interface device structure
2001 *
2002 * The set_multi entry point is called whenever the multicast address
2003 * list or the network interface flags are updated. This routine is
2004 * responsible for configuring the hardware for proper multicast,
2005 * promiscuous mode, and all-multi behavior.
2006 **/
2007 static void igb_set_multi(struct net_device *netdev)
2008 {
2009 struct igb_adapter *adapter = netdev_priv(netdev);
2010 struct e1000_hw *hw = &adapter->hw;
2011 struct e1000_mac_info *mac = &hw->mac;
2012 struct dev_mc_list *mc_ptr;
2013 u8 *mta_list;
2014 u32 rctl;
2015 int i;
2016
2017 /* Check for Promiscuous and All Multicast modes */
2018
2019 rctl = rd32(E1000_RCTL);
2020
2021 if (netdev->flags & IFF_PROMISC)
2022 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2023 else if (netdev->flags & IFF_ALLMULTI) {
2024 rctl |= E1000_RCTL_MPE;
2025 rctl &= ~E1000_RCTL_UPE;
2026 } else
2027 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2028
2029 wr32(E1000_RCTL, rctl);
2030
2031 if (!netdev->mc_count) {
2032 /* nothing to program, so clear mc list */
2033 igb_update_mc_addr_list(hw, NULL, 0, 1,
2034 mac->rar_entry_count);
2035 return;
2036 }
2037
2038 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2039 if (!mta_list)
2040 return;
2041
2042 /* The shared function expects a packed array of only addresses. */
2043 mc_ptr = netdev->mc_list;
2044
2045 for (i = 0; i < netdev->mc_count; i++) {
2046 if (!mc_ptr)
2047 break;
2048 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2049 mc_ptr = mc_ptr->next;
2050 }
2051 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2052 kfree(mta_list);
2053 }
2054
2055 /* Need to wait a few seconds after link up to get diagnostic information from
2056 * the phy */
2057 static void igb_update_phy_info(unsigned long data)
2058 {
2059 struct igb_adapter *adapter = (struct igb_adapter *) data;
2060 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2061 }
2062
2063 /**
2064 * igb_watchdog - Timer Call-back
2065 * @data: pointer to adapter cast into an unsigned long
2066 **/
2067 static void igb_watchdog(unsigned long data)
2068 {
2069 struct igb_adapter *adapter = (struct igb_adapter *)data;
2070 /* Do the rest outside of interrupt context */
2071 schedule_work(&adapter->watchdog_task);
2072 }
2073
2074 static void igb_watchdog_task(struct work_struct *work)
2075 {
2076 struct igb_adapter *adapter = container_of(work,
2077 struct igb_adapter, watchdog_task);
2078 struct e1000_hw *hw = &adapter->hw;
2079
2080 struct net_device *netdev = adapter->netdev;
2081 struct igb_ring *tx_ring = adapter->tx_ring;
2082 struct e1000_mac_info *mac = &adapter->hw.mac;
2083 u32 link;
2084 s32 ret_val;
2085
2086 if ((netif_carrier_ok(netdev)) &&
2087 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2088 goto link_up;
2089
2090 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2091 if ((ret_val == E1000_ERR_PHY) &&
2092 (hw->phy.type == e1000_phy_igp_3) &&
2093 (rd32(E1000_CTRL) &
2094 E1000_PHY_CTRL_GBE_DISABLE))
2095 dev_info(&adapter->pdev->dev,
2096 "Gigabit has been disabled, downgrading speed\n");
2097
2098 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2099 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2100 link = mac->serdes_has_link;
2101 else
2102 link = rd32(E1000_STATUS) &
2103 E1000_STATUS_LU;
2104
2105 if (link) {
2106 if (!netif_carrier_ok(netdev)) {
2107 u32 ctrl;
2108 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2109 &adapter->link_speed,
2110 &adapter->link_duplex);
2111
2112 ctrl = rd32(E1000_CTRL);
2113 dev_info(&adapter->pdev->dev,
2114 "NIC Link is Up %d Mbps %s, "
2115 "Flow Control: %s\n",
2116 adapter->link_speed,
2117 adapter->link_duplex == FULL_DUPLEX ?
2118 "Full Duplex" : "Half Duplex",
2119 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2120 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2121 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2122 E1000_CTRL_TFCE) ? "TX" : "None")));
2123
2124 /* tweak tx_queue_len according to speed/duplex and
2125 * adjust the timeout factor */
2126 netdev->tx_queue_len = adapter->tx_queue_len;
2127 adapter->tx_timeout_factor = 1;
2128 switch (adapter->link_speed) {
2129 case SPEED_10:
2130 netdev->tx_queue_len = 10;
2131 adapter->tx_timeout_factor = 14;
2132 break;
2133 case SPEED_100:
2134 netdev->tx_queue_len = 100;
2135 /* maybe add some timeout factor ? */
2136 break;
2137 }
2138
2139 netif_carrier_on(netdev);
2140 netif_wake_queue(netdev);
2141
2142 if (!test_bit(__IGB_DOWN, &adapter->state))
2143 mod_timer(&adapter->phy_info_timer,
2144 round_jiffies(jiffies + 2 * HZ));
2145 }
2146 } else {
2147 if (netif_carrier_ok(netdev)) {
2148 adapter->link_speed = 0;
2149 adapter->link_duplex = 0;
2150 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2151 netif_carrier_off(netdev);
2152 netif_stop_queue(netdev);
2153 if (!test_bit(__IGB_DOWN, &adapter->state))
2154 mod_timer(&adapter->phy_info_timer,
2155 round_jiffies(jiffies + 2 * HZ));
2156 }
2157 }
2158
2159 link_up:
2160 igb_update_stats(adapter);
2161
2162 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2163 adapter->tpt_old = adapter->stats.tpt;
2164 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2165 adapter->colc_old = adapter->stats.colc;
2166
2167 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2168 adapter->gorc_old = adapter->stats.gorc;
2169 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2170 adapter->gotc_old = adapter->stats.gotc;
2171
2172 igb_update_adaptive(&adapter->hw);
2173
2174 if (!netif_carrier_ok(netdev)) {
2175 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2176 /* We've lost link, so the controller stops DMA,
2177 * but we've got queued Tx work that's never going
2178 * to get done, so reset controller to flush Tx.
2179 * (Do the reset outside of interrupt context). */
2180 adapter->tx_timeout_count++;
2181 schedule_work(&adapter->reset_task);
2182 }
2183 }
2184
2185 /* Cause software interrupt to ensure rx ring is cleaned */
2186 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2187
2188 /* Force detection of hung controller every watchdog period */
2189 tx_ring->detect_tx_hung = true;
2190
2191 /* Reset the timer */
2192 if (!test_bit(__IGB_DOWN, &adapter->state))
2193 mod_timer(&adapter->watchdog_timer,
2194 round_jiffies(jiffies + 2 * HZ));
2195 }
2196
2197 enum latency_range {
2198 lowest_latency = 0,
2199 low_latency = 1,
2200 bulk_latency = 2,
2201 latency_invalid = 255
2202 };
2203
2204
2205 static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2206 struct igb_ring *rx_ring)
2207 {
2208 struct e1000_hw *hw = &adapter->hw;
2209 int new_val;
2210
2211 new_val = rx_ring->itr_val / 2;
2212 if (new_val < IGB_MIN_DYN_ITR)
2213 new_val = IGB_MIN_DYN_ITR;
2214
2215 if (new_val != rx_ring->itr_val) {
2216 rx_ring->itr_val = new_val;
2217 wr32(rx_ring->itr_register,
2218 1000000000 / (new_val * 256));
2219 }
2220 }
2221
2222 static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2223 struct igb_ring *rx_ring)
2224 {
2225 struct e1000_hw *hw = &adapter->hw;
2226 int new_val;
2227
2228 new_val = rx_ring->itr_val * 2;
2229 if (new_val > IGB_MAX_DYN_ITR)
2230 new_val = IGB_MAX_DYN_ITR;
2231
2232 if (new_val != rx_ring->itr_val) {
2233 rx_ring->itr_val = new_val;
2234 wr32(rx_ring->itr_register,
2235 1000000000 / (new_val * 256));
2236 }
2237 }
2238
2239 /**
2240 * igb_update_itr - update the dynamic ITR value based on statistics
2241 * Stores a new ITR value based on packets and byte
2242 * counts during the last interrupt. The advantage of per interrupt
2243 * computation is faster updates and more accurate ITR for the current
2244 * traffic pattern. Constants in this function were computed
2245 * based on theoretical maximum wire speed and thresholds were set based
2246 * on testing data as well as attempting to minimize response time
2247 * while increasing bulk throughput.
2248 * this functionality is controlled by the InterruptThrottleRate module
2249 * parameter (see igb_param.c)
2250 * NOTE: These calculations are only valid when operating in a single-
2251 * queue environment.
2252 * @adapter: pointer to adapter
2253 * @itr_setting: current adapter->itr
2254 * @packets: the number of packets during this measurement interval
2255 * @bytes: the number of bytes during this measurement interval
2256 **/
2257 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2258 int packets, int bytes)
2259 {
2260 unsigned int retval = itr_setting;
2261
2262 if (packets == 0)
2263 goto update_itr_done;
2264
2265 switch (itr_setting) {
2266 case lowest_latency:
2267 /* handle TSO and jumbo frames */
2268 if (bytes/packets > 8000)
2269 retval = bulk_latency;
2270 else if ((packets < 5) && (bytes > 512))
2271 retval = low_latency;
2272 break;
2273 case low_latency: /* 50 usec aka 20000 ints/s */
2274 if (bytes > 10000) {
2275 /* this if handles the TSO accounting */
2276 if (bytes/packets > 8000) {
2277 retval = bulk_latency;
2278 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2279 retval = bulk_latency;
2280 } else if ((packets > 35)) {
2281 retval = lowest_latency;
2282 }
2283 } else if (bytes/packets > 2000) {
2284 retval = bulk_latency;
2285 } else if (packets <= 2 && bytes < 512) {
2286 retval = lowest_latency;
2287 }
2288 break;
2289 case bulk_latency: /* 250 usec aka 4000 ints/s */
2290 if (bytes > 25000) {
2291 if (packets > 35)
2292 retval = low_latency;
2293 } else if (bytes < 6000) {
2294 retval = low_latency;
2295 }
2296 break;
2297 }
2298
2299 update_itr_done:
2300 return retval;
2301 }
2302
2303 static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2304 int rx_only)
2305 {
2306 u16 current_itr;
2307 u32 new_itr = adapter->itr;
2308
2309 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2310 if (adapter->link_speed != SPEED_1000) {
2311 current_itr = 0;
2312 new_itr = 4000;
2313 goto set_itr_now;
2314 }
2315
2316 adapter->rx_itr = igb_update_itr(adapter,
2317 adapter->rx_itr,
2318 adapter->rx_ring->total_packets,
2319 adapter->rx_ring->total_bytes);
2320 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2321 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2322 adapter->rx_itr = low_latency;
2323
2324 if (!rx_only) {
2325 adapter->tx_itr = igb_update_itr(adapter,
2326 adapter->tx_itr,
2327 adapter->tx_ring->total_packets,
2328 adapter->tx_ring->total_bytes);
2329 /* conservative mode (itr 3) eliminates the
2330 * lowest_latency setting */
2331 if (adapter->itr_setting == 3 &&
2332 adapter->tx_itr == lowest_latency)
2333 adapter->tx_itr = low_latency;
2334
2335 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2336 } else {
2337 current_itr = adapter->rx_itr;
2338 }
2339
2340 switch (current_itr) {
2341 /* counts and packets in update_itr are dependent on these numbers */
2342 case lowest_latency:
2343 new_itr = 70000;
2344 break;
2345 case low_latency:
2346 new_itr = 20000; /* aka hwitr = ~200 */
2347 break;
2348 case bulk_latency:
2349 new_itr = 4000;
2350 break;
2351 default:
2352 break;
2353 }
2354
2355 set_itr_now:
2356 if (new_itr != adapter->itr) {
2357 /* this attempts to bias the interrupt rate towards Bulk
2358 * by adding intermediate steps when interrupt rate is
2359 * increasing */
2360 new_itr = new_itr > adapter->itr ?
2361 min(adapter->itr + (new_itr >> 2), new_itr) :
2362 new_itr;
2363 /* Don't write the value here; it resets the adapter's
2364 * internal timer, and causes us to delay far longer than
2365 * we should between interrupts. Instead, we write the ITR
2366 * value at the beginning of the next interrupt so the timing
2367 * ends up being correct.
2368 */
2369 adapter->itr = new_itr;
2370 adapter->set_itr = 1;
2371 }
2372
2373 return;
2374 }
2375
2376
2377 #define IGB_TX_FLAGS_CSUM 0x00000001
2378 #define IGB_TX_FLAGS_VLAN 0x00000002
2379 #define IGB_TX_FLAGS_TSO 0x00000004
2380 #define IGB_TX_FLAGS_IPV4 0x00000008
2381 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2382 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2383
2384 static inline int igb_tso_adv(struct igb_adapter *adapter,
2385 struct igb_ring *tx_ring,
2386 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2387 {
2388 struct e1000_adv_tx_context_desc *context_desc;
2389 unsigned int i;
2390 int err;
2391 struct igb_buffer *buffer_info;
2392 u32 info = 0, tu_cmd = 0;
2393 u32 mss_l4len_idx, l4len;
2394 *hdr_len = 0;
2395
2396 if (skb_header_cloned(skb)) {
2397 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2398 if (err)
2399 return err;
2400 }
2401
2402 l4len = tcp_hdrlen(skb);
2403 *hdr_len += l4len;
2404
2405 if (skb->protocol == htons(ETH_P_IP)) {
2406 struct iphdr *iph = ip_hdr(skb);
2407 iph->tot_len = 0;
2408 iph->check = 0;
2409 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2410 iph->daddr, 0,
2411 IPPROTO_TCP,
2412 0);
2413 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2414 ipv6_hdr(skb)->payload_len = 0;
2415 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2416 &ipv6_hdr(skb)->daddr,
2417 0, IPPROTO_TCP, 0);
2418 }
2419
2420 i = tx_ring->next_to_use;
2421
2422 buffer_info = &tx_ring->buffer_info[i];
2423 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2424 /* VLAN MACLEN IPLEN */
2425 if (tx_flags & IGB_TX_FLAGS_VLAN)
2426 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2427 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2428 *hdr_len += skb_network_offset(skb);
2429 info |= skb_network_header_len(skb);
2430 *hdr_len += skb_network_header_len(skb);
2431 context_desc->vlan_macip_lens = cpu_to_le32(info);
2432
2433 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2434 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2435
2436 if (skb->protocol == htons(ETH_P_IP))
2437 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2438 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2439
2440 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2441
2442 /* MSS L4LEN IDX */
2443 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2444 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2445
2446 /* Context index must be unique per ring. Luckily, so is the interrupt
2447 * mask value. */
2448 mss_l4len_idx |= tx_ring->eims_value >> 4;
2449
2450 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2451 context_desc->seqnum_seed = 0;
2452
2453 buffer_info->time_stamp = jiffies;
2454 buffer_info->dma = 0;
2455 i++;
2456 if (i == tx_ring->count)
2457 i = 0;
2458
2459 tx_ring->next_to_use = i;
2460
2461 return true;
2462 }
2463
2464 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2465 struct igb_ring *tx_ring,
2466 struct sk_buff *skb, u32 tx_flags)
2467 {
2468 struct e1000_adv_tx_context_desc *context_desc;
2469 unsigned int i;
2470 struct igb_buffer *buffer_info;
2471 u32 info = 0, tu_cmd = 0;
2472
2473 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2474 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2475 i = tx_ring->next_to_use;
2476 buffer_info = &tx_ring->buffer_info[i];
2477 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2478
2479 if (tx_flags & IGB_TX_FLAGS_VLAN)
2480 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2481 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2482 if (skb->ip_summed == CHECKSUM_PARTIAL)
2483 info |= skb_network_header_len(skb);
2484
2485 context_desc->vlan_macip_lens = cpu_to_le32(info);
2486
2487 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2488
2489 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2490 if (skb->protocol == htons(ETH_P_IP))
2491 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2492 if (skb->sk && (skb->sk->sk_protocol == IPPROTO_TCP))
2493 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2494 }
2495
2496 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2497 context_desc->seqnum_seed = 0;
2498 context_desc->mss_l4len_idx =
2499 cpu_to_le32(tx_ring->eims_value >> 4);
2500
2501 buffer_info->time_stamp = jiffies;
2502 buffer_info->dma = 0;
2503
2504 i++;
2505 if (i == tx_ring->count)
2506 i = 0;
2507 tx_ring->next_to_use = i;
2508
2509 return true;
2510 }
2511
2512
2513 return false;
2514 }
2515
2516 #define IGB_MAX_TXD_PWR 16
2517 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2518
2519 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2520 struct igb_ring *tx_ring,
2521 struct sk_buff *skb)
2522 {
2523 struct igb_buffer *buffer_info;
2524 unsigned int len = skb_headlen(skb);
2525 unsigned int count = 0, i;
2526 unsigned int f;
2527
2528 i = tx_ring->next_to_use;
2529
2530 buffer_info = &tx_ring->buffer_info[i];
2531 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2532 buffer_info->length = len;
2533 /* set time_stamp *before* dma to help avoid a possible race */
2534 buffer_info->time_stamp = jiffies;
2535 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2536 PCI_DMA_TODEVICE);
2537 count++;
2538 i++;
2539 if (i == tx_ring->count)
2540 i = 0;
2541
2542 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2543 struct skb_frag_struct *frag;
2544
2545 frag = &skb_shinfo(skb)->frags[f];
2546 len = frag->size;
2547
2548 buffer_info = &tx_ring->buffer_info[i];
2549 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2550 buffer_info->length = len;
2551 buffer_info->time_stamp = jiffies;
2552 buffer_info->dma = pci_map_page(adapter->pdev,
2553 frag->page,
2554 frag->page_offset,
2555 len,
2556 PCI_DMA_TODEVICE);
2557
2558 count++;
2559 i++;
2560 if (i == tx_ring->count)
2561 i = 0;
2562 }
2563
2564 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2565 tx_ring->buffer_info[i].skb = skb;
2566
2567 return count;
2568 }
2569
2570 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2571 struct igb_ring *tx_ring,
2572 int tx_flags, int count, u32 paylen,
2573 u8 hdr_len)
2574 {
2575 union e1000_adv_tx_desc *tx_desc = NULL;
2576 struct igb_buffer *buffer_info;
2577 u32 olinfo_status = 0, cmd_type_len;
2578 unsigned int i;
2579
2580 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2581 E1000_ADVTXD_DCMD_DEXT);
2582
2583 if (tx_flags & IGB_TX_FLAGS_VLAN)
2584 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2585
2586 if (tx_flags & IGB_TX_FLAGS_TSO) {
2587 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2588
2589 /* insert tcp checksum */
2590 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2591
2592 /* insert ip checksum */
2593 if (tx_flags & IGB_TX_FLAGS_IPV4)
2594 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2595
2596 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2597 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2598 }
2599
2600 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2601 IGB_TX_FLAGS_VLAN))
2602 olinfo_status |= tx_ring->eims_value >> 4;
2603
2604 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2605
2606 i = tx_ring->next_to_use;
2607 while (count--) {
2608 buffer_info = &tx_ring->buffer_info[i];
2609 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2610 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2611 tx_desc->read.cmd_type_len =
2612 cpu_to_le32(cmd_type_len | buffer_info->length);
2613 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2614 i++;
2615 if (i == tx_ring->count)
2616 i = 0;
2617 }
2618
2619 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2620 /* Force memory writes to complete before letting h/w
2621 * know there are new descriptors to fetch. (Only
2622 * applicable for weak-ordered memory model archs,
2623 * such as IA-64). */
2624 wmb();
2625
2626 tx_ring->next_to_use = i;
2627 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2628 /* we need this if more than one processor can write to our tail
2629 * at a time, it syncronizes IO on IA64/Altix systems */
2630 mmiowb();
2631 }
2632
2633 static int __igb_maybe_stop_tx(struct net_device *netdev,
2634 struct igb_ring *tx_ring, int size)
2635 {
2636 struct igb_adapter *adapter = netdev_priv(netdev);
2637
2638 netif_stop_queue(netdev);
2639 /* Herbert's original patch had:
2640 * smp_mb__after_netif_stop_queue();
2641 * but since that doesn't exist yet, just open code it. */
2642 smp_mb();
2643
2644 /* We need to check again in a case another CPU has just
2645 * made room available. */
2646 if (IGB_DESC_UNUSED(tx_ring) < size)
2647 return -EBUSY;
2648
2649 /* A reprieve! */
2650 netif_start_queue(netdev);
2651 ++adapter->restart_queue;
2652 return 0;
2653 }
2654
2655 static int igb_maybe_stop_tx(struct net_device *netdev,
2656 struct igb_ring *tx_ring, int size)
2657 {
2658 if (IGB_DESC_UNUSED(tx_ring) >= size)
2659 return 0;
2660 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2661 }
2662
2663 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2664
2665 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2666 struct net_device *netdev,
2667 struct igb_ring *tx_ring)
2668 {
2669 struct igb_adapter *adapter = netdev_priv(netdev);
2670 unsigned int tx_flags = 0;
2671 unsigned int len;
2672 unsigned long irq_flags;
2673 u8 hdr_len = 0;
2674 int tso = 0;
2675
2676 len = skb_headlen(skb);
2677
2678 if (test_bit(__IGB_DOWN, &adapter->state)) {
2679 dev_kfree_skb_any(skb);
2680 return NETDEV_TX_OK;
2681 }
2682
2683 if (skb->len <= 0) {
2684 dev_kfree_skb_any(skb);
2685 return NETDEV_TX_OK;
2686 }
2687
2688 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2689 /* Collision - tell upper layer to requeue */
2690 return NETDEV_TX_LOCKED;
2691
2692 /* need: 1 descriptor per page,
2693 * + 2 desc gap to keep tail from touching head,
2694 * + 1 desc for skb->data,
2695 * + 1 desc for context descriptor,
2696 * otherwise try next time */
2697 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2698 /* this is a hard error */
2699 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2700 return NETDEV_TX_BUSY;
2701 }
2702
2703 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2704 tx_flags |= IGB_TX_FLAGS_VLAN;
2705 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2706 }
2707
2708 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2709 &hdr_len) : 0;
2710
2711 if (tso < 0) {
2712 dev_kfree_skb_any(skb);
2713 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2714 return NETDEV_TX_OK;
2715 }
2716
2717 if (tso)
2718 tx_flags |= IGB_TX_FLAGS_TSO;
2719 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2720 if (skb->ip_summed == CHECKSUM_PARTIAL)
2721 tx_flags |= IGB_TX_FLAGS_CSUM;
2722
2723 if (skb->protocol == htons(ETH_P_IP))
2724 tx_flags |= IGB_TX_FLAGS_IPV4;
2725
2726 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2727 igb_tx_map_adv(adapter, tx_ring, skb),
2728 skb->len, hdr_len);
2729
2730 netdev->trans_start = jiffies;
2731
2732 /* Make sure there is space in the ring for the next send. */
2733 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2734
2735 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2736 return NETDEV_TX_OK;
2737 }
2738
2739 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2740 {
2741 struct igb_adapter *adapter = netdev_priv(netdev);
2742 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2743
2744 /* This goes back to the question of how to logically map a tx queue
2745 * to a flow. Right now, performance is impacted slightly negatively
2746 * if using multiple tx queues. If the stack breaks away from a
2747 * single qdisc implementation, we can look at this again. */
2748 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2749 }
2750
2751 /**
2752 * igb_tx_timeout - Respond to a Tx Hang
2753 * @netdev: network interface device structure
2754 **/
2755 static void igb_tx_timeout(struct net_device *netdev)
2756 {
2757 struct igb_adapter *adapter = netdev_priv(netdev);
2758 struct e1000_hw *hw = &adapter->hw;
2759
2760 /* Do the reset outside of interrupt context */
2761 adapter->tx_timeout_count++;
2762 schedule_work(&adapter->reset_task);
2763 wr32(E1000_EICS, adapter->eims_enable_mask &
2764 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2765 }
2766
2767 static void igb_reset_task(struct work_struct *work)
2768 {
2769 struct igb_adapter *adapter;
2770 adapter = container_of(work, struct igb_adapter, reset_task);
2771
2772 igb_reinit_locked(adapter);
2773 }
2774
2775 /**
2776 * igb_get_stats - Get System Network Statistics
2777 * @netdev: network interface device structure
2778 *
2779 * Returns the address of the device statistics structure.
2780 * The statistics are actually updated from the timer callback.
2781 **/
2782 static struct net_device_stats *
2783 igb_get_stats(struct net_device *netdev)
2784 {
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786
2787 /* only return the current stats */
2788 return &adapter->net_stats;
2789 }
2790
2791 /**
2792 * igb_change_mtu - Change the Maximum Transfer Unit
2793 * @netdev: network interface device structure
2794 * @new_mtu: new value for maximum frame size
2795 *
2796 * Returns 0 on success, negative on failure
2797 **/
2798 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2799 {
2800 struct igb_adapter *adapter = netdev_priv(netdev);
2801 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2802
2803 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2804 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2805 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2806 return -EINVAL;
2807 }
2808
2809 #define MAX_STD_JUMBO_FRAME_SIZE 9234
2810 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2811 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2812 return -EINVAL;
2813 }
2814
2815 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2816 msleep(1);
2817 /* igb_down has a dependency on max_frame_size */
2818 adapter->max_frame_size = max_frame;
2819 if (netif_running(netdev))
2820 igb_down(adapter);
2821
2822 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2823 * means we reserve 2 more, this pushes us to allocate from the next
2824 * larger slab size.
2825 * i.e. RXBUFFER_2048 --> size-4096 slab
2826 */
2827
2828 if (max_frame <= IGB_RXBUFFER_256)
2829 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2830 else if (max_frame <= IGB_RXBUFFER_512)
2831 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2832 else if (max_frame <= IGB_RXBUFFER_1024)
2833 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2834 else if (max_frame <= IGB_RXBUFFER_2048)
2835 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2836 else
2837 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2838 /* adjust allocation if LPE protects us, and we aren't using SBP */
2839 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2840 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2841 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2842
2843 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2844 netdev->mtu, new_mtu);
2845 netdev->mtu = new_mtu;
2846
2847 if (netif_running(netdev))
2848 igb_up(adapter);
2849 else
2850 igb_reset(adapter);
2851
2852 clear_bit(__IGB_RESETTING, &adapter->state);
2853
2854 return 0;
2855 }
2856
2857 /**
2858 * igb_update_stats - Update the board statistics counters
2859 * @adapter: board private structure
2860 **/
2861
2862 void igb_update_stats(struct igb_adapter *adapter)
2863 {
2864 struct e1000_hw *hw = &adapter->hw;
2865 struct pci_dev *pdev = adapter->pdev;
2866 u16 phy_tmp;
2867
2868 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2869
2870 /*
2871 * Prevent stats update while adapter is being reset, or if the pci
2872 * connection is down.
2873 */
2874 if (adapter->link_speed == 0)
2875 return;
2876 if (pci_channel_offline(pdev))
2877 return;
2878
2879 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2880 adapter->stats.gprc += rd32(E1000_GPRC);
2881 adapter->stats.gorc += rd32(E1000_GORCL);
2882 rd32(E1000_GORCH); /* clear GORCL */
2883 adapter->stats.bprc += rd32(E1000_BPRC);
2884 adapter->stats.mprc += rd32(E1000_MPRC);
2885 adapter->stats.roc += rd32(E1000_ROC);
2886
2887 adapter->stats.prc64 += rd32(E1000_PRC64);
2888 adapter->stats.prc127 += rd32(E1000_PRC127);
2889 adapter->stats.prc255 += rd32(E1000_PRC255);
2890 adapter->stats.prc511 += rd32(E1000_PRC511);
2891 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2892 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2893 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2894 adapter->stats.sec += rd32(E1000_SEC);
2895
2896 adapter->stats.mpc += rd32(E1000_MPC);
2897 adapter->stats.scc += rd32(E1000_SCC);
2898 adapter->stats.ecol += rd32(E1000_ECOL);
2899 adapter->stats.mcc += rd32(E1000_MCC);
2900 adapter->stats.latecol += rd32(E1000_LATECOL);
2901 adapter->stats.dc += rd32(E1000_DC);
2902 adapter->stats.rlec += rd32(E1000_RLEC);
2903 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2904 adapter->stats.xontxc += rd32(E1000_XONTXC);
2905 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2906 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2907 adapter->stats.fcruc += rd32(E1000_FCRUC);
2908 adapter->stats.gptc += rd32(E1000_GPTC);
2909 adapter->stats.gotc += rd32(E1000_GOTCL);
2910 rd32(E1000_GOTCH); /* clear GOTCL */
2911 adapter->stats.rnbc += rd32(E1000_RNBC);
2912 adapter->stats.ruc += rd32(E1000_RUC);
2913 adapter->stats.rfc += rd32(E1000_RFC);
2914 adapter->stats.rjc += rd32(E1000_RJC);
2915 adapter->stats.tor += rd32(E1000_TORH);
2916 adapter->stats.tot += rd32(E1000_TOTH);
2917 adapter->stats.tpr += rd32(E1000_TPR);
2918
2919 adapter->stats.ptc64 += rd32(E1000_PTC64);
2920 adapter->stats.ptc127 += rd32(E1000_PTC127);
2921 adapter->stats.ptc255 += rd32(E1000_PTC255);
2922 adapter->stats.ptc511 += rd32(E1000_PTC511);
2923 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2924 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2925
2926 adapter->stats.mptc += rd32(E1000_MPTC);
2927 adapter->stats.bptc += rd32(E1000_BPTC);
2928
2929 /* used for adaptive IFS */
2930
2931 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2932 adapter->stats.tpt += hw->mac.tx_packet_delta;
2933 hw->mac.collision_delta = rd32(E1000_COLC);
2934 adapter->stats.colc += hw->mac.collision_delta;
2935
2936 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2937 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2938 adapter->stats.tncrs += rd32(E1000_TNCRS);
2939 adapter->stats.tsctc += rd32(E1000_TSCTC);
2940 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2941
2942 adapter->stats.iac += rd32(E1000_IAC);
2943 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2944 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2945 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2946 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2947 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2948 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2949 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2950 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2951
2952 /* Fill out the OS statistics structure */
2953 adapter->net_stats.multicast = adapter->stats.mprc;
2954 adapter->net_stats.collisions = adapter->stats.colc;
2955
2956 /* Rx Errors */
2957
2958 /* RLEC on some newer hardware can be incorrect so build
2959 * our own version based on RUC and ROC */
2960 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2961 adapter->stats.crcerrs + adapter->stats.algnerrc +
2962 adapter->stats.ruc + adapter->stats.roc +
2963 adapter->stats.cexterr;
2964 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
2965 adapter->stats.roc;
2966 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2967 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2968 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2969
2970 /* Tx Errors */
2971 adapter->net_stats.tx_errors = adapter->stats.ecol +
2972 adapter->stats.latecol;
2973 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
2974 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
2975 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
2976
2977 /* Tx Dropped needs to be maintained elsewhere */
2978
2979 /* Phy Stats */
2980 if (hw->phy.media_type == e1000_media_type_copper) {
2981 if ((adapter->link_speed == SPEED_1000) &&
2982 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
2983 &phy_tmp))) {
2984 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
2985 adapter->phy_stats.idle_errors += phy_tmp;
2986 }
2987 }
2988
2989 /* Management Stats */
2990 adapter->stats.mgptc += rd32(E1000_MGTPTC);
2991 adapter->stats.mgprc += rd32(E1000_MGTPRC);
2992 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
2993 }
2994
2995
2996 static irqreturn_t igb_msix_other(int irq, void *data)
2997 {
2998 struct net_device *netdev = data;
2999 struct igb_adapter *adapter = netdev_priv(netdev);
3000 struct e1000_hw *hw = &adapter->hw;
3001 u32 eicr;
3002 /* disable interrupts from the "other" bit, avoid re-entry */
3003 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3004
3005 eicr = rd32(E1000_EICR);
3006
3007 if (eicr & E1000_EIMS_OTHER) {
3008 u32 icr = rd32(E1000_ICR);
3009 /* reading ICR causes bit 31 of EICR to be cleared */
3010 if (!(icr & E1000_ICR_LSC))
3011 goto no_link_interrupt;
3012 hw->mac.get_link_status = 1;
3013 /* guard against interrupt when we're going down */
3014 if (!test_bit(__IGB_DOWN, &adapter->state))
3015 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3016 }
3017
3018 no_link_interrupt:
3019 wr32(E1000_IMS, E1000_IMS_LSC);
3020 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3021
3022 return IRQ_HANDLED;
3023 }
3024
3025 static irqreturn_t igb_msix_tx(int irq, void *data)
3026 {
3027 struct igb_ring *tx_ring = data;
3028 struct igb_adapter *adapter = tx_ring->adapter;
3029 struct e1000_hw *hw = &adapter->hw;
3030
3031 if (!tx_ring->itr_val)
3032 wr32(E1000_EIMC, tx_ring->eims_value);
3033
3034 tx_ring->total_bytes = 0;
3035 tx_ring->total_packets = 0;
3036 if (!igb_clean_tx_irq(adapter, tx_ring))
3037 /* Ring was not completely cleaned, so fire another interrupt */
3038 wr32(E1000_EICS, tx_ring->eims_value);
3039
3040 if (!tx_ring->itr_val)
3041 wr32(E1000_EIMS, tx_ring->eims_value);
3042 return IRQ_HANDLED;
3043 }
3044
3045 static irqreturn_t igb_msix_rx(int irq, void *data)
3046 {
3047 struct igb_ring *rx_ring = data;
3048 struct igb_adapter *adapter = rx_ring->adapter;
3049 struct e1000_hw *hw = &adapter->hw;
3050
3051 if (!rx_ring->itr_val)
3052 wr32(E1000_EIMC, rx_ring->eims_value);
3053
3054 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3055 rx_ring->total_bytes = 0;
3056 rx_ring->total_packets = 0;
3057 rx_ring->no_itr_adjust = 0;
3058 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3059 } else {
3060 if (!rx_ring->no_itr_adjust) {
3061 igb_lower_rx_eitr(adapter, rx_ring);
3062 rx_ring->no_itr_adjust = 1;
3063 }
3064 }
3065
3066 return IRQ_HANDLED;
3067 }
3068
3069
3070 /**
3071 * igb_intr_msi - Interrupt Handler
3072 * @irq: interrupt number
3073 * @data: pointer to a network interface device structure
3074 **/
3075 static irqreturn_t igb_intr_msi(int irq, void *data)
3076 {
3077 struct net_device *netdev = data;
3078 struct igb_adapter *adapter = netdev_priv(netdev);
3079 struct napi_struct *napi = &adapter->napi;
3080 struct e1000_hw *hw = &adapter->hw;
3081 /* read ICR disables interrupts using IAM */
3082 u32 icr = rd32(E1000_ICR);
3083
3084 /* Write the ITR value calculated at the end of the
3085 * previous interrupt.
3086 */
3087 if (adapter->set_itr) {
3088 wr32(E1000_ITR,
3089 1000000000 / (adapter->itr * 256));
3090 adapter->set_itr = 0;
3091 }
3092
3093 /* read ICR disables interrupts using IAM */
3094 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3095 hw->mac.get_link_status = 1;
3096 if (!test_bit(__IGB_DOWN, &adapter->state))
3097 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3098 }
3099
3100 if (netif_rx_schedule_prep(netdev, napi)) {
3101 adapter->tx_ring->total_bytes = 0;
3102 adapter->tx_ring->total_packets = 0;
3103 adapter->rx_ring->total_bytes = 0;
3104 adapter->rx_ring->total_packets = 0;
3105 __netif_rx_schedule(netdev, napi);
3106 }
3107
3108 return IRQ_HANDLED;
3109 }
3110
3111 /**
3112 * igb_intr - Interrupt Handler
3113 * @irq: interrupt number
3114 * @data: pointer to a network interface device structure
3115 **/
3116 static irqreturn_t igb_intr(int irq, void *data)
3117 {
3118 struct net_device *netdev = data;
3119 struct igb_adapter *adapter = netdev_priv(netdev);
3120 struct napi_struct *napi = &adapter->napi;
3121 struct e1000_hw *hw = &adapter->hw;
3122 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3123 * need for the IMC write */
3124 u32 icr = rd32(E1000_ICR);
3125 u32 eicr = 0;
3126 if (!icr)
3127 return IRQ_NONE; /* Not our interrupt */
3128
3129 /* Write the ITR value calculated at the end of the
3130 * previous interrupt.
3131 */
3132 if (adapter->set_itr) {
3133 wr32(E1000_ITR,
3134 1000000000 / (adapter->itr * 256));
3135 adapter->set_itr = 0;
3136 }
3137
3138 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3139 * not set, then the adapter didn't send an interrupt */
3140 if (!(icr & E1000_ICR_INT_ASSERTED))
3141 return IRQ_NONE;
3142
3143 eicr = rd32(E1000_EICR);
3144
3145 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3146 hw->mac.get_link_status = 1;
3147 /* guard against interrupt when we're going down */
3148 if (!test_bit(__IGB_DOWN, &adapter->state))
3149 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3150 }
3151
3152 if (netif_rx_schedule_prep(netdev, napi)) {
3153 adapter->tx_ring->total_bytes = 0;
3154 adapter->rx_ring->total_bytes = 0;
3155 adapter->tx_ring->total_packets = 0;
3156 adapter->rx_ring->total_packets = 0;
3157 __netif_rx_schedule(netdev, napi);
3158 }
3159
3160 return IRQ_HANDLED;
3161 }
3162
3163 /**
3164 * igb_clean - NAPI Rx polling callback
3165 * @adapter: board private structure
3166 **/
3167 static int igb_clean(struct napi_struct *napi, int budget)
3168 {
3169 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3170 napi);
3171 struct net_device *netdev = adapter->netdev;
3172 int tx_clean_complete = 1, work_done = 0;
3173 int i;
3174
3175 /* Must NOT use netdev_priv macro here. */
3176 adapter = netdev->priv;
3177
3178 /* Keep link state information with original netdev */
3179 if (!netif_carrier_ok(netdev))
3180 goto quit_polling;
3181
3182 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3183 * being cleaned by multiple cpus simultaneously. A failure obtaining
3184 * the lock means tx_ring[i] is currently being cleaned anyway. */
3185 for (i = 0; i < adapter->num_tx_queues; i++) {
3186 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3187 tx_clean_complete &= igb_clean_tx_irq(adapter,
3188 &adapter->tx_ring[i]);
3189 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3190 }
3191 }
3192
3193 for (i = 0; i < adapter->num_rx_queues; i++)
3194 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done,
3195 adapter->rx_ring[i].napi.weight);
3196
3197 /* If no Tx and not enough Rx work done, exit the polling mode */
3198 if ((tx_clean_complete && (work_done < budget)) ||
3199 !netif_running(netdev)) {
3200 quit_polling:
3201 if (adapter->itr_setting & 3)
3202 igb_set_itr(adapter, E1000_ITR, false);
3203 netif_rx_complete(netdev, napi);
3204 if (!test_bit(__IGB_DOWN, &adapter->state))
3205 igb_irq_enable(adapter);
3206 return 0;
3207 }
3208
3209 return 1;
3210 }
3211
3212 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3213 {
3214 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3215 struct igb_adapter *adapter = rx_ring->adapter;
3216 struct e1000_hw *hw = &adapter->hw;
3217 struct net_device *netdev = adapter->netdev;
3218 int work_done = 0;
3219
3220 /* Keep link state information with original netdev */
3221 if (!netif_carrier_ok(netdev))
3222 goto quit_polling;
3223
3224 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget);
3225
3226
3227 /* If not enough Rx work done, exit the polling mode */
3228 if ((work_done == 0) || !netif_running(netdev)) {
3229 quit_polling:
3230 netif_rx_complete(netdev, napi);
3231
3232 wr32(E1000_EIMS, rx_ring->eims_value);
3233 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3234 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3235 int mean_size = rx_ring->total_bytes /
3236 rx_ring->total_packets;
3237 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3238 igb_raise_rx_eitr(adapter, rx_ring);
3239 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3240 igb_lower_rx_eitr(adapter, rx_ring);
3241 }
3242 return 0;
3243 }
3244
3245 return 1;
3246 }
3247 /**
3248 * igb_clean_tx_irq - Reclaim resources after transmit completes
3249 * @adapter: board private structure
3250 * returns true if ring is completely cleaned
3251 **/
3252 static bool igb_clean_tx_irq(struct igb_adapter *adapter,
3253 struct igb_ring *tx_ring)
3254 {
3255 struct net_device *netdev = adapter->netdev;
3256 struct e1000_hw *hw = &adapter->hw;
3257 struct e1000_tx_desc *tx_desc;
3258 struct igb_buffer *buffer_info;
3259 struct sk_buff *skb;
3260 unsigned int i;
3261 u32 head, oldhead;
3262 unsigned int count = 0;
3263 bool cleaned = false;
3264 bool retval = true;
3265 unsigned int total_bytes = 0, total_packets = 0;
3266
3267 rmb();
3268 head = *(volatile u32 *)((struct e1000_tx_desc *)tx_ring->desc
3269 + tx_ring->count);
3270 head = le32_to_cpu(head);
3271 i = tx_ring->next_to_clean;
3272 while (1) {
3273 while (i != head) {
3274 cleaned = true;
3275 tx_desc = E1000_TX_DESC(*tx_ring, i);
3276 buffer_info = &tx_ring->buffer_info[i];
3277 skb = buffer_info->skb;
3278
3279 if (skb) {
3280 unsigned int segs, bytecount;
3281 /* gso_segs is currently only valid for tcp */
3282 segs = skb_shinfo(skb)->gso_segs ?: 1;
3283 /* multiply data chunks by size of headers */
3284 bytecount = ((segs - 1) * skb_headlen(skb)) +
3285 skb->len;
3286 total_packets += segs;
3287 total_bytes += bytecount;
3288 }
3289
3290 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3291 tx_desc->upper.data = 0;
3292
3293 i++;
3294 if (i == tx_ring->count)
3295 i = 0;
3296
3297 count++;
3298 if (count == IGB_MAX_TX_CLEAN) {
3299 retval = false;
3300 goto done_cleaning;
3301 }
3302 }
3303 oldhead = head;
3304 rmb();
3305 head = *(volatile u32 *)((struct e1000_tx_desc *)tx_ring->desc
3306 + tx_ring->count);
3307 head = le32_to_cpu(head);
3308 if (head == oldhead)
3309 goto done_cleaning;
3310 } /* while (1) */
3311
3312 done_cleaning:
3313 tx_ring->next_to_clean = i;
3314
3315 if (unlikely(cleaned &&
3316 netif_carrier_ok(netdev) &&
3317 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3318 /* Make sure that anybody stopping the queue after this
3319 * sees the new next_to_clean.
3320 */
3321 smp_mb();
3322 if (netif_queue_stopped(netdev) &&
3323 !(test_bit(__IGB_DOWN, &adapter->state))) {
3324 netif_wake_queue(netdev);
3325 ++adapter->restart_queue;
3326 }
3327 }
3328
3329 if (tx_ring->detect_tx_hung) {
3330 /* Detect a transmit hang in hardware, this serializes the
3331 * check with the clearing of time_stamp and movement of i */
3332 tx_ring->detect_tx_hung = false;
3333 if (tx_ring->buffer_info[i].time_stamp &&
3334 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3335 (adapter->tx_timeout_factor * HZ))
3336 && !(rd32(E1000_STATUS) &
3337 E1000_STATUS_TXOFF)) {
3338
3339 tx_desc = E1000_TX_DESC(*tx_ring, i);
3340 /* detected Tx unit hang */
3341 dev_err(&adapter->pdev->dev,
3342 "Detected Tx Unit Hang\n"
3343 " Tx Queue <%lu>\n"
3344 " TDH <%x>\n"
3345 " TDT <%x>\n"
3346 " next_to_use <%x>\n"
3347 " next_to_clean <%x>\n"
3348 " head (WB) <%x>\n"
3349 "buffer_info[next_to_clean]\n"
3350 " time_stamp <%lx>\n"
3351 " jiffies <%lx>\n"
3352 " desc.status <%x>\n",
3353 (unsigned long)((tx_ring - adapter->tx_ring) /
3354 sizeof(struct igb_ring)),
3355 readl(adapter->hw.hw_addr + tx_ring->head),
3356 readl(adapter->hw.hw_addr + tx_ring->tail),
3357 tx_ring->next_to_use,
3358 tx_ring->next_to_clean,
3359 head,
3360 tx_ring->buffer_info[i].time_stamp,
3361 jiffies,
3362 tx_desc->upper.fields.status);
3363 netif_stop_queue(netdev);
3364 }
3365 }
3366 tx_ring->total_bytes += total_bytes;
3367 tx_ring->total_packets += total_packets;
3368 adapter->net_stats.tx_bytes += total_bytes;
3369 adapter->net_stats.tx_packets += total_packets;
3370 return retval;
3371 }
3372
3373
3374 /**
3375 * igb_receive_skb - helper function to handle rx indications
3376 * @adapter: board private structure
3377 * @status: descriptor status field as written by hardware
3378 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3379 * @skb: pointer to sk_buff to be indicated to stack
3380 **/
3381 static void igb_receive_skb(struct igb_adapter *adapter, u8 status, u16 vlan,
3382 struct sk_buff *skb)
3383 {
3384 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3385 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3386 le16_to_cpu(vlan) &
3387 E1000_RXD_SPC_VLAN_MASK);
3388 else
3389 netif_receive_skb(skb);
3390 }
3391
3392
3393 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3394 u32 status_err, struct sk_buff *skb)
3395 {
3396 skb->ip_summed = CHECKSUM_NONE;
3397
3398 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3399 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3400 return;
3401 /* TCP/UDP checksum error bit is set */
3402 if (status_err &
3403 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3404 /* let the stack verify checksum errors */
3405 adapter->hw_csum_err++;
3406 return;
3407 }
3408 /* It must be a TCP or UDP packet with a valid checksum */
3409 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3410 skb->ip_summed = CHECKSUM_UNNECESSARY;
3411
3412 adapter->hw_csum_good++;
3413 }
3414
3415 static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3416 struct igb_ring *rx_ring,
3417 int *work_done, int budget)
3418 {
3419 struct net_device *netdev = adapter->netdev;
3420 struct pci_dev *pdev = adapter->pdev;
3421 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3422 struct igb_buffer *buffer_info , *next_buffer;
3423 struct sk_buff *skb;
3424 unsigned int i, j;
3425 u32 length, hlen, staterr;
3426 bool cleaned = false;
3427 int cleaned_count = 0;
3428 unsigned int total_bytes = 0, total_packets = 0;
3429
3430 i = rx_ring->next_to_clean;
3431 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3432 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3433
3434 while (staterr & E1000_RXD_STAT_DD) {
3435 if (*work_done >= budget)
3436 break;
3437 (*work_done)++;
3438 buffer_info = &rx_ring->buffer_info[i];
3439
3440 /* HW will not DMA in data larger than the given buffer, even
3441 * if it parses the (NFS, of course) header to be larger. In
3442 * that case, it fills the header buffer and spills the rest
3443 * into the page.
3444 */
3445 hlen = le16_to_cpu((rx_desc->wb.lower.lo_dword.hdr_info &
3446 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT);
3447 if (hlen > adapter->rx_ps_hdr_size)
3448 hlen = adapter->rx_ps_hdr_size;
3449
3450 length = le16_to_cpu(rx_desc->wb.upper.length);
3451 cleaned = true;
3452 cleaned_count++;
3453
3454 if (rx_ring->pending_skb != NULL) {
3455 skb = rx_ring->pending_skb;
3456 rx_ring->pending_skb = NULL;
3457 j = rx_ring->pending_skb_page;
3458 } else {
3459 skb = buffer_info->skb;
3460 prefetch(skb->data - NET_IP_ALIGN);
3461 buffer_info->skb = NULL;
3462 if (hlen) {
3463 pci_unmap_single(pdev, buffer_info->dma,
3464 adapter->rx_ps_hdr_size +
3465 NET_IP_ALIGN,
3466 PCI_DMA_FROMDEVICE);
3467 skb_put(skb, hlen);
3468 } else {
3469 pci_unmap_single(pdev, buffer_info->dma,
3470 adapter->rx_buffer_len +
3471 NET_IP_ALIGN,
3472 PCI_DMA_FROMDEVICE);
3473 skb_put(skb, length);
3474 goto send_up;
3475 }
3476 j = 0;
3477 }
3478
3479 while (length) {
3480 pci_unmap_page(pdev, buffer_info->page_dma,
3481 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3482 buffer_info->page_dma = 0;
3483 skb_fill_page_desc(skb, j, buffer_info->page,
3484 0, length);
3485 buffer_info->page = NULL;
3486
3487 skb->len += length;
3488 skb->data_len += length;
3489 skb->truesize += length;
3490 rx_desc->wb.upper.status_error = 0;
3491 if (staterr & E1000_RXD_STAT_EOP)
3492 break;
3493
3494 j++;
3495 cleaned_count++;
3496 i++;
3497 if (i == rx_ring->count)
3498 i = 0;
3499
3500 buffer_info = &rx_ring->buffer_info[i];
3501 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3502 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3503 length = le16_to_cpu(rx_desc->wb.upper.length);
3504 if (!(staterr & E1000_RXD_STAT_DD)) {
3505 rx_ring->pending_skb = skb;
3506 rx_ring->pending_skb_page = j;
3507 goto out;
3508 }
3509 }
3510 send_up:
3511 pskb_trim(skb, skb->len - 4);
3512 i++;
3513 if (i == rx_ring->count)
3514 i = 0;
3515 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3516 prefetch(next_rxd);
3517 next_buffer = &rx_ring->buffer_info[i];
3518
3519 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3520 dev_kfree_skb_irq(skb);
3521 goto next_desc;
3522 }
3523 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3524
3525 total_bytes += skb->len;
3526 total_packets++;
3527
3528 igb_rx_checksum_adv(adapter, staterr, skb);
3529
3530 skb->protocol = eth_type_trans(skb, netdev);
3531
3532 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3533
3534 netdev->last_rx = jiffies;
3535
3536 next_desc:
3537 rx_desc->wb.upper.status_error = 0;
3538
3539 /* return some buffers to hardware, one at a time is too slow */
3540 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3541 igb_alloc_rx_buffers_adv(adapter, rx_ring,
3542 cleaned_count);
3543 cleaned_count = 0;
3544 }
3545
3546 /* use prefetched values */
3547 rx_desc = next_rxd;
3548 buffer_info = next_buffer;
3549
3550 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3551 }
3552 out:
3553 rx_ring->next_to_clean = i;
3554 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3555
3556 if (cleaned_count)
3557 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count);
3558
3559 rx_ring->total_packets += total_packets;
3560 rx_ring->total_bytes += total_bytes;
3561 rx_ring->rx_stats.packets += total_packets;
3562 rx_ring->rx_stats.bytes += total_bytes;
3563 adapter->net_stats.rx_bytes += total_bytes;
3564 adapter->net_stats.rx_packets += total_packets;
3565 return cleaned;
3566 }
3567
3568
3569 /**
3570 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3571 * @adapter: address of board private structure
3572 **/
3573 static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3574 struct igb_ring *rx_ring,
3575 int cleaned_count)
3576 {
3577 struct net_device *netdev = adapter->netdev;
3578 struct pci_dev *pdev = adapter->pdev;
3579 union e1000_adv_rx_desc *rx_desc;
3580 struct igb_buffer *buffer_info;
3581 struct sk_buff *skb;
3582 unsigned int i;
3583
3584 i = rx_ring->next_to_use;
3585 buffer_info = &rx_ring->buffer_info[i];
3586
3587 while (cleaned_count--) {
3588 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3589
3590 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3591 buffer_info->page = alloc_page(GFP_ATOMIC);
3592 if (!buffer_info->page) {
3593 adapter->alloc_rx_buff_failed++;
3594 goto no_buffers;
3595 }
3596 buffer_info->page_dma =
3597 pci_map_page(pdev,
3598 buffer_info->page,
3599 0, PAGE_SIZE,
3600 PCI_DMA_FROMDEVICE);
3601 }
3602
3603 if (!buffer_info->skb) {
3604 int bufsz;
3605
3606 if (adapter->rx_ps_hdr_size)
3607 bufsz = adapter->rx_ps_hdr_size;
3608 else
3609 bufsz = adapter->rx_buffer_len;
3610 bufsz += NET_IP_ALIGN;
3611 skb = netdev_alloc_skb(netdev, bufsz);
3612
3613 if (!skb) {
3614 adapter->alloc_rx_buff_failed++;
3615 goto no_buffers;
3616 }
3617
3618 /* Make buffer alignment 2 beyond a 16 byte boundary
3619 * this will result in a 16 byte aligned IP header after
3620 * the 14 byte MAC header is removed
3621 */
3622 skb_reserve(skb, NET_IP_ALIGN);
3623
3624 buffer_info->skb = skb;
3625 buffer_info->dma = pci_map_single(pdev, skb->data,
3626 bufsz,
3627 PCI_DMA_FROMDEVICE);
3628
3629 }
3630 /* Refresh the desc even if buffer_addrs didn't change because
3631 * each write-back erases this info. */
3632 if (adapter->rx_ps_hdr_size) {
3633 rx_desc->read.pkt_addr =
3634 cpu_to_le64(buffer_info->page_dma);
3635 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3636 } else {
3637 rx_desc->read.pkt_addr =
3638 cpu_to_le64(buffer_info->dma);
3639 rx_desc->read.hdr_addr = 0;
3640 }
3641
3642 i++;
3643 if (i == rx_ring->count)
3644 i = 0;
3645 buffer_info = &rx_ring->buffer_info[i];
3646 }
3647
3648 no_buffers:
3649 if (rx_ring->next_to_use != i) {
3650 rx_ring->next_to_use = i;
3651 if (i == 0)
3652 i = (rx_ring->count - 1);
3653 else
3654 i--;
3655
3656 /* Force memory writes to complete before letting h/w
3657 * know there are new descriptors to fetch. (Only
3658 * applicable for weak-ordered memory model archs,
3659 * such as IA-64). */
3660 wmb();
3661 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3662 }
3663 }
3664
3665 /**
3666 * igb_mii_ioctl -
3667 * @netdev:
3668 * @ifreq:
3669 * @cmd:
3670 **/
3671 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3672 {
3673 struct igb_adapter *adapter = netdev_priv(netdev);
3674 struct mii_ioctl_data *data = if_mii(ifr);
3675
3676 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3677 return -EOPNOTSUPP;
3678
3679 switch (cmd) {
3680 case SIOCGMIIPHY:
3681 data->phy_id = adapter->hw.phy.addr;
3682 break;
3683 case SIOCGMIIREG:
3684 if (!capable(CAP_NET_ADMIN))
3685 return -EPERM;
3686 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3687 data->reg_num
3688 & 0x1F, &data->val_out))
3689 return -EIO;
3690 break;
3691 case SIOCSMIIREG:
3692 default:
3693 return -EOPNOTSUPP;
3694 }
3695 return 0;
3696 }
3697
3698 /**
3699 * igb_ioctl -
3700 * @netdev:
3701 * @ifreq:
3702 * @cmd:
3703 **/
3704 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3705 {
3706 switch (cmd) {
3707 case SIOCGMIIPHY:
3708 case SIOCGMIIREG:
3709 case SIOCSMIIREG:
3710 return igb_mii_ioctl(netdev, ifr, cmd);
3711 default:
3712 return -EOPNOTSUPP;
3713 }
3714 }
3715
3716 static void igb_vlan_rx_register(struct net_device *netdev,
3717 struct vlan_group *grp)
3718 {
3719 struct igb_adapter *adapter = netdev_priv(netdev);
3720 struct e1000_hw *hw = &adapter->hw;
3721 u32 ctrl, rctl;
3722
3723 igb_irq_disable(adapter);
3724 adapter->vlgrp = grp;
3725
3726 if (grp) {
3727 /* enable VLAN tag insert/strip */
3728 ctrl = rd32(E1000_CTRL);
3729 ctrl |= E1000_CTRL_VME;
3730 wr32(E1000_CTRL, ctrl);
3731
3732 /* enable VLAN receive filtering */
3733 rctl = rd32(E1000_RCTL);
3734 rctl |= E1000_RCTL_VFE;
3735 rctl &= ~E1000_RCTL_CFIEN;
3736 wr32(E1000_RCTL, rctl);
3737 igb_update_mng_vlan(adapter);
3738 wr32(E1000_RLPML,
3739 adapter->max_frame_size + VLAN_TAG_SIZE);
3740 } else {
3741 /* disable VLAN tag insert/strip */
3742 ctrl = rd32(E1000_CTRL);
3743 ctrl &= ~E1000_CTRL_VME;
3744 wr32(E1000_CTRL, ctrl);
3745
3746 /* disable VLAN filtering */
3747 rctl = rd32(E1000_RCTL);
3748 rctl &= ~E1000_RCTL_VFE;
3749 wr32(E1000_RCTL, rctl);
3750 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3751 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3752 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3753 }
3754 wr32(E1000_RLPML,
3755 adapter->max_frame_size);
3756 }
3757
3758 if (!test_bit(__IGB_DOWN, &adapter->state))
3759 igb_irq_enable(adapter);
3760 }
3761
3762 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3763 {
3764 struct igb_adapter *adapter = netdev_priv(netdev);
3765 struct e1000_hw *hw = &adapter->hw;
3766 u32 vfta, index;
3767
3768 if ((adapter->hw.mng_cookie.status &
3769 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3770 (vid == adapter->mng_vlan_id))
3771 return;
3772 /* add VID to filter table */
3773 index = (vid >> 5) & 0x7F;
3774 vfta = array_rd32(E1000_VFTA, index);
3775 vfta |= (1 << (vid & 0x1F));
3776 igb_write_vfta(&adapter->hw, index, vfta);
3777 }
3778
3779 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3780 {
3781 struct igb_adapter *adapter = netdev_priv(netdev);
3782 struct e1000_hw *hw = &adapter->hw;
3783 u32 vfta, index;
3784
3785 igb_irq_disable(adapter);
3786 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3787
3788 if (!test_bit(__IGB_DOWN, &adapter->state))
3789 igb_irq_enable(adapter);
3790
3791 if ((adapter->hw.mng_cookie.status &
3792 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3793 (vid == adapter->mng_vlan_id)) {
3794 /* release control to f/w */
3795 igb_release_hw_control(adapter);
3796 return;
3797 }
3798
3799 /* remove VID from filter table */
3800 index = (vid >> 5) & 0x7F;
3801 vfta = array_rd32(E1000_VFTA, index);
3802 vfta &= ~(1 << (vid & 0x1F));
3803 igb_write_vfta(&adapter->hw, index, vfta);
3804 }
3805
3806 static void igb_restore_vlan(struct igb_adapter *adapter)
3807 {
3808 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3809
3810 if (adapter->vlgrp) {
3811 u16 vid;
3812 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3813 if (!vlan_group_get_device(adapter->vlgrp, vid))
3814 continue;
3815 igb_vlan_rx_add_vid(adapter->netdev, vid);
3816 }
3817 }
3818 }
3819
3820 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3821 {
3822 struct e1000_mac_info *mac = &adapter->hw.mac;
3823
3824 mac->autoneg = 0;
3825
3826 /* Fiber NICs only allow 1000 gbps Full duplex */
3827 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3828 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3829 dev_err(&adapter->pdev->dev,
3830 "Unsupported Speed/Duplex configuration\n");
3831 return -EINVAL;
3832 }
3833
3834 switch (spddplx) {
3835 case SPEED_10 + DUPLEX_HALF:
3836 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3837 break;
3838 case SPEED_10 + DUPLEX_FULL:
3839 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3840 break;
3841 case SPEED_100 + DUPLEX_HALF:
3842 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3843 break;
3844 case SPEED_100 + DUPLEX_FULL:
3845 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3846 break;
3847 case SPEED_1000 + DUPLEX_FULL:
3848 mac->autoneg = 1;
3849 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3850 break;
3851 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3852 default:
3853 dev_err(&adapter->pdev->dev,
3854 "Unsupported Speed/Duplex configuration\n");
3855 return -EINVAL;
3856 }
3857 return 0;
3858 }
3859
3860
3861 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3862 {
3863 struct net_device *netdev = pci_get_drvdata(pdev);
3864 struct igb_adapter *adapter = netdev_priv(netdev);
3865 struct e1000_hw *hw = &adapter->hw;
3866 u32 ctrl, ctrl_ext, rctl, status;
3867 u32 wufc = adapter->wol;
3868 #ifdef CONFIG_PM
3869 int retval = 0;
3870 #endif
3871
3872 netif_device_detach(netdev);
3873
3874 if (netif_running(netdev)) {
3875 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3876 igb_down(adapter);
3877 igb_free_irq(adapter);
3878 }
3879
3880 #ifdef CONFIG_PM
3881 retval = pci_save_state(pdev);
3882 if (retval)
3883 return retval;
3884 #endif
3885
3886 status = rd32(E1000_STATUS);
3887 if (status & E1000_STATUS_LU)
3888 wufc &= ~E1000_WUFC_LNKC;
3889
3890 if (wufc) {
3891 igb_setup_rctl(adapter);
3892 igb_set_multi(netdev);
3893
3894 /* turn on all-multi mode if wake on multicast is enabled */
3895 if (wufc & E1000_WUFC_MC) {
3896 rctl = rd32(E1000_RCTL);
3897 rctl |= E1000_RCTL_MPE;
3898 wr32(E1000_RCTL, rctl);
3899 }
3900
3901 ctrl = rd32(E1000_CTRL);
3902 /* advertise wake from D3Cold */
3903 #define E1000_CTRL_ADVD3WUC 0x00100000
3904 /* phy power management enable */
3905 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3906 ctrl |= E1000_CTRL_ADVD3WUC;
3907 wr32(E1000_CTRL, ctrl);
3908
3909 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3910 adapter->hw.phy.media_type ==
3911 e1000_media_type_internal_serdes) {
3912 /* keep the laser running in D3 */
3913 ctrl_ext = rd32(E1000_CTRL_EXT);
3914 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3915 wr32(E1000_CTRL_EXT, ctrl_ext);
3916 }
3917
3918 /* Allow time for pending master requests to run */
3919 igb_disable_pcie_master(&adapter->hw);
3920
3921 wr32(E1000_WUC, E1000_WUC_PME_EN);
3922 wr32(E1000_WUFC, wufc);
3923 pci_enable_wake(pdev, PCI_D3hot, 1);
3924 pci_enable_wake(pdev, PCI_D3cold, 1);
3925 } else {
3926 wr32(E1000_WUC, 0);
3927 wr32(E1000_WUFC, 0);
3928 pci_enable_wake(pdev, PCI_D3hot, 0);
3929 pci_enable_wake(pdev, PCI_D3cold, 0);
3930 }
3931
3932 /* make sure adapter isn't asleep if manageability is enabled */
3933 if (adapter->en_mng_pt) {
3934 pci_enable_wake(pdev, PCI_D3hot, 1);
3935 pci_enable_wake(pdev, PCI_D3cold, 1);
3936 }
3937
3938 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3939 * would have already happened in close and is redundant. */
3940 igb_release_hw_control(adapter);
3941
3942 pci_disable_device(pdev);
3943
3944 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3945
3946 return 0;
3947 }
3948
3949 #ifdef CONFIG_PM
3950 static int igb_resume(struct pci_dev *pdev)
3951 {
3952 struct net_device *netdev = pci_get_drvdata(pdev);
3953 struct igb_adapter *adapter = netdev_priv(netdev);
3954 struct e1000_hw *hw = &adapter->hw;
3955 u32 err;
3956
3957 pci_set_power_state(pdev, PCI_D0);
3958 pci_restore_state(pdev);
3959 err = pci_enable_device(pdev);
3960 if (err) {
3961 dev_err(&pdev->dev,
3962 "igb: Cannot enable PCI device from suspend\n");
3963 return err;
3964 }
3965 pci_set_master(pdev);
3966
3967 pci_enable_wake(pdev, PCI_D3hot, 0);
3968 pci_enable_wake(pdev, PCI_D3cold, 0);
3969
3970 if (netif_running(netdev)) {
3971 err = igb_request_irq(adapter);
3972 if (err)
3973 return err;
3974 }
3975
3976 /* e1000_power_up_phy(adapter); */
3977
3978 igb_reset(adapter);
3979 wr32(E1000_WUS, ~0);
3980
3981 igb_init_manageability(adapter);
3982
3983 if (netif_running(netdev))
3984 igb_up(adapter);
3985
3986 netif_device_attach(netdev);
3987
3988 /* let the f/w know that the h/w is now under the control of the
3989 * driver. */
3990 igb_get_hw_control(adapter);
3991
3992 return 0;
3993 }
3994 #endif
3995
3996 static void igb_shutdown(struct pci_dev *pdev)
3997 {
3998 igb_suspend(pdev, PMSG_SUSPEND);
3999 }
4000
4001 #ifdef CONFIG_NET_POLL_CONTROLLER
4002 /*
4003 * Polling 'interrupt' - used by things like netconsole to send skbs
4004 * without having to re-enable interrupts. It's not called while
4005 * the interrupt routine is executing.
4006 */
4007 static void igb_netpoll(struct net_device *netdev)
4008 {
4009 struct igb_adapter *adapter = netdev_priv(netdev);
4010 int i;
4011 int work_done = 0;
4012
4013 igb_irq_disable(adapter);
4014 for (i = 0; i < adapter->num_tx_queues; i++)
4015 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]);
4016
4017 for (i = 0; i < adapter->num_rx_queues; i++)
4018 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i],
4019 &work_done,
4020 adapter->rx_ring[i].napi.weight);
4021
4022 igb_irq_enable(adapter);
4023 }
4024 #endif /* CONFIG_NET_POLL_CONTROLLER */
4025
4026 /**
4027 * igb_io_error_detected - called when PCI error is detected
4028 * @pdev: Pointer to PCI device
4029 * @state: The current pci connection state
4030 *
4031 * This function is called after a PCI bus error affecting
4032 * this device has been detected.
4033 */
4034 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4035 pci_channel_state_t state)
4036 {
4037 struct net_device *netdev = pci_get_drvdata(pdev);
4038 struct igb_adapter *adapter = netdev_priv(netdev);
4039
4040 netif_device_detach(netdev);
4041
4042 if (netif_running(netdev))
4043 igb_down(adapter);
4044 pci_disable_device(pdev);
4045
4046 /* Request a slot slot reset. */
4047 return PCI_ERS_RESULT_NEED_RESET;
4048 }
4049
4050 /**
4051 * igb_io_slot_reset - called after the pci bus has been reset.
4052 * @pdev: Pointer to PCI device
4053 *
4054 * Restart the card from scratch, as if from a cold-boot. Implementation
4055 * resembles the first-half of the igb_resume routine.
4056 */
4057 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4058 {
4059 struct net_device *netdev = pci_get_drvdata(pdev);
4060 struct igb_adapter *adapter = netdev_priv(netdev);
4061 struct e1000_hw *hw = &adapter->hw;
4062
4063 if (pci_enable_device(pdev)) {
4064 dev_err(&pdev->dev,
4065 "Cannot re-enable PCI device after reset.\n");
4066 return PCI_ERS_RESULT_DISCONNECT;
4067 }
4068 pci_set_master(pdev);
4069
4070 pci_enable_wake(pdev, PCI_D3hot, 0);
4071 pci_enable_wake(pdev, PCI_D3cold, 0);
4072
4073 igb_reset(adapter);
4074 wr32(E1000_WUS, ~0);
4075
4076 return PCI_ERS_RESULT_RECOVERED;
4077 }
4078
4079 /**
4080 * igb_io_resume - called when traffic can start flowing again.
4081 * @pdev: Pointer to PCI device
4082 *
4083 * This callback is called when the error recovery driver tells us that
4084 * its OK to resume normal operation. Implementation resembles the
4085 * second-half of the igb_resume routine.
4086 */
4087 static void igb_io_resume(struct pci_dev *pdev)
4088 {
4089 struct net_device *netdev = pci_get_drvdata(pdev);
4090 struct igb_adapter *adapter = netdev_priv(netdev);
4091
4092 igb_init_manageability(adapter);
4093
4094 if (netif_running(netdev)) {
4095 if (igb_up(adapter)) {
4096 dev_err(&pdev->dev, "igb_up failed after reset\n");
4097 return;
4098 }
4099 }
4100
4101 netif_device_attach(netdev);
4102
4103 /* let the f/w know that the h/w is now under the control of the
4104 * driver. */
4105 igb_get_hw_control(adapter);
4106
4107 }
4108
4109 /* igb_main.c */
WRT350N Kernel Patches