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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / ata / pata_legacy.c
blobaca5e7f27aa81832a163d3562e57840cdb6c7c63
1 /*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * An ATA driver for the legacy ATA ports.
20 *
21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series:
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 *
29 * Unsupported but docs exist:
30 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
31 *
32 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
33 * on PC class systems. There are three hybrid devices that are exceptions
34 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
35 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
36 *
37 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
38 * opti82c465mv/promise 20230c/20630/winbond83759A
39 *
40 * Use the autospeed and pio_mask options with:
41 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
42 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
43 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
44 * Winbond W83759A, Promise PDC20230-B
45 *
46 * For now use autospeed and pio_mask as above with the W83759A. This may
47 * change.
48 *
49 */
50
51 #include <linux/kernel.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/init.h>
55 #include <linux/blkdev.h>
56 #include <linux/delay.h>
57 #include <scsi/scsi_host.h>
58 #include <linux/ata.h>
59 #include <linux/libata.h>
60 #include <linux/platform_device.h>
61
62 #define DRV_NAME "pata_legacy"
63 #define DRV_VERSION "0.6.5"
64
65 #define NR_HOST 6
66
67 static int all;
68 module_param(all, int, 0444);
69 MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
70
71 struct legacy_data {
72 unsigned long timing;
73 u8 clock[2];
74 u8 last;
75 int fast;
76 struct platform_device *platform_dev;
77
78 };
79
80 enum controller {
81 BIOS = 0,
82 SNOOP = 1,
83 PDC20230 = 2,
84 HT6560A = 3,
85 HT6560B = 4,
86 OPTI611A = 5,
87 OPTI46X = 6,
88 QDI6500 = 7,
89 QDI6580 = 8,
90 QDI6580DP = 9, /* Dual channel mode is different */
91 W83759A = 10,
92
93 UNKNOWN = -1
94 };
95
96
97 struct legacy_probe {
98 unsigned char *name;
99 unsigned long port;
100 unsigned int irq;
101 unsigned int slot;
102 enum controller type;
103 unsigned long private;
104 };
105
106 struct legacy_controller {
107 const char *name;
108 struct ata_port_operations *ops;
109 unsigned int pio_mask;
110 unsigned int flags;
111 int (*setup)(struct platform_device *, struct legacy_probe *probe,
112 struct legacy_data *data);
113 };
114
115 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
116
117 static struct legacy_probe probe_list[NR_HOST];
118 static struct legacy_data legacy_data[NR_HOST];
119 static struct ata_host *legacy_host[NR_HOST];
120 static int nr_legacy_host;
121
122
123 static int probe_all; /* Set to check all ISA port ranges */
124 static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
125 static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
126 static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
127 static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
128 static int qdi; /* Set to probe QDI controllers */
129 static int winbond; /* Set to probe Winbond controllers,
130 give I/O port if non standard */
131 static int autospeed; /* Chip present which snoops speed changes */
132 static int pio_mask = 0x1F; /* PIO range for autospeed devices */
133 static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
134
135 /**
136 * legacy_probe_add - Add interface to probe list
137 * @port: Controller port
138 * @irq: IRQ number
139 * @type: Controller type
140 * @private: Controller specific info
141 *
142 * Add an entry into the probe list for ATA controllers. This is used
143 * to add the default ISA slots and then to build up the table
144 * further according to other ISA/VLB/Weird device scans
145 *
146 * An I/O port list is used to keep ordering stable and sane, as we
147 * don't have any good way to talk about ordering otherwise
148 */
149
150 static int legacy_probe_add(unsigned long port, unsigned int irq,
151 enum controller type, unsigned long private)
152 {
153 struct legacy_probe *lp = &probe_list[0];
154 int i;
155 struct legacy_probe *free = NULL;
156
157 for (i = 0; i < NR_HOST; i++) {
158 if (lp->port == 0 && free == NULL)
159 free = lp;
160 /* Matching port, or the correct slot for ordering */
161 if (lp->port == port || legacy_port[i] == port) {
162 free = lp;
163 break;
164 }
165 lp++;
166 }
167 if (free == NULL) {
168 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
169 return -1;
170 }
171 /* Fill in the entry for later probing */
172 free->port = port;
173 free->irq = irq;
174 free->type = type;
175 free->private = private;
176 return 0;
177 }
178
179
180 /**
181 * legacy_set_mode - mode setting
182 * @link: IDE link
183 * @unused: Device that failed when error is returned
184 *
185 * Use a non standard set_mode function. We don't want to be tuned.
186 *
187 * The BIOS configured everything. Our job is not to fiddle. Just use
188 * whatever PIO the hardware is using and leave it at that. When we
189 * get some kind of nice user driven API for control then we can
190 * expand on this as per hdparm in the base kernel.
191 */
192
193 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
194 {
195 struct ata_device *dev;
196
197 ata_link_for_each_dev(dev, link) {
198 if (ata_dev_enabled(dev)) {
199 ata_dev_printk(dev, KERN_INFO,
200 "configured for PIO\n");
201 dev->pio_mode = XFER_PIO_0;
202 dev->xfer_mode = XFER_PIO_0;
203 dev->xfer_shift = ATA_SHIFT_PIO;
204 dev->flags |= ATA_DFLAG_PIO;
205 }
206 }
207 return 0;
208 }
209
210 static struct scsi_host_template legacy_sht = {
211 .module = THIS_MODULE,
212 .name = DRV_NAME,
213 .ioctl = ata_scsi_ioctl,
214 .queuecommand = ata_scsi_queuecmd,
215 .can_queue = ATA_DEF_QUEUE,
216 .this_id = ATA_SHT_THIS_ID,
217 .sg_tablesize = LIBATA_MAX_PRD,
218 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
219 .emulated = ATA_SHT_EMULATED,
220 .use_clustering = ATA_SHT_USE_CLUSTERING,
221 .proc_name = DRV_NAME,
222 .dma_boundary = ATA_DMA_BOUNDARY,
223 .slave_configure = ata_scsi_slave_config,
224 .slave_destroy = ata_scsi_slave_destroy,
225 .bios_param = ata_std_bios_param,
226 };
227
228 /*
229 * These ops are used if the user indicates the hardware
230 * snoops the commands to decide on the mode and handles the
231 * mode selection "magically" itself. Several legacy controllers
232 * do this. The mode range can be set if it is not 0x1F by setting
233 * pio_mask as well.
234 */
235
236 static struct ata_port_operations simple_port_ops = {
237 .tf_load = ata_tf_load,
238 .tf_read = ata_tf_read,
239 .check_status = ata_check_status,
240 .exec_command = ata_exec_command,
241 .dev_select = ata_std_dev_select,
242
243 .freeze = ata_bmdma_freeze,
244 .thaw = ata_bmdma_thaw,
245 .error_handler = ata_bmdma_error_handler,
246 .post_internal_cmd = ata_bmdma_post_internal_cmd,
247 .cable_detect = ata_cable_40wire,
248
249 .qc_prep = ata_qc_prep,
250 .qc_issue = ata_qc_issue_prot,
251
252 .data_xfer = ata_data_xfer_noirq,
253
254 .irq_handler = ata_interrupt,
255 .irq_clear = ata_bmdma_irq_clear,
256 .irq_on = ata_irq_on,
257
258 .port_start = ata_sff_port_start,
259 };
260
261 static struct ata_port_operations legacy_port_ops = {
262 .set_mode = legacy_set_mode,
263
264 .tf_load = ata_tf_load,
265 .tf_read = ata_tf_read,
266 .check_status = ata_check_status,
267 .exec_command = ata_exec_command,
268 .dev_select = ata_std_dev_select,
269 .cable_detect = ata_cable_40wire,
270
271 .freeze = ata_bmdma_freeze,
272 .thaw = ata_bmdma_thaw,
273 .error_handler = ata_bmdma_error_handler,
274 .post_internal_cmd = ata_bmdma_post_internal_cmd,
275
276 .qc_prep = ata_qc_prep,
277 .qc_issue = ata_qc_issue_prot,
278
279 .data_xfer = ata_data_xfer_noirq,
280
281 .irq_handler = ata_interrupt,
282 .irq_clear = ata_bmdma_irq_clear,
283 .irq_on = ata_irq_on,
284
285 .port_start = ata_sff_port_start,
286 };
287
288 /*
289 * Promise 20230C and 20620 support
290 *
291 * This controller supports PIO0 to PIO2. We set PIO timings
292 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
293 * support is weird being DMA to controller and PIO'd to the host
294 * and not supported.
295 */
296
297 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
298 {
299 int tries = 5;
300 int pio = adev->pio_mode - XFER_PIO_0;
301 u8 rt;
302 unsigned long flags;
303
304 /* Safe as UP only. Force I/Os to occur together */
305
306 local_irq_save(flags);
307
308 /* Unlock the control interface */
309 do {
310 inb(0x1F5);
311 outb(inb(0x1F2) | 0x80, 0x1F2);
312 inb(0x1F2);
313 inb(0x3F6);
314 inb(0x3F6);
315 inb(0x1F2);
316 inb(0x1F2);
317 }
318 while ((inb(0x1F2) & 0x80) && --tries);
319
320 local_irq_restore(flags);
321
322 outb(inb(0x1F4) & 0x07, 0x1F4);
323
324 rt = inb(0x1F3);
325 rt &= 0x07 << (3 * adev->devno);
326 if (pio)
327 rt |= (1 + 3 * pio) << (3 * adev->devno);
328
329 udelay(100);
330 outb(inb(0x1F2) | 0x01, 0x1F2);
331 udelay(100);
332 inb(0x1F5);
333
334 }
335
336 static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
337 unsigned char *buf, unsigned int buflen, int rw)
338 {
339 if (ata_id_has_dword_io(dev->id)) {
340 struct ata_port *ap = dev->link->ap;
341 int slop = buflen & 3;
342 unsigned long flags;
343
344 local_irq_save(flags);
345
346 /* Perform the 32bit I/O synchronization sequence */
347 ioread8(ap->ioaddr.nsect_addr);
348 ioread8(ap->ioaddr.nsect_addr);
349 ioread8(ap->ioaddr.nsect_addr);
350
351 /* Now the data */
352 if (rw == READ)
353 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
354 else
355 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
356
357 if (unlikely(slop)) {
358 u32 pad;
359 if (rw == READ) {
360 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
361 memcpy(buf + buflen - slop, &pad, slop);
362 } else {
363 memcpy(&pad, buf + buflen - slop, slop);
364 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
365 }
366 buflen += 4 - slop;
367 }
368 local_irq_restore(flags);
369 } else
370 buflen = ata_data_xfer_noirq(dev, buf, buflen, rw);
371
372 return buflen;
373 }
374
375 static struct ata_port_operations pdc20230_port_ops = {
376 .set_piomode = pdc20230_set_piomode,
377
378 .tf_load = ata_tf_load,
379 .tf_read = ata_tf_read,
380 .check_status = ata_check_status,
381 .exec_command = ata_exec_command,
382 .dev_select = ata_std_dev_select,
383
384 .freeze = ata_bmdma_freeze,
385 .thaw = ata_bmdma_thaw,
386 .error_handler = ata_bmdma_error_handler,
387 .post_internal_cmd = ata_bmdma_post_internal_cmd,
388 .cable_detect = ata_cable_40wire,
389
390 .qc_prep = ata_qc_prep,
391 .qc_issue = ata_qc_issue_prot,
392
393 .data_xfer = pdc_data_xfer_vlb,
394
395 .irq_handler = ata_interrupt,
396 .irq_clear = ata_bmdma_irq_clear,
397 .irq_on = ata_irq_on,
398
399 .port_start = ata_sff_port_start,
400 };
401
402 /*
403 * Holtek 6560A support
404 *
405 * This controller supports PIO0 to PIO2 (no IORDY even though higher
406 * timings can be loaded).
407 */
408
409 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
410 {
411 u8 active, recover;
412 struct ata_timing t;
413
414 /* Get the timing data in cycles. For now play safe at 50Mhz */
415 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
416
417 active = FIT(t.active, 2, 15);
418 recover = FIT(t.recover, 4, 15);
419
420 inb(0x3E6);
421 inb(0x3E6);
422 inb(0x3E6);
423 inb(0x3E6);
424
425 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
426 ioread8(ap->ioaddr.status_addr);
427 }
428
429 static struct ata_port_operations ht6560a_port_ops = {
430 .set_piomode = ht6560a_set_piomode,
431
432 .tf_load = ata_tf_load,
433 .tf_read = ata_tf_read,
434 .check_status = ata_check_status,
435 .exec_command = ata_exec_command,
436 .dev_select = ata_std_dev_select,
437
438 .freeze = ata_bmdma_freeze,
439 .thaw = ata_bmdma_thaw,
440 .error_handler = ata_bmdma_error_handler,
441 .post_internal_cmd = ata_bmdma_post_internal_cmd,
442 .cable_detect = ata_cable_40wire,
443
444 .qc_prep = ata_qc_prep,
445 .qc_issue = ata_qc_issue_prot,
446
447 .data_xfer = ata_data_xfer, /* Check vlb/noirq */
448
449 .irq_handler = ata_interrupt,
450 .irq_clear = ata_bmdma_irq_clear,
451 .irq_on = ata_irq_on,
452
453 .port_start = ata_sff_port_start,
454 };
455
456 /*
457 * Holtek 6560B support
458 *
459 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
460 * setting unless we see an ATAPI device in which case we force it off.
461 *
462 * FIXME: need to implement 2nd channel support.
463 */
464
465 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
466 {
467 u8 active, recover;
468 struct ata_timing t;
469
470 /* Get the timing data in cycles. For now play safe at 50Mhz */
471 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
472
473 active = FIT(t.active, 2, 15);
474 recover = FIT(t.recover, 2, 16);
475 recover &= 0x15;
476
477 inb(0x3E6);
478 inb(0x3E6);
479 inb(0x3E6);
480 inb(0x3E6);
481
482 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
483
484 if (adev->class != ATA_DEV_ATA) {
485 u8 rconf = inb(0x3E6);
486 if (rconf & 0x24) {
487 rconf &= ~0x24;
488 outb(rconf, 0x3E6);
489 }
490 }
491 ioread8(ap->ioaddr.status_addr);
492 }
493
494 static struct ata_port_operations ht6560b_port_ops = {
495 .set_piomode = ht6560b_set_piomode,
496
497 .tf_load = ata_tf_load,
498 .tf_read = ata_tf_read,
499 .check_status = ata_check_status,
500 .exec_command = ata_exec_command,
501 .dev_select = ata_std_dev_select,
502
503 .freeze = ata_bmdma_freeze,
504 .thaw = ata_bmdma_thaw,
505 .error_handler = ata_bmdma_error_handler,
506 .post_internal_cmd = ata_bmdma_post_internal_cmd,
507 .cable_detect = ata_cable_40wire,
508
509 .qc_prep = ata_qc_prep,
510 .qc_issue = ata_qc_issue_prot,
511
512 .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */
513
514 .irq_handler = ata_interrupt,
515 .irq_clear = ata_bmdma_irq_clear,
516 .irq_on = ata_irq_on,
517
518 .port_start = ata_sff_port_start,
519 };
520
521 /*
522 * Opti core chipset helpers
523 */
524
525 /**
526 * opti_syscfg - read OPTI chipset configuration
527 * @reg: Configuration register to read
528 *
529 * Returns the value of an OPTI system board configuration register.
530 */
531
532 static u8 opti_syscfg(u8 reg)
533 {
534 unsigned long flags;
535 u8 r;
536
537 /* Uniprocessor chipset and must force cycles adjancent */
538 local_irq_save(flags);
539 outb(reg, 0x22);
540 r = inb(0x24);
541 local_irq_restore(flags);
542 return r;
543 }
544
545 /*
546 * Opti 82C611A
547 *
548 * This controller supports PIO0 to PIO3.
549 */
550
551 static void opti82c611a_set_piomode(struct ata_port *ap,
552 struct ata_device *adev)
553 {
554 u8 active, recover, setup;
555 struct ata_timing t;
556 struct ata_device *pair = ata_dev_pair(adev);
557 int clock;
558 int khz[4] = { 50000, 40000, 33000, 25000 };
559 u8 rc;
560
561 /* Enter configuration mode */
562 ioread16(ap->ioaddr.error_addr);
563 ioread16(ap->ioaddr.error_addr);
564 iowrite8(3, ap->ioaddr.nsect_addr);
565
566 /* Read VLB clock strapping */
567 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
568
569 /* Get the timing data in cycles */
570 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
571
572 /* Setup timing is shared */
573 if (pair) {
574 struct ata_timing tp;
575 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
576
577 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
578 }
579
580 active = FIT(t.active, 2, 17) - 2;
581 recover = FIT(t.recover, 1, 16) - 1;
582 setup = FIT(t.setup, 1, 4) - 1;
583
584 /* Select the right timing bank for write timing */
585 rc = ioread8(ap->ioaddr.lbal_addr);
586 rc &= 0x7F;
587 rc |= (adev->devno << 7);
588 iowrite8(rc, ap->ioaddr.lbal_addr);
589
590 /* Write the timings */
591 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
592
593 /* Select the right bank for read timings, also
594 load the shared timings for address */
595 rc = ioread8(ap->ioaddr.device_addr);
596 rc &= 0xC0;
597 rc |= adev->devno; /* Index select */
598 rc |= (setup << 4) | 0x04;
599 iowrite8(rc, ap->ioaddr.device_addr);
600
601 /* Load the read timings */
602 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
603
604 /* Ensure the timing register mode is right */
605 rc = ioread8(ap->ioaddr.lbal_addr);
606 rc &= 0x73;
607 rc |= 0x84;
608 iowrite8(rc, ap->ioaddr.lbal_addr);
609
610 /* Exit command mode */
611 iowrite8(0x83, ap->ioaddr.nsect_addr);
612 }
613
614
615 static struct ata_port_operations opti82c611a_port_ops = {
616 .set_piomode = opti82c611a_set_piomode,
617
618 .tf_load = ata_tf_load,
619 .tf_read = ata_tf_read,
620 .check_status = ata_check_status,
621 .exec_command = ata_exec_command,
622 .dev_select = ata_std_dev_select,
623
624 .freeze = ata_bmdma_freeze,
625 .thaw = ata_bmdma_thaw,
626 .error_handler = ata_bmdma_error_handler,
627 .post_internal_cmd = ata_bmdma_post_internal_cmd,
628 .cable_detect = ata_cable_40wire,
629
630 .qc_prep = ata_qc_prep,
631 .qc_issue = ata_qc_issue_prot,
632
633 .data_xfer = ata_data_xfer,
634
635 .irq_handler = ata_interrupt,
636 .irq_clear = ata_bmdma_irq_clear,
637 .irq_on = ata_irq_on,
638
639 .port_start = ata_sff_port_start,
640 };
641
642 /*
643 * Opti 82C465MV
644 *
645 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
646 * version is dual channel but doesn't have a lot of unique registers.
647 */
648
649 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
650 {
651 u8 active, recover, setup;
652 struct ata_timing t;
653 struct ata_device *pair = ata_dev_pair(adev);
654 int clock;
655 int khz[4] = { 50000, 40000, 33000, 25000 };
656 u8 rc;
657 u8 sysclk;
658
659 /* Get the clock */
660 sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */
661
662 /* Enter configuration mode */
663 ioread16(ap->ioaddr.error_addr);
664 ioread16(ap->ioaddr.error_addr);
665 iowrite8(3, ap->ioaddr.nsect_addr);
666
667 /* Read VLB clock strapping */
668 clock = 1000000000 / khz[sysclk];
669
670 /* Get the timing data in cycles */
671 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
672
673 /* Setup timing is shared */
674 if (pair) {
675 struct ata_timing tp;
676 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
677
678 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
679 }
680
681 active = FIT(t.active, 2, 17) - 2;
682 recover = FIT(t.recover, 1, 16) - 1;
683 setup = FIT(t.setup, 1, 4) - 1;
684
685 /* Select the right timing bank for write timing */
686 rc = ioread8(ap->ioaddr.lbal_addr);
687 rc &= 0x7F;
688 rc |= (adev->devno << 7);
689 iowrite8(rc, ap->ioaddr.lbal_addr);
690
691 /* Write the timings */
692 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
693
694 /* Select the right bank for read timings, also
695 load the shared timings for address */
696 rc = ioread8(ap->ioaddr.device_addr);
697 rc &= 0xC0;
698 rc |= adev->devno; /* Index select */
699 rc |= (setup << 4) | 0x04;
700 iowrite8(rc, ap->ioaddr.device_addr);
701
702 /* Load the read timings */
703 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
704
705 /* Ensure the timing register mode is right */
706 rc = ioread8(ap->ioaddr.lbal_addr);
707 rc &= 0x73;
708 rc |= 0x84;
709 iowrite8(rc, ap->ioaddr.lbal_addr);
710
711 /* Exit command mode */
712 iowrite8(0x83, ap->ioaddr.nsect_addr);
713
714 /* We need to know this for quad device on the MVB */
715 ap->host->private_data = ap;
716 }
717
718 /**
719 * opt82c465mv_qc_issue_prot - command issue
720 * @qc: command pending
721 *
722 * Called when the libata layer is about to issue a command. We wrap
723 * this interface so that we can load the correct ATA timings. The
724 * MVB has a single set of timing registers and these are shared
725 * across channels. As there are two registers we really ought to
726 * track the last two used values as a sort of register window. For
727 * now we just reload on a channel switch. On the single channel
728 * setup this condition never fires so we do nothing extra.
729 *
730 * FIXME: dual channel needs ->serialize support
731 */
732
733 static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc)
734 {
735 struct ata_port *ap = qc->ap;
736 struct ata_device *adev = qc->dev;
737
738 /* If timings are set and for the wrong channel (2nd test is
739 due to a libata shortcoming and will eventually go I hope) */
740 if (ap->host->private_data != ap->host
741 && ap->host->private_data != NULL)
742 opti82c46x_set_piomode(ap, adev);
743
744 return ata_qc_issue_prot(qc);
745 }
746
747 static struct ata_port_operations opti82c46x_port_ops = {
748 .set_piomode = opti82c46x_set_piomode,
749
750 .tf_load = ata_tf_load,
751 .tf_read = ata_tf_read,
752 .check_status = ata_check_status,
753 .exec_command = ata_exec_command,
754 .dev_select = ata_std_dev_select,
755
756 .freeze = ata_bmdma_freeze,
757 .thaw = ata_bmdma_thaw,
758 .error_handler = ata_bmdma_error_handler,
759 .post_internal_cmd = ata_bmdma_post_internal_cmd,
760 .cable_detect = ata_cable_40wire,
761
762 .qc_prep = ata_qc_prep,
763 .qc_issue = opti82c46x_qc_issue_prot,
764
765 .data_xfer = ata_data_xfer,
766
767 .irq_handler = ata_interrupt,
768 .irq_clear = ata_bmdma_irq_clear,
769 .irq_on = ata_irq_on,
770
771 .port_start = ata_sff_port_start,
772 };
773
774 static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
775 {
776 struct ata_timing t;
777 <<<<<<< HEAD:drivers/ata/pata_legacy.c
778 struct legacy_data *qdi = ap->host->private_data;
779 =======
780 struct legacy_data *ld_qdi = ap->host->private_data;
781 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
782 int active, recovery;
783 u8 timing;
784
785 /* Get the timing data in cycles */
786 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
787
788 <<<<<<< HEAD:drivers/ata/pata_legacy.c
789 if (qdi->fast) {
790 =======
791 if (ld_qdi->fast) {
792 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
793 active = 8 - FIT(t.active, 1, 8);
794 recovery = 18 - FIT(t.recover, 3, 18);
795 } else {
796 active = 9 - FIT(t.active, 2, 9);
797 recovery = 15 - FIT(t.recover, 0, 15);
798 }
799 timing = (recovery << 4) | active | 0x08;
800
801 <<<<<<< HEAD:drivers/ata/pata_legacy.c
802 qdi->clock[adev->devno] = timing;
803 =======
804 ld_qdi->clock[adev->devno] = timing;
805 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
806
807 <<<<<<< HEAD:drivers/ata/pata_legacy.c
808 outb(timing, qdi->timing);
809 =======
810 outb(timing, ld_qdi->timing);
811 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
812 }
813
814 /**
815 * qdi6580dp_set_piomode - PIO setup for dual channel
816 * @ap: Port
817 * @adev: Device
818 * @irq: interrupt line
819 *
820 * In dual channel mode the 6580 has one clock per channel and we have
821 * to software clockswitch in qc_issue_prot.
822 */
823
824 static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev)
825 {
826 struct ata_timing t;
827 <<<<<<< HEAD:drivers/ata/pata_legacy.c
828 struct legacy_data *qdi = ap->host->private_data;
829 =======
830 struct legacy_data *ld_qdi = ap->host->private_data;
831 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
832 int active, recovery;
833 u8 timing;
834
835 /* Get the timing data in cycles */
836 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
837
838 <<<<<<< HEAD:drivers/ata/pata_legacy.c
839 if (qdi->fast) {
840 =======
841 if (ld_qdi->fast) {
842 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
843 active = 8 - FIT(t.active, 1, 8);
844 recovery = 18 - FIT(t.recover, 3, 18);
845 } else {
846 active = 9 - FIT(t.active, 2, 9);
847 recovery = 15 - FIT(t.recover, 0, 15);
848 }
849 timing = (recovery << 4) | active | 0x08;
850
851 <<<<<<< HEAD:drivers/ata/pata_legacy.c
852 qdi->clock[adev->devno] = timing;
853 =======
854 ld_qdi->clock[adev->devno] = timing;
855 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
856
857 <<<<<<< HEAD:drivers/ata/pata_legacy.c
858 outb(timing, qdi->timing + 2 * ap->port_no);
859 =======
860 outb(timing, ld_qdi->timing + 2 * ap->port_no);
861 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
862 /* Clear the FIFO */
863 if (adev->class != ATA_DEV_ATA)
864 <<<<<<< HEAD:drivers/ata/pata_legacy.c
865 outb(0x5F, qdi->timing + 3);
866 =======
867 outb(0x5F, ld_qdi->timing + 3);
868 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
869 }
870
871 /**
872 * qdi6580_set_piomode - PIO setup for single channel
873 * @ap: Port
874 * @adev: Device
875 *
876 * In single channel mode the 6580 has one clock per device and we can
877 * avoid the requirement to clock switch. We also have to load the timing
878 * into the right clock according to whether we are master or slave.
879 */
880
881 static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
882 {
883 struct ata_timing t;
884 <<<<<<< HEAD:drivers/ata/pata_legacy.c
885 struct legacy_data *qdi = ap->host->private_data;
886 =======
887 struct legacy_data *ld_qdi = ap->host->private_data;
888 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
889 int active, recovery;
890 u8 timing;
891
892 /* Get the timing data in cycles */
893 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
894
895 <<<<<<< HEAD:drivers/ata/pata_legacy.c
896 if (qdi->fast) {
897 =======
898 if (ld_qdi->fast) {
899 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
900 active = 8 - FIT(t.active, 1, 8);
901 recovery = 18 - FIT(t.recover, 3, 18);
902 } else {
903 active = 9 - FIT(t.active, 2, 9);
904 recovery = 15 - FIT(t.recover, 0, 15);
905 }
906 timing = (recovery << 4) | active | 0x08;
907 <<<<<<< HEAD:drivers/ata/pata_legacy.c
908 qdi->clock[adev->devno] = timing;
909 outb(timing, qdi->timing + 2 * adev->devno);
910 =======
911 ld_qdi->clock[adev->devno] = timing;
912 outb(timing, ld_qdi->timing + 2 * adev->devno);
913 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
914 /* Clear the FIFO */
915 if (adev->class != ATA_DEV_ATA)
916 <<<<<<< HEAD:drivers/ata/pata_legacy.c
917 outb(0x5F, qdi->timing + 3);
918 =======
919 outb(0x5F, ld_qdi->timing + 3);
920 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
921 }
922
923 /**
924 * qdi_qc_issue_prot - command issue
925 * @qc: command pending
926 *
927 * Called when the libata layer is about to issue a command. We wrap
928 * this interface so that we can load the correct ATA timings.
929 */
930
931 static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc)
932 {
933 struct ata_port *ap = qc->ap;
934 struct ata_device *adev = qc->dev;
935 <<<<<<< HEAD:drivers/ata/pata_legacy.c
936 struct legacy_data *qdi = ap->host->private_data;
937 =======
938 struct legacy_data *ld_qdi = ap->host->private_data;
939 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
940
941 <<<<<<< HEAD:drivers/ata/pata_legacy.c
942 if (qdi->clock[adev->devno] != qdi->last) {
943 =======
944 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
945 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
946 if (adev->pio_mode) {
947 <<<<<<< HEAD:drivers/ata/pata_legacy.c
948 qdi->last = qdi->clock[adev->devno];
949 outb(qdi->clock[adev->devno], qdi->timing +
950 =======
951 ld_qdi->last = ld_qdi->clock[adev->devno];
952 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
953 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
954 2 * ap->port_no);
955 }
956 }
957 return ata_qc_issue_prot(qc);
958 }
959
960 static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
961 unsigned int buflen, int rw)
962 {
963 struct ata_port *ap = adev->link->ap;
964 int slop = buflen & 3;
965
966 if (ata_id_has_dword_io(adev->id)) {
967 if (rw == WRITE)
968 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
969 else
970 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
971
972 if (unlikely(slop)) {
973 u32 pad;
974 if (rw == WRITE) {
975 memcpy(&pad, buf + buflen - slop, slop);
976 pad = le32_to_cpu(pad);
977 iowrite32(pad, ap->ioaddr.data_addr);
978 } else {
979 pad = ioread32(ap->ioaddr.data_addr);
980 pad = cpu_to_le32(pad);
981 memcpy(buf + buflen - slop, &pad, slop);
982 }
983 }
984 return (buflen + 3) & ~3;
985 } else
986 return ata_data_xfer(adev, buf, buflen, rw);
987 }
988
989 static int qdi_port(struct platform_device *dev,
990 struct legacy_probe *lp, struct legacy_data *ld)
991 {
992 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
993 return -EBUSY;
994 ld->timing = lp->private;
995 return 0;
996 }
997
998 static struct ata_port_operations qdi6500_port_ops = {
999 .set_piomode = qdi6500_set_piomode,
1000
1001 .tf_load = ata_tf_load,
1002 .tf_read = ata_tf_read,
1003 .check_status = ata_check_status,
1004 .exec_command = ata_exec_command,
1005 .dev_select = ata_std_dev_select,
1006
1007 .freeze = ata_bmdma_freeze,
1008 .thaw = ata_bmdma_thaw,
1009 .error_handler = ata_bmdma_error_handler,
1010 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1011 .cable_detect = ata_cable_40wire,
1012
1013 .qc_prep = ata_qc_prep,
1014 .qc_issue = qdi_qc_issue_prot,
1015
1016 .data_xfer = vlb32_data_xfer,
1017
1018 .irq_handler = ata_interrupt,
1019 .irq_clear = ata_bmdma_irq_clear,
1020 .irq_on = ata_irq_on,
1021
1022 .port_start = ata_sff_port_start,
1023 };
1024
1025 static struct ata_port_operations qdi6580_port_ops = {
1026 .set_piomode = qdi6580_set_piomode,
1027
1028 .tf_load = ata_tf_load,
1029 .tf_read = ata_tf_read,
1030 .check_status = ata_check_status,
1031 .exec_command = ata_exec_command,
1032 .dev_select = ata_std_dev_select,
1033
1034 .freeze = ata_bmdma_freeze,
1035 .thaw = ata_bmdma_thaw,
1036 .error_handler = ata_bmdma_error_handler,
1037 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1038 .cable_detect = ata_cable_40wire,
1039
1040 .qc_prep = ata_qc_prep,
1041 .qc_issue = ata_qc_issue_prot,
1042
1043 .data_xfer = vlb32_data_xfer,
1044
1045 .irq_handler = ata_interrupt,
1046 .irq_clear = ata_bmdma_irq_clear,
1047 .irq_on = ata_irq_on,
1048
1049 .port_start = ata_sff_port_start,
1050 };
1051
1052 static struct ata_port_operations qdi6580dp_port_ops = {
1053 .set_piomode = qdi6580dp_set_piomode,
1054
1055 .tf_load = ata_tf_load,
1056 .tf_read = ata_tf_read,
1057 .check_status = ata_check_status,
1058 .exec_command = ata_exec_command,
1059 .dev_select = ata_std_dev_select,
1060
1061 .freeze = ata_bmdma_freeze,
1062 .thaw = ata_bmdma_thaw,
1063 .error_handler = ata_bmdma_error_handler,
1064 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1065 .cable_detect = ata_cable_40wire,
1066
1067 .qc_prep = ata_qc_prep,
1068 .qc_issue = qdi_qc_issue_prot,
1069
1070 .data_xfer = vlb32_data_xfer,
1071
1072 .irq_handler = ata_interrupt,
1073 .irq_clear = ata_bmdma_irq_clear,
1074 .irq_on = ata_irq_on,
1075
1076 .port_start = ata_sff_port_start,
1077 };
1078
1079 static DEFINE_SPINLOCK(winbond_lock);
1080
1081 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
1082 {
1083 unsigned long flags;
1084 spin_lock_irqsave(&winbond_lock, flags);
1085 outb(reg, port + 0x01);
1086 outb(val, port + 0x02);
1087 spin_unlock_irqrestore(&winbond_lock, flags);
1088 }
1089
1090 static u8 winbond_readcfg(unsigned long port, u8 reg)
1091 {
1092 u8 val;
1093
1094 unsigned long flags;
1095 spin_lock_irqsave(&winbond_lock, flags);
1096 outb(reg, port + 0x01);
1097 val = inb(port + 0x02);
1098 spin_unlock_irqrestore(&winbond_lock, flags);
1099
1100 return val;
1101 }
1102
1103 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
1104 {
1105 struct ata_timing t;
1106 <<<<<<< HEAD:drivers/ata/pata_legacy.c
1107 struct legacy_data *winbond = ap->host->private_data;
1108 =======
1109 struct legacy_data *ld_winbond = ap->host->private_data;
1110 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
1111 int active, recovery;
1112 u8 reg;
1113 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
1114
1115 <<<<<<< HEAD:drivers/ata/pata_legacy.c
1116 reg = winbond_readcfg(winbond->timing, 0x81);
1117 =======
1118 reg = winbond_readcfg(ld_winbond->timing, 0x81);
1119 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
1120
1121 /* Get the timing data in cycles */
1122 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
1123 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
1124 else
1125 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
1126
1127 active = (FIT(t.active, 3, 17) - 1) & 0x0F;
1128 recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F;
1129 timing = (active << 4) | recovery;
1130 <<<<<<< HEAD:drivers/ata/pata_legacy.c
1131 winbond_writecfg(winbond->timing, timing, reg);
1132 =======
1133 winbond_writecfg(ld_winbond->timing, timing, reg);
1134 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
1135
1136 /* Load the setup timing */
1137
1138 reg = 0x35;
1139 if (adev->class != ATA_DEV_ATA)
1140 reg |= 0x08; /* FIFO off */
1141 if (!ata_pio_need_iordy(adev))
1142 reg |= 0x02; /* IORDY off */
1143 reg |= (FIT(t.setup, 0, 3) << 6);
1144 <<<<<<< HEAD:drivers/ata/pata_legacy.c
1145 winbond_writecfg(winbond->timing, timing + 1, reg);
1146 =======
1147 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
1148 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_legacy.c
1149 }
1150
1151 static int winbond_port(struct platform_device *dev,
1152 struct legacy_probe *lp, struct legacy_data *ld)
1153 {
1154 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
1155 return -EBUSY;
1156 ld->timing = lp->private;
1157 return 0;
1158 }
1159
1160 static struct ata_port_operations winbond_port_ops = {
1161 .set_piomode = winbond_set_piomode,
1162
1163 .tf_load = ata_tf_load,
1164 .tf_read = ata_tf_read,
1165 .check_status = ata_check_status,
1166 .exec_command = ata_exec_command,
1167 .dev_select = ata_std_dev_select,
1168
1169 .freeze = ata_bmdma_freeze,
1170 .thaw = ata_bmdma_thaw,
1171 .error_handler = ata_bmdma_error_handler,
1172 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1173 .cable_detect = ata_cable_40wire,
1174
1175 .qc_prep = ata_qc_prep,
1176 .qc_issue = ata_qc_issue_prot,
1177
1178 .data_xfer = vlb32_data_xfer,
1179
1180 .irq_clear = ata_bmdma_irq_clear,
1181 .irq_on = ata_irq_on,
1182
1183 .port_start = ata_sff_port_start,
1184 };
1185
1186 static struct legacy_controller controllers[] = {
1187 {"BIOS", &legacy_port_ops, 0x1F,
1188 ATA_FLAG_NO_IORDY, NULL },
1189 {"Snooping", &simple_port_ops, 0x1F,
1190 0 , NULL },
1191 {"PDC20230", &pdc20230_port_ops, 0x7,
1192 ATA_FLAG_NO_IORDY, NULL },
1193 {"HT6560A", &ht6560a_port_ops, 0x07,
1194 ATA_FLAG_NO_IORDY, NULL },
1195 {"HT6560B", &ht6560b_port_ops, 0x1F,
1196 ATA_FLAG_NO_IORDY, NULL },
1197 {"OPTI82C611A", &opti82c611a_port_ops, 0x0F,
1198 0 , NULL },
1199 {"OPTI82C46X", &opti82c46x_port_ops, 0x0F,
1200 0 , NULL },
1201 {"QDI6500", &qdi6500_port_ops, 0x07,
1202 ATA_FLAG_NO_IORDY, qdi_port },
1203 {"QDI6580", &qdi6580_port_ops, 0x1F,
1204 0 , qdi_port },
1205 {"QDI6580DP", &qdi6580dp_port_ops, 0x1F,
1206 0 , qdi_port },
1207 {"W83759A", &winbond_port_ops, 0x1F,
1208 0 , winbond_port }
1209 };
1210
1211 /**
1212 * probe_chip_type - Discover controller
1213 * @probe: Probe entry to check
1214 *
1215 * Probe an ATA port and identify the type of controller. We don't
1216 * check if the controller appears to be driveless at this point.
1217 */
1218
1219 static __init int probe_chip_type(struct legacy_probe *probe)
1220 {
1221 int mask = 1 << probe->slot;
1222
1223 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
1224 u8 reg = winbond_readcfg(winbond, 0x81);
1225 reg |= 0x80; /* jumpered mode off */
1226 winbond_writecfg(winbond, 0x81, reg);
1227 reg = winbond_readcfg(winbond, 0x83);
1228 reg |= 0xF0; /* local control */
1229 winbond_writecfg(winbond, 0x83, reg);
1230 reg = winbond_readcfg(winbond, 0x85);
1231 reg |= 0xF0; /* programmable timing */
1232 winbond_writecfg(winbond, 0x85, reg);
1233
1234 reg = winbond_readcfg(winbond, 0x81);
1235
1236 if (reg & mask)
1237 return W83759A;
1238 }
1239 if (probe->port == 0x1F0) {
1240 unsigned long flags;
1241 local_irq_save(flags);
1242 /* Probes */
1243 outb(inb(0x1F2) | 0x80, 0x1F2);
1244 inb(0x1F5);
1245 inb(0x1F2);
1246 inb(0x3F6);
1247 inb(0x3F6);
1248 inb(0x1F2);
1249 inb(0x1F2);
1250
1251 if ((inb(0x1F2) & 0x80) == 0) {
1252 /* PDC20230c or 20630 ? */
1253 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
1254 " detected.\n");
1255 udelay(100);
1256 inb(0x1F5);
1257 local_irq_restore(flags);
1258 return PDC20230;
1259 } else {
1260 outb(0x55, 0x1F2);
1261 inb(0x1F2);
1262 inb(0x1F2);
1263 if (inb(0x1F2) == 0x00)
1264 printk(KERN_INFO "PDC20230-B VLB ATA "
1265 "controller detected.\n");
1266 local_irq_restore(flags);
1267 return BIOS;
1268 }
1269 local_irq_restore(flags);
1270 }
1271
1272 if (ht6560a & mask)
1273 return HT6560A;
1274 if (ht6560b & mask)
1275 return HT6560B;
1276 if (opti82c611a & mask)
1277 return OPTI611A;
1278 if (opti82c46x & mask)
1279 return OPTI46X;
1280 if (autospeed & mask)
1281 return SNOOP;
1282 return BIOS;
1283 }
1284
1285
1286 /**
1287 * legacy_init_one - attach a legacy interface
1288 * @pl: probe record
1289 *
1290 * Register an ISA bus IDE interface. Such interfaces are PIO and we
1291 * assume do not support IRQ sharing.
1292 */
1293
1294 static __init int legacy_init_one(struct legacy_probe *probe)
1295 {
1296 struct legacy_controller *controller = &controllers[probe->type];
1297 int pio_modes = controller->pio_mask;
1298 unsigned long io = probe->port;
1299 u32 mask = (1 << probe->slot);
1300 struct ata_port_operations *ops = controller->ops;
1301 struct legacy_data *ld = &legacy_data[probe->slot];
1302 struct ata_host *host = NULL;
1303 struct ata_port *ap;
1304 struct platform_device *pdev;
1305 struct ata_device *dev;
1306 void __iomem *io_addr, *ctrl_addr;
1307 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
1308 int ret;
1309
1310 iordy |= controller->flags;
1311
1312 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
1313 if (IS_ERR(pdev))
1314 return PTR_ERR(pdev);
1315
1316 ret = -EBUSY;
1317 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
1318 devm_request_region(&pdev->dev, io + 0x0206, 1,
1319 "pata_legacy") == NULL)
1320 goto fail;
1321
1322 ret = -ENOMEM;
1323 io_addr = devm_ioport_map(&pdev->dev, io, 8);
1324 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
1325 if (!io_addr || !ctrl_addr)
1326 goto fail;
1327 if (controller->setup)
1328 if (controller->setup(pdev, probe, ld) < 0)
1329 goto fail;
1330 host = ata_host_alloc(&pdev->dev, 1);
1331 if (!host)
1332 goto fail;
1333 ap = host->ports[0];
1334
1335 ap->ops = ops;
1336 ap->pio_mask = pio_modes;
1337 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
1338 ap->ioaddr.cmd_addr = io_addr;
1339 ap->ioaddr.altstatus_addr = ctrl_addr;
1340 ap->ioaddr.ctl_addr = ctrl_addr;
1341 ata_std_ports(&ap->ioaddr);
1342 ap->host->private_data = ld;
1343
1344 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1345
1346 ret = ata_host_activate(host, probe->irq, ata_interrupt, 0,
1347 &legacy_sht);
1348 if (ret)
1349 goto fail;
1350 ld->platform_dev = pdev;
1351
1352 /* Nothing found means we drop the port as its probably not there */
1353
1354 ret = -ENODEV;
1355 ata_link_for_each_dev(dev, &ap->link) {
1356 if (!ata_dev_absent(dev)) {
1357 legacy_host[probe->slot] = host;
1358 ld->platform_dev = pdev;
1359 return 0;
1360 }
1361 }
1362 fail:
1363 platform_device_unregister(pdev);
1364 return ret;
1365 }
1366
1367 /**
1368 * legacy_check_special_cases - ATA special cases
1369 * @p: PCI device to check
1370 * @master: set this if we find an ATA master
1371 * @master: set this if we find an ATA secondary
1372 *
1373 * A small number of vendors implemented early PCI ATA interfaces
1374 * on bridge logic without the ATA interface being PCI visible.
1375 * Where we have a matching PCI driver we must skip the relevant
1376 * device here. If we don't know about it then the legacy driver
1377 * is the right driver anyway.
1378 */
1379
1380 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1381 int *secondary)
1382 {
1383 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1384 if (p->vendor == 0x1078 && p->device == 0x0000) {
1385 *primary = *secondary = 1;
1386 return;
1387 }
1388 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1389 if (p->vendor == 0x1078 && p->device == 0x0002) {
1390 *primary = *secondary = 1;
1391 return;
1392 }
1393 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1394 if (p->vendor == 0x8086 && p->device == 0x1234) {
1395 u16 r;
1396 pci_read_config_word(p, 0x6C, &r);
1397 if (r & 0x8000) {
1398 /* ATA port enabled */
1399 if (r & 0x4000)
1400 *secondary = 1;
1401 else
1402 *primary = 1;
1403 }
1404 return;
1405 }
1406 }
1407
1408 static __init void probe_opti_vlb(void)
1409 {
1410 /* If an OPTI 82C46X is present find out where the channels are */
1411 static const char *optis[4] = {
1412 "3/463MV", "5MV",
1413 "5MVA", "5MVB"
1414 };
1415 u8 chans = 1;
1416 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1417
1418 opti82c46x = 3; /* Assume master and slave first */
1419 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1420 optis[ctrl]);
1421 if (ctrl == 3)
1422 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1423 ctrl = opti_syscfg(0xAC);
1424 /* Check enabled and this port is the 465MV port. On the
1425 MVB we may have two channels */
1426 if (ctrl & 8) {
1427 if (chans == 2) {
1428 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1429 legacy_probe_add(0x170, 15, OPTI46X, 0);
1430 }
1431 if (ctrl & 4)
1432 legacy_probe_add(0x170, 15, OPTI46X, 0);
1433 else
1434 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1435 } else
1436 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1437 }
1438
1439 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1440 {
1441 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1442 /* Check card type */
1443 if ((r & 0xF0) == 0xC0) {
1444 /* QD6500: single channel */
1445 if (r & 8)
1446 /* Disabled ? */
1447 return;
1448 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1449 QDI6500, port);
1450 }
1451 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1452 /* QD6580: dual channel */
1453 if (!request_region(port + 2 , 2, "pata_qdi")) {
1454 release_region(port, 2);
1455 return;
1456 }
1457 res = inb(port + 3);
1458 /* Single channel mode ? */
1459 if (res & 1)
1460 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1461 QDI6580, port);
1462 else { /* Dual channel mode */
1463 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1464 /* port + 0x02, r & 0x04 */
1465 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1466 }
1467 release_region(port + 2, 2);
1468 }
1469 }
1470
1471 static __init void probe_qdi_vlb(void)
1472 {
1473 unsigned long flags;
1474 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1475 int i;
1476
1477 /*
1478 * Check each possible QD65xx base address
1479 */
1480
1481 for (i = 0; i < 2; i++) {
1482 unsigned long port = qd_port[i];
1483 u8 r, res;
1484
1485
1486 if (request_region(port, 2, "pata_qdi")) {
1487 /* Check for a card */
1488 local_irq_save(flags);
1489 /* I have no h/w that needs this delay but it
1490 is present in the historic code */
1491 r = inb(port);
1492 udelay(1);
1493 outb(0x19, port);
1494 udelay(1);
1495 res = inb(port);
1496 udelay(1);
1497 outb(r, port);
1498 udelay(1);
1499 local_irq_restore(flags);
1500
1501 /* Fail */
1502 if (res == 0x19) {
1503 release_region(port, 2);
1504 continue;
1505 }
1506 /* Passes the presence test */
1507 r = inb(port + 1);
1508 udelay(1);
1509 /* Check port agrees with port set */
1510 if ((r & 2) >> 1 == i)
1511 qdi65_identify_port(r, res, port);
1512 release_region(port, 2);
1513 }
1514 }
1515 }
1516
1517 /**
1518 * legacy_init - attach legacy interfaces
1519 *
1520 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1521 * Right now we do not scan the ide0 and ide1 address but should do so
1522 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1523 * If you fix that note there are special cases to consider like VLB
1524 * drivers and CS5510/20.
1525 */
1526
1527 static __init int legacy_init(void)
1528 {
1529 int i;
1530 int ct = 0;
1531 int primary = 0;
1532 int secondary = 0;
1533 int pci_present = 0;
1534 struct legacy_probe *pl = &probe_list[0];
1535 int slot = 0;
1536
1537 struct pci_dev *p = NULL;
1538
1539 for_each_pci_dev(p) {
1540 int r;
1541 /* Check for any overlap of the system ATA mappings. Native
1542 mode controllers stuck on these addresses or some devices
1543 in 'raid' mode won't be found by the storage class test */
1544 for (r = 0; r < 6; r++) {
1545 if (pci_resource_start(p, r) == 0x1f0)
1546 primary = 1;
1547 if (pci_resource_start(p, r) == 0x170)
1548 secondary = 1;
1549 }
1550 /* Check for special cases */
1551 legacy_check_special_cases(p, &primary, &secondary);
1552
1553 /* If PCI bus is present then don't probe for tertiary
1554 legacy ports */
1555 pci_present = 1;
1556 }
1557
1558 if (winbond == 1)
1559 winbond = 0x130; /* Default port, alt is 1B0 */
1560
1561 if (primary == 0 || all)
1562 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1563 if (secondary == 0 || all)
1564 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1565
1566 if (probe_all || !pci_present) {
1567 /* ISA/VLB extra ports */
1568 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1569 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1570 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1571 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1572 }
1573
1574 if (opti82c46x)
1575 probe_opti_vlb();
1576 if (qdi)
1577 probe_qdi_vlb();
1578
1579 for (i = 0; i < NR_HOST; i++, pl++) {
1580 if (pl->port == 0)
1581 continue;
1582 if (pl->type == UNKNOWN)
1583 pl->type = probe_chip_type(pl);
1584 pl->slot = slot++;
1585 if (legacy_init_one(pl) == 0)
1586 ct++;
1587 }
1588 if (ct != 0)
1589 return 0;
1590 return -ENODEV;
1591 }
1592
1593 static __exit void legacy_exit(void)
1594 {
1595 int i;
1596
1597 for (i = 0; i < nr_legacy_host; i++) {
1598 struct legacy_data *ld = &legacy_data[i];
1599 ata_host_detach(legacy_host[i]);
1600 platform_device_unregister(ld->platform_dev);
1601 }
1602 }
1603
1604 MODULE_AUTHOR("Alan Cox");
1605 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1606 MODULE_LICENSE("GPL");
1607 MODULE_VERSION(DRV_VERSION);
1608
1609 module_param(probe_all, int, 0);
1610 module_param(autospeed, int, 0);
1611 module_param(ht6560a, int, 0);
1612 module_param(ht6560b, int, 0);
1613 module_param(opti82c611a, int, 0);
1614 module_param(opti82c46x, int, 0);
1615 module_param(qdi, int, 0);
1616 module_param(pio_mask, int, 0);
1617 module_param(iordy_mask, int, 0);
1618
1619 module_init(legacy_init);
1620 module_exit(legacy_exit);
WRT350N Kernel Patches