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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / char / agp / amd-k7-agp.c
blob752055a66147e02bd4fde93eb9202796ad5825ad
1 /*
2 * AMD K7 AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
9 #include <linux/gfp.h>
10 #include <linux/page-flags.h>
11 #include <linux/mm.h>
12 #include "agp.h"
13
14 #define AMD_MMBASE 0x14
15 #define AMD_APSIZE 0xac
16 #define AMD_MODECNTL 0xb0
17 #define AMD_MODECNTL2 0xb2
18 #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
19 #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
20 #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
21 #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
22
23 static struct pci_device_id agp_amdk7_pci_table[];
24
25 struct amd_page_map {
26 unsigned long *real;
27 unsigned long __iomem *remapped;
28 };
29
30 static struct _amd_irongate_private {
31 volatile u8 __iomem *registers;
32 struct amd_page_map **gatt_pages;
33 int num_tables;
34 } amd_irongate_private;
35
36 static int amd_create_page_map(struct amd_page_map *page_map)
37 {
38 int i;
39
40 page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
41 if (page_map->real == NULL)
42 return -ENOMEM;
43
44 <<<<<<< HEAD:drivers/char/agp/amd-k7-agp.c
45 =======
46 #ifndef CONFIG_X86
47 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/amd-k7-agp.c
48 SetPageReserved(virt_to_page(page_map->real));
49 global_cache_flush();
50 page_map->remapped = ioremap_nocache(virt_to_gart(page_map->real),
51 PAGE_SIZE);
52 if (page_map->remapped == NULL) {
53 ClearPageReserved(virt_to_page(page_map->real));
54 free_page((unsigned long) page_map->real);
55 page_map->real = NULL;
56 return -ENOMEM;
57 }
58 global_cache_flush();
59 <<<<<<< HEAD:drivers/char/agp/amd-k7-agp.c
60 =======
61 #else
62 set_memory_uc((unsigned long)page_map->real, 1);
63 page_map->remapped = page_map->real;
64 #endif
65 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/amd-k7-agp.c
66
67 for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
68 writel(agp_bridge->scratch_page, page_map->remapped+i);
69 readl(page_map->remapped+i); /* PCI Posting. */
70 }
71
72 return 0;
73 }
74
75 static void amd_free_page_map(struct amd_page_map *page_map)
76 {
77 <<<<<<< HEAD:drivers/char/agp/amd-k7-agp.c
78 =======
79 #ifndef CONFIG_X86
80 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/amd-k7-agp.c
81 iounmap(page_map->remapped);
82 ClearPageReserved(virt_to_page(page_map->real));
83 <<<<<<< HEAD:drivers/char/agp/amd-k7-agp.c
84 =======
85 #else
86 set_memory_wb((unsigned long)page_map->real, 1);
87 #endif
88 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/amd-k7-agp.c
89 free_page((unsigned long) page_map->real);
90 }
91
92 static void amd_free_gatt_pages(void)
93 {
94 int i;
95 struct amd_page_map **tables;
96 struct amd_page_map *entry;
97
98 tables = amd_irongate_private.gatt_pages;
99 for (i = 0; i < amd_irongate_private.num_tables; i++) {
100 entry = tables[i];
101 if (entry != NULL) {
102 if (entry->real != NULL)
103 amd_free_page_map(entry);
104 kfree(entry);
105 }
106 }
107 kfree(tables);
108 amd_irongate_private.gatt_pages = NULL;
109 }
110
111 static int amd_create_gatt_pages(int nr_tables)
112 {
113 struct amd_page_map **tables;
114 struct amd_page_map *entry;
115 int retval = 0;
116 int i;
117
118 tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
119 if (tables == NULL)
120 return -ENOMEM;
121
122 for (i = 0; i < nr_tables; i++) {
123 entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
124 tables[i] = entry;
125 if (entry == NULL) {
126 retval = -ENOMEM;
127 break;
128 }
129 retval = amd_create_page_map(entry);
130 if (retval != 0)
131 break;
132 }
133 amd_irongate_private.num_tables = i;
134 amd_irongate_private.gatt_pages = tables;
135
136 if (retval != 0)
137 amd_free_gatt_pages();
138
139 return retval;
140 }
141
142 /* Since we don't need contiguous memory we just try
143 * to get the gatt table once
144 */
145
146 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
147 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
148 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
149 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
150 #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
151 GET_PAGE_DIR_IDX(addr)]->remapped)
152
153 static int amd_create_gatt_table(struct agp_bridge_data *bridge)
154 {
155 struct aper_size_info_lvl2 *value;
156 struct amd_page_map page_dir;
157 unsigned long addr;
158 int retval;
159 u32 temp;
160 int i;
161
162 value = A_SIZE_LVL2(agp_bridge->current_size);
163 retval = amd_create_page_map(&page_dir);
164 if (retval != 0)
165 return retval;
166
167 retval = amd_create_gatt_pages(value->num_entries / 1024);
168 if (retval != 0) {
169 amd_free_page_map(&page_dir);
170 return retval;
171 }
172
173 agp_bridge->gatt_table_real = (u32 *)page_dir.real;
174 agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
175 agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
176
177 /* Get the address for the gart region.
178 * This is a bus address even on the alpha, b/c its
179 * used to program the agp master not the cpu
180 */
181
182 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
183 addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
184 agp_bridge->gart_bus_addr = addr;
185
186 /* Calculate the agp offset */
187 for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
188 writel(virt_to_gart(amd_irongate_private.gatt_pages[i]->real) | 1,
189 page_dir.remapped+GET_PAGE_DIR_OFF(addr));
190 readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
191 }
192
193 return 0;
194 }
195
196 static int amd_free_gatt_table(struct agp_bridge_data *bridge)
197 {
198 struct amd_page_map page_dir;
199
200 page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
201 page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
202
203 amd_free_gatt_pages();
204 amd_free_page_map(&page_dir);
205 return 0;
206 }
207
208 static int amd_irongate_fetch_size(void)
209 {
210 int i;
211 u32 temp;
212 struct aper_size_info_lvl2 *values;
213
214 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
215 temp = (temp & 0x0000000e);
216 values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
217 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
218 if (temp == values[i].size_value) {
219 agp_bridge->previous_size =
220 agp_bridge->current_size = (void *) (values + i);
221
222 agp_bridge->aperture_size_idx = i;
223 return values[i].size;
224 }
225 }
226
227 return 0;
228 }
229
230 static int amd_irongate_configure(void)
231 {
232 struct aper_size_info_lvl2 *current_size;
233 u32 temp;
234 u16 enable_reg;
235
236 current_size = A_SIZE_LVL2(agp_bridge->current_size);
237
238 /* Get the memory mapped registers */
239 pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
240 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
241 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
242 if (!amd_irongate_private.registers)
243 return -ENOMEM;
244
245 /* Write out the address of the gatt table */
246 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
247 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
248
249 /* Write the Sync register */
250 pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
251
252 /* Set indexing mode */
253 pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
254
255 /* Write the enable register */
256 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
257 enable_reg = (enable_reg | 0x0004);
258 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
259 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
260
261 /* Write out the size register */
262 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
263 temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
264 pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
265
266 /* Flush the tlb */
267 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
268 readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
269 return 0;
270 }
271
272 static void amd_irongate_cleanup(void)
273 {
274 struct aper_size_info_lvl2 *previous_size;
275 u32 temp;
276 u16 enable_reg;
277
278 previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
279
280 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
281 enable_reg = (enable_reg & ~(0x0004));
282 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
283 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
284
285 /* Write back the previous size and disable gart translation */
286 pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
287 temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
288 pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
289 iounmap((void __iomem *) amd_irongate_private.registers);
290 }
291
292 /*
293 * This routine could be implemented by taking the addresses
294 * written to the GATT, and flushing them individually. However
295 * currently it just flushes the whole table. Which is probably
296 * more efficent, since agp_memory blocks can be a large number of
297 * entries.
298 */
299
300 static void amd_irongate_tlbflush(struct agp_memory *temp)
301 {
302 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
303 readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
304 }
305
306 static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
307 {
308 int i, j, num_entries;
309 unsigned long __iomem *cur_gatt;
310 unsigned long addr;
311
312 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
313
314 if (type != 0 || mem->type != 0)
315 return -EINVAL;
316
317 if ((pg_start + mem->page_count) > num_entries)
318 return -EINVAL;
319
320 j = pg_start;
321 while (j < (pg_start + mem->page_count)) {
322 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
323 cur_gatt = GET_GATT(addr);
324 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
325 return -EBUSY;
326 j++;
327 }
328
329 if (mem->is_flushed == FALSE) {
330 global_cache_flush();
331 mem->is_flushed = TRUE;
332 }
333
334 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
335 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
336 cur_gatt = GET_GATT(addr);
337 writel(agp_generic_mask_memory(agp_bridge,
338 mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
339 readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
340 }
341 amd_irongate_tlbflush(mem);
342 return 0;
343 }
344
345 static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
346 {
347 int i;
348 unsigned long __iomem *cur_gatt;
349 unsigned long addr;
350
351 if (type != 0 || mem->type != 0)
352 return -EINVAL;
353
354 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
355 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
356 cur_gatt = GET_GATT(addr);
357 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
358 readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
359 }
360
361 amd_irongate_tlbflush(mem);
362 return 0;
363 }
364
365 static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
366 {
367 {2048, 524288, 0x0000000c},
368 {1024, 262144, 0x0000000a},
369 {512, 131072, 0x00000008},
370 {256, 65536, 0x00000006},
371 {128, 32768, 0x00000004},
372 {64, 16384, 0x00000002},
373 {32, 8192, 0x00000000}
374 };
375
376 static const struct gatt_mask amd_irongate_masks[] =
377 {
378 {.mask = 1, .type = 0}
379 };
380
381 static const struct agp_bridge_driver amd_irongate_driver = {
382 .owner = THIS_MODULE,
383 .aperture_sizes = amd_irongate_sizes,
384 .size_type = LVL2_APER_SIZE,
385 .num_aperture_sizes = 7,
386 .configure = amd_irongate_configure,
387 .fetch_size = amd_irongate_fetch_size,
388 .cleanup = amd_irongate_cleanup,
389 .tlb_flush = amd_irongate_tlbflush,
390 .mask_memory = agp_generic_mask_memory,
391 .masks = amd_irongate_masks,
392 .agp_enable = agp_generic_enable,
393 .cache_flush = global_cache_flush,
394 .create_gatt_table = amd_create_gatt_table,
395 .free_gatt_table = amd_free_gatt_table,
396 .insert_memory = amd_insert_memory,
397 .remove_memory = amd_remove_memory,
398 .alloc_by_type = agp_generic_alloc_by_type,
399 .free_by_type = agp_generic_free_by_type,
400 .agp_alloc_page = agp_generic_alloc_page,
401 .agp_destroy_page = agp_generic_destroy_page,
402 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
403 };
404
405 static struct agp_device_ids amd_agp_device_ids[] __devinitdata =
406 {
407 {
408 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
409 .chipset_name = "Irongate",
410 },
411 {
412 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
413 .chipset_name = "761",
414 },
415 {
416 .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
417 .chipset_name = "760MP",
418 },
419 { }, /* dummy final entry, always present */
420 };
421
422 static int __devinit agp_amdk7_probe(struct pci_dev *pdev,
423 const struct pci_device_id *ent)
424 {
425 struct agp_bridge_data *bridge;
426 u8 cap_ptr;
427 int j;
428
429 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
430 if (!cap_ptr)
431 return -ENODEV;
432
433 j = ent - agp_amdk7_pci_table;
434 printk(KERN_INFO PFX "Detected AMD %s chipset\n",
435 amd_agp_device_ids[j].chipset_name);
436
437 bridge = agp_alloc_bridge();
438 if (!bridge)
439 return -ENOMEM;
440
441 bridge->driver = &amd_irongate_driver;
442 bridge->dev_private_data = &amd_irongate_private,
443 bridge->dev = pdev;
444 bridge->capndx = cap_ptr;
445
446 /* 751 Errata (22564_B-1.PDF)
447 erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
448 system controller may experience noise due to strong drive strengths
449 */
450 if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
451 u8 cap_ptr=0;
452 struct pci_dev *gfxcard=NULL;
453 while (!cap_ptr) {
454 gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
455 if (!gfxcard) {
456 printk (KERN_INFO PFX "Couldn't find an AGP VGA controller.\n");
457 return -ENODEV;
458 }
459 cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
460 }
461
462 /* With so many variants of NVidia cards, it's simpler just
463 to blacklist them all, and then whitelist them as needed
464 (if necessary at all). */
465 if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
466 agp_bridge->flags |= AGP_ERRATA_1X;
467 printk (KERN_INFO PFX "AMD 751 chipset with NVidia GeForce detected. Forcing to 1X due to errata.\n");
468 }
469 pci_dev_put(gfxcard);
470 }
471
472 /* 761 Errata (23613_F.pdf)
473 * Revisions B0/B1 were a disaster.
474 * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
475 * erratum 45: Timing problem prevents fast writes -- Disable fast write.
476 * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
477 * With this lot disabled, we should prevent lockups. */
478 if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
479 if (pdev->revision == 0x10 || pdev->revision == 0x11) {
480 agp_bridge->flags = AGP_ERRATA_FASTWRITES;
481 agp_bridge->flags |= AGP_ERRATA_SBA;
482 agp_bridge->flags |= AGP_ERRATA_1X;
483 printk (KERN_INFO PFX "AMD 761 chipset with errata detected - disabling AGP fast writes & SBA and forcing to 1X.\n");
484 }
485 }
486
487 /* Fill in the mode register */
488 pci_read_config_dword(pdev,
489 bridge->capndx+PCI_AGP_STATUS,
490 &bridge->mode);
491
492 pci_set_drvdata(pdev, bridge);
493 return agp_add_bridge(bridge);
494 }
495
496 static void __devexit agp_amdk7_remove(struct pci_dev *pdev)
497 {
498 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
499
500 agp_remove_bridge(bridge);
501 agp_put_bridge(bridge);
502 }
503
504 /* must be the same order as name table above */
505 static struct pci_device_id agp_amdk7_pci_table[] = {
506 {
507 .class = (PCI_CLASS_BRIDGE_HOST << 8),
508 .class_mask = ~0,
509 .vendor = PCI_VENDOR_ID_AMD,
510 .device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
511 .subvendor = PCI_ANY_ID,
512 .subdevice = PCI_ANY_ID,
513 },
514 {
515 .class = (PCI_CLASS_BRIDGE_HOST << 8),
516 .class_mask = ~0,
517 .vendor = PCI_VENDOR_ID_AMD,
518 .device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
519 .subvendor = PCI_ANY_ID,
520 .subdevice = PCI_ANY_ID,
521 },
522 {
523 .class = (PCI_CLASS_BRIDGE_HOST << 8),
524 .class_mask = ~0,
525 .vendor = PCI_VENDOR_ID_AMD,
526 .device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
527 .subvendor = PCI_ANY_ID,
528 .subdevice = PCI_ANY_ID,
529 },
530 { }
531 };
532
533 MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
534
535 static struct pci_driver agp_amdk7_pci_driver = {
536 .name = "agpgart-amdk7",
537 .id_table = agp_amdk7_pci_table,
538 .probe = agp_amdk7_probe,
539 .remove = agp_amdk7_remove,
540 };
541
542 static int __init agp_amdk7_init(void)
543 {
544 if (agp_off)
545 return -EINVAL;
546 return pci_register_driver(&agp_amdk7_pci_driver);
547 }
548
549 static void __exit agp_amdk7_cleanup(void)
550 {
551 pci_unregister_driver(&agp_amdk7_pci_driver);
552 }
553
554 module_init(agp_amdk7_init);
555 module_exit(agp_amdk7_cleanup);
556
557 MODULE_LICENSE("GPL and additional rights");
WRT350N Kernel Patches