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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / enc28j60.c
blob6c561d7e395cab0f2e1c57faad707d026789130b
1 /*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/tcp.h>
29 #include <linux/skbuff.h>
30 #include <linux/delay.h>
31 #include <linux/spi/spi.h>
32
33 #include "enc28j60_hw.h"
34
35 #define DRV_NAME "enc28j60"
36 #define DRV_VERSION "1.01"
37
38 #define SPI_OPLEN 1
39
40 #define ENC28J60_MSG_DEFAULT \
41 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
42
43 /* Buffer size required for the largest SPI transfer (i.e., reading a
44 * frame). */
45 #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
46
47 #define TX_TIMEOUT (4 * HZ)
48
49 /* Max TX retries in case of collision as suggested by errata datasheet */
50 #define MAX_TX_RETRYCOUNT 16
51
52 enum {
53 RXFILTER_NORMAL,
54 RXFILTER_MULTI,
55 RXFILTER_PROMISC
56 };
57
58 /* Driver local data */
59 struct enc28j60_net {
60 struct net_device *netdev;
61 struct spi_device *spi;
62 struct mutex lock;
63 struct sk_buff *tx_skb;
64 struct work_struct tx_work;
65 struct work_struct irq_work;
66 struct work_struct setrx_work;
67 struct work_struct restart_work;
68 u8 bank; /* current register bank selected */
69 u16 next_pk_ptr; /* next packet pointer within FIFO */
70 u16 max_pk_counter; /* statistics: max packet counter */
71 u16 tx_retry_count;
72 bool hw_enable;
73 bool full_duplex;
74 int rxfilter;
75 u32 msg_enable;
76 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
77 };
78
79 /* use ethtool to change the level for any given device */
80 static struct {
81 u32 msg_enable;
82 } debug = { -1 };
83
84 /*
85 * SPI read buffer
86 * wait for the SPI transfer and copy received data to destination
87 */
88 static int
89 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
90 {
91 u8 *rx_buf = priv->spi_transfer_buf + 4;
92 u8 *tx_buf = priv->spi_transfer_buf;
93 struct spi_transfer t = {
94 .tx_buf = tx_buf,
95 .rx_buf = rx_buf,
96 .len = SPI_OPLEN + len,
97 };
98 struct spi_message msg;
99 int ret;
100
101 tx_buf[0] = ENC28J60_READ_BUF_MEM;
102 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
103
104 spi_message_init(&msg);
105 spi_message_add_tail(&t, &msg);
106 ret = spi_sync(priv->spi, &msg);
107 if (ret == 0) {
108 memcpy(data, &rx_buf[SPI_OPLEN], len);
109 ret = msg.status;
110 }
111 if (ret && netif_msg_drv(priv))
112 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
113 __FUNCTION__, ret);
114
115 return ret;
116 }
117
118 /*
119 * SPI write buffer
120 */
121 static int spi_write_buf(struct enc28j60_net *priv, int len,
122 const u8 *data)
123 {
124 int ret;
125
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
127 ret = -EINVAL;
128 else {
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 memcpy(&priv->spi_transfer_buf[1], data, len);
131 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 if (ret && netif_msg_drv(priv))
133 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
134 __FUNCTION__, ret);
135 }
136 return ret;
137 }
138
139 /*
140 * basic SPI read operation
141 */
142 static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
143 u8 addr)
144 {
145 u8 tx_buf[2];
146 u8 rx_buf[4];
147 u8 val = 0;
148 int ret;
149 int slen = SPI_OPLEN;
150
151 /* do dummy read if needed */
152 if (addr & SPRD_MASK)
153 slen++;
154
155 tx_buf[0] = op | (addr & ADDR_MASK);
156 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
157 if (ret)
158 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
159 __FUNCTION__, ret);
160 else
161 val = rx_buf[slen - 1];
162
163 return val;
164 }
165
166 /*
167 * basic SPI write operation
168 */
169 static int spi_write_op(struct enc28j60_net *priv, u8 op,
170 u8 addr, u8 val)
171 {
172 int ret;
173
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 priv->spi_transfer_buf[1] = val;
176 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 if (ret && netif_msg_drv(priv))
178 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
179 __FUNCTION__, ret);
180 return ret;
181 }
182
183 static void enc28j60_soft_reset(struct enc28j60_net *priv)
184 {
185 if (netif_msg_hw(priv))
186 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
187
188 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
189 /* Errata workaround #1, CLKRDY check is unreliable,
190 * delay at least 1 mS instead */
191 udelay(2000);
192 }
193
194 /*
195 * select the current register bank if necessary
196 */
197 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
198 {
199 if ((addr & BANK_MASK) != priv->bank) {
200 u8 b = (addr & BANK_MASK) >> 5;
201
202 if (b != (ECON1_BSEL1 | ECON1_BSEL0))
203 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
204 ECON1_BSEL1 | ECON1_BSEL0);
205 if (b != 0)
206 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b);
207 priv->bank = (addr & BANK_MASK);
208 }
209 }
210
211 /*
212 * Register access routines through the SPI bus.
213 * Every register access comes in two flavours:
214 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
215 * atomically more than one register
216 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
217 *
218 * Some registers can be accessed through the bit field clear and
219 * bit field set to avoid a read modify write cycle.
220 */
221
222 /*
223 * Register bit field Set
224 */
225 static void nolock_reg_bfset(struct enc28j60_net *priv,
226 u8 addr, u8 mask)
227 {
228 enc28j60_set_bank(priv, addr);
229 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
230 }
231
232 static void locked_reg_bfset(struct enc28j60_net *priv,
233 u8 addr, u8 mask)
234 {
235 mutex_lock(&priv->lock);
236 nolock_reg_bfset(priv, addr, mask);
237 mutex_unlock(&priv->lock);
238 }
239
240 /*
241 * Register bit field Clear
242 */
243 static void nolock_reg_bfclr(struct enc28j60_net *priv,
244 u8 addr, u8 mask)
245 {
246 enc28j60_set_bank(priv, addr);
247 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
248 }
249
250 static void locked_reg_bfclr(struct enc28j60_net *priv,
251 u8 addr, u8 mask)
252 {
253 mutex_lock(&priv->lock);
254 nolock_reg_bfclr(priv, addr, mask);
255 mutex_unlock(&priv->lock);
256 }
257
258 /*
259 * Register byte read
260 */
261 static int nolock_regb_read(struct enc28j60_net *priv,
262 u8 address)
263 {
264 enc28j60_set_bank(priv, address);
265 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
266 }
267
268 static int locked_regb_read(struct enc28j60_net *priv,
269 u8 address)
270 {
271 int ret;
272
273 mutex_lock(&priv->lock);
274 ret = nolock_regb_read(priv, address);
275 mutex_unlock(&priv->lock);
276
277 return ret;
278 }
279
280 /*
281 * Register word read
282 */
283 static int nolock_regw_read(struct enc28j60_net *priv,
284 u8 address)
285 {
286 int rl, rh;
287
288 enc28j60_set_bank(priv, address);
289 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
290 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
291
292 return (rh << 8) | rl;
293 }
294
295 static int locked_regw_read(struct enc28j60_net *priv,
296 u8 address)
297 {
298 int ret;
299
300 mutex_lock(&priv->lock);
301 ret = nolock_regw_read(priv, address);
302 mutex_unlock(&priv->lock);
303
304 return ret;
305 }
306
307 /*
308 * Register byte write
309 */
310 static void nolock_regb_write(struct enc28j60_net *priv,
311 u8 address, u8 data)
312 {
313 enc28j60_set_bank(priv, address);
314 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
315 }
316
317 static void locked_regb_write(struct enc28j60_net *priv,
318 u8 address, u8 data)
319 {
320 mutex_lock(&priv->lock);
321 nolock_regb_write(priv, address, data);
322 mutex_unlock(&priv->lock);
323 }
324
325 /*
326 * Register word write
327 */
328 static void nolock_regw_write(struct enc28j60_net *priv,
329 u8 address, u16 data)
330 {
331 enc28j60_set_bank(priv, address);
332 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
333 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
334 (u8) (data >> 8));
335 }
336
337 static void locked_regw_write(struct enc28j60_net *priv,
338 u8 address, u16 data)
339 {
340 mutex_lock(&priv->lock);
341 nolock_regw_write(priv, address, data);
342 mutex_unlock(&priv->lock);
343 }
344
345 /*
346 * Buffer memory read
347 * Select the starting address and execute a SPI buffer read
348 */
349 static void enc28j60_mem_read(struct enc28j60_net *priv,
350 u16 addr, int len, u8 *data)
351 {
352 mutex_lock(&priv->lock);
353 nolock_regw_write(priv, ERDPTL, addr);
354 #ifdef CONFIG_ENC28J60_WRITEVERIFY
355 if (netif_msg_drv(priv)) {
356 u16 reg;
357 reg = nolock_regw_read(priv, ERDPTL);
358 if (reg != addr)
359 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
360 "(0x%04x - 0x%04x)\n", __FUNCTION__, reg, addr);
361 }
362 #endif
363 spi_read_buf(priv, len, data);
364 mutex_unlock(&priv->lock);
365 }
366
367 /*
368 * Write packet to enc28j60 TX buffer memory
369 */
370 static void
371 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
372 {
373 mutex_lock(&priv->lock);
374 /* Set the write pointer to start of transmit buffer area */
375 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
376 #ifdef CONFIG_ENC28J60_WRITEVERIFY
377 if (netif_msg_drv(priv)) {
378 u16 reg;
379 reg = nolock_regw_read(priv, EWRPTL);
380 if (reg != TXSTART_INIT)
381 printk(KERN_DEBUG DRV_NAME
382 ": %s() ERWPT:0x%04x != 0x%04x\n",
383 __FUNCTION__, reg, TXSTART_INIT);
384 }
385 #endif
386 /* Set the TXND pointer to correspond to the packet size given */
387 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
388 /* write per-packet control byte */
389 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
390 if (netif_msg_hw(priv))
391 printk(KERN_DEBUG DRV_NAME
392 ": %s() after control byte ERWPT:0x%04x\n",
393 __FUNCTION__, nolock_regw_read(priv, EWRPTL));
394 /* copy the packet into the transmit buffer */
395 spi_write_buf(priv, len, data);
396 if (netif_msg_hw(priv))
397 printk(KERN_DEBUG DRV_NAME
398 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
399 __FUNCTION__, nolock_regw_read(priv, EWRPTL), len);
400 mutex_unlock(&priv->lock);
401 }
402
403 /*
404 * Wait until the PHY operation is complete.
405 */
406 static int wait_phy_ready(struct enc28j60_net *priv)
407 {
408 unsigned long timeout = jiffies + 20 * HZ / 1000;
409 int ret = 1;
410
411 /* 20 msec timeout read */
412 while (nolock_regb_read(priv, MISTAT) & MISTAT_BUSY) {
413 if (time_after(jiffies, timeout)) {
414 if (netif_msg_drv(priv))
415 printk(KERN_DEBUG DRV_NAME
416 ": PHY ready timeout!\n");
417 ret = 0;
418 break;
419 }
420 cpu_relax();
421 }
422 return ret;
423 }
424
425 /*
426 * PHY register read
427 * PHY registers are not accessed directly, but through the MII
428 */
429 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
430 {
431 u16 ret;
432
433 mutex_lock(&priv->lock);
434 /* set the PHY register address */
435 nolock_regb_write(priv, MIREGADR, address);
436 /* start the register read operation */
437 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
438 /* wait until the PHY read completes */
439 wait_phy_ready(priv);
440 /* quit reading */
441 nolock_regb_write(priv, MICMD, 0x00);
442 /* return the data */
443 ret = nolock_regw_read(priv, MIRDL);
444 mutex_unlock(&priv->lock);
445
446 return ret;
447 }
448
449 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
450 {
451 int ret;
452
453 mutex_lock(&priv->lock);
454 /* set the PHY register address */
455 nolock_regb_write(priv, MIREGADR, address);
456 /* write the PHY data */
457 nolock_regw_write(priv, MIWRL, data);
458 /* wait until the PHY write completes and return */
459 ret = wait_phy_ready(priv);
460 mutex_unlock(&priv->lock);
461
462 return ret;
463 }
464
465 /*
466 * Program the hardware MAC address from dev->dev_addr.
467 */
468 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
469 {
470 int ret;
471 struct enc28j60_net *priv = netdev_priv(ndev);
472
473 mutex_lock(&priv->lock);
474 if (!priv->hw_enable) {
475 if (netif_msg_drv(priv)) {
476 DECLARE_MAC_BUF(mac);
477 printk(KERN_INFO DRV_NAME
478 ": %s: Setting MAC address to %s\n",
479 ndev->name, print_mac(mac, ndev->dev_addr));
480 }
481 /* NOTE: MAC address in ENC28J60 is byte-backward */
482 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
483 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
484 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
485 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
486 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
487 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
488 ret = 0;
489 } else {
490 if (netif_msg_drv(priv))
491 printk(KERN_DEBUG DRV_NAME
492 ": %s() Hardware must be disabled to set "
493 "Mac address\n", __FUNCTION__);
494 ret = -EBUSY;
495 }
496 mutex_unlock(&priv->lock);
497 return ret;
498 }
499
500 /*
501 * Store the new hardware address in dev->dev_addr, and update the MAC.
502 */
503 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
504 {
505 struct sockaddr *address = addr;
506
507 if (netif_running(dev))
508 return -EBUSY;
509 if (!is_valid_ether_addr(address->sa_data))
510 return -EADDRNOTAVAIL;
511
512 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
513 return enc28j60_set_hw_macaddr(dev);
514 }
515
516 /*
517 * Debug routine to dump useful register contents
518 */
519 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
520 {
521 mutex_lock(&priv->lock);
522 printk(KERN_DEBUG DRV_NAME " %s\n"
523 "HwRevID: 0x%02x\n"
524 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
525 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
526 "MAC : MACON1 MACON3 MACON4\n"
527 " 0x%02x 0x%02x 0x%02x\n"
528 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
529 " 0x%04x 0x%04x 0x%04x 0x%04x "
530 "0x%02x 0x%02x 0x%04x\n"
531 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
532 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
533 msg, nolock_regb_read(priv, EREVID),
534 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
535 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
536 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
537 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
538 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
539 nolock_regw_read(priv, ERXWRPTL),
540 nolock_regw_read(priv, ERXRDPTL),
541 nolock_regb_read(priv, ERXFCON),
542 nolock_regb_read(priv, EPKTCNT),
543 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
544 nolock_regw_read(priv, ETXNDL),
545 nolock_regb_read(priv, MACLCON1),
546 nolock_regb_read(priv, MACLCON2),
547 nolock_regb_read(priv, MAPHSUP));
548 mutex_unlock(&priv->lock);
549 }
550
551 /*
552 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
553 */
554 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
555 {
556 u16 erxrdpt;
557
558 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
559 erxrdpt = end;
560 else
561 erxrdpt = next_packet_ptr - 1;
562
563 return erxrdpt;
564 }
565
566 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
567 {
568 u16 erxrdpt;
569
570 if (start > 0x1FFF || end > 0x1FFF || start > end) {
571 if (netif_msg_drv(priv))
572 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
573 "bad parameters!\n", __FUNCTION__, start, end);
574 return;
575 }
576 /* set receive buffer start + end */
577 priv->next_pk_ptr = start;
578 nolock_regw_write(priv, ERXSTL, start);
579 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
580 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
581 nolock_regw_write(priv, ERXNDL, end);
582 }
583
584 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
585 {
586 if (start > 0x1FFF || end > 0x1FFF || start > end) {
587 if (netif_msg_drv(priv))
588 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
589 "bad parameters!\n", __FUNCTION__, start, end);
590 return;
591 }
592 /* set transmit buffer start + end */
593 nolock_regw_write(priv, ETXSTL, start);
594 nolock_regw_write(priv, ETXNDL, end);
595 }
596
597 static int enc28j60_hw_init(struct enc28j60_net *priv)
598 {
599 u8 reg;
600
601 if (netif_msg_drv(priv))
602 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __FUNCTION__,
603 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
604
605 mutex_lock(&priv->lock);
606 /* first reset the chip */
607 enc28j60_soft_reset(priv);
608 /* Clear ECON1 */
609 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
610 priv->bank = 0;
611 priv->hw_enable = false;
612 priv->tx_retry_count = 0;
613 priv->max_pk_counter = 0;
614 priv->rxfilter = RXFILTER_NORMAL;
615 /* enable address auto increment */
616 nolock_regb_write(priv, ECON2, ECON2_AUTOINC);
617
618 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
619 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
620 mutex_unlock(&priv->lock);
621
622 /*
623 * Check the RevID.
624 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
625 * damaged
626 */
627 reg = locked_regb_read(priv, EREVID);
628 if (netif_msg_drv(priv))
629 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
630 if (reg == 0x00 || reg == 0xff) {
631 if (netif_msg_drv(priv))
632 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
633 __FUNCTION__, reg);
634 return 0;
635 }
636
637 /* default filter mode: (unicast OR broadcast) AND crc valid */
638 locked_regb_write(priv, ERXFCON,
639 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
640
641 /* enable MAC receive */
642 locked_regb_write(priv, MACON1,
643 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
644 /* enable automatic padding and CRC operations */
645 if (priv->full_duplex) {
646 locked_regb_write(priv, MACON3,
647 MACON3_PADCFG0 | MACON3_TXCRCEN |
648 MACON3_FRMLNEN | MACON3_FULDPX);
649 /* set inter-frame gap (non-back-to-back) */
650 locked_regb_write(priv, MAIPGL, 0x12);
651 /* set inter-frame gap (back-to-back) */
652 locked_regb_write(priv, MABBIPG, 0x15);
653 } else {
654 locked_regb_write(priv, MACON3,
655 MACON3_PADCFG0 | MACON3_TXCRCEN |
656 MACON3_FRMLNEN);
657 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
658 /* set inter-frame gap (non-back-to-back) */
659 locked_regw_write(priv, MAIPGL, 0x0C12);
660 /* set inter-frame gap (back-to-back) */
661 locked_regb_write(priv, MABBIPG, 0x12);
662 }
663 /*
664 * MACLCON1 (default)
665 * MACLCON2 (default)
666 * Set the maximum packet size which the controller will accept
667 */
668 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
669
670 /* Configure LEDs */
671 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
672 return 0;
673
674 if (priv->full_duplex) {
675 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
676 return 0;
677 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
678 return 0;
679 } else {
680 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
681 return 0;
682 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
683 return 0;
684 }
685 if (netif_msg_hw(priv))
686 enc28j60_dump_regs(priv, "Hw initialized.");
687
688 return 1;
689 }
690
691 static void enc28j60_hw_enable(struct enc28j60_net *priv)
692 {
693 /* enable interrutps */
694 if (netif_msg_hw(priv))
695 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
696 __FUNCTION__);
697
698 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
699
700 mutex_lock(&priv->lock);
701 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
702 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
703 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
704 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
705
706 /* enable receive logic */
707 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
708 priv->hw_enable = true;
709 mutex_unlock(&priv->lock);
710 }
711
712 static void enc28j60_hw_disable(struct enc28j60_net *priv)
713 {
714 mutex_lock(&priv->lock);
715 /* disable interrutps and packet reception */
716 nolock_regb_write(priv, EIE, 0x00);
717 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
718 priv->hw_enable = false;
719 mutex_unlock(&priv->lock);
720 }
721
722 static int
723 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
724 {
725 struct enc28j60_net *priv = netdev_priv(ndev);
726 int ret = 0;
727
728 if (!priv->hw_enable) {
729 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) {
730 priv->full_duplex = (duplex == DUPLEX_FULL);
731 if (!enc28j60_hw_init(priv)) {
732 if (netif_msg_drv(priv))
733 dev_err(&ndev->dev,
734 "hw_reset() failed\n");
735 ret = -EINVAL;
736 }
737 } else {
738 if (netif_msg_link(priv))
739 dev_warn(&ndev->dev,
740 "unsupported link setting\n");
741 ret = -EOPNOTSUPP;
742 }
743 } else {
744 if (netif_msg_link(priv))
745 dev_warn(&ndev->dev, "Warning: hw must be disabled "
746 "to set link mode\n");
747 ret = -EBUSY;
748 }
749 return ret;
750 }
751
752 /*
753 * Read the Transmit Status Vector
754 */
755 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
756 {
757 int endptr;
758
759 endptr = locked_regw_read(priv, ETXNDL);
760 if (netif_msg_hw(priv))
761 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
762 endptr + 1);
763 enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
764 }
765
766 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
767 u8 tsv[TSV_SIZE])
768 {
769 u16 tmp1, tmp2;
770
771 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
772 tmp1 = tsv[1];
773 tmp1 <<= 8;
774 tmp1 |= tsv[0];
775
776 tmp2 = tsv[5];
777 tmp2 <<= 8;
778 tmp2 |= tsv[4];
779
780 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
781 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
782 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
783 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
784 TSV_GETBIT(tsv, TSV_TXCRCERROR),
785 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
786 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
787 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
788 "PacketDefer: %d, ExDefer: %d\n",
789 TSV_GETBIT(tsv, TSV_TXMULTICAST),
790 TSV_GETBIT(tsv, TSV_TXBROADCAST),
791 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
792 TSV_GETBIT(tsv, TSV_TXEXDEFER));
793 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
794 "Giant: %d, Underrun: %d\n",
795 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
796 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
797 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
798 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
799 "BackPressApp: %d, VLanTagFrame: %d\n",
800 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
801 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
802 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
803 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
804 }
805
806 /*
807 * Receive Status vector
808 */
809 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
810 u16 pk_ptr, int len, u16 sts)
811 {
812 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
813 msg, pk_ptr);
814 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
815 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
816 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
817 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
818 RSV_GETBIT(sts, RSV_CRCERROR),
819 RSV_GETBIT(sts, RSV_LENCHECKERR),
820 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
821 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
822 "LongDropEvent: %d, CarrierEvent: %d\n",
823 RSV_GETBIT(sts, RSV_RXMULTICAST),
824 RSV_GETBIT(sts, RSV_RXBROADCAST),
825 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
826 RSV_GETBIT(sts, RSV_CARRIEREV));
827 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
828 " UnknownOp: %d, VLanTagFrame: %d\n",
829 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
830 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
831 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
832 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
833 }
834
835 static void dump_packet(const char *msg, int len, const char *data)
836 {
837 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
838 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
839 data, len, true);
840 }
841
842 /*
843 * Hardware receive function.
844 * Read the buffer memory, update the FIFO pointer to free the buffer,
845 * check the status vector and decrement the packet counter.
846 */
847 static void enc28j60_hw_rx(struct net_device *ndev)
848 {
849 struct enc28j60_net *priv = netdev_priv(ndev);
850 struct sk_buff *skb = NULL;
851 u16 erxrdpt, next_packet, rxstat;
852 u8 rsv[RSV_SIZE];
853 int len;
854
855 if (netif_msg_rx_status(priv))
856 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
857 priv->next_pk_ptr);
858
859 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
860 if (netif_msg_rx_err(priv))
861 dev_err(&ndev->dev,
862 "%s() Invalid packet address!! 0x%04x\n",
863 __FUNCTION__, priv->next_pk_ptr);
864 /* packet address corrupted: reset RX logic */
865 mutex_lock(&priv->lock);
866 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
867 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
868 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
869 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
870 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
871 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
872 mutex_unlock(&priv->lock);
873 ndev->stats.rx_errors++;
874 return;
875 }
876 /* Read next packet pointer and rx status vector */
877 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
878
879 next_packet = rsv[1];
880 next_packet <<= 8;
881 next_packet |= rsv[0];
882
883 len = rsv[3];
884 len <<= 8;
885 len |= rsv[2];
886
887 rxstat = rsv[5];
888 rxstat <<= 8;
889 rxstat |= rsv[4];
890
891 if (netif_msg_rx_status(priv))
892 enc28j60_dump_rsv(priv, __FUNCTION__, next_packet, len, rxstat);
893
894 if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
895 if (netif_msg_rx_err(priv))
896 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
897 ndev->stats.rx_errors++;
898 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
899 ndev->stats.rx_crc_errors++;
900 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
901 ndev->stats.rx_frame_errors++;
902 } else {
903 <<<<<<< HEAD:drivers/net/enc28j60.c
904 skb = dev_alloc_skb(len);
905 =======
906 skb = dev_alloc_skb(len + NET_IP_ALIGN);
907 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/enc28j60.c
908 if (!skb) {
909 if (netif_msg_rx_err(priv))
910 dev_err(&ndev->dev,
911 "out of memory for Rx'd frame\n");
912 ndev->stats.rx_dropped++;
913 } else {
914 skb->dev = ndev;
915 <<<<<<< HEAD:drivers/net/enc28j60.c
916 =======
917 skb_reserve(skb, NET_IP_ALIGN);
918 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/enc28j60.c
919 /* copy the packet from the receive buffer */
920 enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv),
921 len, skb_put(skb, len));
922 if (netif_msg_pktdata(priv))
923 dump_packet(__FUNCTION__, skb->len, skb->data);
924 skb->protocol = eth_type_trans(skb, ndev);
925 /* update statistics */
926 ndev->stats.rx_packets++;
927 ndev->stats.rx_bytes += len;
928 ndev->last_rx = jiffies;
929 netif_rx(skb);
930 }
931 }
932 /*
933 * Move the RX read pointer to the start of the next
934 * received packet.
935 * This frees the memory we just read out
936 */
937 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
938 if (netif_msg_hw(priv))
939 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
940 __FUNCTION__, erxrdpt);
941
942 mutex_lock(&priv->lock);
943 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
944 #ifdef CONFIG_ENC28J60_WRITEVERIFY
945 if (netif_msg_drv(priv)) {
946 u16 reg;
947 reg = nolock_regw_read(priv, ERXRDPTL);
948 if (reg != erxrdpt)
949 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
950 "error (0x%04x - 0x%04x)\n", __FUNCTION__,
951 reg, erxrdpt);
952 }
953 #endif
954 priv->next_pk_ptr = next_packet;
955 /* we are done with this packet, decrement the packet counter */
956 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
957 mutex_unlock(&priv->lock);
958 }
959
960 /*
961 * Calculate free space in RxFIFO
962 */
963 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
964 {
965 int epkcnt, erxst, erxnd, erxwr, erxrd;
966 int free_space;
967
968 mutex_lock(&priv->lock);
969 epkcnt = nolock_regb_read(priv, EPKTCNT);
970 if (epkcnt >= 255)
971 free_space = -1;
972 else {
973 erxst = nolock_regw_read(priv, ERXSTL);
974 erxnd = nolock_regw_read(priv, ERXNDL);
975 erxwr = nolock_regw_read(priv, ERXWRPTL);
976 erxrd = nolock_regw_read(priv, ERXRDPTL);
977
978 if (erxwr > erxrd)
979 free_space = (erxnd - erxst) - (erxwr - erxrd);
980 else if (erxwr == erxrd)
981 free_space = (erxnd - erxst);
982 else
983 free_space = erxrd - erxwr - 1;
984 }
985 mutex_unlock(&priv->lock);
986 if (netif_msg_rx_status(priv))
987 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
988 __FUNCTION__, free_space);
989 return free_space;
990 }
991
992 /*
993 * Access the PHY to determine link status
994 */
995 static void enc28j60_check_link_status(struct net_device *ndev)
996 {
997 struct enc28j60_net *priv = netdev_priv(ndev);
998 u16 reg;
999 int duplex;
1000
1001 reg = enc28j60_phy_read(priv, PHSTAT2);
1002 if (netif_msg_hw(priv))
1003 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1004 "PHSTAT2: %04x\n", __FUNCTION__,
1005 enc28j60_phy_read(priv, PHSTAT1), reg);
1006 duplex = reg & PHSTAT2_DPXSTAT;
1007
1008 if (reg & PHSTAT2_LSTAT) {
1009 netif_carrier_on(ndev);
1010 if (netif_msg_ifup(priv))
1011 dev_info(&ndev->dev, "link up - %s\n",
1012 duplex ? "Full duplex" : "Half duplex");
1013 } else {
1014 if (netif_msg_ifdown(priv))
1015 dev_info(&ndev->dev, "link down\n");
1016 netif_carrier_off(ndev);
1017 }
1018 }
1019
1020 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1021 {
1022 struct enc28j60_net *priv = netdev_priv(ndev);
1023
1024 if (err)
1025 ndev->stats.tx_errors++;
1026 else
1027 ndev->stats.tx_packets++;
1028
1029 if (priv->tx_skb) {
1030 if (!err)
1031 ndev->stats.tx_bytes += priv->tx_skb->len;
1032 dev_kfree_skb(priv->tx_skb);
1033 priv->tx_skb = NULL;
1034 }
1035 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1036 netif_wake_queue(ndev);
1037 }
1038
1039 /*
1040 * RX handler
1041 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1042 * check EPKTCNT is the suggested workaround.
1043 * We don't need to clear interrupt flag, automatically done when
1044 * enc28j60_hw_rx() decrements the packet counter.
1045 * Returns how many packet processed.
1046 */
1047 static int enc28j60_rx_interrupt(struct net_device *ndev)
1048 {
1049 struct enc28j60_net *priv = netdev_priv(ndev);
1050 int pk_counter, ret;
1051
1052 pk_counter = locked_regb_read(priv, EPKTCNT);
1053 if (pk_counter && netif_msg_intr(priv))
1054 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1055 if (pk_counter > priv->max_pk_counter) {
1056 /* update statistics */
1057 priv->max_pk_counter = pk_counter;
1058 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1059 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1060 priv->max_pk_counter);
1061 }
1062 ret = pk_counter;
1063 while (pk_counter-- > 0)
1064 enc28j60_hw_rx(ndev);
1065
1066 return ret;
1067 }
1068
1069 static void enc28j60_irq_work_handler(struct work_struct *work)
1070 {
1071 struct enc28j60_net *priv =
1072 container_of(work, struct enc28j60_net, irq_work);
1073 struct net_device *ndev = priv->netdev;
1074 int intflags, loop;
1075
1076 if (netif_msg_intr(priv))
1077 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1078 /* disable further interrupts */
1079 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1080
1081 do {
1082 loop = 0;
1083 intflags = locked_regb_read(priv, EIR);
1084 /* DMA interrupt handler (not currently used) */
1085 if ((intflags & EIR_DMAIF) != 0) {
1086 loop++;
1087 if (netif_msg_intr(priv))
1088 printk(KERN_DEBUG DRV_NAME
1089 ": intDMA(%d)\n", loop);
1090 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1091 }
1092 /* LINK changed handler */
1093 if ((intflags & EIR_LINKIF) != 0) {
1094 loop++;
1095 if (netif_msg_intr(priv))
1096 printk(KERN_DEBUG DRV_NAME
1097 ": intLINK(%d)\n", loop);
1098 enc28j60_check_link_status(ndev);
1099 /* read PHIR to clear the flag */
1100 enc28j60_phy_read(priv, PHIR);
1101 }
1102 /* TX complete handler */
1103 if ((intflags & EIR_TXIF) != 0) {
1104 bool err = false;
1105 loop++;
1106 if (netif_msg_intr(priv))
1107 printk(KERN_DEBUG DRV_NAME
1108 ": intTX(%d)\n", loop);
1109 priv->tx_retry_count = 0;
1110 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1111 if (netif_msg_tx_err(priv))
1112 dev_err(&ndev->dev,
1113 "Tx Error (aborted)\n");
1114 err = true;
1115 }
1116 if (netif_msg_tx_done(priv)) {
1117 u8 tsv[TSV_SIZE];
1118 enc28j60_read_tsv(priv, tsv);
1119 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1120 }
1121 enc28j60_tx_clear(ndev, err);
1122 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1123 }
1124 /* TX Error handler */
1125 if ((intflags & EIR_TXERIF) != 0) {
1126 u8 tsv[TSV_SIZE];
1127
1128 loop++;
1129 if (netif_msg_intr(priv))
1130 printk(KERN_DEBUG DRV_NAME
1131 ": intTXErr(%d)\n", loop);
1132 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1133 enc28j60_read_tsv(priv, tsv);
1134 if (netif_msg_tx_err(priv))
1135 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1136 /* Reset TX logic */
1137 mutex_lock(&priv->lock);
1138 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1139 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1140 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1141 mutex_unlock(&priv->lock);
1142 /* Transmit Late collision check for retransmit */
1143 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1144 if (netif_msg_tx_err(priv))
1145 printk(KERN_DEBUG DRV_NAME
1146 ": LateCollision TXErr (%d)\n",
1147 priv->tx_retry_count);
1148 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1149 locked_reg_bfset(priv, ECON1,
1150 ECON1_TXRTS);
1151 else
1152 enc28j60_tx_clear(ndev, true);
1153 } else
1154 enc28j60_tx_clear(ndev, true);
1155 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1156 }
1157 /* RX Error handler */
1158 if ((intflags & EIR_RXERIF) != 0) {
1159 loop++;
1160 if (netif_msg_intr(priv))
1161 printk(KERN_DEBUG DRV_NAME
1162 ": intRXErr(%d)\n", loop);
1163 /* Check free FIFO space to flag RX overrun */
1164 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1165 if (netif_msg_rx_err(priv))
1166 printk(KERN_DEBUG DRV_NAME
1167 ": RX Overrun\n");
1168 ndev->stats.rx_dropped++;
1169 }
1170 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1171 }
1172 /* RX handler */
1173 if (enc28j60_rx_interrupt(ndev))
1174 loop++;
1175 } while (loop);
1176
1177 /* re-enable interrupts */
1178 locked_reg_bfset(priv, EIE, EIE_INTIE);
1179 if (netif_msg_intr(priv))
1180 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __FUNCTION__);
1181 }
1182
1183 /*
1184 * Hardware transmit function.
1185 * Fill the buffer memory and send the contents of the transmit buffer
1186 * onto the network
1187 */
1188 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1189 {
1190 if (netif_msg_tx_queued(priv))
1191 printk(KERN_DEBUG DRV_NAME
1192 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1193
1194 if (netif_msg_pktdata(priv))
1195 dump_packet(__FUNCTION__,
1196 priv->tx_skb->len, priv->tx_skb->data);
1197 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1198
1199 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1200 /* readback and verify written data */
1201 if (netif_msg_drv(priv)) {
1202 int test_len, k;
1203 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1204 int okflag;
1205
1206 test_len = priv->tx_skb->len;
1207 if (test_len > sizeof(test_buf))
1208 test_len = sizeof(test_buf);
1209
1210 /* + 1 to skip control byte */
1211 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1212 okflag = 1;
1213 for (k = 0; k < test_len; k++) {
1214 if (priv->tx_skb->data[k] != test_buf[k]) {
1215 printk(KERN_DEBUG DRV_NAME
1216 ": Error, %d location differ: "
1217 "0x%02x-0x%02x\n", k,
1218 priv->tx_skb->data[k], test_buf[k]);
1219 okflag = 0;
1220 }
1221 }
1222 if (!okflag)
1223 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1224 "verify ERROR!\n");
1225 }
1226 #endif
1227 /* set TX request flag */
1228 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1229 }
1230
1231 static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev)
1232 {
1233 struct enc28j60_net *priv = netdev_priv(dev);
1234
1235 if (netif_msg_tx_queued(priv))
1236 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1237
1238 /* If some error occurs while trying to transmit this
1239 * packet, you should return '1' from this function.
1240 * In such a case you _may not_ do anything to the
1241 * SKB, it is still owned by the network queueing
1242 * layer when an error is returned. This means you
1243 * may not modify any SKB fields, you may not free
1244 * the SKB, etc.
1245 */
1246 netif_stop_queue(dev);
1247
1248 /* save the timestamp */
1249 priv->netdev->trans_start = jiffies;
1250 /* Remember the skb for deferred processing */
1251 priv->tx_skb = skb;
1252 schedule_work(&priv->tx_work);
1253
1254 return 0;
1255 }
1256
1257 static void enc28j60_tx_work_handler(struct work_struct *work)
1258 {
1259 struct enc28j60_net *priv =
1260 container_of(work, struct enc28j60_net, tx_work);
1261
1262 /* actual delivery of data */
1263 enc28j60_hw_tx(priv);
1264 }
1265
1266 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1267 {
1268 struct enc28j60_net *priv = dev_id;
1269
1270 /*
1271 * Can't do anything in interrupt context because we need to
1272 * block (spi_sync() is blocking) so fire of the interrupt
1273 * handling workqueue.
1274 * Remember that we access enc28j60 registers through SPI bus
1275 * via spi_sync() call.
1276 */
1277 schedule_work(&priv->irq_work);
1278
1279 return IRQ_HANDLED;
1280 }
1281
1282 static void enc28j60_tx_timeout(struct net_device *ndev)
1283 {
1284 struct enc28j60_net *priv = netdev_priv(ndev);
1285
1286 if (netif_msg_timer(priv))
1287 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1288
1289 ndev->stats.tx_errors++;
1290 /* can't restart safely under softirq */
1291 schedule_work(&priv->restart_work);
1292 }
1293
1294 /*
1295 * Open/initialize the board. This is called (in the current kernel)
1296 * sometime after booting when the 'ifconfig' program is run.
1297 *
1298 * This routine should set everything up anew at each open, even
1299 * registers that "should" only need to be set once at boot, so that
1300 * there is non-reboot way to recover if something goes wrong.
1301 */
1302 static int enc28j60_net_open(struct net_device *dev)
1303 {
1304 struct enc28j60_net *priv = netdev_priv(dev);
1305
1306 if (netif_msg_drv(priv))
1307 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1308
1309 if (!is_valid_ether_addr(dev->dev_addr)) {
1310 if (netif_msg_ifup(priv)) {
1311 DECLARE_MAC_BUF(mac);
1312 dev_err(&dev->dev, "invalid MAC address %s\n",
1313 print_mac(mac, dev->dev_addr));
1314 }
1315 return -EADDRNOTAVAIL;
1316 }
1317 /* Reset the hardware here */
1318 enc28j60_hw_disable(priv);
1319 if (!enc28j60_hw_init(priv)) {
1320 if (netif_msg_ifup(priv))
1321 dev_err(&dev->dev, "hw_reset() failed\n");
1322 return -EINVAL;
1323 }
1324 /* Update the MAC address (in case user has changed it) */
1325 enc28j60_set_hw_macaddr(dev);
1326 /* Enable interrupts */
1327 enc28j60_hw_enable(priv);
1328 /* check link status */
1329 enc28j60_check_link_status(dev);
1330 /* We are now ready to accept transmit requests from
1331 * the queueing layer of the networking.
1332 */
1333 netif_start_queue(dev);
1334
1335 return 0;
1336 }
1337
1338 /* The inverse routine to net_open(). */
1339 static int enc28j60_net_close(struct net_device *dev)
1340 {
1341 struct enc28j60_net *priv = netdev_priv(dev);
1342
1343 if (netif_msg_drv(priv))
1344 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1345
1346 enc28j60_hw_disable(priv);
1347 netif_stop_queue(dev);
1348
1349 return 0;
1350 }
1351
1352 /*
1353 * Set or clear the multicast filter for this adapter
1354 * num_addrs == -1 Promiscuous mode, receive all packets
1355 * num_addrs == 0 Normal mode, filter out multicast packets
1356 * num_addrs > 0 Multicast mode, receive normal and MC packets
1357 */
1358 static void enc28j60_set_multicast_list(struct net_device *dev)
1359 {
1360 struct enc28j60_net *priv = netdev_priv(dev);
1361 int oldfilter = priv->rxfilter;
1362
1363 if (dev->flags & IFF_PROMISC) {
1364 if (netif_msg_link(priv))
1365 dev_info(&dev->dev, "promiscuous mode\n");
1366 priv->rxfilter = RXFILTER_PROMISC;
1367 } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) {
1368 if (netif_msg_link(priv))
1369 dev_info(&dev->dev, "%smulticast mode\n",
1370 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1371 priv->rxfilter = RXFILTER_MULTI;
1372 } else {
1373 if (netif_msg_link(priv))
1374 dev_info(&dev->dev, "normal mode\n");
1375 priv->rxfilter = RXFILTER_NORMAL;
1376 }
1377
1378 if (oldfilter != priv->rxfilter)
1379 schedule_work(&priv->setrx_work);
1380 }
1381
1382 static void enc28j60_setrx_work_handler(struct work_struct *work)
1383 {
1384 struct enc28j60_net *priv =
1385 container_of(work, struct enc28j60_net, setrx_work);
1386
1387 if (priv->rxfilter == RXFILTER_PROMISC) {
1388 if (netif_msg_drv(priv))
1389 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1390 locked_regb_write(priv, ERXFCON, 0x00);
1391 } else if (priv->rxfilter == RXFILTER_MULTI) {
1392 if (netif_msg_drv(priv))
1393 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1394 locked_regb_write(priv, ERXFCON,
1395 ERXFCON_UCEN | ERXFCON_CRCEN |
1396 ERXFCON_BCEN | ERXFCON_MCEN);
1397 } else {
1398 if (netif_msg_drv(priv))
1399 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1400 locked_regb_write(priv, ERXFCON,
1401 ERXFCON_UCEN | ERXFCON_CRCEN |
1402 ERXFCON_BCEN);
1403 }
1404 }
1405
1406 static void enc28j60_restart_work_handler(struct work_struct *work)
1407 {
1408 struct enc28j60_net *priv =
1409 container_of(work, struct enc28j60_net, restart_work);
1410 struct net_device *ndev = priv->netdev;
1411 int ret;
1412
1413 rtnl_lock();
1414 if (netif_running(ndev)) {
1415 enc28j60_net_close(ndev);
1416 ret = enc28j60_net_open(ndev);
1417 if (unlikely(ret)) {
1418 dev_info(&ndev->dev, " could not restart %d\n", ret);
1419 dev_close(ndev);
1420 }
1421 }
1422 rtnl_unlock();
1423 }
1424
1425 /* ......................... ETHTOOL SUPPORT ........................... */
1426
1427 static void
1428 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1429 {
1430 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1431 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1432 strlcpy(info->bus_info,
1433 dev->dev.parent->bus_id, sizeof(info->bus_info));
1434 }
1435
1436 static int
1437 enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1438 {
1439 struct enc28j60_net *priv = netdev_priv(dev);
1440
1441 cmd->transceiver = XCVR_INTERNAL;
1442 cmd->supported = SUPPORTED_10baseT_Half
1443 | SUPPORTED_10baseT_Full
1444 | SUPPORTED_TP;
1445 cmd->speed = SPEED_10;
1446 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1447 cmd->port = PORT_TP;
1448 cmd->autoneg = AUTONEG_DISABLE;
1449
1450 return 0;
1451 }
1452
1453 static int
1454 enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1455 {
1456 return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1457 }
1458
1459 static u32 enc28j60_get_msglevel(struct net_device *dev)
1460 {
1461 struct enc28j60_net *priv = netdev_priv(dev);
1462 return priv->msg_enable;
1463 }
1464
1465 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1466 {
1467 struct enc28j60_net *priv = netdev_priv(dev);
1468 priv->msg_enable = val;
1469 }
1470
1471 static const struct ethtool_ops enc28j60_ethtool_ops = {
1472 .get_settings = enc28j60_get_settings,
1473 .set_settings = enc28j60_set_settings,
1474 .get_drvinfo = enc28j60_get_drvinfo,
1475 .get_msglevel = enc28j60_get_msglevel,
1476 .set_msglevel = enc28j60_set_msglevel,
1477 };
1478
1479 static int enc28j60_chipset_init(struct net_device *dev)
1480 {
1481 struct enc28j60_net *priv = netdev_priv(dev);
1482
1483 return enc28j60_hw_init(priv);
1484 }
1485
1486 static int __devinit enc28j60_probe(struct spi_device *spi)
1487 {
1488 struct net_device *dev;
1489 struct enc28j60_net *priv;
1490 int ret = 0;
1491
1492 if (netif_msg_drv(&debug))
1493 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1494 DRV_VERSION);
1495
1496 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1497 if (!dev) {
1498 if (netif_msg_drv(&debug))
1499 dev_err(&spi->dev, DRV_NAME
1500 ": unable to alloc new ethernet\n");
1501 ret = -ENOMEM;
1502 goto error_alloc;
1503 }
1504 priv = netdev_priv(dev);
1505
1506 priv->netdev = dev; /* priv to netdev reference */
1507 priv->spi = spi; /* priv to spi reference */
1508 priv->msg_enable = netif_msg_init(debug.msg_enable,
1509 ENC28J60_MSG_DEFAULT);
1510 mutex_init(&priv->lock);
1511 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1512 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1513 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1514 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1515 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1516 SET_NETDEV_DEV(dev, &spi->dev);
1517
1518 if (!enc28j60_chipset_init(dev)) {
1519 if (netif_msg_probe(priv))
1520 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1521 ret = -EIO;
1522 goto error_irq;
1523 }
1524 random_ether_addr(dev->dev_addr);
1525 enc28j60_set_hw_macaddr(dev);
1526
1527 ret = request_irq(spi->irq, enc28j60_irq, IRQF_TRIGGER_FALLING,
1528 DRV_NAME, priv);
1529 if (ret < 0) {
1530 if (netif_msg_probe(priv))
1531 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1532 "(ret = %d)\n", spi->irq, ret);
1533 goto error_irq;
1534 }
1535
1536 dev->if_port = IF_PORT_10BASET;
1537 dev->irq = spi->irq;
1538 dev->open = enc28j60_net_open;
1539 dev->stop = enc28j60_net_close;
1540 dev->hard_start_xmit = enc28j60_send_packet;
1541 dev->set_multicast_list = &enc28j60_set_multicast_list;
1542 dev->set_mac_address = enc28j60_set_mac_address;
1543 dev->tx_timeout = &enc28j60_tx_timeout;
1544 dev->watchdog_timeo = TX_TIMEOUT;
1545 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1546
1547 ret = register_netdev(dev);
1548 if (ret) {
1549 if (netif_msg_probe(priv))
1550 dev_err(&spi->dev, "register netdev " DRV_NAME
1551 " failed (ret = %d)\n", ret);
1552 goto error_register;
1553 }
1554 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1555
1556 return 0;
1557
1558 error_register:
1559 free_irq(spi->irq, priv);
1560 error_irq:
1561 free_netdev(dev);
1562 error_alloc:
1563 return ret;
1564 }
1565
1566 static int enc28j60_remove(struct spi_device *spi)
1567 {
1568 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1569
1570 if (netif_msg_drv(priv))
1571 printk(KERN_DEBUG DRV_NAME ": remove\n");
1572
1573 unregister_netdev(priv->netdev);
1574 free_irq(spi->irq, priv);
1575 free_netdev(priv->netdev);
1576
1577 return 0;
1578 }
1579
1580 static struct spi_driver enc28j60_driver = {
1581 .driver = {
1582 .name = DRV_NAME,
1583 .bus = &spi_bus_type,
1584 .owner = THIS_MODULE,
1585 },
1586 .probe = enc28j60_probe,
1587 .remove = __devexit_p(enc28j60_remove),
1588 };
1589
1590 static int __init enc28j60_init(void)
1591 {
1592 return spi_register_driver(&enc28j60_driver);
1593 }
1594
1595 module_init(enc28j60_init);
1596
1597 static void __exit enc28j60_exit(void)
1598 {
1599 spi_unregister_driver(&enc28j60_driver);
1600 }
1601
1602 module_exit(enc28j60_exit);
1603
1604 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1605 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1606 MODULE_LICENSE("GPL");
1607 module_param_named(debug, debug.msg_enable, int, 0);
1608 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
WRT350N Kernel Patches