drivers/net/gianfar_mii.c

   1 /*
   2  * drivers/net/gianfar_mii.c
   3  *
   4  * Gianfar Ethernet Driver -- MIIM bus implementation
   5  * Provides Bus interface for MIIM regs
   6  *
   7  * Author: Andy Fleming
   8  * Maintainer: Kumar Gala
   9  *
  10  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  *
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/string.h>
  21 #include <linux/errno.h>
  22 #include <linux/unistd.h>
  23 #include <linux/slab.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/skbuff.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/crc32.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40 #include <asm/uaccess.h>
  41
  42 #include "gianfar.h"
  43 #include "gianfar_mii.h"
  44
  45 /*
  46  * Write value to the PHY at mii_id at register regnum,
  47  * on the bus attached to the local interface, which may be different from the
  48  * generic mdio bus (tied to a single interface), waiting until the write is
  49  * done before returning. This is helpful in programming interfaces like
  50  * the TBI which control interfaces like onchip SERDES and are always tied to
  51  * the local mdio pins, which may not be the same as system mdio bus, used for
  52  * controlling the external PHYs, for example.
  53  */
  54 <<<<<<< HEAD:drivers/net/gianfar_mii.c
  55 int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id,
  56 =======
  57 int gfar_local_mdio_write(struct gfar_mii __iomem *regs, int mii_id,
  58 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/gianfar_mii.c
  59                           int regnum, u16 value)
  60 {
  61         /* Set the PHY address and the register address we want to write */
  62         gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
  63
  64         /* Write out the value we want */
  65         gfar_write(&regs->miimcon, value);
  66
  67         /* Wait for the transaction to finish */
  68         while (gfar_read(&regs->miimind) & MIIMIND_BUSY)
  69                 cpu_relax();
  70
  71         return 0;
  72 }
  73
  74 /*
  75  * Read the bus for PHY at addr mii_id, register regnum, and
  76  * return the value.  Clears miimcom first.  All PHY operation
  77  * done on the bus attached to the local interface,
  78  * which may be different from the generic mdio bus
  79  * This is helpful in programming interfaces like
  80  * the TBI which, inturn, control interfaces like onchip SERDES
  81  * and are always tied to the local mdio pins, which may not be the
  82  * same as system mdio bus, used for controlling the external PHYs, for eg.
  83  */
  84 <<<<<<< HEAD:drivers/net/gianfar_mii.c
  85 int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum)
  86 =======
  87 int gfar_local_mdio_read(struct gfar_mii __iomem *regs, int mii_id, int regnum)
  88 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/gianfar_mii.c
  89
  90 {
  91         u16 value;
  92
  93         /* Set the PHY address and the register address we want to read */
  94         gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
  95
  96         /* Clear miimcom, and then initiate a read */
  97         gfar_write(&regs->miimcom, 0);
  98         gfar_write(&regs->miimcom, MII_READ_COMMAND);
  99
 100         /* Wait for the transaction to finish */
 101         while (gfar_read(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
 102                 cpu_relax();
 103
 104         /* Grab the value of the register from miimstat */
 105         value = gfar_read(&regs->miimstat);
 106
 107         return value;
 108 }
 109
 110 /* Write value to the PHY at mii_id at register regnum,
 111  * on the bus, waiting until the write is done before returning.
 112  * All PHY configuration is done through the TSEC1 MIIM regs */
 113 int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
 114 {
 115         struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
 116
 117         /* Write to the local MII regs */
 118         return(gfar_local_mdio_write(regs, mii_id, regnum, value));
 119 }
 120
 121 /* Read the bus for PHY at addr mii_id, register regnum, and
 122  * return the value.  Clears miimcom first.  All PHY
 123  * configuration has to be done through the TSEC1 MIIM regs */
 124 int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 125 {
 126         struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
 127
 128         /* Read the local MII regs */
 129         return(gfar_local_mdio_read(regs, mii_id, regnum));
 130 }
 131
 132 /* Reset the MIIM registers, and wait for the bus to free */
 133 int gfar_mdio_reset(struct mii_bus *bus)
 134 {
 135         struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
 136         unsigned int timeout = PHY_INIT_TIMEOUT;
 137
 138         mutex_lock(&bus->mdio_lock);
 139
 140         /* Reset the management interface */
 141         gfar_write(&regs->miimcfg, MIIMCFG_RESET);
 142
 143         /* Setup the MII Mgmt clock speed */
 144         gfar_write(&regs->miimcfg, MIIMCFG_INIT_VALUE);
 145
 146         /* Wait until the bus is free */
 147         while ((gfar_read(&regs->miimind) & MIIMIND_BUSY) &&
 148                         timeout--)
 149                 cpu_relax();
 150
 151         mutex_unlock(&bus->mdio_lock);
 152
 153         if(timeout <= 0) {
 154                 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
 155                                 bus->name);
 156                 return -EBUSY;
 157         }
 158
 159         return 0;
 160 }
 161
 162
 163 int gfar_mdio_probe(struct device *dev)
 164 {
 165         struct platform_device *pdev = to_platform_device(dev);
 166         struct gianfar_mdio_data *pdata;
 167         struct gfar_mii __iomem *regs;
 168         struct mii_bus *new_bus;
 169         struct resource *r;
 170         int err = 0;
 171
 172         if (NULL == dev)
 173                 return -EINVAL;
 174
 175         new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
 176
 177         if (NULL == new_bus)
 178                 return -ENOMEM;
 179
 180         new_bus->name = "Gianfar MII Bus",
 181         new_bus->read = &gfar_mdio_read,
 182         new_bus->write = &gfar_mdio_write,
 183         new_bus->reset = &gfar_mdio_reset,
 184         new_bus->id = pdev->id;
 185
 186         pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;
 187
 188         if (NULL == pdata) {
 189                 printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
 190                 return -ENODEV;
 191         }
 192
 193         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 194
 195         /* Set the PHY base address */
 196         regs = ioremap(r->start, sizeof (struct gfar_mii));
 197
 198         if (NULL == regs) {
 199                 err = -ENOMEM;
 200                 goto reg_map_fail;
 201         }
 202
 203         new_bus->priv = (void __force *)regs;
 204
 205         new_bus->irq = pdata->irq;
 206
 207         new_bus->dev = dev;
 208         dev_set_drvdata(dev, new_bus);
 209
 210         err = mdiobus_register(new_bus);
 211
 212         if (0 != err) {
 213                 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
 214                                 new_bus->name);
 215                 goto bus_register_fail;
 216         }
 217
 218         return 0;
 219
 220 bus_register_fail:
 221         iounmap(regs);
 222 reg_map_fail:
 223         kfree(new_bus);
 224
 225         return err;
 226 }
 227
 228
 229 int gfar_mdio_remove(struct device *dev)
 230 {
 231         struct mii_bus *bus = dev_get_drvdata(dev);
 232
 233         mdiobus_unregister(bus);
 234
 235         dev_set_drvdata(dev, NULL);
 236
 237         iounmap((void __iomem *)bus->priv);
 238         bus->priv = NULL;
 239         kfree(bus);
 240
 241         return 0;
 242 }
 243
 244 static struct device_driver gianfar_mdio_driver = {
 245         .name = "fsl-gianfar_mdio",
 246         .bus = &platform_bus_type,
 247         .probe = gfar_mdio_probe,
 248         .remove = gfar_mdio_remove,
 249 };
 250
 251 int __init gfar_mdio_init(void)
 252 {
 253         return driver_register(&gianfar_mdio_driver);
 254 }
 255
 256 void gfar_mdio_exit(void)
 257 {
 258         driver_unregister(&gianfar_mdio_driver);
 259 }