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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / igb / igb_main.c
blob39740d78aae58c628136f3cb9bdbcaa0d5a5100f
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/tcp.h>
35 #include <linux/ipv6.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/if_ether.h>
45
46 #include "igb.h"
47
48 #define DRV_VERSION "1.0.8-k2"
49 char igb_driver_name[] = "igb";
50 char igb_driver_version[] = DRV_VERSION;
51 static const char igb_driver_string[] =
52 "Intel(R) Gigabit Ethernet Network Driver";
53 static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
54
55
56 static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58 };
59
60 static struct pci_device_id igb_pci_tbl[] = {
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
64 /* required last entry */
65 {0, }
66 };
67
68 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
69
70 void igb_reset(struct igb_adapter *);
71 static int igb_setup_all_tx_resources(struct igb_adapter *);
72 static int igb_setup_all_rx_resources(struct igb_adapter *);
73 static void igb_free_all_tx_resources(struct igb_adapter *);
74 static void igb_free_all_rx_resources(struct igb_adapter *);
75 static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *);
76 static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *);
77 void igb_update_stats(struct igb_adapter *);
78 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
79 static void __devexit igb_remove(struct pci_dev *pdev);
80 static int igb_sw_init(struct igb_adapter *);
81 static int igb_open(struct net_device *);
82 static int igb_close(struct net_device *);
83 static void igb_configure_tx(struct igb_adapter *);
84 static void igb_configure_rx(struct igb_adapter *);
85 static void igb_setup_rctl(struct igb_adapter *);
86 static void igb_clean_all_tx_rings(struct igb_adapter *);
87 static void igb_clean_all_rx_rings(struct igb_adapter *);
88 static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *);
89 static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *);
90 static void igb_set_multi(struct net_device *);
91 static void igb_update_phy_info(unsigned long);
92 static void igb_watchdog(unsigned long);
93 static void igb_watchdog_task(struct work_struct *);
94 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
95 struct igb_ring *);
96 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
97 static struct net_device_stats *igb_get_stats(struct net_device *);
98 static int igb_change_mtu(struct net_device *, int);
99 static int igb_set_mac(struct net_device *, void *);
100 static irqreturn_t igb_intr(int irq, void *);
101 static irqreturn_t igb_intr_msi(int irq, void *);
102 static irqreturn_t igb_msix_other(int irq, void *);
103 static irqreturn_t igb_msix_rx(int irq, void *);
104 static irqreturn_t igb_msix_tx(int irq, void *);
105 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
106 static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *);
107 static int igb_clean(struct napi_struct *, int);
108 static bool igb_clean_rx_irq_adv(struct igb_adapter *,
109 struct igb_ring *, int *, int);
110 static void igb_alloc_rx_buffers_adv(struct igb_adapter *,
111 struct igb_ring *, int);
112 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
113 static void igb_tx_timeout(struct net_device *);
114 static void igb_reset_task(struct work_struct *);
115 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
116 static void igb_vlan_rx_add_vid(struct net_device *, u16);
117 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
118 static void igb_restore_vlan(struct igb_adapter *);
119
120 static int igb_suspend(struct pci_dev *, pm_message_t);
121 #ifdef CONFIG_PM
122 static int igb_resume(struct pci_dev *);
123 #endif
124 static void igb_shutdown(struct pci_dev *);
125
126 #ifdef CONFIG_NET_POLL_CONTROLLER
127 /* for netdump / net console */
128 static void igb_netpoll(struct net_device *);
129 #endif
130
131 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
132 pci_channel_state_t);
133 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
134 static void igb_io_resume(struct pci_dev *);
135
136 static struct pci_error_handlers igb_err_handler = {
137 .error_detected = igb_io_error_detected,
138 .slot_reset = igb_io_slot_reset,
139 .resume = igb_io_resume,
140 };
141
142
143 static struct pci_driver igb_driver = {
144 .name = igb_driver_name,
145 .id_table = igb_pci_tbl,
146 .probe = igb_probe,
147 .remove = __devexit_p(igb_remove),
148 #ifdef CONFIG_PM
149 /* Power Managment Hooks */
150 .suspend = igb_suspend,
151 .resume = igb_resume,
152 #endif
153 .shutdown = igb_shutdown,
154 .err_handler = &igb_err_handler
155 };
156
157 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
158 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_VERSION);
161
162 #ifdef DEBUG
163 /**
164 * igb_get_hw_dev_name - return device name string
165 * used by hardware layer to print debugging information
166 **/
167 char *igb_get_hw_dev_name(struct e1000_hw *hw)
168 {
169 struct igb_adapter *adapter = hw->back;
170 return adapter->netdev->name;
171 }
172 #endif
173
174 /**
175 * igb_init_module - Driver Registration Routine
176 *
177 * igb_init_module is the first routine called when the driver is
178 * loaded. All it does is register with the PCI subsystem.
179 **/
180 static int __init igb_init_module(void)
181 {
182 int ret;
183 printk(KERN_INFO "%s - version %s\n",
184 igb_driver_string, igb_driver_version);
185
186 printk(KERN_INFO "%s\n", igb_copyright);
187
188 ret = pci_register_driver(&igb_driver);
189 return ret;
190 }
191
192 module_init(igb_init_module);
193
194 /**
195 * igb_exit_module - Driver Exit Cleanup Routine
196 *
197 * igb_exit_module is called just before the driver is removed
198 * from memory.
199 **/
200 static void __exit igb_exit_module(void)
201 {
202 pci_unregister_driver(&igb_driver);
203 }
204
205 module_exit(igb_exit_module);
206
207 /**
208 * igb_alloc_queues - Allocate memory for all rings
209 * @adapter: board private structure to initialize
210 *
211 * We allocate one ring per queue at run-time since we don't know the
212 * number of queues at compile-time.
213 **/
214 static int igb_alloc_queues(struct igb_adapter *adapter)
215 {
216 int i;
217
218 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
219 sizeof(struct igb_ring), GFP_KERNEL);
220 if (!adapter->tx_ring)
221 return -ENOMEM;
222
223 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
224 sizeof(struct igb_ring), GFP_KERNEL);
225 if (!adapter->rx_ring) {
226 kfree(adapter->tx_ring);
227 return -ENOMEM;
228 }
229
230 for (i = 0; i < adapter->num_rx_queues; i++) {
231 struct igb_ring *ring = &(adapter->rx_ring[i]);
232 ring->adapter = adapter;
233 ring->itr_register = E1000_ITR;
234
235 if (!ring->napi.poll)
236 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
237 adapter->napi.weight /
238 adapter->num_rx_queues);
239 }
240 return 0;
241 }
242
243 #define IGB_N0_QUEUE -1
244 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
245 int tx_queue, int msix_vector)
246 {
247 u32 msixbm = 0;
248 struct e1000_hw *hw = &adapter->hw;
249 /* The 82575 assigns vectors using a bitmask, which matches the
250 bitmask for the EICR/EIMS/EIMC registers. To assign one
251 or more queues to a vector, we write the appropriate bits
252 into the MSIXBM register for that vector. */
253 if (rx_queue > IGB_N0_QUEUE) {
254 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
255 adapter->rx_ring[rx_queue].eims_value = msixbm;
256 }
257 if (tx_queue > IGB_N0_QUEUE) {
258 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
259 adapter->tx_ring[tx_queue].eims_value =
260 E1000_EICR_TX_QUEUE0 << tx_queue;
261 }
262 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
263 }
264
265 /**
266 * igb_configure_msix - Configure MSI-X hardware
267 *
268 * igb_configure_msix sets up the hardware to properly
269 * generate MSI-X interrupts.
270 **/
271 static void igb_configure_msix(struct igb_adapter *adapter)
272 {
273 u32 tmp;
274 int i, vector = 0;
275 struct e1000_hw *hw = &adapter->hw;
276
277 adapter->eims_enable_mask = 0;
278
279 for (i = 0; i < adapter->num_tx_queues; i++) {
280 struct igb_ring *tx_ring = &adapter->tx_ring[i];
281 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
282 adapter->eims_enable_mask |= tx_ring->eims_value;
283 if (tx_ring->itr_val)
284 writel(1000000000 / (tx_ring->itr_val * 256),
285 hw->hw_addr + tx_ring->itr_register);
286 else
287 writel(1, hw->hw_addr + tx_ring->itr_register);
288 }
289
290 for (i = 0; i < adapter->num_rx_queues; i++) {
291 struct igb_ring *rx_ring = &adapter->rx_ring[i];
292 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
293 adapter->eims_enable_mask |= rx_ring->eims_value;
294 if (rx_ring->itr_val)
295 writel(1000000000 / (rx_ring->itr_val * 256),
296 hw->hw_addr + rx_ring->itr_register);
297 else
298 writel(1, hw->hw_addr + rx_ring->itr_register);
299 }
300
301
302 /* set vector for other causes, i.e. link changes */
303 array_wr32(E1000_MSIXBM(0), vector++,
304 E1000_EIMS_OTHER);
305
306 /* disable IAM for ICR interrupt bits */
307 wr32(E1000_IAM, 0);
308
309 tmp = rd32(E1000_CTRL_EXT);
310 /* enable MSI-X PBA support*/
311 tmp |= E1000_CTRL_EXT_PBA_CLR;
312
313 /* Auto-Mask interrupts upon ICR read. */
314 tmp |= E1000_CTRL_EXT_EIAME;
315 tmp |= E1000_CTRL_EXT_IRCA;
316
317 wr32(E1000_CTRL_EXT, tmp);
318 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
319
320 wrfl();
321 }
322
323 /**
324 * igb_request_msix - Initialize MSI-X interrupts
325 *
326 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
327 * kernel.
328 **/
329 static int igb_request_msix(struct igb_adapter *adapter)
330 {
331 struct net_device *netdev = adapter->netdev;
332 int i, err = 0, vector = 0;
333
334 vector = 0;
335
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 struct igb_ring *ring = &(adapter->tx_ring[i]);
338 sprintf(ring->name, "%s-tx%d", netdev->name, i);
339 err = request_irq(adapter->msix_entries[vector].vector,
340 &igb_msix_tx, 0, ring->name,
341 &(adapter->tx_ring[i]));
342 if (err)
343 goto out;
344 ring->itr_register = E1000_EITR(0) + (vector << 2);
345 ring->itr_val = adapter->itr;
346 vector++;
347 }
348 for (i = 0; i < adapter->num_rx_queues; i++) {
349 struct igb_ring *ring = &(adapter->rx_ring[i]);
350 if (strlen(netdev->name) < (IFNAMSIZ - 5))
351 sprintf(ring->name, "%s-rx%d", netdev->name, i);
352 else
353 memcpy(ring->name, netdev->name, IFNAMSIZ);
354 err = request_irq(adapter->msix_entries[vector].vector,
355 &igb_msix_rx, 0, ring->name,
356 &(adapter->rx_ring[i]));
357 if (err)
358 goto out;
359 ring->itr_register = E1000_EITR(0) + (vector << 2);
360 ring->itr_val = adapter->itr;
361 vector++;
362 }
363
364 err = request_irq(adapter->msix_entries[vector].vector,
365 &igb_msix_other, 0, netdev->name, netdev);
366 if (err)
367 goto out;
368
369 adapter->napi.poll = igb_clean_rx_ring_msix;
370 for (i = 0; i < adapter->num_rx_queues; i++)
371 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
372 igb_configure_msix(adapter);
373 return 0;
374 out:
375 return err;
376 }
377
378 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
379 {
380 if (adapter->msix_entries) {
381 pci_disable_msix(adapter->pdev);
382 kfree(adapter->msix_entries);
383 adapter->msix_entries = NULL;
384 } else if (adapter->msi_enabled)
385 pci_disable_msi(adapter->pdev);
386 return;
387 }
388
389
390 /**
391 * igb_set_interrupt_capability - set MSI or MSI-X if supported
392 *
393 * Attempt to configure interrupts using the best available
394 * capabilities of the hardware and kernel.
395 **/
396 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
397 {
398 int err;
399 int numvecs, i;
400
401 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
402 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
403 GFP_KERNEL);
404 if (!adapter->msix_entries)
405 goto msi_only;
406
407 for (i = 0; i < numvecs; i++)
408 adapter->msix_entries[i].entry = i;
409
410 err = pci_enable_msix(adapter->pdev,
411 adapter->msix_entries,
412 numvecs);
413 if (err == 0)
414 return;
415
416 igb_reset_interrupt_capability(adapter);
417
418 /* If we can't do MSI-X, try MSI */
419 msi_only:
420 adapter->num_rx_queues = 1;
421 if (!pci_enable_msi(adapter->pdev))
422 adapter->msi_enabled = 1;
423 return;
424 }
425
426 /**
427 * igb_request_irq - initialize interrupts
428 *
429 * Attempts to configure interrupts using the best available
430 * capabilities of the hardware and kernel.
431 **/
432 static int igb_request_irq(struct igb_adapter *adapter)
433 {
434 struct net_device *netdev = adapter->netdev;
435 struct e1000_hw *hw = &adapter->hw;
436 int err = 0;
437
438 if (adapter->msix_entries) {
439 err = igb_request_msix(adapter);
440 if (!err) {
441 /* enable IAM, auto-mask,
442 <<<<<<< HEAD:drivers/net/igb/igb_main.c
443 * DO NOT USE EIAME or IAME in legacy mode */
444 =======
445 * DO NOT USE EIAM or IAM in legacy mode */
446 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
447 wr32(E1000_IAM, IMS_ENABLE_MASK);
448 goto request_done;
449 }
450 /* fall back to MSI */
451 igb_reset_interrupt_capability(adapter);
452 if (!pci_enable_msi(adapter->pdev))
453 adapter->msi_enabled = 1;
454 igb_free_all_tx_resources(adapter);
455 igb_free_all_rx_resources(adapter);
456 adapter->num_rx_queues = 1;
457 igb_alloc_queues(adapter);
458 }
459 if (adapter->msi_enabled) {
460 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
461 netdev->name, netdev);
462 if (!err)
463 goto request_done;
464 /* fall back to legacy interrupts */
465 igb_reset_interrupt_capability(adapter);
466 adapter->msi_enabled = 0;
467 }
468
469 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
470 netdev->name, netdev);
471
472 <<<<<<< HEAD:drivers/net/igb/igb_main.c
473 if (err) {
474 =======
475 if (err)
476 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
477 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
478 err);
479 <<<<<<< HEAD:drivers/net/igb/igb_main.c
480 goto request_done;
481 }
482
483 /* enable IAM, auto-mask */
484 wr32(E1000_IAM, IMS_ENABLE_MASK);
485 =======
486 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
487
488 request_done:
489 return err;
490 }
491
492 static void igb_free_irq(struct igb_adapter *adapter)
493 {
494 struct net_device *netdev = adapter->netdev;
495
496 if (adapter->msix_entries) {
497 int vector = 0, i;
498
499 for (i = 0; i < adapter->num_tx_queues; i++)
500 free_irq(adapter->msix_entries[vector++].vector,
501 &(adapter->tx_ring[i]));
502 for (i = 0; i < adapter->num_rx_queues; i++)
503 free_irq(adapter->msix_entries[vector++].vector,
504 &(adapter->rx_ring[i]));
505
506 free_irq(adapter->msix_entries[vector++].vector, netdev);
507 return;
508 }
509
510 free_irq(adapter->pdev->irq, netdev);
511 }
512
513 /**
514 * igb_irq_disable - Mask off interrupt generation on the NIC
515 * @adapter: board private structure
516 **/
517 static void igb_irq_disable(struct igb_adapter *adapter)
518 {
519 struct e1000_hw *hw = &adapter->hw;
520
521 if (adapter->msix_entries) {
522 wr32(E1000_EIMC, ~0);
523 wr32(E1000_EIAC, 0);
524 }
525 wr32(E1000_IMC, ~0);
526 wrfl();
527 synchronize_irq(adapter->pdev->irq);
528 }
529
530 /**
531 * igb_irq_enable - Enable default interrupt generation settings
532 * @adapter: board private structure
533 **/
534 static void igb_irq_enable(struct igb_adapter *adapter)
535 {
536 struct e1000_hw *hw = &adapter->hw;
537
538 if (adapter->msix_entries) {
539 wr32(E1000_EIMS,
540 adapter->eims_enable_mask);
541 wr32(E1000_EIAC,
542 adapter->eims_enable_mask);
543 wr32(E1000_IMS, E1000_IMS_LSC);
544 } else
545 wr32(E1000_IMS, IMS_ENABLE_MASK);
546 }
547
548 static void igb_update_mng_vlan(struct igb_adapter *adapter)
549 {
550 struct net_device *netdev = adapter->netdev;
551 u16 vid = adapter->hw.mng_cookie.vlan_id;
552 u16 old_vid = adapter->mng_vlan_id;
553 if (adapter->vlgrp) {
554 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
555 if (adapter->hw.mng_cookie.status &
556 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
557 igb_vlan_rx_add_vid(netdev, vid);
558 adapter->mng_vlan_id = vid;
559 } else
560 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
561
562 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
563 (vid != old_vid) &&
564 !vlan_group_get_device(adapter->vlgrp, old_vid))
565 igb_vlan_rx_kill_vid(netdev, old_vid);
566 } else
567 adapter->mng_vlan_id = vid;
568 }
569 }
570
571 /**
572 * igb_release_hw_control - release control of the h/w to f/w
573 * @adapter: address of board private structure
574 *
575 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
576 * For ASF and Pass Through versions of f/w this means that the
577 * driver is no longer loaded.
578 *
579 **/
580 static void igb_release_hw_control(struct igb_adapter *adapter)
581 {
582 struct e1000_hw *hw = &adapter->hw;
583 u32 ctrl_ext;
584
585 /* Let firmware take over control of h/w */
586 ctrl_ext = rd32(E1000_CTRL_EXT);
587 wr32(E1000_CTRL_EXT,
588 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
589 }
590
591
592 /**
593 * igb_get_hw_control - get control of the h/w from f/w
594 * @adapter: address of board private structure
595 *
596 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
597 * For ASF and Pass Through versions of f/w this means that
598 * the driver is loaded.
599 *
600 **/
601 static void igb_get_hw_control(struct igb_adapter *adapter)
602 {
603 struct e1000_hw *hw = &adapter->hw;
604 u32 ctrl_ext;
605
606 /* Let firmware know the driver has taken over */
607 ctrl_ext = rd32(E1000_CTRL_EXT);
608 wr32(E1000_CTRL_EXT,
609 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
610 }
611
612 static void igb_init_manageability(struct igb_adapter *adapter)
613 {
614 struct e1000_hw *hw = &adapter->hw;
615
616 if (adapter->en_mng_pt) {
617 u32 manc2h = rd32(E1000_MANC2H);
618 u32 manc = rd32(E1000_MANC);
619
620 <<<<<<< HEAD:drivers/net/igb/igb_main.c
621 /* disable hardware interception of ARP */
622 manc &= ~(E1000_MANC_ARP_EN);
623
624 =======
625 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
626 /* enable receiving management packets to the host */
627 /* this will probably generate destination unreachable messages
628 * from the host OS, but the packets will be handled on SMBUS */
629 manc |= E1000_MANC_EN_MNG2HOST;
630 #define E1000_MNG2HOST_PORT_623 (1 << 5)
631 #define E1000_MNG2HOST_PORT_664 (1 << 6)
632 manc2h |= E1000_MNG2HOST_PORT_623;
633 manc2h |= E1000_MNG2HOST_PORT_664;
634 wr32(E1000_MANC2H, manc2h);
635
636 wr32(E1000_MANC, manc);
637 }
638 }
639
640 <<<<<<< HEAD:drivers/net/igb/igb_main.c
641 static void igb_release_manageability(struct igb_adapter *adapter)
642 {
643 struct e1000_hw *hw = &adapter->hw;
644
645 if (adapter->en_mng_pt) {
646 u32 manc = rd32(E1000_MANC);
647
648 /* re-enable hardware interception of ARP */
649 manc |= E1000_MANC_ARP_EN;
650 manc &= ~E1000_MANC_EN_MNG2HOST;
651
652 /* don't explicitly have to mess with MANC2H since
653 * MANC has an enable disable that gates MANC2H */
654
655 /* XXX stop the hardware watchdog ? */
656 wr32(E1000_MANC, manc);
657 }
658 }
659
660 =======
661 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
662 /**
663 * igb_configure - configure the hardware for RX and TX
664 * @adapter: private board structure
665 **/
666 static void igb_configure(struct igb_adapter *adapter)
667 {
668 struct net_device *netdev = adapter->netdev;
669 int i;
670
671 igb_get_hw_control(adapter);
672 igb_set_multi(netdev);
673
674 igb_restore_vlan(adapter);
675 igb_init_manageability(adapter);
676
677 igb_configure_tx(adapter);
678 igb_setup_rctl(adapter);
679 igb_configure_rx(adapter);
680 /* call IGB_DESC_UNUSED which always leaves
681 * at least 1 descriptor unused to make sure
682 * next_to_use != next_to_clean */
683 for (i = 0; i < adapter->num_rx_queues; i++) {
684 struct igb_ring *ring = &adapter->rx_ring[i];
685 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring));
686 }
687
688
689 adapter->tx_queue_len = netdev->tx_queue_len;
690 }
691
692
693 /**
694 * igb_up - Open the interface and prepare it to handle traffic
695 * @adapter: board private structure
696 **/
697
698 int igb_up(struct igb_adapter *adapter)
699 {
700 struct e1000_hw *hw = &adapter->hw;
701 int i;
702
703 /* hardware has been reset, we need to reload some things */
704 igb_configure(adapter);
705
706 clear_bit(__IGB_DOWN, &adapter->state);
707
708 napi_enable(&adapter->napi);
709
710 if (adapter->msix_entries) {
711 for (i = 0; i < adapter->num_rx_queues; i++)
712 napi_enable(&adapter->rx_ring[i].napi);
713 igb_configure_msix(adapter);
714 }
715
716 /* Clear any pending interrupts. */
717 rd32(E1000_ICR);
718 igb_irq_enable(adapter);
719
720 /* Fire a link change interrupt to start the watchdog. */
721 wr32(E1000_ICS, E1000_ICS_LSC);
722 return 0;
723 }
724
725 void igb_down(struct igb_adapter *adapter)
726 {
727 struct e1000_hw *hw = &adapter->hw;
728 struct net_device *netdev = adapter->netdev;
729 u32 tctl, rctl;
730 int i;
731
732 /* signal that we're down so the interrupt handler does not
733 * reschedule our watchdog timer */
734 set_bit(__IGB_DOWN, &adapter->state);
735
736 /* disable receives in the hardware */
737 rctl = rd32(E1000_RCTL);
738 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
739 /* flush and sleep below */
740
741 netif_stop_queue(netdev);
742
743 /* disable transmits in the hardware */
744 tctl = rd32(E1000_TCTL);
745 tctl &= ~E1000_TCTL_EN;
746 wr32(E1000_TCTL, tctl);
747 /* flush both disables and wait for them to finish */
748 wrfl();
749 msleep(10);
750
751 napi_disable(&adapter->napi);
752
753 if (adapter->msix_entries)
754 for (i = 0; i < adapter->num_rx_queues; i++)
755 napi_disable(&adapter->rx_ring[i].napi);
756 igb_irq_disable(adapter);
757
758 del_timer_sync(&adapter->watchdog_timer);
759 del_timer_sync(&adapter->phy_info_timer);
760
761 netdev->tx_queue_len = adapter->tx_queue_len;
762 netif_carrier_off(netdev);
763 adapter->link_speed = 0;
764 adapter->link_duplex = 0;
765
766 igb_reset(adapter);
767 igb_clean_all_tx_rings(adapter);
768 igb_clean_all_rx_rings(adapter);
769 }
770
771 void igb_reinit_locked(struct igb_adapter *adapter)
772 {
773 WARN_ON(in_interrupt());
774 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
775 msleep(1);
776 igb_down(adapter);
777 igb_up(adapter);
778 clear_bit(__IGB_RESETTING, &adapter->state);
779 }
780
781 void igb_reset(struct igb_adapter *adapter)
782 {
783 struct e1000_hw *hw = &adapter->hw;
784 struct e1000_fc_info *fc = &adapter->hw.fc;
785 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
786 u16 hwm;
787
788 /* Repartition Pba for greater than 9k mtu
789 * To take effect CTRL.RST is required.
790 */
791 pba = E1000_PBA_34K;
792
793 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
794 /* adjust PBA for jumbo frames */
795 wr32(E1000_PBA, pba);
796
797 /* To maintain wire speed transmits, the Tx FIFO should be
798 * large enough to accommodate two full transmit packets,
799 * rounded up to the next 1KB and expressed in KB. Likewise,
800 * the Rx FIFO should be large enough to accommodate at least
801 * one full receive packet and is similarly rounded up and
802 * expressed in KB. */
803 pba = rd32(E1000_PBA);
804 /* upper 16 bits has Tx packet buffer allocation size in KB */
805 tx_space = pba >> 16;
806 /* lower 16 bits has Rx packet buffer allocation size in KB */
807 pba &= 0xffff;
808 /* the tx fifo also stores 16 bytes of information about the tx
809 * but don't include ethernet FCS because hardware appends it */
810 min_tx_space = (adapter->max_frame_size +
811 sizeof(struct e1000_tx_desc) -
812 ETH_FCS_LEN) * 2;
813 min_tx_space = ALIGN(min_tx_space, 1024);
814 min_tx_space >>= 10;
815 /* software strips receive CRC, so leave room for it */
816 min_rx_space = adapter->max_frame_size;
817 min_rx_space = ALIGN(min_rx_space, 1024);
818 min_rx_space >>= 10;
819
820 /* If current Tx allocation is less than the min Tx FIFO size,
821 * and the min Tx FIFO size is less than the current Rx FIFO
822 * allocation, take space away from current Rx allocation */
823 if (tx_space < min_tx_space &&
824 ((min_tx_space - tx_space) < pba)) {
825 pba = pba - (min_tx_space - tx_space);
826
827 /* if short on rx space, rx wins and must trump tx
828 * adjustment */
829 if (pba < min_rx_space)
830 pba = min_rx_space;
831 }
832 }
833 wr32(E1000_PBA, pba);
834
835 /* flow control settings */
836 /* The high water mark must be low enough to fit one full frame
837 * (or the size used for early receive) above it in the Rx FIFO.
838 * Set it to the lower of:
839 * - 90% of the Rx FIFO size, or
840 * - the full Rx FIFO size minus one full frame */
841 hwm = min(((pba << 10) * 9 / 10),
842 ((pba << 10) - adapter->max_frame_size));
843
844 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
845 fc->low_water = fc->high_water - 8;
846 fc->pause_time = 0xFFFF;
847 fc->send_xon = 1;
848 fc->type = fc->original_type;
849
850 /* Allow time for pending master requests to run */
851 adapter->hw.mac.ops.reset_hw(&adapter->hw);
852 wr32(E1000_WUC, 0);
853
854 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
855 dev_err(&adapter->pdev->dev, "Hardware Error\n");
856
857 igb_update_mng_vlan(adapter);
858
859 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
860 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
861
862 igb_reset_adaptive(&adapter->hw);
863 <<<<<<< HEAD:drivers/net/igb/igb_main.c
864 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
865 igb_release_manageability(adapter);
866 =======
867 if (adapter->hw.phy.ops.get_phy_info)
868 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
869 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
870 }
871
872 /**
873 * igb_probe - Device Initialization Routine
874 * @pdev: PCI device information struct
875 * @ent: entry in igb_pci_tbl
876 *
877 * Returns 0 on success, negative on failure
878 *
879 * igb_probe initializes an adapter identified by a pci_dev structure.
880 * The OS initialization, configuring of the adapter private structure,
881 * and a hardware reset occur.
882 **/
883 static int __devinit igb_probe(struct pci_dev *pdev,
884 const struct pci_device_id *ent)
885 {
886 struct net_device *netdev;
887 struct igb_adapter *adapter;
888 struct e1000_hw *hw;
889 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
890 unsigned long mmio_start, mmio_len;
891 static int cards_found;
892 int i, err, pci_using_dac;
893 u16 eeprom_data = 0;
894 u16 eeprom_apme_mask = IGB_EEPROM_APME;
895 u32 part_num;
896
897 err = pci_enable_device(pdev);
898 if (err)
899 return err;
900
901 pci_using_dac = 0;
902 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
903 if (!err) {
904 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
905 if (!err)
906 pci_using_dac = 1;
907 } else {
908 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
909 if (err) {
910 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
911 if (err) {
912 dev_err(&pdev->dev, "No usable DMA "
913 "configuration, aborting\n");
914 goto err_dma;
915 }
916 }
917 }
918
919 err = pci_request_regions(pdev, igb_driver_name);
920 if (err)
921 goto err_pci_reg;
922
923 pci_set_master(pdev);
924
925 err = -ENOMEM;
926 netdev = alloc_etherdev(sizeof(struct igb_adapter));
927 if (!netdev)
928 goto err_alloc_etherdev;
929
930 SET_NETDEV_DEV(netdev, &pdev->dev);
931
932 pci_set_drvdata(pdev, netdev);
933 adapter = netdev_priv(netdev);
934 adapter->netdev = netdev;
935 adapter->pdev = pdev;
936 hw = &adapter->hw;
937 hw->back = adapter;
938 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
939
940 mmio_start = pci_resource_start(pdev, 0);
941 mmio_len = pci_resource_len(pdev, 0);
942
943 err = -EIO;
944 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
945 if (!adapter->hw.hw_addr)
946 goto err_ioremap;
947
948 netdev->open = &igb_open;
949 netdev->stop = &igb_close;
950 netdev->get_stats = &igb_get_stats;
951 netdev->set_multicast_list = &igb_set_multi;
952 netdev->set_mac_address = &igb_set_mac;
953 netdev->change_mtu = &igb_change_mtu;
954 netdev->do_ioctl = &igb_ioctl;
955 igb_set_ethtool_ops(netdev);
956 netdev->tx_timeout = &igb_tx_timeout;
957 netdev->watchdog_timeo = 5 * HZ;
958 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
959 netdev->vlan_rx_register = igb_vlan_rx_register;
960 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
961 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
962 #ifdef CONFIG_NET_POLL_CONTROLLER
963 netdev->poll_controller = igb_netpoll;
964 #endif
965 netdev->hard_start_xmit = &igb_xmit_frame_adv;
966
967 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
968
969 netdev->mem_start = mmio_start;
970 netdev->mem_end = mmio_start + mmio_len;
971
972 adapter->bd_number = cards_found;
973
974 /* PCI config space info */
975 hw->vendor_id = pdev->vendor;
976 hw->device_id = pdev->device;
977 hw->revision_id = pdev->revision;
978 hw->subsystem_vendor_id = pdev->subsystem_vendor;
979 hw->subsystem_device_id = pdev->subsystem_device;
980
981 /* setup the private structure */
982 hw->back = adapter;
983 /* Copy the default MAC, PHY and NVM function pointers */
984 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
985 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
986 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
987 /* Initialize skew-specific constants */
988 err = ei->get_invariants(hw);
989 if (err)
990 goto err_hw_init;
991
992 err = igb_sw_init(adapter);
993 if (err)
994 goto err_sw_init;
995
996 igb_get_bus_info_pcie(hw);
997
998 hw->phy.autoneg_wait_to_complete = false;
999 hw->mac.adaptive_ifs = true;
1000
1001 /* Copper options */
1002 if (hw->phy.media_type == e1000_media_type_copper) {
1003 hw->phy.mdix = AUTO_ALL_MODES;
1004 hw->phy.disable_polarity_correction = false;
1005 hw->phy.ms_type = e1000_ms_hw_default;
1006 }
1007
1008 if (igb_check_reset_block(hw))
1009 dev_info(&pdev->dev,
1010 "PHY reset is blocked due to SOL/IDER session.\n");
1011
1012 netdev->features = NETIF_F_SG |
1013 NETIF_F_HW_CSUM |
1014 NETIF_F_HW_VLAN_TX |
1015 NETIF_F_HW_VLAN_RX |
1016 NETIF_F_HW_VLAN_FILTER;
1017
1018 netdev->features |= NETIF_F_TSO;
1019
1020 netdev->features |= NETIF_F_TSO6;
1021 if (pci_using_dac)
1022 netdev->features |= NETIF_F_HIGHDMA;
1023
1024 netdev->features |= NETIF_F_LLTX;
1025 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1026
1027 /* before reading the NVM, reset the controller to put the device in a
1028 * known good starting state */
1029 hw->mac.ops.reset_hw(hw);
1030
1031 /* make sure the NVM is good */
1032 if (igb_validate_nvm_checksum(hw) < 0) {
1033 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1034 err = -EIO;
1035 goto err_eeprom;
1036 }
1037
1038 /* copy the MAC address out of the NVM */
1039 if (hw->mac.ops.read_mac_addr(hw))
1040 dev_err(&pdev->dev, "NVM Read Error\n");
1041
1042 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1043 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1044
1045 if (!is_valid_ether_addr(netdev->perm_addr)) {
1046 dev_err(&pdev->dev, "Invalid MAC Address\n");
1047 err = -EIO;
1048 goto err_eeprom;
1049 }
1050
1051 init_timer(&adapter->watchdog_timer);
1052 adapter->watchdog_timer.function = &igb_watchdog;
1053 adapter->watchdog_timer.data = (unsigned long) adapter;
1054
1055 init_timer(&adapter->phy_info_timer);
1056 adapter->phy_info_timer.function = &igb_update_phy_info;
1057 adapter->phy_info_timer.data = (unsigned long) adapter;
1058
1059 INIT_WORK(&adapter->reset_task, igb_reset_task);
1060 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1061
1062 /* Initialize link & ring properties that are user-changeable */
1063 adapter->tx_ring->count = 256;
1064 for (i = 0; i < adapter->num_tx_queues; i++)
1065 adapter->tx_ring[i].count = adapter->tx_ring->count;
1066 adapter->rx_ring->count = 256;
1067 for (i = 0; i < adapter->num_rx_queues; i++)
1068 adapter->rx_ring[i].count = adapter->rx_ring->count;
1069
1070 adapter->fc_autoneg = true;
1071 hw->mac.autoneg = true;
1072 hw->phy.autoneg_advertised = 0x2f;
1073
1074 hw->fc.original_type = e1000_fc_default;
1075 hw->fc.type = e1000_fc_default;
1076
1077 adapter->itr_setting = 3;
1078 adapter->itr = IGB_START_ITR;
1079
1080 igb_validate_mdi_setting(hw);
1081
1082 adapter->rx_csum = 1;
1083
1084 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1085 * enable the ACPI Magic Packet filter
1086 */
1087
1088 if (hw->bus.func == 0 ||
1089 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1090 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1091 &eeprom_data);
1092
1093 if (eeprom_data & eeprom_apme_mask)
1094 adapter->eeprom_wol |= E1000_WUFC_MAG;
1095
1096 /* now that we have the eeprom settings, apply the special cases where
1097 * the eeprom may be wrong or the board simply won't support wake on
1098 * lan on a particular port */
1099 switch (pdev->device) {
1100 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1101 adapter->eeprom_wol = 0;
1102 break;
1103 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1104 /* Wake events only supported on port A for dual fiber
1105 * regardless of eeprom setting */
1106 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1107 adapter->eeprom_wol = 0;
1108 break;
1109 }
1110
1111 /* initialize the wol settings based on the eeprom settings */
1112 adapter->wol = adapter->eeprom_wol;
1113
1114 /* reset the hardware with the new settings */
1115 igb_reset(adapter);
1116
1117 /* let the f/w know that the h/w is now under the control of the
1118 * driver. */
1119 igb_get_hw_control(adapter);
1120
1121 /* tell the stack to leave us alone until igb_open() is called */
1122 netif_carrier_off(netdev);
1123 netif_stop_queue(netdev);
1124
1125 strcpy(netdev->name, "eth%d");
1126 err = register_netdev(netdev);
1127 if (err)
1128 goto err_register;
1129
1130 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1131 /* print bus type/speed/width info */
1132 dev_info(&pdev->dev,
1133 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1134 netdev->name,
1135 ((hw->bus.speed == e1000_bus_speed_2500)
1136 ? "2.5Gb/s" : "unknown"),
1137 ((hw->bus.width == e1000_bus_width_pcie_x4)
1138 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1139 ? "Width x1" : "unknown"),
1140 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1141 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1142
1143 igb_read_part_num(hw, &part_num);
1144 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1145 (part_num >> 8), (part_num & 0xff));
1146
1147 dev_info(&pdev->dev,
1148 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1149 adapter->msix_entries ? "MSI-X" :
1150 adapter->msi_enabled ? "MSI" : "legacy",
1151 adapter->num_rx_queues, adapter->num_tx_queues);
1152
1153 cards_found++;
1154 return 0;
1155
1156 err_register:
1157 igb_release_hw_control(adapter);
1158 err_eeprom:
1159 if (!igb_check_reset_block(hw))
1160 hw->phy.ops.reset_phy(hw);
1161
1162 if (hw->flash_address)
1163 iounmap(hw->flash_address);
1164
1165 igb_remove_device(hw);
1166 kfree(adapter->tx_ring);
1167 kfree(adapter->rx_ring);
1168 err_sw_init:
1169 err_hw_init:
1170 iounmap(hw->hw_addr);
1171 err_ioremap:
1172 free_netdev(netdev);
1173 err_alloc_etherdev:
1174 pci_release_regions(pdev);
1175 err_pci_reg:
1176 err_dma:
1177 pci_disable_device(pdev);
1178 return err;
1179 }
1180
1181 /**
1182 * igb_remove - Device Removal Routine
1183 * @pdev: PCI device information struct
1184 *
1185 * igb_remove is called by the PCI subsystem to alert the driver
1186 * that it should release a PCI device. The could be caused by a
1187 * Hot-Plug event, or because the driver is going to be removed from
1188 * memory.
1189 **/
1190 static void __devexit igb_remove(struct pci_dev *pdev)
1191 {
1192 struct net_device *netdev = pci_get_drvdata(pdev);
1193 struct igb_adapter *adapter = netdev_priv(netdev);
1194
1195 /* flush_scheduled work may reschedule our watchdog task, so
1196 * explicitly disable watchdog tasks from being rescheduled */
1197 set_bit(__IGB_DOWN, &adapter->state);
1198 del_timer_sync(&adapter->watchdog_timer);
1199 del_timer_sync(&adapter->phy_info_timer);
1200
1201 flush_scheduled_work();
1202
1203 <<<<<<< HEAD:drivers/net/igb/igb_main.c
1204
1205 igb_release_manageability(adapter);
1206
1207 =======
1208 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
1209 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1210 * would have already happened in close and is redundant. */
1211 igb_release_hw_control(adapter);
1212
1213 unregister_netdev(netdev);
1214
1215 if (!igb_check_reset_block(&adapter->hw))
1216 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1217
1218 igb_remove_device(&adapter->hw);
1219 igb_reset_interrupt_capability(adapter);
1220
1221 kfree(adapter->tx_ring);
1222 kfree(adapter->rx_ring);
1223
1224 iounmap(adapter->hw.hw_addr);
1225 if (adapter->hw.flash_address)
1226 iounmap(adapter->hw.flash_address);
1227 pci_release_regions(pdev);
1228
1229 free_netdev(netdev);
1230
1231 pci_disable_device(pdev);
1232 }
1233
1234 /**
1235 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1236 * @adapter: board private structure to initialize
1237 *
1238 * igb_sw_init initializes the Adapter private data structure.
1239 * Fields are initialized based on PCI device information and
1240 * OS network device settings (MTU size).
1241 **/
1242 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1243 {
1244 struct e1000_hw *hw = &adapter->hw;
1245 struct net_device *netdev = adapter->netdev;
1246 struct pci_dev *pdev = adapter->pdev;
1247
1248 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1249
1250 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1251 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1252 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1253 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1254
1255 /* Number of supported queues. */
1256 /* Having more queues than CPUs doesn't make sense. */
1257 adapter->num_tx_queues = 1;
1258 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1259
1260 igb_set_interrupt_capability(adapter);
1261
1262 if (igb_alloc_queues(adapter)) {
1263 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1264 return -ENOMEM;
1265 }
1266
1267 /* Explicitly disable IRQ since the NIC can be in any state. */
1268 igb_irq_disable(adapter);
1269
1270 set_bit(__IGB_DOWN, &adapter->state);
1271 return 0;
1272 }
1273
1274 /**
1275 * igb_open - Called when a network interface is made active
1276 * @netdev: network interface device structure
1277 *
1278 * Returns 0 on success, negative value on failure
1279 *
1280 * The open entry point is called when a network interface is made
1281 * active by the system (IFF_UP). At this point all resources needed
1282 * for transmit and receive operations are allocated, the interrupt
1283 * handler is registered with the OS, the watchdog timer is started,
1284 * and the stack is notified that the interface is ready.
1285 **/
1286 static int igb_open(struct net_device *netdev)
1287 {
1288 struct igb_adapter *adapter = netdev_priv(netdev);
1289 struct e1000_hw *hw = &adapter->hw;
1290 int err;
1291 int i;
1292
1293 /* disallow open during test */
1294 if (test_bit(__IGB_TESTING, &adapter->state))
1295 return -EBUSY;
1296
1297 /* allocate transmit descriptors */
1298 err = igb_setup_all_tx_resources(adapter);
1299 if (err)
1300 goto err_setup_tx;
1301
1302 /* allocate receive descriptors */
1303 err = igb_setup_all_rx_resources(adapter);
1304 if (err)
1305 goto err_setup_rx;
1306
1307 /* e1000_power_up_phy(adapter); */
1308
1309 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1310 if ((adapter->hw.mng_cookie.status &
1311 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1312 igb_update_mng_vlan(adapter);
1313
1314 /* before we allocate an interrupt, we must be ready to handle it.
1315 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1316 * as soon as we call pci_request_irq, so we have to setup our
1317 * clean_rx handler before we do so. */
1318 igb_configure(adapter);
1319
1320 err = igb_request_irq(adapter);
1321 if (err)
1322 goto err_req_irq;
1323
1324 /* From here on the code is the same as igb_up() */
1325 clear_bit(__IGB_DOWN, &adapter->state);
1326
1327 napi_enable(&adapter->napi);
1328 if (adapter->msix_entries)
1329 for (i = 0; i < adapter->num_rx_queues; i++)
1330 napi_enable(&adapter->rx_ring[i].napi);
1331
1332 igb_irq_enable(adapter);
1333
1334 /* Clear any pending interrupts. */
1335 rd32(E1000_ICR);
1336 /* Fire a link status change interrupt to start the watchdog. */
1337 wr32(E1000_ICS, E1000_ICS_LSC);
1338
1339 return 0;
1340
1341 err_req_irq:
1342 igb_release_hw_control(adapter);
1343 /* e1000_power_down_phy(adapter); */
1344 igb_free_all_rx_resources(adapter);
1345 err_setup_rx:
1346 igb_free_all_tx_resources(adapter);
1347 err_setup_tx:
1348 igb_reset(adapter);
1349
1350 return err;
1351 }
1352
1353 /**
1354 * igb_close - Disables a network interface
1355 * @netdev: network interface device structure
1356 *
1357 * Returns 0, this is not allowed to fail
1358 *
1359 * The close entry point is called when an interface is de-activated
1360 * by the OS. The hardware is still under the driver's control, but
1361 * needs to be disabled. A global MAC reset is issued to stop the
1362 * hardware, and all transmit and receive resources are freed.
1363 **/
1364 static int igb_close(struct net_device *netdev)
1365 {
1366 struct igb_adapter *adapter = netdev_priv(netdev);
1367
1368 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1369 igb_down(adapter);
1370
1371 igb_free_irq(adapter);
1372
1373 igb_free_all_tx_resources(adapter);
1374 igb_free_all_rx_resources(adapter);
1375
1376 /* kill manageability vlan ID if supported, but not if a vlan with
1377 * the same ID is registered on the host OS (let 8021q kill it) */
1378 if ((adapter->hw.mng_cookie.status &
1379 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1380 !(adapter->vlgrp &&
1381 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1382 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1383
1384 return 0;
1385 }
1386
1387 /**
1388 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1389 * @adapter: board private structure
1390 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1391 *
1392 * Return 0 on success, negative on failure
1393 **/
1394
1395 int igb_setup_tx_resources(struct igb_adapter *adapter,
1396 struct igb_ring *tx_ring)
1397 {
1398 struct pci_dev *pdev = adapter->pdev;
1399 int size;
1400
1401 size = sizeof(struct igb_buffer) * tx_ring->count;
1402 tx_ring->buffer_info = vmalloc(size);
1403 if (!tx_ring->buffer_info)
1404 goto err;
1405 memset(tx_ring->buffer_info, 0, size);
1406
1407 /* round up to nearest 4K */
1408 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1409 + sizeof(u32);
1410 tx_ring->size = ALIGN(tx_ring->size, 4096);
1411
1412 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1413 &tx_ring->dma);
1414
1415 if (!tx_ring->desc)
1416 goto err;
1417
1418 tx_ring->adapter = adapter;
1419 tx_ring->next_to_use = 0;
1420 tx_ring->next_to_clean = 0;
1421 spin_lock_init(&tx_ring->tx_clean_lock);
1422 spin_lock_init(&tx_ring->tx_lock);
1423 return 0;
1424
1425 err:
1426 vfree(tx_ring->buffer_info);
1427 dev_err(&adapter->pdev->dev,
1428 "Unable to allocate memory for the transmit descriptor ring\n");
1429 return -ENOMEM;
1430 }
1431
1432 /**
1433 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1434 * (Descriptors) for all queues
1435 * @adapter: board private structure
1436 *
1437 * Return 0 on success, negative on failure
1438 **/
1439 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1440 {
1441 int i, err = 0;
1442
1443 for (i = 0; i < adapter->num_tx_queues; i++) {
1444 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1445 if (err) {
1446 dev_err(&adapter->pdev->dev,
1447 "Allocation for Tx Queue %u failed\n", i);
1448 for (i--; i >= 0; i--)
1449 igb_free_tx_resources(adapter,
1450 &adapter->tx_ring[i]);
1451 break;
1452 }
1453 }
1454
1455 return err;
1456 }
1457
1458 /**
1459 * igb_configure_tx - Configure transmit Unit after Reset
1460 * @adapter: board private structure
1461 *
1462 * Configure the Tx unit of the MAC after a reset.
1463 **/
1464 static void igb_configure_tx(struct igb_adapter *adapter)
1465 {
1466 u64 tdba, tdwba;
1467 struct e1000_hw *hw = &adapter->hw;
1468 u32 tctl;
1469 u32 txdctl, txctrl;
1470 int i;
1471
1472 for (i = 0; i < adapter->num_tx_queues; i++) {
1473 struct igb_ring *ring = &(adapter->tx_ring[i]);
1474
1475 wr32(E1000_TDLEN(i),
1476 ring->count * sizeof(struct e1000_tx_desc));
1477 tdba = ring->dma;
1478 wr32(E1000_TDBAL(i),
1479 tdba & 0x00000000ffffffffULL);
1480 wr32(E1000_TDBAH(i), tdba >> 32);
1481
1482 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1483 tdwba |= 1; /* enable head wb */
1484 wr32(E1000_TDWBAL(i),
1485 tdwba & 0x00000000ffffffffULL);
1486 wr32(E1000_TDWBAH(i), tdwba >> 32);
1487
1488 ring->head = E1000_TDH(i);
1489 ring->tail = E1000_TDT(i);
1490 writel(0, hw->hw_addr + ring->tail);
1491 writel(0, hw->hw_addr + ring->head);
1492 txdctl = rd32(E1000_TXDCTL(i));
1493 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1494 wr32(E1000_TXDCTL(i), txdctl);
1495
1496 /* Turn off Relaxed Ordering on head write-backs. The
1497 * writebacks MUST be delivered in order or it will
1498 * completely screw up our bookeeping.
1499 */
1500 txctrl = rd32(E1000_DCA_TXCTRL(i));
1501 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1502 wr32(E1000_DCA_TXCTRL(i), txctrl);
1503 }
1504
1505
1506
1507 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1508
1509 /* Program the Transmit Control Register */
1510
1511 tctl = rd32(E1000_TCTL);
1512 tctl &= ~E1000_TCTL_CT;
1513 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1514 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1515
1516 igb_config_collision_dist(hw);
1517
1518 /* Setup Transmit Descriptor Settings for eop descriptor */
1519 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1520
1521 /* Enable transmits */
1522 tctl |= E1000_TCTL_EN;
1523
1524 wr32(E1000_TCTL, tctl);
1525 }
1526
1527 /**
1528 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1529 * @adapter: board private structure
1530 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1531 *
1532 * Returns 0 on success, negative on failure
1533 **/
1534
1535 int igb_setup_rx_resources(struct igb_adapter *adapter,
1536 struct igb_ring *rx_ring)
1537 {
1538 struct pci_dev *pdev = adapter->pdev;
1539 int size, desc_len;
1540
1541 size = sizeof(struct igb_buffer) * rx_ring->count;
1542 rx_ring->buffer_info = vmalloc(size);
1543 if (!rx_ring->buffer_info)
1544 goto err;
1545 memset(rx_ring->buffer_info, 0, size);
1546
1547 desc_len = sizeof(union e1000_adv_rx_desc);
1548
1549 /* Round up to nearest 4K */
1550 rx_ring->size = rx_ring->count * desc_len;
1551 rx_ring->size = ALIGN(rx_ring->size, 4096);
1552
1553 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1554 &rx_ring->dma);
1555
1556 if (!rx_ring->desc)
1557 goto err;
1558
1559 rx_ring->next_to_clean = 0;
1560 rx_ring->next_to_use = 0;
1561 rx_ring->pending_skb = NULL;
1562
1563 rx_ring->adapter = adapter;
1564 /* FIXME: do we want to setup ring->napi->poll here? */
1565 rx_ring->napi.poll = adapter->napi.poll;
1566
1567 return 0;
1568
1569 err:
1570 vfree(rx_ring->buffer_info);
1571 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1572 "the receive descriptor ring\n");
1573 return -ENOMEM;
1574 }
1575
1576 /**
1577 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1578 * (Descriptors) for all queues
1579 * @adapter: board private structure
1580 *
1581 * Return 0 on success, negative on failure
1582 **/
1583 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1584 {
1585 int i, err = 0;
1586
1587 for (i = 0; i < adapter->num_rx_queues; i++) {
1588 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1589 if (err) {
1590 dev_err(&adapter->pdev->dev,
1591 "Allocation for Rx Queue %u failed\n", i);
1592 for (i--; i >= 0; i--)
1593 igb_free_rx_resources(adapter,
1594 &adapter->rx_ring[i]);
1595 break;
1596 }
1597 }
1598
1599 return err;
1600 }
1601
1602 /**
1603 * igb_setup_rctl - configure the receive control registers
1604 * @adapter: Board private structure
1605 **/
1606 static void igb_setup_rctl(struct igb_adapter *adapter)
1607 {
1608 struct e1000_hw *hw = &adapter->hw;
1609 u32 rctl;
1610 u32 srrctl = 0;
1611 int i;
1612
1613 rctl = rd32(E1000_RCTL);
1614
1615 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1616
1617 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1618 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1619 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1620
1621 /* disable the stripping of CRC because it breaks
1622 * BMC firmware connected over SMBUS
1623 rctl |= E1000_RCTL_SECRC;
1624 */
1625
1626 rctl &= ~E1000_RCTL_SBP;
1627
1628 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1629 rctl &= ~E1000_RCTL_LPE;
1630 else
1631 rctl |= E1000_RCTL_LPE;
1632 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1633 /* Setup buffer sizes */
1634 rctl &= ~E1000_RCTL_SZ_4096;
1635 rctl |= E1000_RCTL_BSEX;
1636 switch (adapter->rx_buffer_len) {
1637 case IGB_RXBUFFER_256:
1638 rctl |= E1000_RCTL_SZ_256;
1639 rctl &= ~E1000_RCTL_BSEX;
1640 break;
1641 case IGB_RXBUFFER_512:
1642 rctl |= E1000_RCTL_SZ_512;
1643 rctl &= ~E1000_RCTL_BSEX;
1644 break;
1645 case IGB_RXBUFFER_1024:
1646 rctl |= E1000_RCTL_SZ_1024;
1647 rctl &= ~E1000_RCTL_BSEX;
1648 break;
1649 case IGB_RXBUFFER_2048:
1650 default:
1651 rctl |= E1000_RCTL_SZ_2048;
1652 rctl &= ~E1000_RCTL_BSEX;
1653 break;
1654 case IGB_RXBUFFER_4096:
1655 rctl |= E1000_RCTL_SZ_4096;
1656 break;
1657 case IGB_RXBUFFER_8192:
1658 rctl |= E1000_RCTL_SZ_8192;
1659 break;
1660 case IGB_RXBUFFER_16384:
1661 rctl |= E1000_RCTL_SZ_16384;
1662 break;
1663 }
1664 } else {
1665 rctl &= ~E1000_RCTL_BSEX;
1666 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1667 }
1668
1669 /* 82575 and greater support packet-split where the protocol
1670 * header is placed in skb->data and the packet data is
1671 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1672 * In the case of a non-split, skb->data is linearly filled,
1673 * followed by the page buffers. Therefore, skb->data is
1674 * sized to hold the largest protocol header.
1675 */
1676 /* allocations using alloc_page take too long for regular MTU
1677 * so only enable packet split for jumbo frames */
1678 if (rctl & E1000_RCTL_LPE) {
1679 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1680 srrctl = adapter->rx_ps_hdr_size <<
1681 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1682 /* buffer size is ALWAYS one page */
1683 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1684 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1685 } else {
1686 adapter->rx_ps_hdr_size = 0;
1687 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1688 }
1689
1690 for (i = 0; i < adapter->num_rx_queues; i++)
1691 wr32(E1000_SRRCTL(i), srrctl);
1692
1693 wr32(E1000_RCTL, rctl);
1694 }
1695
1696 /**
1697 * igb_configure_rx - Configure receive Unit after Reset
1698 * @adapter: board private structure
1699 *
1700 * Configure the Rx unit of the MAC after a reset.
1701 **/
1702 static void igb_configure_rx(struct igb_adapter *adapter)
1703 {
1704 u64 rdba;
1705 struct e1000_hw *hw = &adapter->hw;
1706 u32 rctl, rxcsum;
1707 u32 rxdctl;
1708 int i;
1709
1710 /* disable receives while setting up the descriptors */
1711 rctl = rd32(E1000_RCTL);
1712 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1713 wrfl();
1714 mdelay(10);
1715
1716 if (adapter->itr_setting > 3)
1717 wr32(E1000_ITR,
1718 1000000000 / (adapter->itr * 256));
1719
1720 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1721 * the Base and Length of the Rx Descriptor Ring */
1722 for (i = 0; i < adapter->num_rx_queues; i++) {
1723 struct igb_ring *ring = &(adapter->rx_ring[i]);
1724 rdba = ring->dma;
1725 wr32(E1000_RDBAL(i),
1726 rdba & 0x00000000ffffffffULL);
1727 wr32(E1000_RDBAH(i), rdba >> 32);
1728 wr32(E1000_RDLEN(i),
1729 ring->count * sizeof(union e1000_adv_rx_desc));
1730
1731 ring->head = E1000_RDH(i);
1732 ring->tail = E1000_RDT(i);
1733 writel(0, hw->hw_addr + ring->tail);
1734 writel(0, hw->hw_addr + ring->head);
1735
1736 rxdctl = rd32(E1000_RXDCTL(i));
1737 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1738 rxdctl &= 0xFFF00000;
1739 rxdctl |= IGB_RX_PTHRESH;
1740 rxdctl |= IGB_RX_HTHRESH << 8;
1741 rxdctl |= IGB_RX_WTHRESH << 16;
1742 wr32(E1000_RXDCTL(i), rxdctl);
1743 }
1744
1745 if (adapter->num_rx_queues > 1) {
1746 u32 random[10];
1747 u32 mrqc;
1748 u32 j, shift;
1749 union e1000_reta {
1750 u32 dword;
1751 u8 bytes[4];
1752 } reta;
1753
1754 get_random_bytes(&random[0], 40);
1755
1756 shift = 6;
1757 for (j = 0; j < (32 * 4); j++) {
1758 reta.bytes[j & 3] =
1759 (j % adapter->num_rx_queues) << shift;
1760 if ((j & 3) == 3)
1761 writel(reta.dword,
1762 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1763 }
1764 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1765
1766 /* Fill out hash function seeds */
1767 for (j = 0; j < 10; j++)
1768 array_wr32(E1000_RSSRK(0), j, random[j]);
1769
1770 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1771 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1772 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1773 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1774 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1775 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1776 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1777 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1778
1779
1780 wr32(E1000_MRQC, mrqc);
1781
1782 /* Multiqueue and raw packet checksumming are mutually
1783 * exclusive. Note that this not the same as TCP/IP
1784 * checksumming, which works fine. */
1785 rxcsum = rd32(E1000_RXCSUM);
1786 rxcsum |= E1000_RXCSUM_PCSD;
1787 wr32(E1000_RXCSUM, rxcsum);
1788 } else {
1789 /* Enable Receive Checksum Offload for TCP and UDP */
1790 rxcsum = rd32(E1000_RXCSUM);
1791 if (adapter->rx_csum) {
1792 rxcsum |= E1000_RXCSUM_TUOFL;
1793
1794 /* Enable IPv4 payload checksum for UDP fragments
1795 * Must be used in conjunction with packet-split. */
1796 if (adapter->rx_ps_hdr_size)
1797 rxcsum |= E1000_RXCSUM_IPPCSE;
1798 } else {
1799 rxcsum &= ~E1000_RXCSUM_TUOFL;
1800 /* don't need to clear IPPCSE as it defaults to 0 */
1801 }
1802 wr32(E1000_RXCSUM, rxcsum);
1803 }
1804
1805 if (adapter->vlgrp)
1806 wr32(E1000_RLPML,
1807 adapter->max_frame_size + VLAN_TAG_SIZE);
1808 else
1809 wr32(E1000_RLPML, adapter->max_frame_size);
1810
1811 /* Enable Receives */
1812 wr32(E1000_RCTL, rctl);
1813 }
1814
1815 /**
1816 * igb_free_tx_resources - Free Tx Resources per Queue
1817 * @adapter: board private structure
1818 * @tx_ring: Tx descriptor ring for a specific queue
1819 *
1820 * Free all transmit software resources
1821 **/
1822 static void igb_free_tx_resources(struct igb_adapter *adapter,
1823 struct igb_ring *tx_ring)
1824 {
1825 struct pci_dev *pdev = adapter->pdev;
1826
1827 igb_clean_tx_ring(adapter, tx_ring);
1828
1829 vfree(tx_ring->buffer_info);
1830 tx_ring->buffer_info = NULL;
1831
1832 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1833
1834 tx_ring->desc = NULL;
1835 }
1836
1837 /**
1838 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1839 * @adapter: board private structure
1840 *
1841 * Free all transmit software resources
1842 **/
1843 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1844 {
1845 int i;
1846
1847 for (i = 0; i < adapter->num_tx_queues; i++)
1848 igb_free_tx_resources(adapter, &adapter->tx_ring[i]);
1849 }
1850
1851 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1852 struct igb_buffer *buffer_info)
1853 {
1854 if (buffer_info->dma) {
1855 pci_unmap_page(adapter->pdev,
1856 buffer_info->dma,
1857 buffer_info->length,
1858 PCI_DMA_TODEVICE);
1859 buffer_info->dma = 0;
1860 }
1861 if (buffer_info->skb) {
1862 dev_kfree_skb_any(buffer_info->skb);
1863 buffer_info->skb = NULL;
1864 }
1865 buffer_info->time_stamp = 0;
1866 /* buffer_info must be completely set up in the transmit path */
1867 }
1868
1869 /**
1870 * igb_clean_tx_ring - Free Tx Buffers
1871 * @adapter: board private structure
1872 * @tx_ring: ring to be cleaned
1873 **/
1874 static void igb_clean_tx_ring(struct igb_adapter *adapter,
1875 struct igb_ring *tx_ring)
1876 {
1877 struct igb_buffer *buffer_info;
1878 unsigned long size;
1879 unsigned int i;
1880
1881 if (!tx_ring->buffer_info)
1882 return;
1883 /* Free all the Tx ring sk_buffs */
1884
1885 for (i = 0; i < tx_ring->count; i++) {
1886 buffer_info = &tx_ring->buffer_info[i];
1887 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1888 }
1889
1890 size = sizeof(struct igb_buffer) * tx_ring->count;
1891 memset(tx_ring->buffer_info, 0, size);
1892
1893 /* Zero out the descriptor ring */
1894
1895 memset(tx_ring->desc, 0, tx_ring->size);
1896
1897 tx_ring->next_to_use = 0;
1898 tx_ring->next_to_clean = 0;
1899
1900 writel(0, adapter->hw.hw_addr + tx_ring->head);
1901 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1902 }
1903
1904 /**
1905 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1906 * @adapter: board private structure
1907 **/
1908 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1909 {
1910 int i;
1911
1912 for (i = 0; i < adapter->num_tx_queues; i++)
1913 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1914 }
1915
1916 /**
1917 * igb_free_rx_resources - Free Rx Resources
1918 * @adapter: board private structure
1919 * @rx_ring: ring to clean the resources from
1920 *
1921 * Free all receive software resources
1922 **/
1923 static void igb_free_rx_resources(struct igb_adapter *adapter,
1924 struct igb_ring *rx_ring)
1925 {
1926 struct pci_dev *pdev = adapter->pdev;
1927
1928 igb_clean_rx_ring(adapter, rx_ring);
1929
1930 vfree(rx_ring->buffer_info);
1931 rx_ring->buffer_info = NULL;
1932
1933 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1934
1935 rx_ring->desc = NULL;
1936 }
1937
1938 /**
1939 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1940 * @adapter: board private structure
1941 *
1942 * Free all receive software resources
1943 **/
1944 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1945 {
1946 int i;
1947
1948 for (i = 0; i < adapter->num_rx_queues; i++)
1949 igb_free_rx_resources(adapter, &adapter->rx_ring[i]);
1950 }
1951
1952 /**
1953 * igb_clean_rx_ring - Free Rx Buffers per Queue
1954 * @adapter: board private structure
1955 * @rx_ring: ring to free buffers from
1956 **/
1957 static void igb_clean_rx_ring(struct igb_adapter *adapter,
1958 struct igb_ring *rx_ring)
1959 {
1960 struct igb_buffer *buffer_info;
1961 struct pci_dev *pdev = adapter->pdev;
1962 unsigned long size;
1963 unsigned int i;
1964
1965 if (!rx_ring->buffer_info)
1966 return;
1967 /* Free all the Rx ring sk_buffs */
1968 for (i = 0; i < rx_ring->count; i++) {
1969 buffer_info = &rx_ring->buffer_info[i];
1970 if (buffer_info->dma) {
1971 if (adapter->rx_ps_hdr_size)
1972 pci_unmap_single(pdev, buffer_info->dma,
1973 adapter->rx_ps_hdr_size,
1974 PCI_DMA_FROMDEVICE);
1975 else
1976 pci_unmap_single(pdev, buffer_info->dma,
1977 adapter->rx_buffer_len,
1978 PCI_DMA_FROMDEVICE);
1979 buffer_info->dma = 0;
1980 }
1981
1982 if (buffer_info->skb) {
1983 dev_kfree_skb(buffer_info->skb);
1984 buffer_info->skb = NULL;
1985 }
1986 if (buffer_info->page) {
1987 pci_unmap_page(pdev, buffer_info->page_dma,
1988 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1989 put_page(buffer_info->page);
1990 buffer_info->page = NULL;
1991 buffer_info->page_dma = 0;
1992 }
1993 }
1994
1995 /* there also may be some cached data from a chained receive */
1996 if (rx_ring->pending_skb) {
1997 dev_kfree_skb(rx_ring->pending_skb);
1998 rx_ring->pending_skb = NULL;
1999 }
2000
2001 size = sizeof(struct igb_buffer) * rx_ring->count;
2002 memset(rx_ring->buffer_info, 0, size);
2003
2004 /* Zero out the descriptor ring */
2005 memset(rx_ring->desc, 0, rx_ring->size);
2006
2007 rx_ring->next_to_clean = 0;
2008 rx_ring->next_to_use = 0;
2009
2010 writel(0, adapter->hw.hw_addr + rx_ring->head);
2011 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2012 }
2013
2014 /**
2015 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2016 * @adapter: board private structure
2017 **/
2018 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2019 {
2020 int i;
2021
2022 for (i = 0; i < adapter->num_rx_queues; i++)
2023 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2024 }
2025
2026 /**
2027 * igb_set_mac - Change the Ethernet Address of the NIC
2028 * @netdev: network interface device structure
2029 * @p: pointer to an address structure
2030 *
2031 * Returns 0 on success, negative on failure
2032 **/
2033 static int igb_set_mac(struct net_device *netdev, void *p)
2034 {
2035 struct igb_adapter *adapter = netdev_priv(netdev);
2036 struct sockaddr *addr = p;
2037
2038 if (!is_valid_ether_addr(addr->sa_data))
2039 return -EADDRNOTAVAIL;
2040
2041 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2042 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2043
2044 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2045
2046 return 0;
2047 }
2048
2049 /**
2050 * igb_set_multi - Multicast and Promiscuous mode set
2051 * @netdev: network interface device structure
2052 *
2053 * The set_multi entry point is called whenever the multicast address
2054 * list or the network interface flags are updated. This routine is
2055 * responsible for configuring the hardware for proper multicast,
2056 * promiscuous mode, and all-multi behavior.
2057 **/
2058 static void igb_set_multi(struct net_device *netdev)
2059 {
2060 struct igb_adapter *adapter = netdev_priv(netdev);
2061 struct e1000_hw *hw = &adapter->hw;
2062 struct e1000_mac_info *mac = &hw->mac;
2063 struct dev_mc_list *mc_ptr;
2064 u8 *mta_list;
2065 u32 rctl;
2066 int i;
2067
2068 /* Check for Promiscuous and All Multicast modes */
2069
2070 rctl = rd32(E1000_RCTL);
2071
2072 if (netdev->flags & IFF_PROMISC)
2073 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2074 else if (netdev->flags & IFF_ALLMULTI) {
2075 rctl |= E1000_RCTL_MPE;
2076 rctl &= ~E1000_RCTL_UPE;
2077 } else
2078 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2079
2080 wr32(E1000_RCTL, rctl);
2081
2082 if (!netdev->mc_count) {
2083 /* nothing to program, so clear mc list */
2084 igb_update_mc_addr_list(hw, NULL, 0, 1,
2085 mac->rar_entry_count);
2086 return;
2087 }
2088
2089 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2090 if (!mta_list)
2091 return;
2092
2093 /* The shared function expects a packed array of only addresses. */
2094 mc_ptr = netdev->mc_list;
2095
2096 for (i = 0; i < netdev->mc_count; i++) {
2097 if (!mc_ptr)
2098 break;
2099 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2100 mc_ptr = mc_ptr->next;
2101 }
2102 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2103 kfree(mta_list);
2104 }
2105
2106 /* Need to wait a few seconds after link up to get diagnostic information from
2107 * the phy */
2108 static void igb_update_phy_info(unsigned long data)
2109 {
2110 struct igb_adapter *adapter = (struct igb_adapter *) data;
2111 <<<<<<< HEAD:drivers/net/igb/igb_main.c
2112 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2113 =======
2114 if (adapter->hw.phy.ops.get_phy_info)
2115 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2116 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
2117 }
2118
2119 /**
2120 * igb_watchdog - Timer Call-back
2121 * @data: pointer to adapter cast into an unsigned long
2122 **/
2123 static void igb_watchdog(unsigned long data)
2124 {
2125 struct igb_adapter *adapter = (struct igb_adapter *)data;
2126 /* Do the rest outside of interrupt context */
2127 schedule_work(&adapter->watchdog_task);
2128 }
2129
2130 static void igb_watchdog_task(struct work_struct *work)
2131 {
2132 struct igb_adapter *adapter = container_of(work,
2133 struct igb_adapter, watchdog_task);
2134 struct e1000_hw *hw = &adapter->hw;
2135
2136 struct net_device *netdev = adapter->netdev;
2137 struct igb_ring *tx_ring = adapter->tx_ring;
2138 struct e1000_mac_info *mac = &adapter->hw.mac;
2139 u32 link;
2140 s32 ret_val;
2141
2142 if ((netif_carrier_ok(netdev)) &&
2143 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2144 goto link_up;
2145
2146 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2147 if ((ret_val == E1000_ERR_PHY) &&
2148 (hw->phy.type == e1000_phy_igp_3) &&
2149 (rd32(E1000_CTRL) &
2150 E1000_PHY_CTRL_GBE_DISABLE))
2151 dev_info(&adapter->pdev->dev,
2152 "Gigabit has been disabled, downgrading speed\n");
2153
2154 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2155 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2156 link = mac->serdes_has_link;
2157 else
2158 link = rd32(E1000_STATUS) &
2159 E1000_STATUS_LU;
2160
2161 if (link) {
2162 if (!netif_carrier_ok(netdev)) {
2163 u32 ctrl;
2164 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2165 &adapter->link_speed,
2166 &adapter->link_duplex);
2167
2168 ctrl = rd32(E1000_CTRL);
2169 dev_info(&adapter->pdev->dev,
2170 "NIC Link is Up %d Mbps %s, "
2171 "Flow Control: %s\n",
2172 adapter->link_speed,
2173 adapter->link_duplex == FULL_DUPLEX ?
2174 "Full Duplex" : "Half Duplex",
2175 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2176 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2177 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2178 E1000_CTRL_TFCE) ? "TX" : "None")));
2179
2180 /* tweak tx_queue_len according to speed/duplex and
2181 * adjust the timeout factor */
2182 netdev->tx_queue_len = adapter->tx_queue_len;
2183 adapter->tx_timeout_factor = 1;
2184 switch (adapter->link_speed) {
2185 case SPEED_10:
2186 netdev->tx_queue_len = 10;
2187 adapter->tx_timeout_factor = 14;
2188 break;
2189 case SPEED_100:
2190 netdev->tx_queue_len = 100;
2191 /* maybe add some timeout factor ? */
2192 break;
2193 }
2194
2195 netif_carrier_on(netdev);
2196 netif_wake_queue(netdev);
2197
2198 if (!test_bit(__IGB_DOWN, &adapter->state))
2199 mod_timer(&adapter->phy_info_timer,
2200 round_jiffies(jiffies + 2 * HZ));
2201 }
2202 } else {
2203 if (netif_carrier_ok(netdev)) {
2204 adapter->link_speed = 0;
2205 adapter->link_duplex = 0;
2206 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2207 netif_carrier_off(netdev);
2208 netif_stop_queue(netdev);
2209 if (!test_bit(__IGB_DOWN, &adapter->state))
2210 mod_timer(&adapter->phy_info_timer,
2211 round_jiffies(jiffies + 2 * HZ));
2212 }
2213 }
2214
2215 link_up:
2216 igb_update_stats(adapter);
2217
2218 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2219 adapter->tpt_old = adapter->stats.tpt;
2220 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2221 adapter->colc_old = adapter->stats.colc;
2222
2223 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2224 adapter->gorc_old = adapter->stats.gorc;
2225 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2226 adapter->gotc_old = adapter->stats.gotc;
2227
2228 igb_update_adaptive(&adapter->hw);
2229
2230 if (!netif_carrier_ok(netdev)) {
2231 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2232 /* We've lost link, so the controller stops DMA,
2233 * but we've got queued Tx work that's never going
2234 * to get done, so reset controller to flush Tx.
2235 * (Do the reset outside of interrupt context). */
2236 adapter->tx_timeout_count++;
2237 schedule_work(&adapter->reset_task);
2238 }
2239 }
2240
2241 /* Cause software interrupt to ensure rx ring is cleaned */
2242 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2243
2244 /* Force detection of hung controller every watchdog period */
2245 tx_ring->detect_tx_hung = true;
2246
2247 /* Reset the timer */
2248 if (!test_bit(__IGB_DOWN, &adapter->state))
2249 mod_timer(&adapter->watchdog_timer,
2250 round_jiffies(jiffies + 2 * HZ));
2251 }
2252
2253 enum latency_range {
2254 lowest_latency = 0,
2255 low_latency = 1,
2256 bulk_latency = 2,
2257 latency_invalid = 255
2258 };
2259
2260
2261 static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2262 struct igb_ring *rx_ring)
2263 {
2264 struct e1000_hw *hw = &adapter->hw;
2265 int new_val;
2266
2267 new_val = rx_ring->itr_val / 2;
2268 if (new_val < IGB_MIN_DYN_ITR)
2269 new_val = IGB_MIN_DYN_ITR;
2270
2271 if (new_val != rx_ring->itr_val) {
2272 rx_ring->itr_val = new_val;
2273 wr32(rx_ring->itr_register,
2274 1000000000 / (new_val * 256));
2275 }
2276 }
2277
2278 static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2279 struct igb_ring *rx_ring)
2280 {
2281 struct e1000_hw *hw = &adapter->hw;
2282 int new_val;
2283
2284 new_val = rx_ring->itr_val * 2;
2285 if (new_val > IGB_MAX_DYN_ITR)
2286 new_val = IGB_MAX_DYN_ITR;
2287
2288 if (new_val != rx_ring->itr_val) {
2289 rx_ring->itr_val = new_val;
2290 wr32(rx_ring->itr_register,
2291 1000000000 / (new_val * 256));
2292 }
2293 }
2294
2295 /**
2296 * igb_update_itr - update the dynamic ITR value based on statistics
2297 * Stores a new ITR value based on packets and byte
2298 * counts during the last interrupt. The advantage of per interrupt
2299 * computation is faster updates and more accurate ITR for the current
2300 * traffic pattern. Constants in this function were computed
2301 * based on theoretical maximum wire speed and thresholds were set based
2302 * on testing data as well as attempting to minimize response time
2303 * while increasing bulk throughput.
2304 * this functionality is controlled by the InterruptThrottleRate module
2305 * parameter (see igb_param.c)
2306 * NOTE: These calculations are only valid when operating in a single-
2307 * queue environment.
2308 * @adapter: pointer to adapter
2309 * @itr_setting: current adapter->itr
2310 * @packets: the number of packets during this measurement interval
2311 * @bytes: the number of bytes during this measurement interval
2312 **/
2313 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2314 int packets, int bytes)
2315 {
2316 unsigned int retval = itr_setting;
2317
2318 if (packets == 0)
2319 goto update_itr_done;
2320
2321 switch (itr_setting) {
2322 case lowest_latency:
2323 /* handle TSO and jumbo frames */
2324 if (bytes/packets > 8000)
2325 retval = bulk_latency;
2326 else if ((packets < 5) && (bytes > 512))
2327 retval = low_latency;
2328 break;
2329 case low_latency: /* 50 usec aka 20000 ints/s */
2330 if (bytes > 10000) {
2331 /* this if handles the TSO accounting */
2332 if (bytes/packets > 8000) {
2333 retval = bulk_latency;
2334 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2335 retval = bulk_latency;
2336 } else if ((packets > 35)) {
2337 retval = lowest_latency;
2338 }
2339 } else if (bytes/packets > 2000) {
2340 retval = bulk_latency;
2341 } else if (packets <= 2 && bytes < 512) {
2342 retval = lowest_latency;
2343 }
2344 break;
2345 case bulk_latency: /* 250 usec aka 4000 ints/s */
2346 if (bytes > 25000) {
2347 if (packets > 35)
2348 retval = low_latency;
2349 } else if (bytes < 6000) {
2350 retval = low_latency;
2351 }
2352 break;
2353 }
2354
2355 update_itr_done:
2356 return retval;
2357 }
2358
2359 static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2360 int rx_only)
2361 {
2362 u16 current_itr;
2363 u32 new_itr = adapter->itr;
2364
2365 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2366 if (adapter->link_speed != SPEED_1000) {
2367 current_itr = 0;
2368 new_itr = 4000;
2369 goto set_itr_now;
2370 }
2371
2372 adapter->rx_itr = igb_update_itr(adapter,
2373 adapter->rx_itr,
2374 adapter->rx_ring->total_packets,
2375 adapter->rx_ring->total_bytes);
2376 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2377 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2378 adapter->rx_itr = low_latency;
2379
2380 if (!rx_only) {
2381 adapter->tx_itr = igb_update_itr(adapter,
2382 adapter->tx_itr,
2383 adapter->tx_ring->total_packets,
2384 adapter->tx_ring->total_bytes);
2385 /* conservative mode (itr 3) eliminates the
2386 * lowest_latency setting */
2387 if (adapter->itr_setting == 3 &&
2388 adapter->tx_itr == lowest_latency)
2389 adapter->tx_itr = low_latency;
2390
2391 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2392 } else {
2393 current_itr = adapter->rx_itr;
2394 }
2395
2396 switch (current_itr) {
2397 /* counts and packets in update_itr are dependent on these numbers */
2398 case lowest_latency:
2399 new_itr = 70000;
2400 break;
2401 case low_latency:
2402 new_itr = 20000; /* aka hwitr = ~200 */
2403 break;
2404 case bulk_latency:
2405 new_itr = 4000;
2406 break;
2407 default:
2408 break;
2409 }
2410
2411 set_itr_now:
2412 if (new_itr != adapter->itr) {
2413 /* this attempts to bias the interrupt rate towards Bulk
2414 * by adding intermediate steps when interrupt rate is
2415 * increasing */
2416 new_itr = new_itr > adapter->itr ?
2417 min(adapter->itr + (new_itr >> 2), new_itr) :
2418 new_itr;
2419 /* Don't write the value here; it resets the adapter's
2420 * internal timer, and causes us to delay far longer than
2421 * we should between interrupts. Instead, we write the ITR
2422 * value at the beginning of the next interrupt so the timing
2423 * ends up being correct.
2424 */
2425 adapter->itr = new_itr;
2426 adapter->set_itr = 1;
2427 }
2428
2429 return;
2430 }
2431
2432
2433 #define IGB_TX_FLAGS_CSUM 0x00000001
2434 #define IGB_TX_FLAGS_VLAN 0x00000002
2435 #define IGB_TX_FLAGS_TSO 0x00000004
2436 #define IGB_TX_FLAGS_IPV4 0x00000008
2437 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2438 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2439
2440 static inline int igb_tso_adv(struct igb_adapter *adapter,
2441 struct igb_ring *tx_ring,
2442 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2443 {
2444 struct e1000_adv_tx_context_desc *context_desc;
2445 unsigned int i;
2446 int err;
2447 struct igb_buffer *buffer_info;
2448 u32 info = 0, tu_cmd = 0;
2449 u32 mss_l4len_idx, l4len;
2450 *hdr_len = 0;
2451
2452 if (skb_header_cloned(skb)) {
2453 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2454 if (err)
2455 return err;
2456 }
2457
2458 l4len = tcp_hdrlen(skb);
2459 *hdr_len += l4len;
2460
2461 if (skb->protocol == htons(ETH_P_IP)) {
2462 struct iphdr *iph = ip_hdr(skb);
2463 iph->tot_len = 0;
2464 iph->check = 0;
2465 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2466 iph->daddr, 0,
2467 IPPROTO_TCP,
2468 0);
2469 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2470 ipv6_hdr(skb)->payload_len = 0;
2471 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2472 &ipv6_hdr(skb)->daddr,
2473 0, IPPROTO_TCP, 0);
2474 }
2475
2476 i = tx_ring->next_to_use;
2477
2478 buffer_info = &tx_ring->buffer_info[i];
2479 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2480 /* VLAN MACLEN IPLEN */
2481 if (tx_flags & IGB_TX_FLAGS_VLAN)
2482 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2483 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2484 *hdr_len += skb_network_offset(skb);
2485 info |= skb_network_header_len(skb);
2486 *hdr_len += skb_network_header_len(skb);
2487 context_desc->vlan_macip_lens = cpu_to_le32(info);
2488
2489 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2490 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2491
2492 if (skb->protocol == htons(ETH_P_IP))
2493 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2494 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2495
2496 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2497
2498 /* MSS L4LEN IDX */
2499 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2500 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2501
2502 /* Context index must be unique per ring. Luckily, so is the interrupt
2503 * mask value. */
2504 mss_l4len_idx |= tx_ring->eims_value >> 4;
2505
2506 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2507 context_desc->seqnum_seed = 0;
2508
2509 buffer_info->time_stamp = jiffies;
2510 buffer_info->dma = 0;
2511 i++;
2512 if (i == tx_ring->count)
2513 i = 0;
2514
2515 tx_ring->next_to_use = i;
2516
2517 return true;
2518 }
2519
2520 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2521 struct igb_ring *tx_ring,
2522 struct sk_buff *skb, u32 tx_flags)
2523 {
2524 struct e1000_adv_tx_context_desc *context_desc;
2525 unsigned int i;
2526 struct igb_buffer *buffer_info;
2527 u32 info = 0, tu_cmd = 0;
2528
2529 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2530 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2531 i = tx_ring->next_to_use;
2532 buffer_info = &tx_ring->buffer_info[i];
2533 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2534
2535 if (tx_flags & IGB_TX_FLAGS_VLAN)
2536 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2537 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2538 if (skb->ip_summed == CHECKSUM_PARTIAL)
2539 info |= skb_network_header_len(skb);
2540
2541 context_desc->vlan_macip_lens = cpu_to_le32(info);
2542
2543 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2544
2545 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2546 if (skb->protocol == htons(ETH_P_IP))
2547 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2548 if (skb->sk && (skb->sk->sk_protocol == IPPROTO_TCP))
2549 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2550 }
2551
2552 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2553 context_desc->seqnum_seed = 0;
2554 context_desc->mss_l4len_idx =
2555 cpu_to_le32(tx_ring->eims_value >> 4);
2556
2557 buffer_info->time_stamp = jiffies;
2558 buffer_info->dma = 0;
2559
2560 i++;
2561 if (i == tx_ring->count)
2562 i = 0;
2563 tx_ring->next_to_use = i;
2564
2565 return true;
2566 }
2567
2568
2569 return false;
2570 }
2571
2572 #define IGB_MAX_TXD_PWR 16
2573 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2574
2575 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2576 struct igb_ring *tx_ring,
2577 struct sk_buff *skb)
2578 {
2579 struct igb_buffer *buffer_info;
2580 unsigned int len = skb_headlen(skb);
2581 unsigned int count = 0, i;
2582 unsigned int f;
2583
2584 i = tx_ring->next_to_use;
2585
2586 buffer_info = &tx_ring->buffer_info[i];
2587 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2588 buffer_info->length = len;
2589 /* set time_stamp *before* dma to help avoid a possible race */
2590 buffer_info->time_stamp = jiffies;
2591 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2592 PCI_DMA_TODEVICE);
2593 count++;
2594 i++;
2595 if (i == tx_ring->count)
2596 i = 0;
2597
2598 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2599 struct skb_frag_struct *frag;
2600
2601 frag = &skb_shinfo(skb)->frags[f];
2602 len = frag->size;
2603
2604 buffer_info = &tx_ring->buffer_info[i];
2605 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2606 buffer_info->length = len;
2607 buffer_info->time_stamp = jiffies;
2608 buffer_info->dma = pci_map_page(adapter->pdev,
2609 frag->page,
2610 frag->page_offset,
2611 len,
2612 PCI_DMA_TODEVICE);
2613
2614 count++;
2615 i++;
2616 if (i == tx_ring->count)
2617 i = 0;
2618 }
2619
2620 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2621 tx_ring->buffer_info[i].skb = skb;
2622
2623 return count;
2624 }
2625
2626 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2627 struct igb_ring *tx_ring,
2628 int tx_flags, int count, u32 paylen,
2629 u8 hdr_len)
2630 {
2631 union e1000_adv_tx_desc *tx_desc = NULL;
2632 struct igb_buffer *buffer_info;
2633 u32 olinfo_status = 0, cmd_type_len;
2634 unsigned int i;
2635
2636 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2637 E1000_ADVTXD_DCMD_DEXT);
2638
2639 if (tx_flags & IGB_TX_FLAGS_VLAN)
2640 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2641
2642 if (tx_flags & IGB_TX_FLAGS_TSO) {
2643 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2644
2645 /* insert tcp checksum */
2646 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2647
2648 /* insert ip checksum */
2649 if (tx_flags & IGB_TX_FLAGS_IPV4)
2650 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2651
2652 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2653 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2654 }
2655
2656 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2657 IGB_TX_FLAGS_VLAN))
2658 olinfo_status |= tx_ring->eims_value >> 4;
2659
2660 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2661
2662 i = tx_ring->next_to_use;
2663 while (count--) {
2664 buffer_info = &tx_ring->buffer_info[i];
2665 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2666 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2667 tx_desc->read.cmd_type_len =
2668 cpu_to_le32(cmd_type_len | buffer_info->length);
2669 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2670 i++;
2671 if (i == tx_ring->count)
2672 i = 0;
2673 }
2674
2675 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2676 /* Force memory writes to complete before letting h/w
2677 * know there are new descriptors to fetch. (Only
2678 * applicable for weak-ordered memory model archs,
2679 * such as IA-64). */
2680 wmb();
2681
2682 tx_ring->next_to_use = i;
2683 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2684 /* we need this if more than one processor can write to our tail
2685 * at a time, it syncronizes IO on IA64/Altix systems */
2686 mmiowb();
2687 }
2688
2689 static int __igb_maybe_stop_tx(struct net_device *netdev,
2690 struct igb_ring *tx_ring, int size)
2691 {
2692 struct igb_adapter *adapter = netdev_priv(netdev);
2693
2694 netif_stop_queue(netdev);
2695 /* Herbert's original patch had:
2696 * smp_mb__after_netif_stop_queue();
2697 * but since that doesn't exist yet, just open code it. */
2698 smp_mb();
2699
2700 /* We need to check again in a case another CPU has just
2701 * made room available. */
2702 if (IGB_DESC_UNUSED(tx_ring) < size)
2703 return -EBUSY;
2704
2705 /* A reprieve! */
2706 netif_start_queue(netdev);
2707 ++adapter->restart_queue;
2708 return 0;
2709 }
2710
2711 static int igb_maybe_stop_tx(struct net_device *netdev,
2712 struct igb_ring *tx_ring, int size)
2713 {
2714 if (IGB_DESC_UNUSED(tx_ring) >= size)
2715 return 0;
2716 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2717 }
2718
2719 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2720
2721 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2722 struct net_device *netdev,
2723 struct igb_ring *tx_ring)
2724 {
2725 struct igb_adapter *adapter = netdev_priv(netdev);
2726 unsigned int tx_flags = 0;
2727 unsigned int len;
2728 unsigned long irq_flags;
2729 u8 hdr_len = 0;
2730 int tso = 0;
2731
2732 len = skb_headlen(skb);
2733
2734 if (test_bit(__IGB_DOWN, &adapter->state)) {
2735 dev_kfree_skb_any(skb);
2736 return NETDEV_TX_OK;
2737 }
2738
2739 if (skb->len <= 0) {
2740 dev_kfree_skb_any(skb);
2741 return NETDEV_TX_OK;
2742 }
2743
2744 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2745 /* Collision - tell upper layer to requeue */
2746 return NETDEV_TX_LOCKED;
2747
2748 /* need: 1 descriptor per page,
2749 * + 2 desc gap to keep tail from touching head,
2750 * + 1 desc for skb->data,
2751 * + 1 desc for context descriptor,
2752 * otherwise try next time */
2753 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2754 /* this is a hard error */
2755 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2756 return NETDEV_TX_BUSY;
2757 }
2758
2759 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2760 tx_flags |= IGB_TX_FLAGS_VLAN;
2761 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2762 }
2763
2764 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2765 &hdr_len) : 0;
2766
2767 if (tso < 0) {
2768 dev_kfree_skb_any(skb);
2769 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2770 return NETDEV_TX_OK;
2771 }
2772
2773 if (tso)
2774 tx_flags |= IGB_TX_FLAGS_TSO;
2775 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2776 if (skb->ip_summed == CHECKSUM_PARTIAL)
2777 tx_flags |= IGB_TX_FLAGS_CSUM;
2778
2779 if (skb->protocol == htons(ETH_P_IP))
2780 tx_flags |= IGB_TX_FLAGS_IPV4;
2781
2782 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2783 igb_tx_map_adv(adapter, tx_ring, skb),
2784 skb->len, hdr_len);
2785
2786 netdev->trans_start = jiffies;
2787
2788 /* Make sure there is space in the ring for the next send. */
2789 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2790
2791 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2792 return NETDEV_TX_OK;
2793 }
2794
2795 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2796 {
2797 struct igb_adapter *adapter = netdev_priv(netdev);
2798 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2799
2800 /* This goes back to the question of how to logically map a tx queue
2801 * to a flow. Right now, performance is impacted slightly negatively
2802 * if using multiple tx queues. If the stack breaks away from a
2803 * single qdisc implementation, we can look at this again. */
2804 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2805 }
2806
2807 /**
2808 * igb_tx_timeout - Respond to a Tx Hang
2809 * @netdev: network interface device structure
2810 **/
2811 static void igb_tx_timeout(struct net_device *netdev)
2812 {
2813 struct igb_adapter *adapter = netdev_priv(netdev);
2814 struct e1000_hw *hw = &adapter->hw;
2815
2816 /* Do the reset outside of interrupt context */
2817 adapter->tx_timeout_count++;
2818 schedule_work(&adapter->reset_task);
2819 wr32(E1000_EICS, adapter->eims_enable_mask &
2820 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2821 }
2822
2823 static void igb_reset_task(struct work_struct *work)
2824 {
2825 struct igb_adapter *adapter;
2826 adapter = container_of(work, struct igb_adapter, reset_task);
2827
2828 igb_reinit_locked(adapter);
2829 }
2830
2831 /**
2832 * igb_get_stats - Get System Network Statistics
2833 * @netdev: network interface device structure
2834 *
2835 * Returns the address of the device statistics structure.
2836 * The statistics are actually updated from the timer callback.
2837 **/
2838 static struct net_device_stats *
2839 igb_get_stats(struct net_device *netdev)
2840 {
2841 struct igb_adapter *adapter = netdev_priv(netdev);
2842
2843 /* only return the current stats */
2844 return &adapter->net_stats;
2845 }
2846
2847 /**
2848 * igb_change_mtu - Change the Maximum Transfer Unit
2849 * @netdev: network interface device structure
2850 * @new_mtu: new value for maximum frame size
2851 *
2852 * Returns 0 on success, negative on failure
2853 **/
2854 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2855 {
2856 struct igb_adapter *adapter = netdev_priv(netdev);
2857 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2858
2859 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2860 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2861 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2862 return -EINVAL;
2863 }
2864
2865 #define MAX_STD_JUMBO_FRAME_SIZE 9234
2866 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2867 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2868 return -EINVAL;
2869 }
2870
2871 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2872 msleep(1);
2873 /* igb_down has a dependency on max_frame_size */
2874 adapter->max_frame_size = max_frame;
2875 if (netif_running(netdev))
2876 igb_down(adapter);
2877
2878 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2879 * means we reserve 2 more, this pushes us to allocate from the next
2880 * larger slab size.
2881 * i.e. RXBUFFER_2048 --> size-4096 slab
2882 */
2883
2884 if (max_frame <= IGB_RXBUFFER_256)
2885 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2886 else if (max_frame <= IGB_RXBUFFER_512)
2887 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2888 else if (max_frame <= IGB_RXBUFFER_1024)
2889 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2890 else if (max_frame <= IGB_RXBUFFER_2048)
2891 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2892 else
2893 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2894 /* adjust allocation if LPE protects us, and we aren't using SBP */
2895 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2896 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2897 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2898
2899 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2900 netdev->mtu, new_mtu);
2901 netdev->mtu = new_mtu;
2902
2903 if (netif_running(netdev))
2904 igb_up(adapter);
2905 else
2906 igb_reset(adapter);
2907
2908 clear_bit(__IGB_RESETTING, &adapter->state);
2909
2910 return 0;
2911 }
2912
2913 /**
2914 * igb_update_stats - Update the board statistics counters
2915 * @adapter: board private structure
2916 **/
2917
2918 void igb_update_stats(struct igb_adapter *adapter)
2919 {
2920 struct e1000_hw *hw = &adapter->hw;
2921 struct pci_dev *pdev = adapter->pdev;
2922 u16 phy_tmp;
2923
2924 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2925
2926 /*
2927 * Prevent stats update while adapter is being reset, or if the pci
2928 * connection is down.
2929 */
2930 if (adapter->link_speed == 0)
2931 return;
2932 if (pci_channel_offline(pdev))
2933 return;
2934
2935 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2936 adapter->stats.gprc += rd32(E1000_GPRC);
2937 adapter->stats.gorc += rd32(E1000_GORCL);
2938 rd32(E1000_GORCH); /* clear GORCL */
2939 adapter->stats.bprc += rd32(E1000_BPRC);
2940 adapter->stats.mprc += rd32(E1000_MPRC);
2941 adapter->stats.roc += rd32(E1000_ROC);
2942
2943 adapter->stats.prc64 += rd32(E1000_PRC64);
2944 adapter->stats.prc127 += rd32(E1000_PRC127);
2945 adapter->stats.prc255 += rd32(E1000_PRC255);
2946 adapter->stats.prc511 += rd32(E1000_PRC511);
2947 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2948 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2949 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2950 adapter->stats.sec += rd32(E1000_SEC);
2951
2952 adapter->stats.mpc += rd32(E1000_MPC);
2953 adapter->stats.scc += rd32(E1000_SCC);
2954 adapter->stats.ecol += rd32(E1000_ECOL);
2955 adapter->stats.mcc += rd32(E1000_MCC);
2956 adapter->stats.latecol += rd32(E1000_LATECOL);
2957 adapter->stats.dc += rd32(E1000_DC);
2958 adapter->stats.rlec += rd32(E1000_RLEC);
2959 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2960 adapter->stats.xontxc += rd32(E1000_XONTXC);
2961 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2962 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2963 adapter->stats.fcruc += rd32(E1000_FCRUC);
2964 adapter->stats.gptc += rd32(E1000_GPTC);
2965 adapter->stats.gotc += rd32(E1000_GOTCL);
2966 rd32(E1000_GOTCH); /* clear GOTCL */
2967 adapter->stats.rnbc += rd32(E1000_RNBC);
2968 adapter->stats.ruc += rd32(E1000_RUC);
2969 adapter->stats.rfc += rd32(E1000_RFC);
2970 adapter->stats.rjc += rd32(E1000_RJC);
2971 adapter->stats.tor += rd32(E1000_TORH);
2972 adapter->stats.tot += rd32(E1000_TOTH);
2973 adapter->stats.tpr += rd32(E1000_TPR);
2974
2975 adapter->stats.ptc64 += rd32(E1000_PTC64);
2976 adapter->stats.ptc127 += rd32(E1000_PTC127);
2977 adapter->stats.ptc255 += rd32(E1000_PTC255);
2978 adapter->stats.ptc511 += rd32(E1000_PTC511);
2979 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2980 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2981
2982 adapter->stats.mptc += rd32(E1000_MPTC);
2983 adapter->stats.bptc += rd32(E1000_BPTC);
2984
2985 /* used for adaptive IFS */
2986
2987 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2988 adapter->stats.tpt += hw->mac.tx_packet_delta;
2989 hw->mac.collision_delta = rd32(E1000_COLC);
2990 adapter->stats.colc += hw->mac.collision_delta;
2991
2992 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2993 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2994 adapter->stats.tncrs += rd32(E1000_TNCRS);
2995 adapter->stats.tsctc += rd32(E1000_TSCTC);
2996 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2997
2998 adapter->stats.iac += rd32(E1000_IAC);
2999 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3000 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3001 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3002 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3003 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3004 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3005 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3006 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3007
3008 /* Fill out the OS statistics structure */
3009 adapter->net_stats.multicast = adapter->stats.mprc;
3010 adapter->net_stats.collisions = adapter->stats.colc;
3011
3012 /* Rx Errors */
3013
3014 /* RLEC on some newer hardware can be incorrect so build
3015 * our own version based on RUC and ROC */
3016 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3017 adapter->stats.crcerrs + adapter->stats.algnerrc +
3018 adapter->stats.ruc + adapter->stats.roc +
3019 adapter->stats.cexterr;
3020 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3021 adapter->stats.roc;
3022 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3023 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3024 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3025
3026 /* Tx Errors */
3027 adapter->net_stats.tx_errors = adapter->stats.ecol +
3028 adapter->stats.latecol;
3029 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3030 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3031 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3032
3033 /* Tx Dropped needs to be maintained elsewhere */
3034
3035 /* Phy Stats */
3036 if (hw->phy.media_type == e1000_media_type_copper) {
3037 if ((adapter->link_speed == SPEED_1000) &&
3038 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3039 &phy_tmp))) {
3040 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3041 adapter->phy_stats.idle_errors += phy_tmp;
3042 }
3043 }
3044
3045 /* Management Stats */
3046 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3047 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3048 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3049 }
3050
3051
3052 static irqreturn_t igb_msix_other(int irq, void *data)
3053 {
3054 struct net_device *netdev = data;
3055 struct igb_adapter *adapter = netdev_priv(netdev);
3056 struct e1000_hw *hw = &adapter->hw;
3057 u32 eicr;
3058 /* disable interrupts from the "other" bit, avoid re-entry */
3059 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3060
3061 eicr = rd32(E1000_EICR);
3062
3063 if (eicr & E1000_EIMS_OTHER) {
3064 u32 icr = rd32(E1000_ICR);
3065 /* reading ICR causes bit 31 of EICR to be cleared */
3066 if (!(icr & E1000_ICR_LSC))
3067 goto no_link_interrupt;
3068 hw->mac.get_link_status = 1;
3069 /* guard against interrupt when we're going down */
3070 if (!test_bit(__IGB_DOWN, &adapter->state))
3071 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3072 }
3073
3074 no_link_interrupt:
3075 wr32(E1000_IMS, E1000_IMS_LSC);
3076 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3077
3078 return IRQ_HANDLED;
3079 }
3080
3081 static irqreturn_t igb_msix_tx(int irq, void *data)
3082 {
3083 struct igb_ring *tx_ring = data;
3084 struct igb_adapter *adapter = tx_ring->adapter;
3085 struct e1000_hw *hw = &adapter->hw;
3086
3087 if (!tx_ring->itr_val)
3088 wr32(E1000_EIMC, tx_ring->eims_value);
3089
3090 tx_ring->total_bytes = 0;
3091 tx_ring->total_packets = 0;
3092 if (!igb_clean_tx_irq(adapter, tx_ring))
3093 /* Ring was not completely cleaned, so fire another interrupt */
3094 wr32(E1000_EICS, tx_ring->eims_value);
3095
3096 if (!tx_ring->itr_val)
3097 wr32(E1000_EIMS, tx_ring->eims_value);
3098 return IRQ_HANDLED;
3099 }
3100
3101 static irqreturn_t igb_msix_rx(int irq, void *data)
3102 {
3103 struct igb_ring *rx_ring = data;
3104 struct igb_adapter *adapter = rx_ring->adapter;
3105 struct e1000_hw *hw = &adapter->hw;
3106
3107 if (!rx_ring->itr_val)
3108 wr32(E1000_EIMC, rx_ring->eims_value);
3109
3110 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3111 rx_ring->total_bytes = 0;
3112 rx_ring->total_packets = 0;
3113 rx_ring->no_itr_adjust = 0;
3114 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3115 } else {
3116 if (!rx_ring->no_itr_adjust) {
3117 igb_lower_rx_eitr(adapter, rx_ring);
3118 rx_ring->no_itr_adjust = 1;
3119 }
3120 }
3121
3122 return IRQ_HANDLED;
3123 }
3124
3125
3126 /**
3127 * igb_intr_msi - Interrupt Handler
3128 * @irq: interrupt number
3129 * @data: pointer to a network interface device structure
3130 **/
3131 static irqreturn_t igb_intr_msi(int irq, void *data)
3132 {
3133 struct net_device *netdev = data;
3134 struct igb_adapter *adapter = netdev_priv(netdev);
3135 struct napi_struct *napi = &adapter->napi;
3136 struct e1000_hw *hw = &adapter->hw;
3137 /* read ICR disables interrupts using IAM */
3138 u32 icr = rd32(E1000_ICR);
3139
3140 /* Write the ITR value calculated at the end of the
3141 * previous interrupt.
3142 */
3143 if (adapter->set_itr) {
3144 wr32(E1000_ITR,
3145 1000000000 / (adapter->itr * 256));
3146 adapter->set_itr = 0;
3147 }
3148
3149 /* read ICR disables interrupts using IAM */
3150 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3151 hw->mac.get_link_status = 1;
3152 if (!test_bit(__IGB_DOWN, &adapter->state))
3153 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3154 }
3155
3156 if (netif_rx_schedule_prep(netdev, napi)) {
3157 adapter->tx_ring->total_bytes = 0;
3158 adapter->tx_ring->total_packets = 0;
3159 adapter->rx_ring->total_bytes = 0;
3160 adapter->rx_ring->total_packets = 0;
3161 __netif_rx_schedule(netdev, napi);
3162 }
3163
3164 return IRQ_HANDLED;
3165 }
3166
3167 /**
3168 * igb_intr - Interrupt Handler
3169 * @irq: interrupt number
3170 * @data: pointer to a network interface device structure
3171 **/
3172 static irqreturn_t igb_intr(int irq, void *data)
3173 {
3174 struct net_device *netdev = data;
3175 struct igb_adapter *adapter = netdev_priv(netdev);
3176 struct napi_struct *napi = &adapter->napi;
3177 struct e1000_hw *hw = &adapter->hw;
3178 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3179 * need for the IMC write */
3180 u32 icr = rd32(E1000_ICR);
3181 u32 eicr = 0;
3182 if (!icr)
3183 return IRQ_NONE; /* Not our interrupt */
3184
3185 /* Write the ITR value calculated at the end of the
3186 * previous interrupt.
3187 */
3188 if (adapter->set_itr) {
3189 wr32(E1000_ITR,
3190 1000000000 / (adapter->itr * 256));
3191 adapter->set_itr = 0;
3192 }
3193
3194 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3195 * not set, then the adapter didn't send an interrupt */
3196 if (!(icr & E1000_ICR_INT_ASSERTED))
3197 return IRQ_NONE;
3198
3199 eicr = rd32(E1000_EICR);
3200
3201 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3202 hw->mac.get_link_status = 1;
3203 /* guard against interrupt when we're going down */
3204 if (!test_bit(__IGB_DOWN, &adapter->state))
3205 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3206 }
3207
3208 if (netif_rx_schedule_prep(netdev, napi)) {
3209 adapter->tx_ring->total_bytes = 0;
3210 adapter->rx_ring->total_bytes = 0;
3211 adapter->tx_ring->total_packets = 0;
3212 adapter->rx_ring->total_packets = 0;
3213 __netif_rx_schedule(netdev, napi);
3214 }
3215
3216 return IRQ_HANDLED;
3217 }
3218
3219 /**
3220 * igb_clean - NAPI Rx polling callback
3221 * @adapter: board private structure
3222 **/
3223 static int igb_clean(struct napi_struct *napi, int budget)
3224 {
3225 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3226 napi);
3227 struct net_device *netdev = adapter->netdev;
3228 int tx_clean_complete = 1, work_done = 0;
3229 int i;
3230
3231 /* Must NOT use netdev_priv macro here. */
3232 adapter = netdev->priv;
3233
3234 /* Keep link state information with original netdev */
3235 if (!netif_carrier_ok(netdev))
3236 goto quit_polling;
3237
3238 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3239 * being cleaned by multiple cpus simultaneously. A failure obtaining
3240 * the lock means tx_ring[i] is currently being cleaned anyway. */
3241 for (i = 0; i < adapter->num_tx_queues; i++) {
3242 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3243 tx_clean_complete &= igb_clean_tx_irq(adapter,
3244 &adapter->tx_ring[i]);
3245 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3246 }
3247 }
3248
3249 for (i = 0; i < adapter->num_rx_queues; i++)
3250 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done,
3251 adapter->rx_ring[i].napi.weight);
3252
3253 /* If no Tx and not enough Rx work done, exit the polling mode */
3254 if ((tx_clean_complete && (work_done < budget)) ||
3255 !netif_running(netdev)) {
3256 quit_polling:
3257 if (adapter->itr_setting & 3)
3258 igb_set_itr(adapter, E1000_ITR, false);
3259 netif_rx_complete(netdev, napi);
3260 if (!test_bit(__IGB_DOWN, &adapter->state))
3261 igb_irq_enable(adapter);
3262 return 0;
3263 }
3264
3265 return 1;
3266 }
3267
3268 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3269 {
3270 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3271 struct igb_adapter *adapter = rx_ring->adapter;
3272 struct e1000_hw *hw = &adapter->hw;
3273 struct net_device *netdev = adapter->netdev;
3274 int work_done = 0;
3275
3276 /* Keep link state information with original netdev */
3277 if (!netif_carrier_ok(netdev))
3278 goto quit_polling;
3279
3280 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget);
3281
3282
3283 /* If not enough Rx work done, exit the polling mode */
3284 if ((work_done == 0) || !netif_running(netdev)) {
3285 quit_polling:
3286 netif_rx_complete(netdev, napi);
3287
3288 wr32(E1000_EIMS, rx_ring->eims_value);
3289 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3290 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3291 int mean_size = rx_ring->total_bytes /
3292 rx_ring->total_packets;
3293 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3294 igb_raise_rx_eitr(adapter, rx_ring);
3295 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3296 igb_lower_rx_eitr(adapter, rx_ring);
3297 }
3298 return 0;
3299 }
3300
3301 return 1;
3302 }
3303 /**
3304 * igb_clean_tx_irq - Reclaim resources after transmit completes
3305 * @adapter: board private structure
3306 * returns true if ring is completely cleaned
3307 **/
3308 static bool igb_clean_tx_irq(struct igb_adapter *adapter,
3309 struct igb_ring *tx_ring)
3310 {
3311 struct net_device *netdev = adapter->netdev;
3312 struct e1000_hw *hw = &adapter->hw;
3313 struct e1000_tx_desc *tx_desc;
3314 struct igb_buffer *buffer_info;
3315 struct sk_buff *skb;
3316 unsigned int i;
3317 u32 head, oldhead;
3318 unsigned int count = 0;
3319 bool cleaned = false;
3320 bool retval = true;
3321 unsigned int total_bytes = 0, total_packets = 0;
3322
3323 rmb();
3324 head = *(volatile u32 *)((struct e1000_tx_desc *)tx_ring->desc
3325 + tx_ring->count);
3326 head = le32_to_cpu(head);
3327 i = tx_ring->next_to_clean;
3328 while (1) {
3329 while (i != head) {
3330 cleaned = true;
3331 tx_desc = E1000_TX_DESC(*tx_ring, i);
3332 buffer_info = &tx_ring->buffer_info[i];
3333 skb = buffer_info->skb;
3334
3335 if (skb) {
3336 unsigned int segs, bytecount;
3337 /* gso_segs is currently only valid for tcp */
3338 segs = skb_shinfo(skb)->gso_segs ?: 1;
3339 /* multiply data chunks by size of headers */
3340 bytecount = ((segs - 1) * skb_headlen(skb)) +
3341 skb->len;
3342 total_packets += segs;
3343 total_bytes += bytecount;
3344 }
3345
3346 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3347 tx_desc->upper.data = 0;
3348
3349 i++;
3350 if (i == tx_ring->count)
3351 i = 0;
3352
3353 count++;
3354 if (count == IGB_MAX_TX_CLEAN) {
3355 retval = false;
3356 goto done_cleaning;
3357 }
3358 }
3359 oldhead = head;
3360 rmb();
3361 head = *(volatile u32 *)((struct e1000_tx_desc *)tx_ring->desc
3362 + tx_ring->count);
3363 head = le32_to_cpu(head);
3364 if (head == oldhead)
3365 goto done_cleaning;
3366 } /* while (1) */
3367
3368 done_cleaning:
3369 tx_ring->next_to_clean = i;
3370
3371 if (unlikely(cleaned &&
3372 netif_carrier_ok(netdev) &&
3373 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3374 /* Make sure that anybody stopping the queue after this
3375 * sees the new next_to_clean.
3376 */
3377 smp_mb();
3378 if (netif_queue_stopped(netdev) &&
3379 !(test_bit(__IGB_DOWN, &adapter->state))) {
3380 netif_wake_queue(netdev);
3381 ++adapter->restart_queue;
3382 }
3383 }
3384
3385 if (tx_ring->detect_tx_hung) {
3386 /* Detect a transmit hang in hardware, this serializes the
3387 * check with the clearing of time_stamp and movement of i */
3388 tx_ring->detect_tx_hung = false;
3389 if (tx_ring->buffer_info[i].time_stamp &&
3390 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3391 (adapter->tx_timeout_factor * HZ))
3392 && !(rd32(E1000_STATUS) &
3393 E1000_STATUS_TXOFF)) {
3394
3395 tx_desc = E1000_TX_DESC(*tx_ring, i);
3396 /* detected Tx unit hang */
3397 dev_err(&adapter->pdev->dev,
3398 "Detected Tx Unit Hang\n"
3399 " Tx Queue <%lu>\n"
3400 " TDH <%x>\n"
3401 " TDT <%x>\n"
3402 " next_to_use <%x>\n"
3403 " next_to_clean <%x>\n"
3404 " head (WB) <%x>\n"
3405 "buffer_info[next_to_clean]\n"
3406 " time_stamp <%lx>\n"
3407 " jiffies <%lx>\n"
3408 " desc.status <%x>\n",
3409 (unsigned long)((tx_ring - adapter->tx_ring) /
3410 sizeof(struct igb_ring)),
3411 readl(adapter->hw.hw_addr + tx_ring->head),
3412 readl(adapter->hw.hw_addr + tx_ring->tail),
3413 tx_ring->next_to_use,
3414 tx_ring->next_to_clean,
3415 head,
3416 tx_ring->buffer_info[i].time_stamp,
3417 jiffies,
3418 tx_desc->upper.fields.status);
3419 netif_stop_queue(netdev);
3420 }
3421 }
3422 tx_ring->total_bytes += total_bytes;
3423 tx_ring->total_packets += total_packets;
3424 adapter->net_stats.tx_bytes += total_bytes;
3425 adapter->net_stats.tx_packets += total_packets;
3426 return retval;
3427 }
3428
3429
3430 /**
3431 * igb_receive_skb - helper function to handle rx indications
3432 * @adapter: board private structure
3433 * @status: descriptor status field as written by hardware
3434 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3435 * @skb: pointer to sk_buff to be indicated to stack
3436 **/
3437 static void igb_receive_skb(struct igb_adapter *adapter, u8 status, u16 vlan,
3438 struct sk_buff *skb)
3439 {
3440 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3441 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3442 le16_to_cpu(vlan) &
3443 E1000_RXD_SPC_VLAN_MASK);
3444 else
3445 netif_receive_skb(skb);
3446 }
3447
3448
3449 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3450 u32 status_err, struct sk_buff *skb)
3451 {
3452 skb->ip_summed = CHECKSUM_NONE;
3453
3454 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3455 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3456 return;
3457 /* TCP/UDP checksum error bit is set */
3458 if (status_err &
3459 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3460 /* let the stack verify checksum errors */
3461 adapter->hw_csum_err++;
3462 return;
3463 }
3464 /* It must be a TCP or UDP packet with a valid checksum */
3465 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3466 skb->ip_summed = CHECKSUM_UNNECESSARY;
3467
3468 adapter->hw_csum_good++;
3469 }
3470
3471 static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3472 struct igb_ring *rx_ring,
3473 int *work_done, int budget)
3474 {
3475 struct net_device *netdev = adapter->netdev;
3476 struct pci_dev *pdev = adapter->pdev;
3477 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3478 struct igb_buffer *buffer_info , *next_buffer;
3479 struct sk_buff *skb;
3480 unsigned int i, j;
3481 u32 length, hlen, staterr;
3482 bool cleaned = false;
3483 int cleaned_count = 0;
3484 unsigned int total_bytes = 0, total_packets = 0;
3485
3486 i = rx_ring->next_to_clean;
3487 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3488 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3489
3490 while (staterr & E1000_RXD_STAT_DD) {
3491 if (*work_done >= budget)
3492 break;
3493 (*work_done)++;
3494 buffer_info = &rx_ring->buffer_info[i];
3495
3496 /* HW will not DMA in data larger than the given buffer, even
3497 * if it parses the (NFS, of course) header to be larger. In
3498 * that case, it fills the header buffer and spills the rest
3499 * into the page.
3500 */
3501 hlen = le16_to_cpu((rx_desc->wb.lower.lo_dword.hdr_info &
3502 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT);
3503 if (hlen > adapter->rx_ps_hdr_size)
3504 hlen = adapter->rx_ps_hdr_size;
3505
3506 length = le16_to_cpu(rx_desc->wb.upper.length);
3507 cleaned = true;
3508 cleaned_count++;
3509
3510 if (rx_ring->pending_skb != NULL) {
3511 skb = rx_ring->pending_skb;
3512 rx_ring->pending_skb = NULL;
3513 j = rx_ring->pending_skb_page;
3514 } else {
3515 skb = buffer_info->skb;
3516 prefetch(skb->data - NET_IP_ALIGN);
3517 buffer_info->skb = NULL;
3518 if (hlen) {
3519 pci_unmap_single(pdev, buffer_info->dma,
3520 adapter->rx_ps_hdr_size +
3521 NET_IP_ALIGN,
3522 PCI_DMA_FROMDEVICE);
3523 skb_put(skb, hlen);
3524 } else {
3525 pci_unmap_single(pdev, buffer_info->dma,
3526 adapter->rx_buffer_len +
3527 NET_IP_ALIGN,
3528 PCI_DMA_FROMDEVICE);
3529 skb_put(skb, length);
3530 goto send_up;
3531 }
3532 j = 0;
3533 }
3534
3535 while (length) {
3536 pci_unmap_page(pdev, buffer_info->page_dma,
3537 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3538 buffer_info->page_dma = 0;
3539 skb_fill_page_desc(skb, j, buffer_info->page,
3540 0, length);
3541 buffer_info->page = NULL;
3542
3543 skb->len += length;
3544 skb->data_len += length;
3545 skb->truesize += length;
3546 rx_desc->wb.upper.status_error = 0;
3547 if (staterr & E1000_RXD_STAT_EOP)
3548 break;
3549
3550 j++;
3551 cleaned_count++;
3552 i++;
3553 if (i == rx_ring->count)
3554 i = 0;
3555
3556 buffer_info = &rx_ring->buffer_info[i];
3557 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3558 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3559 length = le16_to_cpu(rx_desc->wb.upper.length);
3560 if (!(staterr & E1000_RXD_STAT_DD)) {
3561 rx_ring->pending_skb = skb;
3562 rx_ring->pending_skb_page = j;
3563 goto out;
3564 }
3565 }
3566 send_up:
3567 pskb_trim(skb, skb->len - 4);
3568 i++;
3569 if (i == rx_ring->count)
3570 i = 0;
3571 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3572 prefetch(next_rxd);
3573 next_buffer = &rx_ring->buffer_info[i];
3574
3575 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3576 dev_kfree_skb_irq(skb);
3577 goto next_desc;
3578 }
3579 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3580
3581 total_bytes += skb->len;
3582 total_packets++;
3583
3584 igb_rx_checksum_adv(adapter, staterr, skb);
3585
3586 skb->protocol = eth_type_trans(skb, netdev);
3587
3588 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3589
3590 netdev->last_rx = jiffies;
3591
3592 next_desc:
3593 rx_desc->wb.upper.status_error = 0;
3594
3595 /* return some buffers to hardware, one at a time is too slow */
3596 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3597 igb_alloc_rx_buffers_adv(adapter, rx_ring,
3598 cleaned_count);
3599 cleaned_count = 0;
3600 }
3601
3602 /* use prefetched values */
3603 rx_desc = next_rxd;
3604 buffer_info = next_buffer;
3605
3606 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3607 }
3608 out:
3609 rx_ring->next_to_clean = i;
3610 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3611
3612 if (cleaned_count)
3613 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count);
3614
3615 rx_ring->total_packets += total_packets;
3616 rx_ring->total_bytes += total_bytes;
3617 rx_ring->rx_stats.packets += total_packets;
3618 rx_ring->rx_stats.bytes += total_bytes;
3619 adapter->net_stats.rx_bytes += total_bytes;
3620 adapter->net_stats.rx_packets += total_packets;
3621 return cleaned;
3622 }
3623
3624
3625 /**
3626 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3627 * @adapter: address of board private structure
3628 **/
3629 static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3630 struct igb_ring *rx_ring,
3631 int cleaned_count)
3632 {
3633 struct net_device *netdev = adapter->netdev;
3634 struct pci_dev *pdev = adapter->pdev;
3635 union e1000_adv_rx_desc *rx_desc;
3636 struct igb_buffer *buffer_info;
3637 struct sk_buff *skb;
3638 unsigned int i;
3639
3640 i = rx_ring->next_to_use;
3641 buffer_info = &rx_ring->buffer_info[i];
3642
3643 while (cleaned_count--) {
3644 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3645
3646 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3647 buffer_info->page = alloc_page(GFP_ATOMIC);
3648 if (!buffer_info->page) {
3649 adapter->alloc_rx_buff_failed++;
3650 goto no_buffers;
3651 }
3652 buffer_info->page_dma =
3653 pci_map_page(pdev,
3654 buffer_info->page,
3655 0, PAGE_SIZE,
3656 PCI_DMA_FROMDEVICE);
3657 }
3658
3659 if (!buffer_info->skb) {
3660 int bufsz;
3661
3662 if (adapter->rx_ps_hdr_size)
3663 bufsz = adapter->rx_ps_hdr_size;
3664 else
3665 bufsz = adapter->rx_buffer_len;
3666 bufsz += NET_IP_ALIGN;
3667 skb = netdev_alloc_skb(netdev, bufsz);
3668
3669 if (!skb) {
3670 adapter->alloc_rx_buff_failed++;
3671 goto no_buffers;
3672 }
3673
3674 /* Make buffer alignment 2 beyond a 16 byte boundary
3675 * this will result in a 16 byte aligned IP header after
3676 * the 14 byte MAC header is removed
3677 */
3678 skb_reserve(skb, NET_IP_ALIGN);
3679
3680 buffer_info->skb = skb;
3681 buffer_info->dma = pci_map_single(pdev, skb->data,
3682 bufsz,
3683 PCI_DMA_FROMDEVICE);
3684
3685 }
3686 /* Refresh the desc even if buffer_addrs didn't change because
3687 * each write-back erases this info. */
3688 if (adapter->rx_ps_hdr_size) {
3689 rx_desc->read.pkt_addr =
3690 cpu_to_le64(buffer_info->page_dma);
3691 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3692 } else {
3693 rx_desc->read.pkt_addr =
3694 cpu_to_le64(buffer_info->dma);
3695 rx_desc->read.hdr_addr = 0;
3696 }
3697
3698 i++;
3699 if (i == rx_ring->count)
3700 i = 0;
3701 buffer_info = &rx_ring->buffer_info[i];
3702 }
3703
3704 no_buffers:
3705 if (rx_ring->next_to_use != i) {
3706 rx_ring->next_to_use = i;
3707 if (i == 0)
3708 i = (rx_ring->count - 1);
3709 else
3710 i--;
3711
3712 /* Force memory writes to complete before letting h/w
3713 * know there are new descriptors to fetch. (Only
3714 * applicable for weak-ordered memory model archs,
3715 * such as IA-64). */
3716 wmb();
3717 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3718 }
3719 }
3720
3721 /**
3722 * igb_mii_ioctl -
3723 * @netdev:
3724 * @ifreq:
3725 * @cmd:
3726 **/
3727 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3728 {
3729 struct igb_adapter *adapter = netdev_priv(netdev);
3730 struct mii_ioctl_data *data = if_mii(ifr);
3731
3732 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3733 return -EOPNOTSUPP;
3734
3735 switch (cmd) {
3736 case SIOCGMIIPHY:
3737 data->phy_id = adapter->hw.phy.addr;
3738 break;
3739 case SIOCGMIIREG:
3740 if (!capable(CAP_NET_ADMIN))
3741 return -EPERM;
3742 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3743 data->reg_num
3744 & 0x1F, &data->val_out))
3745 return -EIO;
3746 break;
3747 case SIOCSMIIREG:
3748 default:
3749 return -EOPNOTSUPP;
3750 }
3751 return 0;
3752 }
3753
3754 /**
3755 * igb_ioctl -
3756 * @netdev:
3757 * @ifreq:
3758 * @cmd:
3759 **/
3760 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3761 {
3762 switch (cmd) {
3763 case SIOCGMIIPHY:
3764 case SIOCGMIIREG:
3765 case SIOCSMIIREG:
3766 return igb_mii_ioctl(netdev, ifr, cmd);
3767 default:
3768 return -EOPNOTSUPP;
3769 }
3770 }
3771
3772 static void igb_vlan_rx_register(struct net_device *netdev,
3773 struct vlan_group *grp)
3774 {
3775 struct igb_adapter *adapter = netdev_priv(netdev);
3776 struct e1000_hw *hw = &adapter->hw;
3777 u32 ctrl, rctl;
3778
3779 igb_irq_disable(adapter);
3780 adapter->vlgrp = grp;
3781
3782 if (grp) {
3783 /* enable VLAN tag insert/strip */
3784 ctrl = rd32(E1000_CTRL);
3785 ctrl |= E1000_CTRL_VME;
3786 wr32(E1000_CTRL, ctrl);
3787
3788 /* enable VLAN receive filtering */
3789 rctl = rd32(E1000_RCTL);
3790 rctl |= E1000_RCTL_VFE;
3791 rctl &= ~E1000_RCTL_CFIEN;
3792 wr32(E1000_RCTL, rctl);
3793 igb_update_mng_vlan(adapter);
3794 wr32(E1000_RLPML,
3795 adapter->max_frame_size + VLAN_TAG_SIZE);
3796 } else {
3797 /* disable VLAN tag insert/strip */
3798 ctrl = rd32(E1000_CTRL);
3799 ctrl &= ~E1000_CTRL_VME;
3800 wr32(E1000_CTRL, ctrl);
3801
3802 /* disable VLAN filtering */
3803 rctl = rd32(E1000_RCTL);
3804 rctl &= ~E1000_RCTL_VFE;
3805 wr32(E1000_RCTL, rctl);
3806 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3807 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3808 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3809 }
3810 wr32(E1000_RLPML,
3811 adapter->max_frame_size);
3812 }
3813
3814 if (!test_bit(__IGB_DOWN, &adapter->state))
3815 igb_irq_enable(adapter);
3816 }
3817
3818 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3819 {
3820 struct igb_adapter *adapter = netdev_priv(netdev);
3821 struct e1000_hw *hw = &adapter->hw;
3822 u32 vfta, index;
3823
3824 if ((adapter->hw.mng_cookie.status &
3825 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3826 (vid == adapter->mng_vlan_id))
3827 return;
3828 /* add VID to filter table */
3829 index = (vid >> 5) & 0x7F;
3830 vfta = array_rd32(E1000_VFTA, index);
3831 vfta |= (1 << (vid & 0x1F));
3832 igb_write_vfta(&adapter->hw, index, vfta);
3833 }
3834
3835 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3836 {
3837 struct igb_adapter *adapter = netdev_priv(netdev);
3838 struct e1000_hw *hw = &adapter->hw;
3839 u32 vfta, index;
3840
3841 igb_irq_disable(adapter);
3842 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3843
3844 if (!test_bit(__IGB_DOWN, &adapter->state))
3845 igb_irq_enable(adapter);
3846
3847 if ((adapter->hw.mng_cookie.status &
3848 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3849 (vid == adapter->mng_vlan_id)) {
3850 /* release control to f/w */
3851 igb_release_hw_control(adapter);
3852 return;
3853 }
3854
3855 /* remove VID from filter table */
3856 index = (vid >> 5) & 0x7F;
3857 vfta = array_rd32(E1000_VFTA, index);
3858 vfta &= ~(1 << (vid & 0x1F));
3859 igb_write_vfta(&adapter->hw, index, vfta);
3860 }
3861
3862 static void igb_restore_vlan(struct igb_adapter *adapter)
3863 {
3864 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3865
3866 if (adapter->vlgrp) {
3867 u16 vid;
3868 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3869 if (!vlan_group_get_device(adapter->vlgrp, vid))
3870 continue;
3871 igb_vlan_rx_add_vid(adapter->netdev, vid);
3872 }
3873 }
3874 }
3875
3876 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3877 {
3878 struct e1000_mac_info *mac = &adapter->hw.mac;
3879
3880 mac->autoneg = 0;
3881
3882 /* Fiber NICs only allow 1000 gbps Full duplex */
3883 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3884 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3885 dev_err(&adapter->pdev->dev,
3886 "Unsupported Speed/Duplex configuration\n");
3887 return -EINVAL;
3888 }
3889
3890 switch (spddplx) {
3891 case SPEED_10 + DUPLEX_HALF:
3892 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3893 break;
3894 case SPEED_10 + DUPLEX_FULL:
3895 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3896 break;
3897 case SPEED_100 + DUPLEX_HALF:
3898 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3899 break;
3900 case SPEED_100 + DUPLEX_FULL:
3901 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3902 break;
3903 case SPEED_1000 + DUPLEX_FULL:
3904 mac->autoneg = 1;
3905 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3906 break;
3907 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3908 default:
3909 dev_err(&adapter->pdev->dev,
3910 "Unsupported Speed/Duplex configuration\n");
3911 return -EINVAL;
3912 }
3913 return 0;
3914 }
3915
3916
3917 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3918 {
3919 struct net_device *netdev = pci_get_drvdata(pdev);
3920 struct igb_adapter *adapter = netdev_priv(netdev);
3921 struct e1000_hw *hw = &adapter->hw;
3922 u32 ctrl, ctrl_ext, rctl, status;
3923 u32 wufc = adapter->wol;
3924 #ifdef CONFIG_PM
3925 int retval = 0;
3926 #endif
3927
3928 netif_device_detach(netdev);
3929
3930 if (netif_running(netdev)) {
3931 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3932 igb_down(adapter);
3933 igb_free_irq(adapter);
3934 }
3935
3936 #ifdef CONFIG_PM
3937 retval = pci_save_state(pdev);
3938 if (retval)
3939 return retval;
3940 #endif
3941
3942 status = rd32(E1000_STATUS);
3943 if (status & E1000_STATUS_LU)
3944 wufc &= ~E1000_WUFC_LNKC;
3945
3946 if (wufc) {
3947 igb_setup_rctl(adapter);
3948 igb_set_multi(netdev);
3949
3950 /* turn on all-multi mode if wake on multicast is enabled */
3951 if (wufc & E1000_WUFC_MC) {
3952 rctl = rd32(E1000_RCTL);
3953 rctl |= E1000_RCTL_MPE;
3954 wr32(E1000_RCTL, rctl);
3955 }
3956
3957 ctrl = rd32(E1000_CTRL);
3958 /* advertise wake from D3Cold */
3959 #define E1000_CTRL_ADVD3WUC 0x00100000
3960 /* phy power management enable */
3961 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3962 ctrl |= E1000_CTRL_ADVD3WUC;
3963 wr32(E1000_CTRL, ctrl);
3964
3965 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3966 adapter->hw.phy.media_type ==
3967 e1000_media_type_internal_serdes) {
3968 /* keep the laser running in D3 */
3969 ctrl_ext = rd32(E1000_CTRL_EXT);
3970 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3971 wr32(E1000_CTRL_EXT, ctrl_ext);
3972 }
3973
3974 /* Allow time for pending master requests to run */
3975 igb_disable_pcie_master(&adapter->hw);
3976
3977 wr32(E1000_WUC, E1000_WUC_PME_EN);
3978 wr32(E1000_WUFC, wufc);
3979 pci_enable_wake(pdev, PCI_D3hot, 1);
3980 pci_enable_wake(pdev, PCI_D3cold, 1);
3981 } else {
3982 wr32(E1000_WUC, 0);
3983 wr32(E1000_WUFC, 0);
3984 pci_enable_wake(pdev, PCI_D3hot, 0);
3985 pci_enable_wake(pdev, PCI_D3cold, 0);
3986 }
3987
3988 <<<<<<< HEAD:drivers/net/igb/igb_main.c
3989 igb_release_manageability(adapter);
3990
3991 =======
3992 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/igb/igb_main.c
3993 /* make sure adapter isn't asleep if manageability is enabled */
3994 if (adapter->en_mng_pt) {
3995 pci_enable_wake(pdev, PCI_D3hot, 1);
3996 pci_enable_wake(pdev, PCI_D3cold, 1);
3997 }
3998
3999 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4000 * would have already happened in close and is redundant. */
4001 igb_release_hw_control(adapter);
4002
4003 pci_disable_device(pdev);
4004
4005 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4006
4007 return 0;
4008 }
4009
4010 #ifdef CONFIG_PM
4011 static int igb_resume(struct pci_dev *pdev)
4012 {
4013 struct net_device *netdev = pci_get_drvdata(pdev);
4014 struct igb_adapter *adapter = netdev_priv(netdev);
4015 struct e1000_hw *hw = &adapter->hw;
4016 u32 err;
4017
4018 pci_set_power_state(pdev, PCI_D0);
4019 pci_restore_state(pdev);
4020 err = pci_enable_device(pdev);
4021 if (err) {
4022 dev_err(&pdev->dev,
4023 "igb: Cannot enable PCI device from suspend\n");
4024 return err;
4025 }
4026 pci_set_master(pdev);
4027
4028 pci_enable_wake(pdev, PCI_D3hot, 0);
4029 pci_enable_wake(pdev, PCI_D3cold, 0);
4030
4031 if (netif_running(netdev)) {
4032 err = igb_request_irq(adapter);
4033 if (err)
4034 return err;
4035 }
4036
4037 /* e1000_power_up_phy(adapter); */
4038
4039 igb_reset(adapter);
4040 wr32(E1000_WUS, ~0);
4041
4042 igb_init_manageability(adapter);
4043
4044 if (netif_running(netdev))
4045 igb_up(adapter);
4046
4047 netif_device_attach(netdev);
4048
4049 /* let the f/w know that the h/w is now under the control of the
4050 * driver. */
4051 igb_get_hw_control(adapter);
4052
4053 return 0;
4054 }
4055 #endif
4056
4057 static void igb_shutdown(struct pci_dev *pdev)
4058 {
4059 igb_suspend(pdev, PMSG_SUSPEND);
4060 }
4061
4062 #ifdef CONFIG_NET_POLL_CONTROLLER
4063 /*
4064 * Polling 'interrupt' - used by things like netconsole to send skbs
4065 * without having to re-enable interrupts. It's not called while
4066 * the interrupt routine is executing.
4067 */
4068 static void igb_netpoll(struct net_device *netdev)
4069 {
4070 struct igb_adapter *adapter = netdev_priv(netdev);
4071 int i;
4072 int work_done = 0;
4073
4074 igb_irq_disable(adapter);
4075 for (i = 0; i < adapter->num_tx_queues; i++)
4076 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]);
4077
4078 for (i = 0; i < adapter->num_rx_queues; i++)
4079 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i],
4080 &work_done,
4081 adapter->rx_ring[i].napi.weight);
4082
4083 igb_irq_enable(adapter);
4084 }
4085 #endif /* CONFIG_NET_POLL_CONTROLLER */
4086
4087 /**
4088 * igb_io_error_detected - called when PCI error is detected
4089 * @pdev: Pointer to PCI device
4090 * @state: The current pci connection state
4091 *
4092 * This function is called after a PCI bus error affecting
4093 * this device has been detected.
4094 */
4095 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4096 pci_channel_state_t state)
4097 {
4098 struct net_device *netdev = pci_get_drvdata(pdev);
4099 struct igb_adapter *adapter = netdev_priv(netdev);
4100
4101 netif_device_detach(netdev);
4102
4103 if (netif_running(netdev))
4104 igb_down(adapter);
4105 pci_disable_device(pdev);
4106
4107 /* Request a slot slot reset. */
4108 return PCI_ERS_RESULT_NEED_RESET;
4109 }
4110
4111 /**
4112 * igb_io_slot_reset - called after the pci bus has been reset.
4113 * @pdev: Pointer to PCI device
4114 *
4115 * Restart the card from scratch, as if from a cold-boot. Implementation
4116 * resembles the first-half of the igb_resume routine.
4117 */
4118 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4119 {
4120 struct net_device *netdev = pci_get_drvdata(pdev);
4121 struct igb_adapter *adapter = netdev_priv(netdev);
4122 struct e1000_hw *hw = &adapter->hw;
4123
4124 if (pci_enable_device(pdev)) {
4125 dev_err(&pdev->dev,
4126 "Cannot re-enable PCI device after reset.\n");
4127 return PCI_ERS_RESULT_DISCONNECT;
4128 }
4129 pci_set_master(pdev);
4130
4131 pci_enable_wake(pdev, PCI_D3hot, 0);
4132 pci_enable_wake(pdev, PCI_D3cold, 0);
4133
4134 igb_reset(adapter);
4135 wr32(E1000_WUS, ~0);
4136
4137 return PCI_ERS_RESULT_RECOVERED;
4138 }
4139
4140 /**
4141 * igb_io_resume - called when traffic can start flowing again.
4142 * @pdev: Pointer to PCI device
4143 *
4144 * This callback is called when the error recovery driver tells us that
4145 * its OK to resume normal operation. Implementation resembles the
4146 * second-half of the igb_resume routine.
4147 */
4148 static void igb_io_resume(struct pci_dev *pdev)
4149 {
4150 struct net_device *netdev = pci_get_drvdata(pdev);
4151 struct igb_adapter *adapter = netdev_priv(netdev);
4152
4153 igb_init_manageability(adapter);
4154
4155 if (netif_running(netdev)) {
4156 if (igb_up(adapter)) {
4157 dev_err(&pdev->dev, "igb_up failed after reset\n");
4158 return;
4159 }
4160 }
4161
4162 netif_device_attach(netdev);
4163
4164 /* let the f/w know that the h/w is now under the control of the
4165 * driver. */
4166 igb_get_hw_control(adapter);
4167
4168 }
4169
4170 /* igb_main.c */
WRT350N Kernel Patches