drivers/net/wireless/rt2x00/rt2x00reg.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2x00
  23         Abstract: rt2x00 generic register information.
  24  */
  25
  26 #ifndef RT2X00REG_H
  27 #define RT2X00REG_H
  28
  29 /*
  30  * TX result flags.
  31  */
  32 enum TX_STATUS {
  33         TX_SUCCESS = 0,
  34         TX_SUCCESS_RETRY = 1,
  35         TX_FAIL_RETRY = 2,
  36         TX_FAIL_INVALID = 3,
  37         TX_FAIL_OTHER = 4,
  38 };
  39
  40 /*
  41  * Antenna values
  42  */
  43 enum antenna {
  44         ANTENNA_SW_DIVERSITY = 0,
  45         ANTENNA_A = 1,
  46         ANTENNA_B = 2,
  47         ANTENNA_HW_DIVERSITY = 3,
  48 };
  49
  50 /*
  51  * Led mode values.
  52  */
  53 enum led_mode {
  54         LED_MODE_DEFAULT = 0,
  55         LED_MODE_TXRX_ACTIVITY = 1,
  56         LED_MODE_SIGNAL_STRENGTH = 2,
  57         LED_MODE_ASUS = 3,
  58         LED_MODE_ALPHA = 4,
  59 };
  60
  61 /*
  62  * TSF sync values
  63  */
  64 enum tsf_sync {
  65         TSF_SYNC_NONE = 0,
  66         TSF_SYNC_INFRA = 1,
  67         TSF_SYNC_BEACON = 2,
  68 };
  69
  70 /*
  71  * Device states
  72  */
  73 enum dev_state {
  74         STATE_DEEP_SLEEP = 0,
  75         STATE_SLEEP = 1,
  76         STATE_STANDBY = 2,
  77         STATE_AWAKE = 3,
  78
  79 /*
  80  * Additional device states, these values are
  81  * not strict since they are not directly passed
  82  * into the device.
  83  */
  84         STATE_RADIO_ON,
  85         STATE_RADIO_OFF,
  86         STATE_RADIO_RX_ON,
  87         STATE_RADIO_RX_OFF,
  88 <<<<<<< HEAD:drivers/net/wireless/rt2x00/rt2x00reg.h
  89 =======
  90         STATE_RADIO_RX_ON_LINK,
  91         STATE_RADIO_RX_OFF_LINK,
  92 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/wireless/rt2x00/rt2x00reg.h
  93         STATE_RADIO_IRQ_ON,
  94         STATE_RADIO_IRQ_OFF,
  95 };
  96
  97 /*
  98  * IFS backoff values
  99  */
 100 enum ifs {
 101         IFS_BACKOFF = 0,
 102         IFS_SIFS = 1,
 103         IFS_NEW_BACKOFF = 2,
 104         IFS_NONE = 3,
 105 };
 106
 107 /*
 108  * Cipher types for hardware encryption
 109  */
 110 enum cipher {
 111         CIPHER_NONE = 0,
 112         CIPHER_WEP64 = 1,
 113         CIPHER_WEP128 = 2,
 114         CIPHER_TKIP = 3,
 115         CIPHER_AES = 4,
 116 /*
 117  * The following fields were added by rt61pci and rt73usb.
 118  */
 119         CIPHER_CKIP64 = 5,
 120         CIPHER_CKIP128 = 6,
 121         CIPHER_TKIP_NO_MIC = 7,
 122 };
 123
 124 /*
 125  * Register handlers.
 126  * We store the position of a register field inside a field structure,
 127  * This will simplify the process of setting and reading a certain field
 128  * inside the register while making sure the process remains byte order safe.
 129  */
 130 struct rt2x00_field8 {
 131         u8 bit_offset;
 132         u8 bit_mask;
 133 };
 134
 135 struct rt2x00_field16 {
 136         u16 bit_offset;
 137         u16 bit_mask;
 138 };
 139
 140 struct rt2x00_field32 {
 141         u32 bit_offset;
 142         u32 bit_mask;
 143 };
 144
 145 /*
 146  * Power of two check, this will check
 147  * if the mask that has been given contains
 148  * and contiguous set of bits.
 149  */
 150 #define is_power_of_two(x)      ( !((x) & ((x)-1)) )
 151 #define low_bit_mask(x)         ( ((x)-1) & ~(x) )
 152 #define is_valid_mask(x)        is_power_of_two(1 + (x) + low_bit_mask(x))
 153
 154 #define FIELD8(__mask)                          \
 155 ({                                              \
 156         BUILD_BUG_ON(!(__mask) ||               \
 157                      !is_valid_mask(__mask) ||  \
 158                      (__mask) != (u8)(__mask)); \
 159         (struct rt2x00_field8) {                \
 160                 __ffs(__mask), (__mask)         \
 161         };                                      \
 162 })
 163
 164 #define FIELD16(__mask)                         \
 165 ({                                              \
 166         BUILD_BUG_ON(!(__mask) ||               \
 167                      !is_valid_mask(__mask) ||  \
 168                      (__mask) != (u16)(__mask));\
 169         (struct rt2x00_field16) {               \
 170                 __ffs(__mask), (__mask)         \
 171         };                                      \
 172 })
 173
 174 #define FIELD32(__mask)                         \
 175 ({                                              \
 176         BUILD_BUG_ON(!(__mask) ||               \
 177                      !is_valid_mask(__mask) ||  \
 178                      (__mask) != (u32)(__mask));\
 179         (struct rt2x00_field32) {               \
 180                 __ffs(__mask), (__mask)         \
 181         };                                      \
 182 })
 183
 184 static inline void rt2x00_set_field32(u32 *reg,
 185                                       const struct rt2x00_field32 field,
 186                                       const u32 value)
 187 {
 188         *reg &= ~(field.bit_mask);
 189         *reg |= (value << field.bit_offset) & field.bit_mask;
 190 }
 191
 192 static inline u32 rt2x00_get_field32(const u32 reg,
 193                                      const struct rt2x00_field32 field)
 194 {
 195         return (reg & field.bit_mask) >> field.bit_offset;
 196 }
 197
 198 static inline void rt2x00_set_field16(u16 *reg,
 199                                       const struct rt2x00_field16 field,
 200                                       const u16 value)
 201 {
 202         *reg &= ~(field.bit_mask);
 203         *reg |= (value << field.bit_offset) & field.bit_mask;
 204 }
 205
 206 static inline u16 rt2x00_get_field16(const u16 reg,
 207                                      const struct rt2x00_field16 field)
 208 {
 209         return (reg & field.bit_mask) >> field.bit_offset;
 210 }
 211
 212 static inline void rt2x00_set_field8(u8 *reg,
 213                                      const struct rt2x00_field8 field,
 214                                      const u8 value)
 215 {
 216         *reg &= ~(field.bit_mask);
 217         *reg |= (value << field.bit_offset) & field.bit_mask;
 218 }
 219
 220 static inline u8 rt2x00_get_field8(const u8 reg,
 221                                    const struct rt2x00_field8 field)
 222 {
 223         return (reg & field.bit_mask) >> field.bit_offset;
 224 }
 225
 226 /*
 227  * Device specific rate value.
 228  * We will have to create the device specific rate value
 229  * passed to the ieee80211 kernel. We need to make it a consist of
 230  * multiple fields because we want to store more then 1 device specific
 231  * values inside the value.
 232  *      1 - rate, stored as 100 kbit/s.
 233  *      2 - preamble, short_preamble enabled flag.
 234  *      3 - MASK_RATE, which rates are enabled in this mode, this mask
 235  *      corresponds with the TX register format for the current device.
 236  *      4 - plcp, 802.11b rates are device specific,
 237  *      802.11g rates are set according to the ieee802.11a-1999 p.14.
 238  * The bit to enable preamble is set in a seperate define.
 239  */
 240 #define DEV_RATE        FIELD32(0x000007ff)
 241 #define DEV_PREAMBLE    FIELD32(0x00000800)
 242 #define DEV_RATEMASK    FIELD32(0x00fff000)
 243 #define DEV_PLCP        FIELD32(0xff000000)
 244
 245 /*
 246  * Bitfields
 247  */
 248 #define DEV_RATEBIT_1MB         ( 1 << 0 )
 249 #define DEV_RATEBIT_2MB         ( 1 << 1 )
 250 #define DEV_RATEBIT_5_5MB       ( 1 << 2 )
 251 #define DEV_RATEBIT_11MB        ( 1 << 3 )
 252 #define DEV_RATEBIT_6MB         ( 1 << 4 )
 253 #define DEV_RATEBIT_9MB         ( 1 << 5 )
 254 #define DEV_RATEBIT_12MB        ( 1 << 6 )
 255 #define DEV_RATEBIT_18MB        ( 1 << 7 )
 256 #define DEV_RATEBIT_24MB        ( 1 << 8 )
 257 #define DEV_RATEBIT_36MB        ( 1 << 9 )
 258 #define DEV_RATEBIT_48MB        ( 1 << 10 )
 259 #define DEV_RATEBIT_54MB        ( 1 << 11 )
 260
 261 /*
 262  * Bitmasks for DEV_RATEMASK
 263  */
 264 #define DEV_RATEMASK_1MB        ( (DEV_RATEBIT_1MB << 1) -1 )
 265 #define DEV_RATEMASK_2MB        ( (DEV_RATEBIT_2MB << 1) -1 )
 266 #define DEV_RATEMASK_5_5MB      ( (DEV_RATEBIT_5_5MB << 1) -1 )
 267 #define DEV_RATEMASK_11MB       ( (DEV_RATEBIT_11MB << 1) -1 )
 268 #define DEV_RATEMASK_6MB        ( (DEV_RATEBIT_6MB << 1) -1 )
 269 #define DEV_RATEMASK_9MB        ( (DEV_RATEBIT_9MB << 1) -1 )
 270 #define DEV_RATEMASK_12MB       ( (DEV_RATEBIT_12MB << 1) -1 )
 271 #define DEV_RATEMASK_18MB       ( (DEV_RATEBIT_18MB << 1) -1 )
 272 #define DEV_RATEMASK_24MB       ( (DEV_RATEBIT_24MB << 1) -1 )
 273 #define DEV_RATEMASK_36MB       ( (DEV_RATEBIT_36MB << 1) -1 )
 274 #define DEV_RATEMASK_48MB       ( (DEV_RATEBIT_48MB << 1) -1 )
 275 #define DEV_RATEMASK_54MB       ( (DEV_RATEBIT_54MB << 1) -1 )
 276
 277 /*
 278  * Bitmask groups of bitrates
 279  */
 280 #define DEV_BASIC_RATEMASK \
 281         ( DEV_RATEMASK_11MB | \
 282           DEV_RATEBIT_6MB | DEV_RATEBIT_12MB | DEV_RATEBIT_24MB )
 283
 284 #define DEV_CCK_RATEMASK        ( DEV_RATEMASK_11MB )
 285 #define DEV_OFDM_RATEMASK       ( DEV_RATEMASK_54MB & ~DEV_CCK_RATEMASK )
 286
 287 /*
 288  * Macro's to set and get specific fields from the device specific val and val2
 289  * fields inside the ieee80211_rate entry.
 290  */
 291 #define DEVICE_SET_RATE_FIELD(__value, __mask) \
 292         (int)( ((__value) << DEV_##__mask.bit_offset) & DEV_##__mask.bit_mask )
 293
 294 #define DEVICE_GET_RATE_FIELD(__value, __mask) \
 295         (int)( ((__value) & DEV_##__mask.bit_mask) >> DEV_##__mask.bit_offset )
 296
 297 #endif /* RT2X00REG_H */