drivers/pci/intel-iommu.h

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17 <<<<<<< HEAD:drivers/pci/intel-iommu.h
  18  * Copyright (C) Ashok Raj <ashok.raj@intel.com>
  19  * Copyright (C) Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  20 =======
  21  * Copyright (C) 2006-2008 Intel Corporation
  22  * Author: Ashok Raj <ashok.raj@intel.com>
  23  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  24 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/pci/intel-iommu.h
  25  */
  26
  27 #ifndef _INTEL_IOMMU_H_
  28 #define _INTEL_IOMMU_H_
  29
  30 #include <linux/types.h>
  31 #include <linux/msi.h>
  32 #include <linux/sysdev.h>
  33 #include "iova.h"
  34 #include <linux/io.h>
  35
  36 /*
  37  * We need a fixed PAGE_SIZE of 4K irrespective of
  38  * arch PAGE_SIZE for IOMMU page tables.
  39  */
  40 #define PAGE_SHIFT_4K           (12)
  41 #define PAGE_SIZE_4K            (1UL << PAGE_SHIFT_4K)
  42 #define PAGE_MASK_4K            (((u64)-1) << PAGE_SHIFT_4K)
  43 #define PAGE_ALIGN_4K(addr)     (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
  44
  45 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT_4K)
  46 #define DMA_32BIT_PFN           IOVA_PFN(DMA_32BIT_MASK)
  47 #define DMA_64BIT_PFN           IOVA_PFN(DMA_64BIT_MASK)
  48
  49 /*
  50  * Intel IOMMU register specification per version 1.0 public spec.
  51  */
  52
  53 #define DMAR_VER_REG    0x0     /* Arch version supported by this IOMMU */
  54 #define DMAR_CAP_REG    0x8     /* Hardware supported capabilities */
  55 #define DMAR_ECAP_REG   0x10    /* Extended capabilities supported */
  56 #define DMAR_GCMD_REG   0x18    /* Global command register */
  57 #define DMAR_GSTS_REG   0x1c    /* Global status register */
  58 #define DMAR_RTADDR_REG 0x20    /* Root entry table */
  59 #define DMAR_CCMD_REG   0x28    /* Context command reg */
  60 #define DMAR_FSTS_REG   0x34    /* Fault Status register */
  61 #define DMAR_FECTL_REG  0x38    /* Fault control register */
  62 #define DMAR_FEDATA_REG 0x3c    /* Fault event interrupt data register */
  63 #define DMAR_FEADDR_REG 0x40    /* Fault event interrupt addr register */
  64 #define DMAR_FEUADDR_REG 0x44   /* Upper address register */
  65 #define DMAR_AFLOG_REG  0x58    /* Advanced Fault control */
  66 #define DMAR_PMEN_REG   0x64    /* Enable Protected Memory Region */
  67 #define DMAR_PLMBASE_REG 0x68   /* PMRR Low addr */
  68 #define DMAR_PLMLIMIT_REG 0x6c  /* PMRR low limit */
  69 #define DMAR_PHMBASE_REG 0x70   /* pmrr high base addr */
  70 #define DMAR_PHMLIMIT_REG 0x78  /* pmrr high limit */
  71
  72 #define OFFSET_STRIDE           (9)
  73 /*
  74 #define dmar_readl(dmar, reg) readl(dmar + reg)
  75 #define dmar_readq(dmar, reg) ({ \
  76                 u32 lo, hi; \
  77                 lo = readl(dmar + reg); \
  78                 hi = readl(dmar + reg + 4); \
  79                 (((u64) hi) << 32) + lo; })
  80 */
  81 static inline u64 dmar_readq(void __iomem *addr)
  82 {
  83         u32 lo, hi;
  84         lo = readl(addr);
  85         hi = readl(addr + 4);
  86         return (((u64) hi) << 32) + lo;
  87 }
  88
  89 static inline void dmar_writeq(void __iomem *addr, u64 val)
  90 {
  91         writel((u32)val, addr);
  92         writel((u32)(val >> 32), addr + 4);
  93 }
  94
  95 #define DMAR_VER_MAJOR(v)               (((v) & 0xf0) >> 4)
  96 #define DMAR_VER_MINOR(v)               ((v) & 0x0f)
  97
  98 /*
  99  * Decoding Capability Register
 100  */
 101 #define cap_read_drain(c)       (((c) >> 55) & 1)
 102 #define cap_write_drain(c)      (((c) >> 54) & 1)
 103 #define cap_max_amask_val(c)    (((c) >> 48) & 0x3f)
 104 #define cap_num_fault_regs(c)   ((((c) >> 40) & 0xff) + 1)
 105 #define cap_pgsel_inv(c)        (((c) >> 39) & 1)
 106
 107 #define cap_super_page_val(c)   (((c) >> 34) & 0xf)
 108 #define cap_super_offset(c)     (((find_first_bit(&cap_super_page_val(c), 4)) \
 109                                         * OFFSET_STRIDE) + 21)
 110
 111 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
 112 #define cap_max_fault_reg_offset(c) \
 113         (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
 114
 115 #define cap_zlr(c)              (((c) >> 22) & 1)
 116 #define cap_isoch(c)            (((c) >> 23) & 1)
 117 #define cap_mgaw(c)             ((((c) >> 16) & 0x3f) + 1)
 118 #define cap_sagaw(c)            (((c) >> 8) & 0x1f)
 119 #define cap_caching_mode(c)     (((c) >> 7) & 1)
 120 #define cap_phmr(c)             (((c) >> 6) & 1)
 121 #define cap_plmr(c)             (((c) >> 5) & 1)
 122 #define cap_rwbf(c)             (((c) >> 4) & 1)
 123 #define cap_afl(c)              (((c) >> 3) & 1)
 124 #define cap_ndoms(c)            (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
 125 /*
 126  * Extended Capability Register
 127  */
 128
 129 #define ecap_niotlb_iunits(e)   ((((e) >> 24) & 0xff) + 1)
 130 #define ecap_iotlb_offset(e)    ((((e) >> 8) & 0x3ff) * 16)
 131 #define ecap_max_iotlb_offset(e) \
 132         (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
 133 #define ecap_coherent(e)        ((e) & 0x1)
 134
 135
 136 /* IOTLB_REG */
 137 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
 138 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
 139 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
 140 #define DMA_TLB_IIRG(type) ((type >> 60) & 7)
 141 #define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
 142 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
 143 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
 144 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
 145 #define DMA_TLB_IVT (((u64)1) << 63)
 146 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
 147 #define DMA_TLB_MAX_SIZE (0x3f)
 148
 149 /* PMEN_REG */
 150 #define DMA_PMEN_EPM (((u32)1)<<31)
 151 #define DMA_PMEN_PRS (((u32)1)<<0)
 152
 153 /* GCMD_REG */
 154 #define DMA_GCMD_TE (((u32)1) << 31)
 155 #define DMA_GCMD_SRTP (((u32)1) << 30)
 156 #define DMA_GCMD_SFL (((u32)1) << 29)
 157 #define DMA_GCMD_EAFL (((u32)1) << 28)
 158 #define DMA_GCMD_WBF (((u32)1) << 27)
 159
 160 /* GSTS_REG */
 161 #define DMA_GSTS_TES (((u32)1) << 31)
 162 #define DMA_GSTS_RTPS (((u32)1) << 30)
 163 #define DMA_GSTS_FLS (((u32)1) << 29)
 164 #define DMA_GSTS_AFLS (((u32)1) << 28)
 165 #define DMA_GSTS_WBFS (((u32)1) << 27)
 166
 167 /* CCMD_REG */
 168 #define DMA_CCMD_ICC (((u64)1) << 63)
 169 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
 170 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
 171 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
 172 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
 173 #define DMA_CCMD_MASK_NOBIT 0
 174 #define DMA_CCMD_MASK_1BIT 1
 175 #define DMA_CCMD_MASK_2BIT 2
 176 #define DMA_CCMD_MASK_3BIT 3
 177 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
 178 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
 179
 180 /* FECTL_REG */
 181 #define DMA_FECTL_IM (((u32)1) << 31)
 182
 183 /* FSTS_REG */
 184 #define DMA_FSTS_PPF ((u32)2)
 185 #define DMA_FSTS_PFO ((u32)1)
 186 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
 187
 188 /* FRCD_REG, 32 bits access */
 189 #define DMA_FRCD_F (((u32)1) << 31)
 190 #define dma_frcd_type(d) ((d >> 30) & 1)
 191 #define dma_frcd_fault_reason(c) (c & 0xff)
 192 #define dma_frcd_source_id(c) (c & 0xffff)
 193 #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
 194
 195 /*
 196  * 0: Present
 197  * 1-11: Reserved
 198  * 12-63: Context Ptr (12 - (haw-1))
 199  * 64-127: Reserved
 200  */
 201 struct root_entry {
 202         u64     val;
 203         u64     rsvd1;
 204 };
 205 #define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
 206 static inline bool root_present(struct root_entry *root)
 207 {
 208         return (root->val & 1);
 209 }
 210 static inline void set_root_present(struct root_entry *root)
 211 {
 212         root->val |= 1;
 213 }
 214 static inline void set_root_value(struct root_entry *root, unsigned long value)
 215 {
 216         root->val |= value & PAGE_MASK_4K;
 217 }
 218
 219 struct context_entry;
 220 static inline struct context_entry *
 221 get_context_addr_from_root(struct root_entry *root)
 222 {
 223         return (struct context_entry *)
 224                 (root_present(root)?phys_to_virt(
 225                 root->val & PAGE_MASK_4K):
 226                 NULL);
 227 }
 228
 229 /*
 230  * low 64 bits:
 231  * 0: present
 232  * 1: fault processing disable
 233  * 2-3: translation type
 234  * 12-63: address space root
 235  * high 64 bits:
 236  * 0-2: address width
 237  * 3-6: aval
 238  * 8-23: domain id
 239  */
 240 struct context_entry {
 241         u64 lo;
 242         u64 hi;
 243 };
 244 #define context_present(c) ((c).lo & 1)
 245 #define context_fault_disable(c) (((c).lo >> 1) & 1)
 246 #define context_translation_type(c) (((c).lo >> 2) & 3)
 247 #define context_address_root(c) ((c).lo & PAGE_MASK_4K)
 248 #define context_address_width(c) ((c).hi &  7)
 249 #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
 250
 251 #define context_set_present(c) do {(c).lo |= 1;} while (0)
 252 #define context_set_fault_enable(c) \
 253         do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
 254 #define context_set_translation_type(c, val) \
 255         do { \
 256                 (c).lo &= (((u64)-1) << 4) | 3; \
 257                 (c).lo |= ((val) & 3) << 2; \
 258         } while (0)
 259 #define CONTEXT_TT_MULTI_LEVEL 0
 260 #define context_set_address_root(c, val) \
 261         do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
 262 #define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
 263 #define context_set_domain_id(c, val) \
 264         do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
 265 #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
 266
 267 /*
 268  * 0: readable
 269  * 1: writable
 270  * 2-6: reserved
 271  * 7: super page
 272  * 8-11: available
 273  * 12-63: Host physcial address
 274  */
 275 struct dma_pte {
 276         u64 val;
 277 };
 278 #define dma_clear_pte(p)        do {(p).val = 0;} while (0)
 279
 280 #define DMA_PTE_READ (1)
 281 #define DMA_PTE_WRITE (2)
 282
 283 #define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
 284 #define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
 285 #define dma_set_pte_prot(p, prot) \
 286                 do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
 287 #define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
 288 #define dma_set_pte_addr(p, addr) do {\
 289                 (p).val |= ((addr) & PAGE_MASK_4K); } while (0)
 290 #define dma_pte_present(p) (((p).val & 3) != 0)
 291
 292 struct intel_iommu;
 293
 294 struct dmar_domain {
 295         int     id;                     /* domain id */
 296         struct intel_iommu *iommu;      /* back pointer to owning iommu */
 297
 298         struct list_head devices;       /* all devices' list */
 299         struct iova_domain iovad;       /* iova's that belong to this domain */
 300
 301         struct dma_pte  *pgd;           /* virtual address */
 302         spinlock_t      mapping_lock;   /* page table lock */
 303         int             gaw;            /* max guest address width */
 304
 305         /* adjusted guest address width, 0 is level 2 30-bit */
 306         int             agaw;
 307
 308 #define DOMAIN_FLAG_MULTIPLE_DEVICES 1
 309         int             flags;
 310 };
 311
 312 /* PCI domain-device relationship */
 313 struct device_domain_info {
 314         struct list_head link;  /* link to domain siblings */
 315         struct list_head global; /* link to global list */
 316         u8 bus;                 /* PCI bus numer */
 317         u8 devfn;               /* PCI devfn number */
 318         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
 319         struct dmar_domain *domain; /* pointer to domain */
 320 };
 321
 322 extern int init_dmars(void);
 323
 324 struct intel_iommu {
 325         void __iomem    *reg; /* Pointer to hardware regs, virtual addr */
 326         u64             cap;
 327         u64             ecap;
 328         unsigned long   *domain_ids; /* bitmap of domains */
 329         struct dmar_domain **domains; /* ptr to domains */
 330         int             seg;
 331         u32             gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
 332         spinlock_t      lock; /* protect context, domain ids */
 333         spinlock_t      register_lock; /* protect register handling */
 334         struct root_entry *root_entry; /* virtual address */
 335
 336         unsigned int irq;
 337         unsigned char name[7];    /* Device Name */
 338         struct msi_msg saved_msg;
 339         struct sys_device sysdev;
 340 };
 341
 342 #ifndef CONFIG_DMAR_GFX_WA
 343 static inline void iommu_prepare_gfx_mapping(void)
 344 {
 345         return;
 346 }
 347 #endif /* !CONFIG_DMAR_GFX_WA */
 348
 349 #endif