include/asm-x86/processor.h

   1 #ifndef __ASM_X86_PROCESSOR_H
   2 #define __ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* migration helpers, for KVM - will be removed in 2.6.25: */
   7 #include <asm/vm86.h>
   8 #define Xgt_desc_struct desc_ptr
   9
  10 /* Forward declaration, a strange C thing */
  11 struct task_struct;
  12 struct mm_struct;
  13
  14 #include <asm/vm86.h>
  15 #include <asm/math_emu.h>
  16 #include <asm/segment.h>
  17 #include <asm/types.h>
  18 #include <asm/sigcontext.h>
  19 #include <asm/current.h>
  20 #include <asm/cpufeature.h>
  21 #include <asm/system.h>
  22 #include <asm/page.h>
  23 #include <asm/percpu.h>
  24 #include <asm/msr.h>
  25 #include <asm/desc_defs.h>
  26 #include <asm/nops.h>
  27 #include <linux/personality.h>
  28 #include <linux/cpumask.h>
  29 #include <linux/cache.h>
  30 #include <linux/threads.h>
  31 #include <linux/init.h>
  32
  33 /*
  34  * Default implementation of macro that returns current
  35  * instruction pointer ("program counter").
  36  */
  37 static inline void *current_text_addr(void)
  38 {
  39         void *pc;
  40         asm volatile("mov $1f,%0\n1:":"=r" (pc));
  41         return pc;
  42 }
  43
  44 #ifdef CONFIG_X86_VSMP
  45 #define ARCH_MIN_TASKALIGN      (1 << INTERNODE_CACHE_SHIFT)
  46 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
  47 #else
  48 #define ARCH_MIN_TASKALIGN      16
  49 #define ARCH_MIN_MMSTRUCT_ALIGN 0
  50 #endif
  51
  52 /*
  53  *  CPU type and hardware bug flags. Kept separately for each CPU.
  54  *  Members of this structure are referenced in head.S, so think twice
  55  *  before touching them. [mj]
  56  */
  57
  58 struct cpuinfo_x86 {
  59         __u8    x86;            /* CPU family */
  60         __u8    x86_vendor;     /* CPU vendor */
  61         __u8    x86_model;
  62         __u8    x86_mask;
  63 #ifdef CONFIG_X86_32
  64         char    wp_works_ok;    /* It doesn't on 386's */
  65         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  66         char    hard_math;
  67         char    rfu;
  68         char    fdiv_bug;
  69         char    f00f_bug;
  70         char    coma_bug;
  71         char    pad0;
  72 #else
  73         /* number of 4K pages in DTLB/ITLB combined(in pages)*/
  74         int     x86_tlbsize;
  75         __u8    x86_virt_bits, x86_phys_bits;
  76         /* cpuid returned core id bits */
  77         __u8    x86_coreid_bits;
  78         /* Max extended CPUID function supported */
  79         __u32   extended_cpuid_level;
  80 #endif
  81         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  82         __u32   x86_capability[NCAPINTS];
  83         char    x86_vendor_id[16];
  84         char    x86_model_id[64];
  85         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  86                                     call  */
  87         int     x86_cache_alignment;    /* In bytes */
  88         int     x86_power;
  89         unsigned long loops_per_jiffy;
  90 #ifdef CONFIG_SMP
  91         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  92 #endif
  93         u16 x86_max_cores;              /* cpuid returned max cores value */
  94         u16 apicid;
  95         u16 x86_clflush_size;
  96 #ifdef CONFIG_SMP
  97         u16 booted_cores;               /* number of cores as seen by OS */
  98         u16 phys_proc_id;               /* Physical processor id. */
  99         u16 cpu_core_id;                /* Core id */
 100         u16 cpu_index;                  /* index into per_cpu list */
 101 #endif
 102 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 103
 104 #define X86_VENDOR_INTEL 0
 105 #define X86_VENDOR_CYRIX 1
 106 #define X86_VENDOR_AMD 2
 107 #define X86_VENDOR_UMC 3
 108 #define X86_VENDOR_NEXGEN 4
 109 #define X86_VENDOR_CENTAUR 5
 110 #define X86_VENDOR_TRANSMETA 7
 111 #define X86_VENDOR_NSC 8
 112 #define X86_VENDOR_NUM 9
 113 #define X86_VENDOR_UNKNOWN 0xff
 114
 115 /*
 116  * capabilities of CPUs
 117  */
 118 extern struct cpuinfo_x86 boot_cpu_data;
 119 extern struct cpuinfo_x86 new_cpu_data;
 120 extern struct tss_struct doublefault_tss;
 121 extern __u32 cleared_cpu_caps[NCAPINTS];
 122
 123 #ifdef CONFIG_SMP
 124 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 125 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 126 #define current_cpu_data        cpu_data(smp_processor_id())
 127 #else
 128 #define cpu_data(cpu)           boot_cpu_data
 129 #define current_cpu_data        boot_cpu_data
 130 #endif
 131
 132 void cpu_detect(struct cpuinfo_x86 *c);
 133
 134 extern void identify_cpu(struct cpuinfo_x86 *);
 135 extern void identify_boot_cpu(void);
 136 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 137 extern void print_cpu_info(struct cpuinfo_x86 *);
 138 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 139 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 140 extern unsigned short num_cache_leaves;
 141
 142 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
 143 extern void detect_ht(struct cpuinfo_x86 *c);
 144 #else
 145 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 146 #endif
 147
 148 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 149                                          unsigned int *ecx, unsigned int *edx)
 150 {
 151         /* ecx is often an input as well as an output. */
 152         __asm__("cpuid"
 153                 : "=a" (*eax),
 154                   "=b" (*ebx),
 155                   "=c" (*ecx),
 156                   "=d" (*edx)
 157                 : "0" (*eax), "2" (*ecx));
 158 }
 159
 160 static inline void load_cr3(pgd_t *pgdir)
 161 {
 162         write_cr3(__pa(pgdir));
 163 }
 164
 165 #ifdef CONFIG_X86_32
 166 /* This is the TSS defined by the hardware. */
 167 struct x86_hw_tss {
 168         unsigned short  back_link, __blh;
 169         unsigned long   sp0;
 170         unsigned short  ss0, __ss0h;
 171         unsigned long   sp1;
 172         unsigned short  ss1, __ss1h;    /* ss1 caches MSR_IA32_SYSENTER_CS */
 173         unsigned long   sp2;
 174         unsigned short  ss2, __ss2h;
 175         unsigned long   __cr3;
 176         unsigned long   ip;
 177         unsigned long   flags;
 178         unsigned long   ax, cx, dx, bx;
 179         unsigned long   sp, bp, si, di;
 180         unsigned short  es, __esh;
 181         unsigned short  cs, __csh;
 182         unsigned short  ss, __ssh;
 183         unsigned short  ds, __dsh;
 184         unsigned short  fs, __fsh;
 185         unsigned short  gs, __gsh;
 186         unsigned short  ldt, __ldth;
 187         unsigned short  trace, io_bitmap_base;
 188 } __attribute__((packed));
 189 #else
 190 struct x86_hw_tss {
 191         u32 reserved1;
 192         u64 sp0;
 193         u64 sp1;
 194         u64 sp2;
 195         u64 reserved2;
 196         u64 ist[7];
 197         u32 reserved3;
 198         u32 reserved4;
 199         u16 reserved5;
 200         u16 io_bitmap_base;
 201 } __attribute__((packed)) ____cacheline_aligned;
 202 #endif
 203
 204 /*
 205  * Size of io_bitmap.
 206  */
 207 #define IO_BITMAP_BITS  65536
 208 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 209 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 210 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
 211 #define INVALID_IO_BITMAP_OFFSET 0x8000
 212 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 213
 214 struct tss_struct {
 215         struct x86_hw_tss x86_tss;
 216
 217         /*
 218          * The extra 1 is there because the CPU will access an
 219          * additional byte beyond the end of the IO permission
 220          * bitmap. The extra byte must be all 1 bits, and must
 221          * be within the limit.
 222          */
 223         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 224         /*
 225          * Cache the current maximum and the last task that used the bitmap:
 226          */
 227         unsigned long io_bitmap_max;
 228         struct thread_struct *io_bitmap_owner;
 229         /*
 230          * pads the TSS to be cacheline-aligned (size is 0x100)
 231          */
 232         unsigned long __cacheline_filler[35];
 233         /*
 234          * .. and then another 0x100 bytes for emergency kernel stack
 235          */
 236         unsigned long stack[64];
 237 } __attribute__((packed));
 238
 239 DECLARE_PER_CPU(struct tss_struct, init_tss);
 240
 241 /* Save the original ist values for checking stack pointers during debugging */
 242 struct orig_ist {
 243         unsigned long ist[7];
 244 };
 245
 246 #define MXCSR_DEFAULT           0x1f80
 247
 248 struct i387_fsave_struct {
 249         u32     cwd;
 250         u32     swd;
 251         u32     twd;
 252         u32     fip;
 253         u32     fcs;
 254         u32     foo;
 255         u32     fos;
 256         u32     st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 257         u32     status;         /* software status information */
 258 };
 259
 260 struct i387_fxsave_struct {
 261         u16     cwd;
 262         u16     swd;
 263         u16     twd;
 264         u16     fop;
 265         union {
 266                 struct {
 267                         u64     rip;
 268                         u64     rdp;
 269                 };
 270                 struct {
 271                         u32     fip;
 272                         u32     fcs;
 273                         u32     foo;
 274                         u32     fos;
 275                 };
 276         };
 277         u32     mxcsr;
 278         u32     mxcsr_mask;
 279         u32     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 280         u32     xmm_space[64];  /* 16*16 bytes for each XMM-reg = 256 bytes */
 281         u32     padding[24];
 282 } __attribute__((aligned(16)));
 283
 284 struct i387_soft_struct {
 285         u32     cwd;
 286         u32     swd;
 287         u32     twd;
 288         u32     fip;
 289         u32     fcs;
 290         u32     foo;
 291         u32     fos;
 292         u32     st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 293         u8      ftop, changed, lookahead, no_update, rm, alimit;
 294         struct info     *info;
 295         u32     entry_eip;
 296 };
 297
 298 union i387_union {
 299         struct i387_fsave_struct        fsave;
 300         struct i387_fxsave_struct       fxsave;
 301         struct i387_soft_struct         soft;
 302 };
 303
 304 #ifdef CONFIG_X86_32
 305 <<<<<<< HEAD:include/asm-x86/processor.h
 306 /*
 307  * the following now lives in the per cpu area:
 308  * extern       int cpu_llc_id[NR_CPUS];
 309  */
 310 =======
 311 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-x86/processor.h
 312 DECLARE_PER_CPU(u8, cpu_llc_id);
 313 #else
 314 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 315 #endif
 316
 317 extern void print_cpu_info(struct cpuinfo_x86 *);
 318 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 319 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 320 extern unsigned short num_cache_leaves;
 321
 322 struct thread_struct {
 323 /* cached TLS descriptors. */
 324         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 325         unsigned long   sp0;
 326         unsigned long   sp;
 327 #ifdef CONFIG_X86_32
 328         unsigned long   sysenter_cs;
 329 #else
 330         unsigned long   usersp; /* Copy from PDA */
 331         unsigned short  es, ds, fsindex, gsindex;
 332 #endif
 333         unsigned long   ip;
 334         unsigned long   fs;
 335         unsigned long   gs;
 336 /* Hardware debugging registers */
 337         unsigned long   debugreg0;
 338         unsigned long   debugreg1;
 339         unsigned long   debugreg2;
 340         unsigned long   debugreg3;
 341         unsigned long   debugreg6;
 342         unsigned long   debugreg7;
 343 /* fault info */
 344         unsigned long   cr2, trap_no, error_code;
 345 /* floating point info */
 346         union i387_union        i387 __attribute__((aligned(16)));;
 347 #ifdef CONFIG_X86_32
 348 /* virtual 86 mode info */
 349         struct vm86_struct __user *vm86_info;
 350         unsigned long           screen_bitmap;
 351         unsigned long           v86flags, v86mask, saved_sp0;
 352         unsigned int            saved_fs, saved_gs;
 353 #endif
 354 /* IO permissions */
 355         unsigned long   *io_bitmap_ptr;
 356         unsigned long   iopl;
 357 /* max allowed port in the bitmap, in bytes: */
 358         unsigned io_bitmap_max;
 359 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 360         unsigned long   debugctlmsr;
 361 /* Debug Store - if not 0 points to a DS Save Area configuration;
 362  *               goes into MSR_IA32_DS_AREA */
 363         unsigned long   ds_area_msr;
 364 };
 365
 366 static inline unsigned long native_get_debugreg(int regno)
 367 {
 368         unsigned long val = 0;  /* Damn you, gcc! */
 369
 370         switch (regno) {
 371         case 0:
 372                 asm("mov %%db0, %0" :"=r" (val)); break;
 373         case 1:
 374                 asm("mov %%db1, %0" :"=r" (val)); break;
 375         case 2:
 376                 asm("mov %%db2, %0" :"=r" (val)); break;
 377         case 3:
 378                 asm("mov %%db3, %0" :"=r" (val)); break;
 379         case 6:
 380                 asm("mov %%db6, %0" :"=r" (val)); break;
 381         case 7:
 382                 asm("mov %%db7, %0" :"=r" (val)); break;
 383         default:
 384                 BUG();
 385         }
 386         return val;
 387 }
 388
 389 static inline void native_set_debugreg(int regno, unsigned long value)
 390 {
 391         switch (regno) {
 392         case 0:
 393                 asm("mov %0,%%db0"      : /* no output */ :"r" (value));
 394                 break;
 395         case 1:
 396                 asm("mov %0,%%db1"      : /* no output */ :"r" (value));
 397                 break;
 398         case 2:
 399                 asm("mov %0,%%db2"      : /* no output */ :"r" (value));
 400                 break;
 401         case 3:
 402                 asm("mov %0,%%db3"      : /* no output */ :"r" (value));
 403                 break;
 404         case 6:
 405                 asm("mov %0,%%db6"      : /* no output */ :"r" (value));
 406                 break;
 407         case 7:
 408                 asm("mov %0,%%db7"      : /* no output */ :"r" (value));
 409                 break;
 410         default:
 411                 BUG();
 412         }
 413 }
 414
 415 /*
 416  * Set IOPL bits in EFLAGS from given mask
 417  */
 418 static inline void native_set_iopl_mask(unsigned mask)
 419 {
 420 #ifdef CONFIG_X86_32
 421         unsigned int reg;
 422         __asm__ __volatile__ ("pushfl;"
 423                               "popl %0;"
 424                               "andl %1, %0;"
 425                               "orl %2, %0;"
 426                               "pushl %0;"
 427                               "popfl"
 428                                 : "=&r" (reg)
 429                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 430 #endif
 431 }
 432
 433 static inline void native_load_sp0(struct tss_struct *tss,
 434                                    struct thread_struct *thread)
 435 {
 436         tss->x86_tss.sp0 = thread->sp0;
 437 #ifdef CONFIG_X86_32
 438         /* Only happens when SEP is enabled, no need to test "SEP"arately */
 439         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 440                 tss->x86_tss.ss1 = thread->sysenter_cs;
 441                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 442         }
 443 #endif
 444 }
 445
 446 static inline void native_swapgs(void)
 447 {
 448 #ifdef CONFIG_X86_64
 449         asm volatile("swapgs" ::: "memory");
 450 #endif
 451 }
 452
 453 #ifdef CONFIG_PARAVIRT
 454 #include <asm/paravirt.h>
 455 #else
 456 #define __cpuid native_cpuid
 457 #define paravirt_enabled() 0
 458
 459 /*
 460  * These special macros can be used to get or set a debugging register
 461  */
 462 #define get_debugreg(var, register)                             \
 463         (var) = native_get_debugreg(register)
 464 #define set_debugreg(value, register)                           \
 465         native_set_debugreg(register, value)
 466
 467 static inline void load_sp0(struct tss_struct *tss,
 468                             struct thread_struct *thread)
 469 {
 470         native_load_sp0(tss, thread);
 471 }
 472
 473 #define set_iopl_mask native_set_iopl_mask
 474 #define SWAPGS  swapgs
 475 #endif /* CONFIG_PARAVIRT */
 476
 477 /*
 478  * Save the cr4 feature set we're using (ie
 479  * Pentium 4MB enable and PPro Global page
 480  * enable), so that any CPU's that boot up
 481  * after us can get the correct flags.
 482  */
 483 extern unsigned long mmu_cr4_features;
 484
 485 static inline void set_in_cr4(unsigned long mask)
 486 {
 487         unsigned cr4;
 488         mmu_cr4_features |= mask;
 489         cr4 = read_cr4();
 490         cr4 |= mask;
 491         write_cr4(cr4);
 492 }
 493
 494 static inline void clear_in_cr4(unsigned long mask)
 495 {
 496         unsigned cr4;
 497         mmu_cr4_features &= ~mask;
 498         cr4 = read_cr4();
 499         cr4 &= ~mask;
 500         write_cr4(cr4);
 501 }
 502
 503 struct microcode_header {
 504         unsigned int hdrver;
 505         unsigned int rev;
 506         unsigned int date;
 507         unsigned int sig;
 508         unsigned int cksum;
 509         unsigned int ldrver;
 510         unsigned int pf;
 511         unsigned int datasize;
 512         unsigned int totalsize;
 513         unsigned int reserved[3];
 514 };
 515
 516 struct microcode {
 517         struct microcode_header hdr;
 518         unsigned int bits[0];
 519 };
 520
 521 typedef struct microcode microcode_t;
 522 typedef struct microcode_header microcode_header_t;
 523
 524 /* microcode format is extended from prescott processors */
 525 struct extended_signature {
 526         unsigned int sig;
 527         unsigned int pf;
 528         unsigned int cksum;
 529 };
 530
 531 struct extended_sigtable {
 532         unsigned int count;
 533         unsigned int cksum;
 534         unsigned int reserved[3];
 535         struct extended_signature sigs[0];
 536 };
 537
 538 typedef struct {
 539         unsigned long seg;
 540 } mm_segment_t;
 541
 542
 543 /*
 544  * create a kernel thread without removing it from tasklists
 545  */
 546 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 547
 548 /* Free all resources held by a thread. */
 549 extern void release_thread(struct task_struct *);
 550
 551 /* Prepare to copy thread state - unlazy all lazy status */
 552 extern void prepare_to_copy(struct task_struct *tsk);
 553
 554 unsigned long get_wchan(struct task_struct *p);
 555
 556 /*
 557  * Generic CPUID function
 558  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 559  * resulting in stale register contents being returned.
 560  */
 561 static inline void cpuid(unsigned int op,
 562                          unsigned int *eax, unsigned int *ebx,
 563                          unsigned int *ecx, unsigned int *edx)
 564 {
 565         *eax = op;
 566         *ecx = 0;
 567         __cpuid(eax, ebx, ecx, edx);
 568 }
 569
 570 /* Some CPUID calls want 'count' to be placed in ecx */
 571 static inline void cpuid_count(unsigned int op, int count,
 572                                unsigned int *eax, unsigned int *ebx,
 573                                unsigned int *ecx, unsigned int *edx)
 574 {
 575         *eax = op;
 576         *ecx = count;
 577         __cpuid(eax, ebx, ecx, edx);
 578 }
 579
 580 /*
 581  * CPUID functions returning a single datum
 582  */
 583 static inline unsigned int cpuid_eax(unsigned int op)
 584 {
 585         unsigned int eax, ebx, ecx, edx;
 586
 587         cpuid(op, &eax, &ebx, &ecx, &edx);
 588         return eax;
 589 }
 590 static inline unsigned int cpuid_ebx(unsigned int op)
 591 {
 592         unsigned int eax, ebx, ecx, edx;
 593
 594         cpuid(op, &eax, &ebx, &ecx, &edx);
 595         return ebx;
 596 }
 597 static inline unsigned int cpuid_ecx(unsigned int op)
 598 {
 599         unsigned int eax, ebx, ecx, edx;
 600
 601         cpuid(op, &eax, &ebx, &ecx, &edx);
 602         return ecx;
 603 }
 604 static inline unsigned int cpuid_edx(unsigned int op)
 605 {
 606         unsigned int eax, ebx, ecx, edx;
 607
 608         cpuid(op, &eax, &ebx, &ecx, &edx);
 609         return edx;
 610 }
 611
 612 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 613 static inline void rep_nop(void)
 614 {
 615         __asm__ __volatile__("rep;nop": : :"memory");
 616 }
 617
 618 /* Stop speculative execution */
 619 static inline void sync_core(void)
 620 {
 621         int tmp;
 622         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 623                                           : "ebx", "ecx", "edx", "memory");
 624 }
 625
 626 #define cpu_relax()   rep_nop()
 627
 628 static inline void __monitor(const void *eax, unsigned long ecx,
 629                 unsigned long edx)
 630 {
 631         /* "monitor %eax,%ecx,%edx;" */
 632         asm volatile(
 633                 ".byte 0x0f,0x01,0xc8;"
 634                 : :"a" (eax), "c" (ecx), "d"(edx));
 635 }
 636
 637 static inline void __mwait(unsigned long eax, unsigned long ecx)
 638 {
 639         /* "mwait %eax,%ecx;" */
 640         asm volatile(
 641                 ".byte 0x0f,0x01,0xc9;"
 642                 : :"a" (eax), "c" (ecx));
 643 }
 644
 645 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 646 {
 647         /* "mwait %eax,%ecx;" */
 648         asm volatile(
 649                 "sti; .byte 0x0f,0x01,0xc9;"
 650                 : :"a" (eax), "c" (ecx));
 651 }
 652
 653 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 654
 655 extern int force_mwait;
 656
 657 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 658
 659 extern unsigned long boot_option_idle_override;
 660
 661 extern void enable_sep_cpu(void);
 662 extern int sysenter_setup(void);
 663
 664 /* Defined in head.S */
 665 extern struct desc_ptr early_gdt_descr;
 666
 667 extern void cpu_set_gdt(int);
 668 extern void switch_to_new_gdt(void);
 669 extern void cpu_init(void);
 670 extern void init_gdt(int cpu);
 671
 672 /* from system description table in BIOS.  Mostly for MCA use, but
 673  * others may find it useful. */
 674 extern unsigned int machine_id;
 675 extern unsigned int machine_submodel_id;
 676 extern unsigned int BIOS_revision;
 677 <<<<<<< HEAD:include/asm-x86/processor.h
 678 extern unsigned int mca_pentium_flag;
 679 =======
 680 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-x86/processor.h
 681
 682 /* Boot loader type from the setup header */
 683 extern int bootloader_type;
 684
 685 extern char ignore_fpu_irq;
 686 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 687
 688 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 689 #define ARCH_HAS_PREFETCHW
 690 #define ARCH_HAS_SPINLOCK_PREFETCH
 691
 692 #ifdef CONFIG_X86_32
 693 #define BASE_PREFETCH   ASM_NOP4
 694 #define ARCH_HAS_PREFETCH
 695 #else
 696 #define BASE_PREFETCH   "prefetcht0 (%1)"
 697 #endif
 698
 699 /* Prefetch instructions for Pentium III and AMD Athlon */
 700 /* It's not worth to care about 3dnow! prefetches for the K6
 701    because they are microcoded there and very slow.
 702    However we don't do prefetches for pre XP Athlons currently
 703    That should be fixed. */
 704 static inline void prefetch(const void *x)
 705 {
 706         alternative_input(BASE_PREFETCH,
 707                           "prefetchnta (%1)",
 708                           X86_FEATURE_XMM,
 709                           "r" (x));
 710 }
 711
 712 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 713    spinlocks to avoid one state transition in the cache coherency protocol. */
 714 static inline void prefetchw(const void *x)
 715 {
 716         alternative_input(BASE_PREFETCH,
 717                           "prefetchw (%1)",
 718                           X86_FEATURE_3DNOW,
 719                           "r" (x));
 720 }
 721
 722 #define spin_lock_prefetch(x)   prefetchw(x)
 723 #ifdef CONFIG_X86_32
 724 /*
 725  * User space process size: 3GB (default).
 726  */
 727 #define TASK_SIZE       (PAGE_OFFSET)
 728 #define STACK_TOP       TASK_SIZE
 729 #define STACK_TOP_MAX   STACK_TOP
 730
 731 #define INIT_THREAD  {                                                  \
 732         .sp0 = sizeof(init_stack) + (long)&init_stack,                  \
 733         .vm86_info = NULL,                                              \
 734         .sysenter_cs = __KERNEL_CS,                                     \
 735         .io_bitmap_ptr = NULL,                                          \
 736         .fs = __KERNEL_PERCPU,                                          \
 737 }
 738
 739 /*
 740  * Note that the .io_bitmap member must be extra-big. This is because
 741  * the CPU will access an additional byte beyond the end of the IO
 742  * permission bitmap. The extra byte must be all 1 bits, and must
 743  * be within the limit.
 744  */
 745 #define INIT_TSS  {                                                     \
 746         .x86_tss = {                                                    \
 747                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 748                 .ss0            = __KERNEL_DS,                          \
 749                 .ss1            = __KERNEL_CS,                          \
 750                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
 751          },                                                             \
 752         .io_bitmap      = { [0 ... IO_BITMAP_LONGS] = ~0 },             \
 753 }
 754
 755 #define start_thread(regs, new_eip, new_esp) do {               \
 756         __asm__("movl %0,%%gs": :"r" (0));                      \
 757         regs->fs = 0;                                           \
 758         set_fs(USER_DS);                                        \
 759         regs->ds = __USER_DS;                                   \
 760         regs->es = __USER_DS;                                   \
 761         regs->ss = __USER_DS;                                   \
 762         regs->cs = __USER_CS;                                   \
 763         regs->ip = new_eip;                                     \
 764         regs->sp = new_esp;                                     \
 765 } while (0)
 766
 767
 768 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 769
 770 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 771 #define KSTK_TOP(info)                                                 \
 772 ({                                                                     \
 773        unsigned long *__ptr = (unsigned long *)(info);                 \
 774        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 775 })
 776
 777 /*
 778  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 779  * This is necessary to guarantee that the entire "struct pt_regs"
 780  * is accessable even if the CPU haven't stored the SS/ESP registers
 781  * on the stack (interrupt gate does not save these registers
 782  * when switching to the same priv ring).
 783  * Therefore beware: accessing the ss/esp fields of the
 784  * "struct pt_regs" is possible, but they may contain the
 785  * completely wrong values.
 786  */
 787 #define task_pt_regs(task)                                             \
 788 ({                                                                     \
 789        struct pt_regs *__regs__;                                       \
 790        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 791        __regs__ - 1;                                                   \
 792 })
 793
 794 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
 795
 796 #else
 797 /*
 798  * User space process size. 47bits minus one guard page.
 799  */
 800 #define TASK_SIZE64     (0x800000000000UL - 4096)
 801
 802 /* This decides where the kernel will search for a free chunk of vm
 803  * space during mmap's.
 804  */
 805 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
 806                            0xc0000000 : 0xFFFFe000)
 807
 808 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 809                                  IA32_PAGE_OFFSET : TASK_SIZE64)
 810 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 811                                   IA32_PAGE_OFFSET : TASK_SIZE64)
 812
 813 #define STACK_TOP               TASK_SIZE
 814 #define STACK_TOP_MAX           TASK_SIZE64
 815
 816 #define INIT_THREAD  { \
 817         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 818 }
 819
 820 #define INIT_TSS  { \
 821         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 822 }
 823
 824 #define start_thread(regs, new_rip, new_rsp) do {                            \
 825         asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0));  \
 826         load_gs_index(0);                                                    \
 827         (regs)->ip = (new_rip);                                              \
 828         (regs)->sp = (new_rsp);                                              \
 829         write_pda(oldrsp, (new_rsp));                                        \
 830         (regs)->cs = __USER_CS;                                              \
 831         (regs)->ss = __USER_DS;                                              \
 832         (regs)->flags = 0x200;                                               \
 833         set_fs(USER_DS);                                                     \
 834 } while (0)
 835
 836 /*
 837  * Return saved PC of a blocked thread.
 838  * What is this good for? it will be always the scheduler or ret_from_fork.
 839  */
 840 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
 841
 842 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 843 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
 844 #endif /* CONFIG_X86_64 */
 845
 846 /* This decides where the kernel will search for a free chunk of vm
 847  * space during mmap's.
 848  */
 849 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 850
 851 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
 852
 853 #endif