include/asm-mips/jmr3927/jmr3927.h

   1 /*
   2  * Defines for the TJSYS JMR-TX3927
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000-2001 Toshiba Corporation
   9  */
  10 #ifndef __ASM_TX3927_JMR3927_H
  11 #define __ASM_TX3927_JMR3927_H
  12
  13 #include <asm/jmr3927/tx3927.h>
  14 #include <asm/addrspace.h>
  15 #include <asm/system.h>
  16 #include <asm/txx9irq.h>
  17
  18 /* CS */
  19 #define JMR3927_ROMCE0  0x1fc00000      /* 4M */
  20 #define JMR3927_ROMCE1  0x1e000000      /* 4M */
  21 #define JMR3927_ROMCE2  0x14000000      /* 16M */
  22 #define JMR3927_ROMCE3  0x10000000      /* 64M */
  23 #define JMR3927_ROMCE5  0x1d000000      /* 4M */
  24 #define JMR3927_SDCS0   0x00000000      /* 32M */
  25 #define JMR3927_SDCS1   0x02000000      /* 32M */
  26 /* PCI Direct Mappings */
  27
  28 #define JMR3927_PCIMEM  0x08000000
  29 #define JMR3927_PCIMEM_SIZE     0x08000000      /* 128M */
  30 #define JMR3927_PCIIO   0x15000000
  31 #define JMR3927_PCIIO_SIZE      0x01000000      /* 16M */
  32
  33 #define JMR3927_SDRAM_SIZE      0x02000000      /* 32M */
  34 #define JMR3927_PORT_BASE       KSEG1
  35
  36 /* Address map (virtual address) */
  37 #define JMR3927_ROM0_BASE       (KSEG1 + JMR3927_ROMCE0)
  38 #define JMR3927_ROM1_BASE       (KSEG1 + JMR3927_ROMCE1)
  39 #define JMR3927_IOC_BASE        (KSEG1 + JMR3927_ROMCE2)
  40 #define JMR3927_PCIMEM_BASE     (KSEG1 + JMR3927_PCIMEM)
  41 #define JMR3927_PCIIO_BASE      (KSEG1 + JMR3927_PCIIO)
  42
  43 #define JMR3927_IOC_REV_ADDR    (JMR3927_IOC_BASE + 0x00000000)
  44 #define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
  45 #define JMR3927_IOC_LED_ADDR    (JMR3927_IOC_BASE + 0x00020000)
  46 #define JMR3927_IOC_DIPSW_ADDR  (JMR3927_IOC_BASE + 0x00030000)
  47 #define JMR3927_IOC_BREV_ADDR   (JMR3927_IOC_BASE + 0x00040000)
  48 #define JMR3927_IOC_DTR_ADDR    (JMR3927_IOC_BASE + 0x00050000)
  49 #define JMR3927_IOC_INTS1_ADDR  (JMR3927_IOC_BASE + 0x00080000)
  50 #define JMR3927_IOC_INTS2_ADDR  (JMR3927_IOC_BASE + 0x00090000)
  51 #define JMR3927_IOC_INTM_ADDR   (JMR3927_IOC_BASE + 0x000a0000)
  52 #define JMR3927_IOC_INTP_ADDR   (JMR3927_IOC_BASE + 0x000b0000)
  53 #define JMR3927_IOC_RESET_ADDR  (JMR3927_IOC_BASE + 0x000f0000)
  54
  55 /* Flash ROM */
  56 #define JMR3927_FLASH_BASE      (JMR3927_ROM0_BASE)
  57 #define JMR3927_FLASH_SIZE      0x00400000
  58
  59 /* bits for IOC_REV/IOC_BREV (high byte) */
  60 #define JMR3927_IDT_MASK        0xfc
  61 #define JMR3927_REV_MASK        0x03
  62 #define JMR3927_IOC_IDT         0xe0
  63
  64 /* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
  65 #define JMR3927_IOC_INTB_PCIA   0
  66 #define JMR3927_IOC_INTB_PCIB   1
  67 #define JMR3927_IOC_INTB_PCIC   2
  68 #define JMR3927_IOC_INTB_PCID   3
  69 #define JMR3927_IOC_INTB_MODEM  4
  70 #define JMR3927_IOC_INTB_INT6   5
  71 #define JMR3927_IOC_INTB_INT7   6
  72 #define JMR3927_IOC_INTB_SOFT   7
  73 #define JMR3927_IOC_INTF_PCIA   (1 << JMR3927_IOC_INTF_PCIA)
  74 #define JMR3927_IOC_INTF_PCIB   (1 << JMR3927_IOC_INTB_PCIB)
  75 #define JMR3927_IOC_INTF_PCIC   (1 << JMR3927_IOC_INTB_PCIC)
  76 #define JMR3927_IOC_INTF_PCID   (1 << JMR3927_IOC_INTB_PCID)
  77 #define JMR3927_IOC_INTF_MODEM  (1 << JMR3927_IOC_INTB_MODEM)
  78 #define JMR3927_IOC_INTF_INT6   (1 << JMR3927_IOC_INTB_INT6)
  79 #define JMR3927_IOC_INTF_INT7   (1 << JMR3927_IOC_INTB_INT7)
  80 #define JMR3927_IOC_INTF_SOFT   (1 << JMR3927_IOC_INTB_SOFT)
  81
  82 /* bits for IOC_RESET (high byte) */
  83 #define JMR3927_IOC_RESET_CPU   1
  84 #define JMR3927_IOC_RESET_PCI   2
  85
  86 #if defined(__BIG_ENDIAN)
  87 #define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)(a)) = (d))
  88 #define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)(a))
  89 #elif defined(__LITTLE_ENDIAN)
  90 #define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)((a)^1)) = (d))
  91 #define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)((a)^1))
  92 #else
  93 #error "No Endian"
  94 #endif
  95
  96 /* LED macro */
  97 #define jmr3927_led_set(n/*0-16*/)      jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
  98
  99 #define jmr3927_led_and_set(n/*0-16*/)  jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
 100
 101 /* DIPSW4 macro */
 102 #define jmr3927_dipsw1()        ((tx3927_pioptr->din & (1 << 11)) == 0)
 103 #define jmr3927_dipsw2()        ((tx3927_pioptr->din & (1 << 10)) == 0)
 104 #define jmr3927_dipsw3()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
 105 #define jmr3927_dipsw4()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
 106
 107 /*
 108  * IRQ mappings
 109  */
 110
 111 /* These are the virtual IRQ numbers, we divide all IRQ's into
 112  * 'spaces', the 'space' determines where and how to enable/disable
 113  * that particular IRQ on an JMR machine.  Add new 'spaces' as new
 114  * IRQ hardware is supported.
 115  */
 116 #define JMR3927_NR_IRQ_IRC      16      /* On-Chip IRC */
 117 #define JMR3927_NR_IRQ_IOC      8       /* PCI/MODEM/INT[6:7] */
 118
 119 #define JMR3927_IRQ_IRC TXX9_IRQ_BASE
 120 #define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
 121 #define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
 122
 123 #define JMR3927_IRQ_IRC_INT0    (JMR3927_IRQ_IRC + TX3927_IR_INT0)
 124 #define JMR3927_IRQ_IRC_INT1    (JMR3927_IRQ_IRC + TX3927_IR_INT1)
 125 #define JMR3927_IRQ_IRC_INT2    (JMR3927_IRQ_IRC + TX3927_IR_INT2)
 126 #define JMR3927_IRQ_IRC_INT3    (JMR3927_IRQ_IRC + TX3927_IR_INT3)
 127 #define JMR3927_IRQ_IRC_INT4    (JMR3927_IRQ_IRC + TX3927_IR_INT4)
 128 #define JMR3927_IRQ_IRC_INT5    (JMR3927_IRQ_IRC + TX3927_IR_INT5)
 129 #define JMR3927_IRQ_IRC_SIO0    (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
 130 #define JMR3927_IRQ_IRC_SIO1    (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
 131 #define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
 132 #define JMR3927_IRQ_IRC_DMA     (JMR3927_IRQ_IRC + TX3927_IR_DMA)
 133 #define JMR3927_IRQ_IRC_PIO     (JMR3927_IRQ_IRC + TX3927_IR_PIO)
 134 #define JMR3927_IRQ_IRC_PCI     (JMR3927_IRQ_IRC + TX3927_IR_PCI)
 135 #define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
 136 #define JMR3927_IRQ_IOC_PCIA    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
 137 #define JMR3927_IRQ_IOC_PCIB    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
 138 #define JMR3927_IRQ_IOC_PCIC    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
 139 #define JMR3927_IRQ_IOC_PCID    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
 140 #define JMR3927_IRQ_IOC_MODEM   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
 141 #define JMR3927_IRQ_IOC_INT6    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
 142 #define JMR3927_IRQ_IOC_INT7    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
 143 #define JMR3927_IRQ_IOC_SOFT    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
 144
 145 /* IOC (PCI, MODEM) */
 146 #define JMR3927_IRQ_IOCINT      JMR3927_IRQ_IRC_INT1
 147 /* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
 148 #define JMR3927_IRQ_ETHER0      JMR3927_IRQ_IRC_INT3
 149
 150 /* Clocks */
 151 #define JMR3927_CORECLK 132710400       /* 132.7MHz */
 152 #define JMR3927_GBUSCLK (JMR3927_CORECLK / 2)   /* 66.35MHz */
 153 #define JMR3927_IMCLK   (JMR3927_CORECLK / 4)   /* 33.17MHz */
 154
 155 /*
 156  * TX3927 Pin Configuration:
 157  *
 158  *      PCFG bits               Avail                   Dead
 159  *      SELSIO[1:0]:11          RXD[1:0], TXD[1:0]      PIO[6:3]
 160  *      SELSIOC[0]:1            CTS[0], RTS[0]          INT[5:4]
 161  *      SELSIOC[1]:0,SELDSF:0,  GSDAO[0],GPCST[3]       CTS[1], RTS[1],DSF,
 162  *        GDBGE*                                          PIO[2:1]
 163  *      SELDMA[2]:1             DMAREQ[2],DMAACK[2]     PIO[13:12]
 164  *      SELTMR[2:0]:000                                 TIMER[1:0]
 165  *      SELCS:0,SELDMA[1]:0     PIO[11;10]              SDCS_CE[7:6],
 166  *                                                        DMAREQ[1],DMAACK[1]
 167  *      SELDMA[0]:1             DMAREQ[0],DMAACK[0]     PIO[9:8]
 168  *      SELDMA[3]:1             DMAREQ[3],DMAACK[3]     PIO[15:14]
 169  *      SELDONE:1               DMADONE                 PIO[7]
 170  *
 171  * Usable pins are:
 172  *      RXD[1;0],TXD[1:0],CTS[0],RTS[0],
 173  *      DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
 174  *      INT[3:0]
 175  */
 176
 177 #endif /* __ASM_TX3927_JMR3927_H */