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x86: 64-bit, add the new split_large_page() function
[wrt350n-kernel.git] / drivers / video / s3fb.c
blob7d53bc23b9c75fac01392afcb4d26421d5f36c03
1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/version.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/fb.h>
24 #include <linux/svga.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
28 #include <video/vga.h>
29
30 #ifdef CONFIG_MTRR
31 #include <asm/mtrr.h>
32 #endif
33
34 struct s3fb_info {
35 int chip, rev, mclk_freq;
36 int mtrr_reg;
37 struct vgastate state;
38 struct mutex open_lock;
39 unsigned int ref_count;
40 u32 pseudo_palette[16];
41 };
42
43
44 /* ------------------------------------------------------------------------- */
45
46 static const struct svga_fb_format s3fb_formats[] = {
47 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
48 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
49 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
50 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
51 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
52 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
55 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
56 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
57 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
59 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
61 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
63 SVGA_FORMAT_END
64 };
65
66
67 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
68 35000, 240000, 14318};
69
70 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
71
72 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
73 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
74 "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
75 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
76 "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};
77
78 #define CHIP_UNKNOWN 0x00
79 #define CHIP_732_TRIO32 0x01
80 #define CHIP_764_TRIO64 0x02
81 #define CHIP_765_TRIO64VP 0x03
82 #define CHIP_767_TRIO64UVP 0x04
83 #define CHIP_775_TRIO64V2_DX 0x05
84 #define CHIP_785_TRIO64V2_GX 0x06
85 #define CHIP_551_PLATO_PX 0x07
86 #define CHIP_M65_AURORA64VP 0x08
87 #define CHIP_325_VIRGE 0x09
88 #define CHIP_988_VIRGE_VX 0x0A
89 #define CHIP_375_VIRGE_DX 0x0B
90 #define CHIP_385_VIRGE_GX 0x0C
91 #define CHIP_356_VIRGE_GX2 0x0D
92 #define CHIP_357_VIRGE_GX2P 0x0E
93 #define CHIP_359_VIRGE_GX2P 0x0F
94
95 #define CHIP_XXX_TRIO 0x80
96 #define CHIP_XXX_TRIO64V2_DXGX 0x81
97 #define CHIP_XXX_VIRGE_DXGX 0x82
98
99 #define CHIP_UNDECIDED_FLAG 0x80
100 #define CHIP_MASK 0xFF
101
102 /* CRT timing register sets */
103
104 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
105 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
106 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
107 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
108 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
109 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
110
111 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
112 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
113 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
114 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
115 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
116 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
117
118 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
119 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
120 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
121
122 static const struct svga_timing_regs s3_timing_regs = {
123 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
124 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
125 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
126 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
127 };
128
129
130 /* ------------------------------------------------------------------------- */
131
132 /* Module parameters */
133
134
135 static char *mode = "640x480-8@60";
136
137 #ifdef CONFIG_MTRR
138 static int mtrr = 1;
139 #endif
140
141 static int fasttext = 1;
142
143
144 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
145 MODULE_LICENSE("GPL");
146 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
147
148 module_param(mode, charp, 0444);
149 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");
150
151 #ifdef CONFIG_MTRR
152 module_param(mtrr, int, 0444);
153 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
154 #endif
155
156 module_param(fasttext, int, 0644);
157 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
158
159
160 /* ------------------------------------------------------------------------- */
161
162 /* Set font in S3 fast text mode */
163
164 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
165 {
166 const u8 *font = map->data;
167 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
168 int i, c;
169
170 if ((map->width != 8) || (map->height != 16) ||
171 (map->depth != 1) || (map->length != 256)) {
172 printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
173 info->node, map->width, map->height, map->depth, map->length);
174 return;
175 }
176
177 fb += 2;
178 for (i = 0; i < map->height; i++) {
179 for (c = 0; c < map->length; c++) {
180 fb_writeb(font[c * map->height + i], fb + c * 4);
181 }
182 fb += 1024;
183 }
184 }
185
186 static struct fb_tile_ops s3fb_tile_ops = {
187 .fb_settile = svga_settile,
188 .fb_tilecopy = svga_tilecopy,
189 .fb_tilefill = svga_tilefill,
190 .fb_tileblit = svga_tileblit,
191 .fb_tilecursor = svga_tilecursor,
192 .fb_get_tilemax = svga_get_tilemax,
193 };
194
195 static struct fb_tile_ops s3fb_fast_tile_ops = {
196 .fb_settile = s3fb_settile_fast,
197 .fb_tilecopy = svga_tilecopy,
198 .fb_tilefill = svga_tilefill,
199 .fb_tileblit = svga_tileblit,
200 .fb_tilecursor = svga_tilecursor,
201 .fb_get_tilemax = svga_get_tilemax,
202 };
203
204
205 /* ------------------------------------------------------------------------- */
206
207 /* image data is MSB-first, fb structure is MSB-first too */
208 static inline u32 expand_color(u32 c)
209 {
210 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
211 }
212
213 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
214 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
215 {
216 u32 fg = expand_color(image->fg_color);
217 u32 bg = expand_color(image->bg_color);
218 const u8 *src1, *src;
219 u8 __iomem *dst1;
220 u32 __iomem *dst;
221 u32 val;
222 int x, y;
223
224 src1 = image->data;
225 dst1 = info->screen_base + (image->dy * info->fix.line_length)
226 + ((image->dx / 8) * 4);
227
228 for (y = 0; y < image->height; y++) {
229 src = src1;
230 dst = (u32 __iomem *) dst1;
231 for (x = 0; x < image->width; x += 8) {
232 val = *(src++) * 0x01010101;
233 val = (val & fg) | (~val & bg);
234 fb_writel(val, dst++);
235 }
236 src1 += image->width / 8;
237 dst1 += info->fix.line_length;
238 }
239
240 }
241
242 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
243 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
244 {
245 u32 fg = expand_color(rect->color);
246 u8 __iomem *dst1;
247 u32 __iomem *dst;
248 int x, y;
249
250 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
251 + ((rect->dx / 8) * 4);
252
253 for (y = 0; y < rect->height; y++) {
254 dst = (u32 __iomem *) dst1;
255 for (x = 0; x < rect->width; x += 8) {
256 fb_writel(fg, dst++);
257 }
258 dst1 += info->fix.line_length;
259 }
260 }
261
262
263 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
264 static inline u32 expand_pixel(u32 c)
265 {
266 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
267 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
268 }
269
270 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
271 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
272 {
273 u32 fg = image->fg_color * 0x11111111;
274 u32 bg = image->bg_color * 0x11111111;
275 const u8 *src1, *src;
276 u8 __iomem *dst1;
277 u32 __iomem *dst;
278 u32 val;
279 int x, y;
280
281 src1 = image->data;
282 dst1 = info->screen_base + (image->dy * info->fix.line_length)
283 + ((image->dx / 8) * 4);
284
285 for (y = 0; y < image->height; y++) {
286 src = src1;
287 dst = (u32 __iomem *) dst1;
288 for (x = 0; x < image->width; x += 8) {
289 val = expand_pixel(*(src++));
290 val = (val & fg) | (~val & bg);
291 fb_writel(val, dst++);
292 }
293 src1 += image->width / 8;
294 dst1 += info->fix.line_length;
295 }
296 }
297
298 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
299 {
300 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
301 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
302 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
303 s3fb_iplan_imageblit(info, image);
304 else
305 s3fb_cfb4_imageblit(info, image);
306 } else
307 cfb_imageblit(info, image);
308 }
309
310 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
311 {
312 if ((info->var.bits_per_pixel == 4)
313 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
314 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
315 s3fb_iplan_fillrect(info, rect);
316 else
317 cfb_fillrect(info, rect);
318 }
319
320
321
322 /* ------------------------------------------------------------------------- */
323
324
325 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
326 {
327 u16 m, n, r;
328 u8 regval;
329 int rv;
330
331 rv = svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
332 if (rv < 0) {
333 printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node);
334 return;
335 }
336
337 /* Set VGA misc register */
338 regval = vga_r(NULL, VGA_MIS_R);
339 vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
340
341 /* Set S3 clock registers */
342 vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));
343 vga_wseq(NULL, 0x13, m - 2);
344
345 udelay(1000);
346
347 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
348 regval = vga_rseq (NULL, 0x15); /* | 0x80; */
349 vga_wseq(NULL, 0x15, regval & ~(1<<5));
350 vga_wseq(NULL, 0x15, regval | (1<<5));
351 vga_wseq(NULL, 0x15, regval & ~(1<<5));
352 }
353
354
355 /* Open framebuffer */
356
357 static int s3fb_open(struct fb_info *info, int user)
358 {
359 struct s3fb_info *par = info->par;
360
361 mutex_lock(&(par->open_lock));
362 if (par->ref_count == 0) {
363 memset(&(par->state), 0, sizeof(struct vgastate));
364 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
365 par->state.num_crtc = 0x70;
366 par->state.num_seq = 0x20;
367 save_vga(&(par->state));
368 }
369
370 par->ref_count++;
371 mutex_unlock(&(par->open_lock));
372
373 return 0;
374 }
375
376 /* Close framebuffer */
377
378 static int s3fb_release(struct fb_info *info, int user)
379 {
380 struct s3fb_info *par = info->par;
381
382 mutex_lock(&(par->open_lock));
383 if (par->ref_count == 0) {
384 mutex_unlock(&(par->open_lock));
385 return -EINVAL;
386 }
387
388 if (par->ref_count == 1)
389 restore_vga(&(par->state));
390
391 par->ref_count--;
392 mutex_unlock(&(par->open_lock));
393
394 return 0;
395 }
396
397 /* Validate passed in var */
398
399 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
400 {
401 struct s3fb_info *par = info->par;
402 int rv, mem, step;
403 u16 m, n, r;
404
405 /* Find appropriate format */
406 rv = svga_match_format (s3fb_formats, var, NULL);
407
408 /* 32bpp mode is not supported on VIRGE VX,
409 24bpp is not supported on others */
410 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
411 rv = -EINVAL;
412
413 if (rv < 0) {
414 printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
415 return rv;
416 }
417
418 /* Do not allow to have real resoulution larger than virtual */
419 if (var->xres > var->xres_virtual)
420 var->xres_virtual = var->xres;
421
422 if (var->yres > var->yres_virtual)
423 var->yres_virtual = var->yres;
424
425 /* Round up xres_virtual to have proper alignment of lines */
426 step = s3fb_formats[rv].xresstep - 1;
427 var->xres_virtual = (var->xres_virtual+step) & ~step;
428
429 /* Check whether have enough memory */
430 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
431 if (mem > info->screen_size) {
432 printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
433 info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
434 return -EINVAL;
435 }
436
437 rv = svga_check_timings (&s3_timing_regs, var, info->node);
438 if (rv < 0) {
439 printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
440 return rv;
441 }
442
443 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
444 info->node);
445 if (rv < 0) {
446 printk(KERN_ERR "fb%d: invalid pixclock value requested\n",
447 info->node);
448 return rv;
449 }
450
451 return 0;
452 }
453
454 /* Set video mode from par */
455
456 static int s3fb_set_par(struct fb_info *info)
457 {
458 struct s3fb_info *par = info->par;
459 u32 value, mode, hmul, offset_value, screen_size, multiplex;
460 u32 bpp = info->var.bits_per_pixel;
461
462 if (bpp != 0) {
463 info->fix.ypanstep = 1;
464 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
465
466 info->flags &= ~FBINFO_MISC_TILEBLITTING;
467 info->tileops = NULL;
468
469 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
470 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
471 info->pixmap.blit_y = ~(u32)0;
472
473 offset_value = (info->var.xres_virtual * bpp) / 64;
474 screen_size = info->var.yres_virtual * info->fix.line_length;
475 } else {
476 info->fix.ypanstep = 16;
477 info->fix.line_length = 0;
478
479 info->flags |= FBINFO_MISC_TILEBLITTING;
480 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
481
482 /* supports 8x16 tiles only */
483 info->pixmap.blit_x = 1 << (8 - 1);
484 info->pixmap.blit_y = 1 << (16 - 1);
485
486 offset_value = info->var.xres_virtual / 16;
487 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
488 }
489
490 info->var.xoffset = 0;
491 info->var.yoffset = 0;
492 info->var.activate = FB_ACTIVATE_NOW;
493
494 /* Unlock registers */
495 vga_wcrt(NULL, 0x38, 0x48);
496 vga_wcrt(NULL, 0x39, 0xA5);
497 vga_wseq(NULL, 0x08, 0x06);
498 svga_wcrt_mask(0x11, 0x00, 0x80);
499
500 /* Blank screen and turn off sync */
501 svga_wseq_mask(0x01, 0x20, 0x20);
502 svga_wcrt_mask(0x17, 0x00, 0x80);
503
504 /* Set default values */
505 svga_set_default_gfx_regs();
506 svga_set_default_atc_regs();
507 svga_set_default_seq_regs();
508 svga_set_default_crt_regs();
509 svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
510 svga_wcrt_multi(s3_start_address_regs, 0);
511
512 /* S3 specific initialization */
513 svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
514 svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
515
516 /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */
517 /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */
518 svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */
519 svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */
520
521 svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits
522
523 /* svga_wcrt_mask(0x58, 0x03, 0x03); */
524
525 /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
526 /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
527
528
529 /* Set the offset register */
530 pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
531 svga_wcrt_multi(s3_offset_regs, offset_value);
532
533 vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
534 vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
535 vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
536 vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
537
538 vga_wcrt(NULL, 0x3A, 0x35);
539 svga_wattr(0x33, 0x00);
540
541 if (info->var.vmode & FB_VMODE_DOUBLE)
542 svga_wcrt_mask(0x09, 0x80, 0x80);
543 else
544 svga_wcrt_mask(0x09, 0x00, 0x80);
545
546 if (info->var.vmode & FB_VMODE_INTERLACED)
547 svga_wcrt_mask(0x42, 0x20, 0x20);
548 else
549 svga_wcrt_mask(0x42, 0x00, 0x20);
550
551 /* Disable hardware graphics cursor */
552 svga_wcrt_mask(0x45, 0x00, 0x01);
553 /* Disable Streams engine */
554 svga_wcrt_mask(0x67, 0x00, 0x0C);
555
556 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
557
558 /* S3 virge DX hack */
559 if (par->chip == CHIP_375_VIRGE_DX) {
560 vga_wcrt(NULL, 0x86, 0x80);
561 vga_wcrt(NULL, 0x90, 0x00);
562 }
563
564 /* S3 virge VX hack */
565 if (par->chip == CHIP_988_VIRGE_VX) {
566 vga_wcrt(NULL, 0x50, 0x00);
567 vga_wcrt(NULL, 0x67, 0x50);
568
569 vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
570 vga_wcrt(NULL, 0x66, 0x90);
571 }
572
573 svga_wcrt_mask(0x31, 0x00, 0x40);
574 multiplex = 0;
575 hmul = 1;
576
577 /* Set mode-specific register values */
578 switch (mode) {
579 case 0:
580 pr_debug("fb%d: text mode\n", info->node);
581 svga_set_textmode_vga_regs();
582
583 /* Set additional registers like in 8-bit mode */
584 svga_wcrt_mask(0x50, 0x00, 0x30);
585 svga_wcrt_mask(0x67, 0x00, 0xF0);
586
587 /* Disable enhanced mode */
588 svga_wcrt_mask(0x3A, 0x00, 0x30);
589
590 if (fasttext) {
591 pr_debug("fb%d: high speed text mode set\n", info->node);
592 svga_wcrt_mask(0x31, 0x40, 0x40);
593 }
594 break;
595 case 1:
596 pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
597 vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
598
599 /* Set additional registers like in 8-bit mode */
600 svga_wcrt_mask(0x50, 0x00, 0x30);
601 svga_wcrt_mask(0x67, 0x00, 0xF0);
602
603 /* disable enhanced mode */
604 svga_wcrt_mask(0x3A, 0x00, 0x30);
605 break;
606 case 2:
607 pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
608
609 /* Set additional registers like in 8-bit mode */
610 svga_wcrt_mask(0x50, 0x00, 0x30);
611 svga_wcrt_mask(0x67, 0x00, 0xF0);
612
613 /* disable enhanced mode */
614 svga_wcrt_mask(0x3A, 0x00, 0x30);
615 break;
616 case 3:
617 pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
618 if (info->var.pixclock > 20000) {
619 svga_wcrt_mask(0x50, 0x00, 0x30);
620 svga_wcrt_mask(0x67, 0x00, 0xF0);
621 } else {
622 svga_wcrt_mask(0x50, 0x00, 0x30);
623 svga_wcrt_mask(0x67, 0x10, 0xF0);
624 multiplex = 1;
625 }
626 break;
627 case 4:
628 pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
629 if (par->chip == CHIP_988_VIRGE_VX) {
630 if (info->var.pixclock > 20000)
631 svga_wcrt_mask(0x67, 0x20, 0xF0);
632 else
633 svga_wcrt_mask(0x67, 0x30, 0xF0);
634 } else {
635 svga_wcrt_mask(0x50, 0x10, 0x30);
636 svga_wcrt_mask(0x67, 0x30, 0xF0);
637 hmul = 2;
638 }
639 break;
640 case 5:
641 pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
642 if (par->chip == CHIP_988_VIRGE_VX) {
643 if (info->var.pixclock > 20000)
644 svga_wcrt_mask(0x67, 0x40, 0xF0);
645 else
646 svga_wcrt_mask(0x67, 0x50, 0xF0);
647 } else {
648 svga_wcrt_mask(0x50, 0x10, 0x30);
649 svga_wcrt_mask(0x67, 0x50, 0xF0);
650 hmul = 2;
651 }
652 break;
653 case 6:
654 /* VIRGE VX case */
655 pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
656 svga_wcrt_mask(0x67, 0xD0, 0xF0);
657 break;
658 case 7:
659 pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
660 svga_wcrt_mask(0x50, 0x30, 0x30);
661 svga_wcrt_mask(0x67, 0xD0, 0xF0);
662 break;
663 default:
664 printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
665 return -EINVAL;
666 }
667
668 if (par->chip != CHIP_988_VIRGE_VX) {
669 svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
670 svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
671 }
672
673 s3_set_pixclock(info, info->var.pixclock);
674 svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
675 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
676 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
677 hmul, info->node);
678
679 /* Set interlaced mode start/end register */
680 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
681 value = ((value * hmul) / 8) - 5;
682 vga_wcrt(NULL, 0x3C, (value + 1) / 2);
683
684 memset_io(info->screen_base, 0x00, screen_size);
685 /* Device and screen back on */
686 svga_wcrt_mask(0x17, 0x80, 0x80);
687 svga_wseq_mask(0x01, 0x00, 0x20);
688
689 return 0;
690 }
691
692 /* Set a colour register */
693
694 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
695 u_int transp, struct fb_info *fb)
696 {
697 switch (fb->var.bits_per_pixel) {
698 case 0:
699 case 4:
700 if (regno >= 16)
701 return -EINVAL;
702
703 if ((fb->var.bits_per_pixel == 4) &&
704 (fb->var.nonstd == 0)) {
705 outb(0xF0, VGA_PEL_MSK);
706 outb(regno*16, VGA_PEL_IW);
707 } else {
708 outb(0x0F, VGA_PEL_MSK);
709 outb(regno, VGA_PEL_IW);
710 }
711 outb(red >> 10, VGA_PEL_D);
712 outb(green >> 10, VGA_PEL_D);
713 outb(blue >> 10, VGA_PEL_D);
714 break;
715 case 8:
716 if (regno >= 256)
717 return -EINVAL;
718
719 outb(0xFF, VGA_PEL_MSK);
720 outb(regno, VGA_PEL_IW);
721 outb(red >> 10, VGA_PEL_D);
722 outb(green >> 10, VGA_PEL_D);
723 outb(blue >> 10, VGA_PEL_D);
724 break;
725 case 16:
726 if (regno >= 16)
727 return 0;
728
729 if (fb->var.green.length == 5)
730 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
731 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
732 else if (fb->var.green.length == 6)
733 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
734 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
735 else return -EINVAL;
736 break;
737 case 24:
738 case 32:
739 if (regno >= 16)
740 return 0;
741
742 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
743 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
744 break;
745 default:
746 return -EINVAL;
747 }
748
749 return 0;
750 }
751
752
753 /* Set the display blanking state */
754
755 static int s3fb_blank(int blank_mode, struct fb_info *info)
756 {
757 switch (blank_mode) {
758 case FB_BLANK_UNBLANK:
759 pr_debug("fb%d: unblank\n", info->node);
760 svga_wcrt_mask(0x56, 0x00, 0x06);
761 svga_wseq_mask(0x01, 0x00, 0x20);
762 break;
763 case FB_BLANK_NORMAL:
764 pr_debug("fb%d: blank\n", info->node);
765 svga_wcrt_mask(0x56, 0x00, 0x06);
766 svga_wseq_mask(0x01, 0x20, 0x20);
767 break;
768 case FB_BLANK_HSYNC_SUSPEND:
769 pr_debug("fb%d: hsync\n", info->node);
770 svga_wcrt_mask(0x56, 0x02, 0x06);
771 svga_wseq_mask(0x01, 0x20, 0x20);
772 break;
773 case FB_BLANK_VSYNC_SUSPEND:
774 pr_debug("fb%d: vsync\n", info->node);
775 svga_wcrt_mask(0x56, 0x04, 0x06);
776 svga_wseq_mask(0x01, 0x20, 0x20);
777 break;
778 case FB_BLANK_POWERDOWN:
779 pr_debug("fb%d: sync down\n", info->node);
780 svga_wcrt_mask(0x56, 0x06, 0x06);
781 svga_wseq_mask(0x01, 0x20, 0x20);
782 break;
783 }
784
785 return 0;
786 }
787
788
789 /* Pan the display */
790
791 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
792
793 unsigned int offset;
794
795 /* Calculate the offset */
796 if (var->bits_per_pixel == 0) {
797 offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
798 offset = offset >> 2;
799 } else {
800 offset = (var->yoffset * info->fix.line_length) +
801 (var->xoffset * var->bits_per_pixel / 8);
802 offset = offset >> 2;
803 }
804
805 /* Set the offset */
806 svga_wcrt_multi(s3_start_address_regs, offset);
807
808 return 0;
809 }
810
811 /* ------------------------------------------------------------------------- */
812
813 /* Frame buffer operations */
814
815 static struct fb_ops s3fb_ops = {
816 .owner = THIS_MODULE,
817 .fb_open = s3fb_open,
818 .fb_release = s3fb_release,
819 .fb_check_var = s3fb_check_var,
820 .fb_set_par = s3fb_set_par,
821 .fb_setcolreg = s3fb_setcolreg,
822 .fb_blank = s3fb_blank,
823 .fb_pan_display = s3fb_pan_display,
824 .fb_fillrect = s3fb_fillrect,
825 .fb_copyarea = cfb_copyarea,
826 .fb_imageblit = s3fb_imageblit,
827 .fb_get_caps = svga_get_caps,
828 };
829
830 /* ------------------------------------------------------------------------- */
831
832 static int __devinit s3_identification(int chip)
833 {
834 if (chip == CHIP_XXX_TRIO) {
835 u8 cr30 = vga_rcrt(NULL, 0x30);
836 u8 cr2e = vga_rcrt(NULL, 0x2e);
837 u8 cr2f = vga_rcrt(NULL, 0x2f);
838
839 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
840 if (cr2e == 0x10)
841 return CHIP_732_TRIO32;
842 if (cr2e == 0x11) {
843 if (! (cr2f & 0x40))
844 return CHIP_764_TRIO64;
845 else
846 return CHIP_765_TRIO64VP;
847 }
848 }
849 }
850
851 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
852 u8 cr6f = vga_rcrt(NULL, 0x6f);
853
854 if (! (cr6f & 0x01))
855 return CHIP_775_TRIO64V2_DX;
856 else
857 return CHIP_785_TRIO64V2_GX;
858 }
859
860 if (chip == CHIP_XXX_VIRGE_DXGX) {
861 u8 cr6f = vga_rcrt(NULL, 0x6f);
862
863 if (! (cr6f & 0x01))
864 return CHIP_375_VIRGE_DX;
865 else
866 return CHIP_385_VIRGE_GX;
867 }
868
869 return CHIP_UNKNOWN;
870 }
871
872
873 /* PCI probe */
874
875 static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
876 {
877 struct fb_info *info;
878 struct s3fb_info *par;
879 int rc;
880 u8 regval, cr38, cr39;
881
882 /* Ignore secondary VGA device because there is no VGA arbitration */
883 if (! svga_primary_device(dev)) {
884 dev_info(&(dev->dev), "ignoring secondary device\n");
885 return -ENODEV;
886 }
887
888 /* Allocate and fill driver data structure */
889 info = framebuffer_alloc(sizeof(struct s3fb_info), NULL);
890 if (!info) {
891 dev_err(&(dev->dev), "cannot allocate memory\n");
892 return -ENOMEM;
893 }
894
895 par = info->par;
896 mutex_init(&par->open_lock);
897
898 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
899 info->fbops = &s3fb_ops;
900
901 /* Prepare PCI device */
902 rc = pci_enable_device(dev);
903 if (rc < 0) {
904 dev_err(&(dev->dev), "cannot enable PCI device\n");
905 goto err_enable_device;
906 }
907
908 rc = pci_request_regions(dev, "s3fb");
909 if (rc < 0) {
910 dev_err(&(dev->dev), "cannot reserve framebuffer region\n");
911 goto err_request_regions;
912 }
913
914
915 info->fix.smem_start = pci_resource_start(dev, 0);
916 info->fix.smem_len = pci_resource_len(dev, 0);
917
918 /* Map physical IO memory address into kernel space */
919 info->screen_base = pci_iomap(dev, 0, 0);
920 if (! info->screen_base) {
921 rc = -ENOMEM;
922 dev_err(&(dev->dev), "iomap for framebuffer failed\n");
923 goto err_iomap;
924 }
925
926 /* Unlock regs */
927 cr38 = vga_rcrt(NULL, 0x38);
928 cr39 = vga_rcrt(NULL, 0x39);
929 vga_wseq(NULL, 0x08, 0x06);
930 vga_wcrt(NULL, 0x38, 0x48);
931 vga_wcrt(NULL, 0x39, 0xA5);
932
933 /* Find how many physical memory there is on card */
934 /* 0x36 register is accessible even if other registers are locked */
935 regval = vga_rcrt(NULL, 0x36);
936 info->screen_size = s3_memsizes[regval >> 5] << 10;
937 info->fix.smem_len = info->screen_size;
938
939 par->chip = id->driver_data & CHIP_MASK;
940 par->rev = vga_rcrt(NULL, 0x2f);
941 if (par->chip & CHIP_UNDECIDED_FLAG)
942 par->chip = s3_identification(par->chip);
943
944 /* Find MCLK frequency */
945 regval = vga_rseq(NULL, 0x10);
946 par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
947 par->mclk_freq = par->mclk_freq >> (regval >> 5);
948
949 /* Restore locks */
950 vga_wcrt(NULL, 0x38, cr38);
951 vga_wcrt(NULL, 0x39, cr39);
952
953 strcpy(info->fix.id, s3_names [par->chip]);
954 info->fix.mmio_start = 0;
955 info->fix.mmio_len = 0;
956 info->fix.type = FB_TYPE_PACKED_PIXELS;
957 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
958 info->fix.ypanstep = 0;
959 info->fix.accel = FB_ACCEL_NONE;
960 info->pseudo_palette = (void*) (par->pseudo_palette);
961
962 /* Prepare startup mode */
963 rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8);
964 if (! ((rc == 1) || (rc == 2))) {
965 rc = -EINVAL;
966 dev_err(&(dev->dev), "mode %s not found\n", mode);
967 goto err_find_mode;
968 }
969
970 rc = fb_alloc_cmap(&info->cmap, 256, 0);
971 if (rc < 0) {
972 dev_err(&(dev->dev), "cannot allocate colormap\n");
973 goto err_alloc_cmap;
974 }
975
976 rc = register_framebuffer(info);
977 if (rc < 0) {
978 dev_err(&(dev->dev), "cannot register framebuffer\n");
979 goto err_reg_fb;
980 }
981
982 printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
983 pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
984
985 if (par->chip == CHIP_UNKNOWN)
986 printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
987 info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
988 vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
989
990 /* Record a reference to the driver data */
991 pci_set_drvdata(dev, info);
992
993 #ifdef CONFIG_MTRR
994 if (mtrr) {
995 par->mtrr_reg = -1;
996 par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
997 }
998 #endif
999
1000 return 0;
1001
1002 /* Error handling */
1003 err_reg_fb:
1004 fb_dealloc_cmap(&info->cmap);
1005 err_alloc_cmap:
1006 err_find_mode:
1007 pci_iounmap(dev, info->screen_base);
1008 err_iomap:
1009 pci_release_regions(dev);
1010 err_request_regions:
1011 /* pci_disable_device(dev); */
1012 err_enable_device:
1013 framebuffer_release(info);
1014 return rc;
1015 }
1016
1017
1018 /* PCI remove */
1019
1020 static void __devexit s3_pci_remove(struct pci_dev *dev)
1021 {
1022 struct fb_info *info = pci_get_drvdata(dev);
1023
1024 if (info) {
1025
1026 #ifdef CONFIG_MTRR
1027 struct s3fb_info *par = info->par;
1028
1029 if (par->mtrr_reg >= 0) {
1030 mtrr_del(par->mtrr_reg, 0, 0);
1031 par->mtrr_reg = -1;
1032 }
1033 #endif
1034
1035 unregister_framebuffer(info);
1036 fb_dealloc_cmap(&info->cmap);
1037
1038 pci_iounmap(dev, info->screen_base);
1039 pci_release_regions(dev);
1040 /* pci_disable_device(dev); */
1041
1042 pci_set_drvdata(dev, NULL);
1043 framebuffer_release(info);
1044 }
1045 }
1046
1047 /* PCI suspend */
1048
1049 static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
1050 {
1051 struct fb_info *info = pci_get_drvdata(dev);
1052 struct s3fb_info *par = info->par;
1053
1054 dev_info(&(dev->dev), "suspend\n");
1055
1056 acquire_console_sem();
1057 mutex_lock(&(par->open_lock));
1058
1059 if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1060 mutex_unlock(&(par->open_lock));
1061 release_console_sem();
1062 return 0;
1063 }
1064
1065 fb_set_suspend(info, 1);
1066
1067 pci_save_state(dev);
1068 pci_disable_device(dev);
1069 pci_set_power_state(dev, pci_choose_state(dev, state));
1070
1071 mutex_unlock(&(par->open_lock));
1072 release_console_sem();
1073
1074 return 0;
1075 }
1076
1077
1078 /* PCI resume */
1079
1080 static int s3_pci_resume(struct pci_dev* dev)
1081 {
1082 struct fb_info *info = pci_get_drvdata(dev);
1083 struct s3fb_info *par = info->par;
1084 int err;
1085
1086 dev_info(&(dev->dev), "resume\n");
1087
1088 acquire_console_sem();
1089 mutex_lock(&(par->open_lock));
1090
1091 if (par->ref_count == 0) {
1092 mutex_unlock(&(par->open_lock));
1093 release_console_sem();
1094 return 0;
1095 }
1096
1097 pci_set_power_state(dev, PCI_D0);
1098 pci_restore_state(dev);
1099 err = pci_enable_device(dev);
1100 if (err) {
1101 mutex_unlock(&(par->open_lock));
1102 release_console_sem();
1103 dev_err(&(dev->dev), "error %d enabling device for resume\n", err);
1104 return err;
1105 }
1106 pci_set_master(dev);
1107
1108 s3fb_set_par(info);
1109 fb_set_suspend(info, 0);
1110
1111 mutex_unlock(&(par->open_lock));
1112 release_console_sem();
1113
1114 return 0;
1115 }
1116
1117
1118 /* List of boards that we are trying to support */
1119
1120 static struct pci_device_id s3_devices[] __devinitdata = {
1121 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1122 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1123 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1124 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1125 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1126 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1127
1128 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1129 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1130 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1131 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
1132 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
1133 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1134
1135 {0, 0, 0, 0, 0, 0, 0}
1136 };
1137
1138
1139 MODULE_DEVICE_TABLE(pci, s3_devices);
1140
1141 static struct pci_driver s3fb_pci_driver = {
1142 .name = "s3fb",
1143 .id_table = s3_devices,
1144 .probe = s3_pci_probe,
1145 .remove = __devexit_p(s3_pci_remove),
1146 .suspend = s3_pci_suspend,
1147 .resume = s3_pci_resume,
1148 };
1149
1150 /* Parse user speficied options */
1151
1152 #ifndef MODULE
1153 static int __init s3fb_setup(char *options)
1154 {
1155 char *opt;
1156
1157 if (!options || !*options)
1158 return 0;
1159
1160 while ((opt = strsep(&options, ",")) != NULL) {
1161
1162 if (!*opt)
1163 continue;
1164 #ifdef CONFIG_MTRR
1165 else if (!strncmp(opt, "mtrr:", 5))
1166 mtrr = simple_strtoul(opt + 5, NULL, 0);
1167 #endif
1168 else if (!strncmp(opt, "fasttext:", 9))
1169 fasttext = simple_strtoul(opt + 9, NULL, 0);
1170 else
1171 mode = opt;
1172 }
1173
1174 return 0;
1175 }
1176 #endif
1177
1178 /* Cleanup */
1179
1180 static void __exit s3fb_cleanup(void)
1181 {
1182 pr_debug("s3fb: cleaning up\n");
1183 pci_unregister_driver(&s3fb_pci_driver);
1184 }
1185
1186 /* Driver Initialisation */
1187
1188 static int __init s3fb_init(void)
1189 {
1190
1191 #ifndef MODULE
1192 char *option = NULL;
1193
1194 if (fb_get_options("s3fb", &option))
1195 return -ENODEV;
1196 s3fb_setup(option);
1197 #endif
1198
1199 pr_debug("s3fb: initializing\n");
1200 return pci_register_driver(&s3fb_pci_driver);
1201 }
1202
1203 /* ------------------------------------------------------------------------- */
1204
1205 /* Modularization */
1206
1207 module_init(s3fb_init);
1208 module_exit(s3fb_cleanup);
WRT350N Kernel Patches