?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: 64-bit, add the new split_large_page() function
[wrt350n-kernel.git] / sound / pci / cmipci.c
blob1fa5f004e858fd8d0e0994aa20642e5eb974bede
1 /*
2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
22
23 #include <sound/driver.h>
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <linux/mutex.h>
33 #include <sound/core.h>
34 #include <sound/info.h>
35 #include <sound/control.h>
36 #include <sound/pcm.h>
37 #include <sound/rawmidi.h>
38 #include <sound/mpu401.h>
39 #include <sound/opl3.h>
40 #include <sound/sb.h>
41 #include <sound/asoundef.h>
42 #include <sound/initval.h>
43
44 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
45 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
46 MODULE_LICENSE("GPL");
47 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
48 "{C-Media,CMI8738B},"
49 "{C-Media,CMI8338A},"
50 "{C-Media,CMI8338B}}");
51
52 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
53 #define SUPPORT_JOYSTICK 1
54 #endif
55
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
59 static long mpu_port[SNDRV_CARDS];
60 static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
61 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
62 #ifdef SUPPORT_JOYSTICK
63 static int joystick_port[SNDRV_CARDS];
64 #endif
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
68 module_param_array(id, charp, NULL, 0444);
69 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
70 module_param_array(enable, bool, NULL, 0444);
71 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
72 module_param_array(mpu_port, long, NULL, 0444);
73 MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
74 module_param_array(fm_port, long, NULL, 0444);
75 MODULE_PARM_DESC(fm_port, "FM port.");
76 module_param_array(soft_ac3, bool, NULL, 0444);
77 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only).");
78 #ifdef SUPPORT_JOYSTICK
79 module_param_array(joystick_port, int, NULL, 0444);
80 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
81 #endif
82
83 /*
84 * CM8x38 registers definition
85 */
86
87 #define CM_REG_FUNCTRL0 0x00
88 #define CM_RST_CH1 0x00080000
89 #define CM_RST_CH0 0x00040000
90 #define CM_CHEN1 0x00020000 /* ch1: enable */
91 #define CM_CHEN0 0x00010000 /* ch0: enable */
92 #define CM_PAUSE1 0x00000008 /* ch1: pause */
93 #define CM_PAUSE0 0x00000004 /* ch0: pause */
94 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
95 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96
97 #define CM_REG_FUNCTRL1 0x04
98 #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
99 #define CM_DSFC_SHIFT 13
100 #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
101 #define CM_ASFC_SHIFT 10
102 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
103 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
104 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
105 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
106 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
107 #define CM_BREQ 0x00000010 /* bus master enabled */
108 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
109 #define CM_UART_EN 0x00000004 /* legacy UART */
110 #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
111 #define CM_ZVPORT 0x00000001 /* ZVPORT */
112
113 #define CM_REG_CHFORMAT 0x08
114
115 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
116 #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
117 #define CM_CHB3D 0x20000000 /* 4 channels */
118
119 #define CM_CHIP_MASK1 0x1f000000
120 #define CM_CHIP_037 0x01000000
121 #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
122 #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
123 #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
124 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
125 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
126 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
127 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
128
129 #define CM_ADCBITLEN_MASK 0x0000C000
130 #define CM_ADCBITLEN_16 0x00000000
131 #define CM_ADCBITLEN_15 0x00004000
132 #define CM_ADCBITLEN_14 0x00008000
133 #define CM_ADCBITLEN_13 0x0000C000
134
135 #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
136 #define CM_ADCDACLEN_060 0x00000000
137 #define CM_ADCDACLEN_066 0x00001000
138 #define CM_ADCDACLEN_130 0x00002000
139 #define CM_ADCDACLEN_280 0x00003000
140
141 #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
142 #define CM_ADCDLEN_ORIGINAL 0x00000000
143 #define CM_ADCDLEN_EXTRA 0x00001000
144 #define CM_ADCDLEN_24K 0x00002000
145 #define CM_ADCDLEN_WEIGHT 0x00003000
146
147 #define CM_CH1_SRATE_176K 0x00000800
148 #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
149 #define CM_CH1_SRATE_88K 0x00000400
150 #define CM_CH0_SRATE_176K 0x00000200
151 #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
152 #define CM_CH0_SRATE_88K 0x00000100
153
154 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
155 #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
156 #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
157 #define CM_SPDLOCKED 0x00000010
158
159 #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
160 #define CM_CH1FMT_SHIFT 2
161 #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
162 #define CM_CH0FMT_SHIFT 0
163
164 #define CM_REG_INT_HLDCLR 0x0C
165 #define CM_CHIP_MASK2 0xff000000
166 #define CM_CHIP_8768 0x20000000
167 #define CM_CHIP_055 0x08000000
168 #define CM_CHIP_039 0x04000000
169 #define CM_CHIP_039_6CH 0x01000000
170 #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
171 #define CM_TDMA_INT_EN 0x00040000
172 #define CM_CH1_INT_EN 0x00020000
173 #define CM_CH0_INT_EN 0x00010000
174
175 #define CM_REG_INT_STATUS 0x10
176 #define CM_INTR 0x80000000
177 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
178 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
179 #define CM_UARTINT 0x00010000
180 #define CM_LTDMAINT 0x00008000
181 #define CM_HTDMAINT 0x00004000
182 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
183 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
184 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
185 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
186 #define CM_CH1BUSY 0x00000008
187 #define CM_CH0BUSY 0x00000004
188 #define CM_CHINT1 0x00000002
189 #define CM_CHINT0 0x00000001
190
191 #define CM_REG_LEGACY_CTRL 0x14
192 #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
193 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
194 #define CM_VMPU_330 0x00000000
195 #define CM_VMPU_320 0x20000000
196 #define CM_VMPU_310 0x40000000
197 #define CM_VMPU_300 0x60000000
198 #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
199 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
200 #define CM_VSBSEL_220 0x00000000
201 #define CM_VSBSEL_240 0x04000000
202 #define CM_VSBSEL_260 0x08000000
203 #define CM_VSBSEL_280 0x0C000000
204 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
205 #define CM_FMSEL_388 0x00000000
206 #define CM_FMSEL_3C8 0x01000000
207 #define CM_FMSEL_3E0 0x02000000
208 #define CM_FMSEL_3E8 0x03000000
209 #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
210 #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
211 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
212 #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
213 #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
214 #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
215 #define CM_C_EECS 0x00040000
216 #define CM_C_EEDI46 0x00020000
217 #define CM_C_EECK46 0x00010000
218 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
219 #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
220 #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
221 #define CM_EXBASEN 0x00001000 /* external bass input enable */
222
223 #define CM_REG_MISC_CTRL 0x18
224 #define CM_PWD 0x80000000 /* power down */
225 #define CM_RESET 0x40000000
226 #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
227 #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
228 #define CM_TXVX 0x08000000 /* model 037? */
229 #define CM_N4SPK3D 0x04000000 /* copy front to rear */
230 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
231 #define CM_SPDIF48K 0x01000000 /* write */
232 #define CM_SPATUS48K 0x01000000 /* read */
233 #define CM_ENDBDAC 0x00800000 /* enable double dac */
234 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
235 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
236 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
237 #define CM_FM_EN 0x00080000 /* enable legacy FM */
238 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
239 #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
240 #define CM_VIDWPDSB 0x00010000 /* model 037? */
241 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
242 #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
243 #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
244 #define CM_VIDWPPRT 0x00002000 /* model 037? */
245 #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
246 #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
247 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
248 #define CM_ENCENTER 0x00000080
249 #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
250 #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
251 #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
252 #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
253 #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
254 #define CM_UPDDMA_2048 0x00000000
255 #define CM_UPDDMA_1024 0x00000004
256 #define CM_UPDDMA_512 0x00000008
257 #define CM_UPDDMA_256 0x0000000C
258 #define CM_TWAIT_MASK 0x00000003 /* model 037 */
259 #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
260 #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
261
262 #define CM_REG_TDMA_POSITION 0x1C
263 #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
264 #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
265
266 /* byte */
267 #define CM_REG_MIXER0 0x20
268 #define CM_REG_SBVR 0x20 /* write: sb16 version */
269 #define CM_REG_DEV 0x20 /* read: hardware device version */
270
271 #define CM_REG_MIXER21 0x21
272 #define CM_UNKNOWN_21_MASK 0x78 /* ? */
273 #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
274 #define CM_PROINV 0x02 /* SBPro left/right channel switching */
275 #define CM_X_SB16 0x01 /* SB16 compatible */
276
277 #define CM_REG_SB16_DATA 0x22
278 #define CM_REG_SB16_ADDR 0x23
279
280 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
281 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
282 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
283 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
284
285 #define CM_REG_MIXER1 0x24
286 #define CM_FMMUTE 0x80 /* mute FM */
287 #define CM_FMMUTE_SHIFT 7
288 #define CM_WSMUTE 0x40 /* mute PCM */
289 #define CM_WSMUTE_SHIFT 6
290 #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
291 #define CM_REAR2LIN_SHIFT 5
292 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
293 #define CM_REAR2FRONT_SHIFT 4
294 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
295 #define CM_WAVEINL_SHIFT 3
296 #define CM_WAVEINR 0x04 /* digical wave rec. right */
297 #define CM_WAVEINR_SHIFT 2
298 #define CM_X3DEN 0x02 /* 3D surround enable */
299 #define CM_X3DEN_SHIFT 1
300 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
301 #define CM_CDPLAY_SHIFT 0
302
303 #define CM_REG_MIXER2 0x25
304 #define CM_RAUXREN 0x80 /* AUX right capture */
305 #define CM_RAUXREN_SHIFT 7
306 #define CM_RAUXLEN 0x40 /* AUX left capture */
307 #define CM_RAUXLEN_SHIFT 6
308 #define CM_VAUXRM 0x20 /* AUX right mute */
309 #define CM_VAUXRM_SHIFT 5
310 #define CM_VAUXLM 0x10 /* AUX left mute */
311 #define CM_VAUXLM_SHIFT 4
312 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
313 #define CM_VADMIC_SHIFT 1
314 #define CM_MICGAINZ 0x01 /* mic boost */
315 #define CM_MICGAINZ_SHIFT 0
316
317 #define CM_REG_MIXER3 0x24
318 #define CM_REG_AUX_VOL 0x26
319 #define CM_VAUXL_MASK 0xf0
320 #define CM_VAUXR_MASK 0x0f
321
322 #define CM_REG_MISC 0x27
323 #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
324 #define CM_XGPO1 0x20
325 // #define CM_XGPBIO 0x04
326 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
327 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
328 #define CM_SPDVALID 0x02 /* spdif input valid check */
329 #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
330
331 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
332 /*
333 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
334 * or identical with AC97 codec?
335 */
336 #define CM_REG_EXTERN_CODEC CM_REG_AC97
337
338 /*
339 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
340 */
341 #define CM_REG_MPU_PCI 0x40
342
343 /*
344 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
345 */
346 #define CM_REG_FM_PCI 0x50
347
348 /*
349 * access from SB-mixer port
350 */
351 #define CM_REG_EXTENT_IND 0xf0
352 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
353 #define CM_VPHONE_SHIFT 5
354 #define CM_VPHOM 0x10 /* Phone mute control */
355 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
356 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
357 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
358 #define CM_VADMIC3 0x01 /* Mic record boost */
359
360 /*
361 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
362 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
363 * unit (readonly?).
364 */
365 #define CM_REG_PLL 0xf8
366
367 /*
368 * extended registers
369 */
370 #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
371 #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
372 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
373 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
374
375 #define CM_REG_EXT_MISC 0x90
376 #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
377 #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
378 #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
379 #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
380 #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
381 #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
382 #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
383 #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
384
385 /*
386 * size of i/o region
387 */
388 #define CM_EXTENT_CODEC 0x100
389 #define CM_EXTENT_MIDI 0x2
390 #define CM_EXTENT_SYNTH 0x4
391
392
393 /*
394 * channels for playback / capture
395 */
396 #define CM_CH_PLAY 0
397 #define CM_CH_CAPT 1
398
399 /*
400 * flags to check device open/close
401 */
402 #define CM_OPEN_NONE 0
403 #define CM_OPEN_CH_MASK 0x01
404 #define CM_OPEN_DAC 0x10
405 #define CM_OPEN_ADC 0x20
406 #define CM_OPEN_SPDIF 0x40
407 #define CM_OPEN_MCHAN 0x80
408 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
409 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
410 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
411 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
412 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
413 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
414
415
416 #if CM_CH_PLAY == 1
417 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
418 #define CM_PLAYBACK_SPDF CM_SPDF_1
419 #define CM_CAPTURE_SPDF CM_SPDF_0
420 #else
421 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
422 #define CM_PLAYBACK_SPDF CM_SPDF_0
423 #define CM_CAPTURE_SPDF CM_SPDF_1
424 #endif
425
426
427 /*
428 * driver data
429 */
430
431 struct cmipci_pcm {
432 struct snd_pcm_substream *substream;
433 u8 running; /* dac/adc running? */
434 u8 fmt; /* format bits */
435 u8 is_dac;
436 u8 needs_silencing;
437 unsigned int dma_size; /* in frames */
438 unsigned int shift;
439 unsigned int ch; /* channel (0/1) */
440 unsigned int offset; /* physical address of the buffer */
441 };
442
443 /* mixer elements toggled/resumed during ac3 playback */
444 struct cmipci_mixer_auto_switches {
445 const char *name; /* switch to toggle */
446 int toggle_on; /* value to change when ac3 mode */
447 };
448 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
449 {"PCM Playback Switch", 0},
450 {"IEC958 Output Switch", 1},
451 {"IEC958 Mix Analog", 0},
452 // {"IEC958 Out To DAC", 1}, // no longer used
453 {"IEC958 Loop", 0},
454 };
455 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
456
457 struct cmipci {
458 struct snd_card *card;
459
460 struct pci_dev *pci;
461 unsigned int device; /* device ID */
462 int irq;
463
464 unsigned long iobase;
465 unsigned int ctrl; /* FUNCTRL0 current value */
466
467 struct snd_pcm *pcm; /* DAC/ADC PCM */
468 struct snd_pcm *pcm2; /* 2nd DAC */
469 struct snd_pcm *pcm_spdif; /* SPDIF */
470
471 int chip_version;
472 int max_channels;
473 unsigned int can_ac3_sw: 1;
474 unsigned int can_ac3_hw: 1;
475 unsigned int can_multi_ch: 1;
476 unsigned int do_soft_ac3: 1;
477
478 unsigned int spdif_playback_avail: 1; /* spdif ready? */
479 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
480 int spdif_counter; /* for software AC3 */
481
482 unsigned int dig_status;
483 unsigned int dig_pcm_status;
484
485 struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
486
487 int opened[2]; /* open mode */
488 struct mutex open_mutex;
489
490 unsigned int mixer_insensitive: 1;
491 struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
492 int mixer_res_status[CM_SAVED_MIXERS];
493
494 struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
495
496 /* external MIDI */
497 struct snd_rawmidi *rmidi;
498
499 #ifdef SUPPORT_JOYSTICK
500 struct gameport *gameport;
501 #endif
502
503 spinlock_t reg_lock;
504
505 #ifdef CONFIG_PM
506 unsigned int saved_regs[0x20];
507 unsigned char saved_mixers[0x20];
508 #endif
509 };
510
511
512 /* read/write operations for dword register */
513 static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
514 {
515 outl(data, cm->iobase + cmd);
516 }
517
518 static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
519 {
520 return inl(cm->iobase + cmd);
521 }
522
523 /* read/write operations for word register */
524 static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
525 {
526 outw(data, cm->iobase + cmd);
527 }
528
529 static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
530 {
531 return inw(cm->iobase + cmd);
532 }
533
534 /* read/write operations for byte register */
535 static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
536 {
537 outb(data, cm->iobase + cmd);
538 }
539
540 static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
541 {
542 return inb(cm->iobase + cmd);
543 }
544
545 /* bit operations for dword register */
546 static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
547 {
548 unsigned int val, oval;
549 val = oval = inl(cm->iobase + cmd);
550 val |= flag;
551 if (val == oval)
552 return 0;
553 outl(val, cm->iobase + cmd);
554 return 1;
555 }
556
557 static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
558 {
559 unsigned int val, oval;
560 val = oval = inl(cm->iobase + cmd);
561 val &= ~flag;
562 if (val == oval)
563 return 0;
564 outl(val, cm->iobase + cmd);
565 return 1;
566 }
567
568 /* bit operations for byte register */
569 static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
570 {
571 unsigned char val, oval;
572 val = oval = inb(cm->iobase + cmd);
573 val |= flag;
574 if (val == oval)
575 return 0;
576 outb(val, cm->iobase + cmd);
577 return 1;
578 }
579
580 static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
581 {
582 unsigned char val, oval;
583 val = oval = inb(cm->iobase + cmd);
584 val &= ~flag;
585 if (val == oval)
586 return 0;
587 outb(val, cm->iobase + cmd);
588 return 1;
589 }
590
591
592 /*
593 * PCM interface
594 */
595
596 /*
597 * calculate frequency
598 */
599
600 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
601
602 static unsigned int snd_cmipci_rate_freq(unsigned int rate)
603 {
604 unsigned int i;
605
606 if (rate > 48000)
607 rate /= 2;
608 for (i = 0; i < ARRAY_SIZE(rates); i++) {
609 if (rates[i] == rate)
610 return i;
611 }
612 snd_BUG();
613 return 0;
614 }
615
616 #ifdef USE_VAR48KRATE
617 /*
618 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
619 * does it this way .. maybe not. Never get any information from C-Media about
620 * that <werner@suse.de>.
621 */
622 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
623 {
624 unsigned int delta, tolerance;
625 int xm, xn, xr;
626
627 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
628 rate <<= 1;
629 *n = -1;
630 if (*r > 0xff)
631 goto out;
632 tolerance = rate*CM_TOLERANCE_RATE;
633
634 for (xn = (1+2); xn < (0x1f+2); xn++) {
635 for (xm = (1+2); xm < (0xff+2); xm++) {
636 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
637
638 if (xr < rate)
639 delta = rate - xr;
640 else
641 delta = xr - rate;
642
643 /*
644 * If we found one, remember this,
645 * and try to find a closer one
646 */
647 if (delta < tolerance) {
648 tolerance = delta;
649 *m = xm - 2;
650 *n = xn - 2;
651 }
652 }
653 }
654 out:
655 return (*n > -1);
656 }
657
658 /*
659 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
660 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
661 * at the register CM_REG_FUNCTRL1 (0x04).
662 * Problem: other ways are also possible (any information about that?)
663 */
664 static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
665 {
666 unsigned int reg = CM_REG_PLL + slot;
667 /*
668 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
669 * for DSFC/ASFC (000 upto 111).
670 */
671
672 /* FIXME: Init (Do we've to set an other register first before programming?) */
673
674 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
675 snd_cmipci_write_b(cm, reg, rate>>8);
676 snd_cmipci_write_b(cm, reg, rate&0xff);
677
678 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
679 }
680 #endif /* USE_VAR48KRATE */
681
682 static int snd_cmipci_hw_params(struct snd_pcm_substream *substream,
683 struct snd_pcm_hw_params *hw_params)
684 {
685 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
686 }
687
688 static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
689 struct snd_pcm_hw_params *hw_params)
690 {
691 struct cmipci *cm = snd_pcm_substream_chip(substream);
692 if (params_channels(hw_params) > 2) {
693 mutex_lock(&cm->open_mutex);
694 if (cm->opened[CM_CH_PLAY]) {
695 mutex_unlock(&cm->open_mutex);
696 return -EBUSY;
697 }
698 /* reserve the channel A */
699 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
700 mutex_unlock(&cm->open_mutex);
701 }
702 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
703 }
704
705 static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
706 {
707 int reset = CM_RST_CH0 << (cm->channel[ch].ch);
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
710 udelay(10);
711 }
712
713 static int snd_cmipci_hw_free(struct snd_pcm_substream *substream)
714 {
715 return snd_pcm_lib_free_pages(substream);
716 }
717
718
719 /*
720 */
721
722 static unsigned int hw_channels[] = {1, 2, 4, 6, 8};
723 static struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
724 .count = 3,
725 .list = hw_channels,
726 .mask = 0,
727 };
728 static struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
729 .count = 4,
730 .list = hw_channels,
731 .mask = 0,
732 };
733 static struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
734 .count = 5,
735 .list = hw_channels,
736 .mask = 0,
737 };
738
739 static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
740 {
741 if (channels > 2) {
742 if (!cm->can_multi_ch || !rec->ch)
743 return -EINVAL;
744 if (rec->fmt != 0x03) /* stereo 16bit only */
745 return -EINVAL;
746 }
747
748 if (cm->can_multi_ch) {
749 spin_lock_irq(&cm->reg_lock);
750 if (channels > 2) {
751 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
752 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
753 } else {
754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
756 }
757 if (channels == 8)
758 snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
759 else
760 snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
761 if (channels == 6) {
762 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
763 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
764 } else {
765 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
766 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
767 }
768 if (channels == 4)
769 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
770 else
771 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
772 spin_unlock_irq(&cm->reg_lock);
773 }
774 return 0;
775 }
776
777
778 /*
779 * prepare playback/capture channel
780 * channel to be used must have been set in rec->ch.
781 */
782 static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
783 struct snd_pcm_substream *substream)
784 {
785 unsigned int reg, freq, val;
786 unsigned int period_size;
787 struct snd_pcm_runtime *runtime = substream->runtime;
788
789 rec->fmt = 0;
790 rec->shift = 0;
791 if (snd_pcm_format_width(runtime->format) >= 16) {
792 rec->fmt |= 0x02;
793 if (snd_pcm_format_width(runtime->format) > 16)
794 rec->shift++; /* 24/32bit */
795 }
796 if (runtime->channels > 1)
797 rec->fmt |= 0x01;
798 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
799 snd_printd("cannot set dac channels\n");
800 return -EINVAL;
801 }
802
803 rec->offset = runtime->dma_addr;
804 /* buffer and period sizes in frame */
805 rec->dma_size = runtime->buffer_size << rec->shift;
806 period_size = runtime->period_size << rec->shift;
807 if (runtime->channels > 2) {
808 /* multi-channels */
809 rec->dma_size = (rec->dma_size * runtime->channels) / 2;
810 period_size = (period_size * runtime->channels) / 2;
811 }
812
813 spin_lock_irq(&cm->reg_lock);
814
815 /* set buffer address */
816 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
817 snd_cmipci_write(cm, reg, rec->offset);
818 /* program sample counts */
819 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
820 snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
821 snd_cmipci_write_w(cm, reg + 2, period_size - 1);
822
823 /* set adc/dac flag */
824 val = rec->ch ? CM_CHADC1 : CM_CHADC0;
825 if (rec->is_dac)
826 cm->ctrl &= ~val;
827 else
828 cm->ctrl |= val;
829 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
830 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
831
832 /* set sample rate */
833 freq = snd_cmipci_rate_freq(runtime->rate);
834 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
835 if (rec->ch) {
836 val &= ~CM_DSFC_MASK;
837 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
838 } else {
839 val &= ~CM_ASFC_MASK;
840 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
841 }
842 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
843 //snd_printd("cmipci: functrl1 = %08x\n", val);
844
845 /* set format */
846 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
847 if (rec->ch) {
848 val &= ~CM_CH1FMT_MASK;
849 val |= rec->fmt << CM_CH1FMT_SHIFT;
850 } else {
851 val &= ~CM_CH0FMT_MASK;
852 val |= rec->fmt << CM_CH0FMT_SHIFT;
853 }
854 if (cm->chip_version == 68) {
855 if (runtime->rate == 88200)
856 val |= CM_CH0_SRATE_88K << (rec->ch * 2);
857 else
858 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
859 if (runtime->rate == 96000)
860 val |= CM_CH0_SRATE_96K << (rec->ch * 2);
861 else
862 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
863 }
864 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
865 //snd_printd("cmipci: chformat = %08x\n", val);
866
867 rec->running = 0;
868 spin_unlock_irq(&cm->reg_lock);
869
870 return 0;
871 }
872
873 /*
874 * PCM trigger/stop
875 */
876 static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
877 int cmd)
878 {
879 unsigned int inthld, chen, reset, pause;
880 int result = 0;
881
882 inthld = CM_CH0_INT_EN << rec->ch;
883 chen = CM_CHEN0 << rec->ch;
884 reset = CM_RST_CH0 << rec->ch;
885 pause = CM_PAUSE0 << rec->ch;
886
887 spin_lock(&cm->reg_lock);
888 switch (cmd) {
889 case SNDRV_PCM_TRIGGER_START:
890 rec->running = 1;
891 /* set interrupt */
892 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
893 cm->ctrl |= chen;
894 /* enable channel */
895 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
896 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
897 break;
898 case SNDRV_PCM_TRIGGER_STOP:
899 rec->running = 0;
900 /* disable interrupt */
901 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
902 /* reset */
903 cm->ctrl &= ~chen;
904 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
905 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
906 rec->needs_silencing = rec->is_dac;
907 break;
908 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
909 case SNDRV_PCM_TRIGGER_SUSPEND:
910 cm->ctrl |= pause;
911 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
912 break;
913 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
914 case SNDRV_PCM_TRIGGER_RESUME:
915 cm->ctrl &= ~pause;
916 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
917 break;
918 default:
919 result = -EINVAL;
920 break;
921 }
922 spin_unlock(&cm->reg_lock);
923 return result;
924 }
925
926 /*
927 * return the current pointer
928 */
929 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
930 struct snd_pcm_substream *substream)
931 {
932 size_t ptr;
933 unsigned int reg;
934 if (!rec->running)
935 return 0;
936 #if 1 // this seems better..
937 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
938 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1);
939 ptr >>= rec->shift;
940 #else
941 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
942 ptr = snd_cmipci_read(cm, reg) - rec->offset;
943 ptr = bytes_to_frames(substream->runtime, ptr);
944 #endif
945 if (substream->runtime->channels > 2)
946 ptr = (ptr * 2) / substream->runtime->channels;
947 return ptr;
948 }
949
950 /*
951 * playback
952 */
953
954 static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
955 int cmd)
956 {
957 struct cmipci *cm = snd_pcm_substream_chip(substream);
958 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
959 }
960
961 static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
962 {
963 struct cmipci *cm = snd_pcm_substream_chip(substream);
964 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
965 }
966
967
968
969 /*
970 * capture
971 */
972
973 static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
974 int cmd)
975 {
976 struct cmipci *cm = snd_pcm_substream_chip(substream);
977 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
978 }
979
980 static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
981 {
982 struct cmipci *cm = snd_pcm_substream_chip(substream);
983 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
984 }
985
986
987 /*
988 * hw preparation for spdif
989 */
990
991 static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
992 struct snd_ctl_elem_info *uinfo)
993 {
994 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
995 uinfo->count = 1;
996 return 0;
997 }
998
999 static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001 {
1002 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1003 int i;
1004
1005 spin_lock_irq(&chip->reg_lock);
1006 for (i = 0; i < 4; i++)
1007 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
1008 spin_unlock_irq(&chip->reg_lock);
1009 return 0;
1010 }
1011
1012 static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
1013 struct snd_ctl_elem_value *ucontrol)
1014 {
1015 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1016 int i, change;
1017 unsigned int val;
1018
1019 val = 0;
1020 spin_lock_irq(&chip->reg_lock);
1021 for (i = 0; i < 4; i++)
1022 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1023 change = val != chip->dig_status;
1024 chip->dig_status = val;
1025 spin_unlock_irq(&chip->reg_lock);
1026 return change;
1027 }
1028
1029 static struct snd_kcontrol_new snd_cmipci_spdif_default __devinitdata =
1030 {
1031 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1032 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1033 .info = snd_cmipci_spdif_default_info,
1034 .get = snd_cmipci_spdif_default_get,
1035 .put = snd_cmipci_spdif_default_put
1036 };
1037
1038 static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_info *uinfo)
1040 {
1041 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1042 uinfo->count = 1;
1043 return 0;
1044 }
1045
1046 static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1048 {
1049 ucontrol->value.iec958.status[0] = 0xff;
1050 ucontrol->value.iec958.status[1] = 0xff;
1051 ucontrol->value.iec958.status[2] = 0xff;
1052 ucontrol->value.iec958.status[3] = 0xff;
1053 return 0;
1054 }
1055
1056 static struct snd_kcontrol_new snd_cmipci_spdif_mask __devinitdata =
1057 {
1058 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1059 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1060 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1061 .info = snd_cmipci_spdif_mask_info,
1062 .get = snd_cmipci_spdif_mask_get,
1063 };
1064
1065 static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1066 struct snd_ctl_elem_info *uinfo)
1067 {
1068 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1069 uinfo->count = 1;
1070 return 0;
1071 }
1072
1073 static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1074 struct snd_ctl_elem_value *ucontrol)
1075 {
1076 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1077 int i;
1078
1079 spin_lock_irq(&chip->reg_lock);
1080 for (i = 0; i < 4; i++)
1081 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1082 spin_unlock_irq(&chip->reg_lock);
1083 return 0;
1084 }
1085
1086 static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1087 struct snd_ctl_elem_value *ucontrol)
1088 {
1089 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1090 int i, change;
1091 unsigned int val;
1092
1093 val = 0;
1094 spin_lock_irq(&chip->reg_lock);
1095 for (i = 0; i < 4; i++)
1096 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1097 change = val != chip->dig_pcm_status;
1098 chip->dig_pcm_status = val;
1099 spin_unlock_irq(&chip->reg_lock);
1100 return change;
1101 }
1102
1103 static struct snd_kcontrol_new snd_cmipci_spdif_stream __devinitdata =
1104 {
1105 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1106 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1107 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1108 .info = snd_cmipci_spdif_stream_info,
1109 .get = snd_cmipci_spdif_stream_get,
1110 .put = snd_cmipci_spdif_stream_put
1111 };
1112
1113 /*
1114 */
1115
1116 /* save mixer setting and mute for AC3 playback */
1117 static int save_mixer_state(struct cmipci *cm)
1118 {
1119 if (! cm->mixer_insensitive) {
1120 struct snd_ctl_elem_value *val;
1121 unsigned int i;
1122
1123 val = kmalloc(sizeof(*val), GFP_ATOMIC);
1124 if (!val)
1125 return -ENOMEM;
1126 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1127 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1128 if (ctl) {
1129 int event;
1130 memset(val, 0, sizeof(*val));
1131 ctl->get(ctl, val);
1132 cm->mixer_res_status[i] = val->value.integer.value[0];
1133 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1134 event = SNDRV_CTL_EVENT_MASK_INFO;
1135 if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1136 ctl->put(ctl, val); /* toggle */
1137 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1138 }
1139 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1140 snd_ctl_notify(cm->card, event, &ctl->id);
1141 }
1142 }
1143 kfree(val);
1144 cm->mixer_insensitive = 1;
1145 }
1146 return 0;
1147 }
1148
1149
1150 /* restore the previously saved mixer status */
1151 static void restore_mixer_state(struct cmipci *cm)
1152 {
1153 if (cm->mixer_insensitive) {
1154 struct snd_ctl_elem_value *val;
1155 unsigned int i;
1156
1157 val = kmalloc(sizeof(*val), GFP_KERNEL);
1158 if (!val)
1159 return;
1160 cm->mixer_insensitive = 0; /* at first clear this;
1161 otherwise the changes will be ignored */
1162 for (i = 0; i < CM_SAVED_MIXERS; i++) {
1163 struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1164 if (ctl) {
1165 int event;
1166
1167 memset(val, 0, sizeof(*val));
1168 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1169 ctl->get(ctl, val);
1170 event = SNDRV_CTL_EVENT_MASK_INFO;
1171 if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1172 val->value.integer.value[0] = cm->mixer_res_status[i];
1173 ctl->put(ctl, val);
1174 event |= SNDRV_CTL_EVENT_MASK_VALUE;
1175 }
1176 snd_ctl_notify(cm->card, event, &ctl->id);
1177 }
1178 }
1179 kfree(val);
1180 }
1181 }
1182
1183 /* spinlock held! */
1184 static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1185 {
1186 if (do_ac3) {
1187 /* AC3EN for 037 */
1188 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1189 /* AC3EN for 039 */
1190 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1191
1192 if (cm->can_ac3_hw) {
1193 /* SPD24SEL for 037, 0x02 */
1194 /* SPD24SEL for 039, 0x20, but cannot be set */
1195 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1196 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1197 } else { /* can_ac3_sw */
1198 /* SPD32SEL for 037 & 039, 0x20 */
1199 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1200 /* set 176K sample rate to fix 033 HW bug */
1201 if (cm->chip_version == 33) {
1202 if (rate >= 48000) {
1203 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1204 } else {
1205 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1206 }
1207 }
1208 }
1209
1210 } else {
1211 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1212 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1213
1214 if (cm->can_ac3_hw) {
1215 /* chip model >= 37 */
1216 if (snd_pcm_format_width(subs->runtime->format) > 16) {
1217 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1218 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1219 } else {
1220 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1221 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1222 }
1223 } else {
1224 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1225 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1226 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1227 }
1228 }
1229 }
1230
1231 static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1232 {
1233 int rate, err;
1234
1235 rate = subs->runtime->rate;
1236
1237 if (up && do_ac3)
1238 if ((err = save_mixer_state(cm)) < 0)
1239 return err;
1240
1241 spin_lock_irq(&cm->reg_lock);
1242 cm->spdif_playback_avail = up;
1243 if (up) {
1244 /* they are controlled via "IEC958 Output Switch" */
1245 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1246 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1247 if (cm->spdif_playback_enabled)
1248 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1249 setup_ac3(cm, subs, do_ac3, rate);
1250
1251 if (rate == 48000 || rate == 96000)
1252 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1253 else
1254 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1255 if (rate > 48000)
1256 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1257 else
1258 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1259 } else {
1260 /* they are controlled via "IEC958 Output Switch" */
1261 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1262 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1263 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1264 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1265 setup_ac3(cm, subs, 0, 0);
1266 }
1267 spin_unlock_irq(&cm->reg_lock);
1268 return 0;
1269 }
1270
1271
1272 /*
1273 * preparation
1274 */
1275
1276 /* playback - enable spdif only on the certain condition */
1277 static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1278 {
1279 struct cmipci *cm = snd_pcm_substream_chip(substream);
1280 int rate = substream->runtime->rate;
1281 int err, do_spdif, do_ac3 = 0;
1282
1283 do_spdif = (rate >= 44100 &&
1284 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1285 substream->runtime->channels == 2);
1286 if (do_spdif && cm->can_ac3_hw)
1287 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1288 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
1289 return err;
1290 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1291 }
1292
1293 /* playback (via device #2) - enable spdif always */
1294 static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1295 {
1296 struct cmipci *cm = snd_pcm_substream_chip(substream);
1297 int err, do_ac3;
1298
1299 if (cm->can_ac3_hw)
1300 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1301 else
1302 do_ac3 = 1; /* doesn't matter */
1303 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
1304 return err;
1305 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
1306 }
1307
1308 /*
1309 * Apparently, the samples last played on channel A stay in some buffer, even
1310 * after the channel is reset, and get added to the data for the rear DACs when
1311 * playing a multichannel stream on channel B. This is likely to generate
1312 * wraparounds and thus distortions.
1313 * To avoid this, we play at least one zero sample after the actual stream has
1314 * stopped.
1315 */
1316 static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1317 {
1318 struct snd_pcm_runtime *runtime = rec->substream->runtime;
1319 unsigned int reg, val;
1320
1321 if (rec->needs_silencing && runtime && runtime->dma_area) {
1322 /* set up a small silence buffer */
1323 memset(runtime->dma_area, 0, PAGE_SIZE);
1324 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1325 val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1326 snd_cmipci_write(cm, reg, val);
1327
1328 /* configure for 16 bits, 2 channels, 8 kHz */
1329 if (runtime->channels > 2)
1330 set_dac_channels(cm, rec, 2);
1331 spin_lock_irq(&cm->reg_lock);
1332 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1333 val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1334 val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1335 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
1336 val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1337 val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1338 val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1339 if (cm->chip_version == 68) {
1340 val &= ~(CM_CH0_SRATE_88K << (rec->ch * 2));
1341 val &= ~(CM_CH0_SRATE_96K << (rec->ch * 2));
1342 }
1343 snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
1344
1345 /* start stream (we don't need interrupts) */
1346 cm->ctrl |= CM_CHEN0 << rec->ch;
1347 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1348 spin_unlock_irq(&cm->reg_lock);
1349
1350 msleep(1);
1351
1352 /* stop and reset stream */
1353 spin_lock_irq(&cm->reg_lock);
1354 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1355 val = CM_RST_CH0 << rec->ch;
1356 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1357 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
1358 spin_unlock_irq(&cm->reg_lock);
1359
1360 rec->needs_silencing = 0;
1361 }
1362 }
1363
1364 static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1365 {
1366 struct cmipci *cm = snd_pcm_substream_chip(substream);
1367 setup_spdif_playback(cm, substream, 0, 0);
1368 restore_mixer_state(cm);
1369 snd_cmipci_silence_hack(cm, &cm->channel[0]);
1370 return snd_cmipci_hw_free(substream);
1371 }
1372
1373 static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1374 {
1375 struct cmipci *cm = snd_pcm_substream_chip(substream);
1376 snd_cmipci_silence_hack(cm, &cm->channel[1]);
1377 return snd_cmipci_hw_free(substream);
1378 }
1379
1380 /* capture */
1381 static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1382 {
1383 struct cmipci *cm = snd_pcm_substream_chip(substream);
1384 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1385 }
1386
1387 /* capture with spdif (via device #2) */
1388 static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1389 {
1390 struct cmipci *cm = snd_pcm_substream_chip(substream);
1391
1392 spin_lock_irq(&cm->reg_lock);
1393 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1394 spin_unlock_irq(&cm->reg_lock);
1395
1396 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
1397 }
1398
1399 static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1400 {
1401 struct cmipci *cm = snd_pcm_substream_chip(subs);
1402
1403 spin_lock_irq(&cm->reg_lock);
1404 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1405 spin_unlock_irq(&cm->reg_lock);
1406
1407 return snd_cmipci_hw_free(subs);
1408 }
1409
1410
1411 /*
1412 * interrupt handler
1413 */
1414 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1415 {
1416 struct cmipci *cm = dev_id;
1417 unsigned int status, mask = 0;
1418
1419 /* fastpath out, to ease interrupt sharing */
1420 status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1421 if (!(status & CM_INTR))
1422 return IRQ_NONE;
1423
1424 /* acknowledge interrupt */
1425 spin_lock(&cm->reg_lock);
1426 if (status & CM_CHINT0)
1427 mask |= CM_CH0_INT_EN;
1428 if (status & CM_CHINT1)
1429 mask |= CM_CH1_INT_EN;
1430 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
1431 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
1432 spin_unlock(&cm->reg_lock);
1433
1434 if (cm->rmidi && (status & CM_UARTINT))
1435 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
1436
1437 if (cm->pcm) {
1438 if ((status & CM_CHINT0) && cm->channel[0].running)
1439 snd_pcm_period_elapsed(cm->channel[0].substream);
1440 if ((status & CM_CHINT1) && cm->channel[1].running)
1441 snd_pcm_period_elapsed(cm->channel[1].substream);
1442 }
1443 return IRQ_HANDLED;
1444 }
1445
1446 /*
1447 * h/w infos
1448 */
1449
1450 /* playback on channel A */
1451 static struct snd_pcm_hardware snd_cmipci_playback =
1452 {
1453 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1454 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1455 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1456 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1457 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1458 .rate_min = 5512,
1459 .rate_max = 48000,
1460 .channels_min = 1,
1461 .channels_max = 2,
1462 .buffer_bytes_max = (128*1024),
1463 .period_bytes_min = 64,
1464 .period_bytes_max = (128*1024),
1465 .periods_min = 2,
1466 .periods_max = 1024,
1467 .fifo_size = 0,
1468 };
1469
1470 /* capture on channel B */
1471 static struct snd_pcm_hardware snd_cmipci_capture =
1472 {
1473 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1474 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1475 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1476 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1477 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1478 .rate_min = 5512,
1479 .rate_max = 48000,
1480 .channels_min = 1,
1481 .channels_max = 2,
1482 .buffer_bytes_max = (128*1024),
1483 .period_bytes_min = 64,
1484 .period_bytes_max = (128*1024),
1485 .periods_min = 2,
1486 .periods_max = 1024,
1487 .fifo_size = 0,
1488 };
1489
1490 /* playback on channel B - stereo 16bit only? */
1491 static struct snd_pcm_hardware snd_cmipci_playback2 =
1492 {
1493 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1494 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1495 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1496 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1497 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1498 .rate_min = 5512,
1499 .rate_max = 48000,
1500 .channels_min = 2,
1501 .channels_max = 2,
1502 .buffer_bytes_max = (128*1024),
1503 .period_bytes_min = 64,
1504 .period_bytes_max = (128*1024),
1505 .periods_min = 2,
1506 .periods_max = 1024,
1507 .fifo_size = 0,
1508 };
1509
1510 /* spdif playback on channel A */
1511 static struct snd_pcm_hardware snd_cmipci_playback_spdif =
1512 {
1513 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1514 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1515 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1516 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1517 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1518 .rate_min = 44100,
1519 .rate_max = 48000,
1520 .channels_min = 2,
1521 .channels_max = 2,
1522 .buffer_bytes_max = (128*1024),
1523 .period_bytes_min = 64,
1524 .period_bytes_max = (128*1024),
1525 .periods_min = 2,
1526 .periods_max = 1024,
1527 .fifo_size = 0,
1528 };
1529
1530 /* spdif playback on channel A (32bit, IEC958 subframes) */
1531 static struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1532 {
1533 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1534 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1535 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1536 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1537 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1538 .rate_min = 44100,
1539 .rate_max = 48000,
1540 .channels_min = 2,
1541 .channels_max = 2,
1542 .buffer_bytes_max = (128*1024),
1543 .period_bytes_min = 64,
1544 .period_bytes_max = (128*1024),
1545 .periods_min = 2,
1546 .periods_max = 1024,
1547 .fifo_size = 0,
1548 };
1549
1550 /* spdif capture on channel B */
1551 static struct snd_pcm_hardware snd_cmipci_capture_spdif =
1552 {
1553 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1554 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1555 SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1556 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1557 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1558 .rate_min = 44100,
1559 .rate_max = 48000,
1560 .channels_min = 2,
1561 .channels_max = 2,
1562 .buffer_bytes_max = (128*1024),
1563 .period_bytes_min = 64,
1564 .period_bytes_max = (128*1024),
1565 .periods_min = 2,
1566 .periods_max = 1024,
1567 .fifo_size = 0,
1568 };
1569
1570 /*
1571 * check device open/close
1572 */
1573 static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1574 {
1575 int ch = mode & CM_OPEN_CH_MASK;
1576
1577 /* FIXME: a file should wait until the device becomes free
1578 * when it's opened on blocking mode. however, since the current
1579 * pcm framework doesn't pass file pointer before actually opened,
1580 * we can't know whether blocking mode or not in open callback..
1581 */
1582 mutex_lock(&cm->open_mutex);
1583 if (cm->opened[ch]) {
1584 mutex_unlock(&cm->open_mutex);
1585 return -EBUSY;
1586 }
1587 cm->opened[ch] = mode;
1588 cm->channel[ch].substream = subs;
1589 if (! (mode & CM_OPEN_DAC)) {
1590 /* disable dual DAC mode */
1591 cm->channel[ch].is_dac = 0;
1592 spin_lock_irq(&cm->reg_lock);
1593 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1594 spin_unlock_irq(&cm->reg_lock);
1595 }
1596 mutex_unlock(&cm->open_mutex);
1597 return 0;
1598 }
1599
1600 static void close_device_check(struct cmipci *cm, int mode)
1601 {
1602 int ch = mode & CM_OPEN_CH_MASK;
1603
1604 mutex_lock(&cm->open_mutex);
1605 if (cm->opened[ch] == mode) {
1606 if (cm->channel[ch].substream) {
1607 snd_cmipci_ch_reset(cm, ch);
1608 cm->channel[ch].running = 0;
1609 cm->channel[ch].substream = NULL;
1610 }
1611 cm->opened[ch] = 0;
1612 if (! cm->channel[ch].is_dac) {
1613 /* enable dual DAC mode again */
1614 cm->channel[ch].is_dac = 1;
1615 spin_lock_irq(&cm->reg_lock);
1616 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1617 spin_unlock_irq(&cm->reg_lock);
1618 }
1619 }
1620 mutex_unlock(&cm->open_mutex);
1621 }
1622
1623 /*
1624 */
1625
1626 static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1627 {
1628 struct cmipci *cm = snd_pcm_substream_chip(substream);
1629 struct snd_pcm_runtime *runtime = substream->runtime;
1630 int err;
1631
1632 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
1633 return err;
1634 runtime->hw = snd_cmipci_playback;
1635 if (cm->chip_version == 68) {
1636 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1637 SNDRV_PCM_RATE_96000;
1638 runtime->hw.rate_max = 96000;
1639 }
1640 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1641 cm->dig_pcm_status = cm->dig_status;
1642 return 0;
1643 }
1644
1645 static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1646 {
1647 struct cmipci *cm = snd_pcm_substream_chip(substream);
1648 struct snd_pcm_runtime *runtime = substream->runtime;
1649 int err;
1650
1651 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
1652 return err;
1653 runtime->hw = snd_cmipci_capture;
1654 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1655 runtime->hw.rate_min = 41000;
1656 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1657 }
1658 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1659 return 0;
1660 }
1661
1662 static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1663 {
1664 struct cmipci *cm = snd_pcm_substream_chip(substream);
1665 struct snd_pcm_runtime *runtime = substream->runtime;
1666 int err;
1667
1668 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
1669 return err;
1670 runtime->hw = snd_cmipci_playback2;
1671 mutex_lock(&cm->open_mutex);
1672 if (! cm->opened[CM_CH_PLAY]) {
1673 if (cm->can_multi_ch) {
1674 runtime->hw.channels_max = cm->max_channels;
1675 if (cm->max_channels == 4)
1676 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
1677 else if (cm->max_channels == 6)
1678 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
1679 else if (cm->max_channels == 8)
1680 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
1681 }
1682 }
1683 mutex_unlock(&cm->open_mutex);
1684 if (cm->chip_version == 68) {
1685 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1686 SNDRV_PCM_RATE_96000;
1687 runtime->hw.rate_max = 96000;
1688 }
1689 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
1690 return 0;
1691 }
1692
1693 static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1694 {
1695 struct cmipci *cm = snd_pcm_substream_chip(substream);
1696 struct snd_pcm_runtime *runtime = substream->runtime;
1697 int err;
1698
1699 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
1700 return err;
1701 if (cm->can_ac3_hw) {
1702 runtime->hw = snd_cmipci_playback_spdif;
1703 if (cm->chip_version >= 37) {
1704 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1705 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1706 }
1707 if (cm->chip_version == 68) {
1708 runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1709 SNDRV_PCM_RATE_96000;
1710 runtime->hw.rate_max = 96000;
1711 }
1712 } else {
1713 runtime->hw = snd_cmipci_playback_iec958_subframe;
1714 }
1715 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1716 cm->dig_pcm_status = cm->dig_status;
1717 return 0;
1718 }
1719
1720 static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1721 {
1722 struct cmipci *cm = snd_pcm_substream_chip(substream);
1723 struct snd_pcm_runtime *runtime = substream->runtime;
1724 int err;
1725
1726 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
1727 return err;
1728 runtime->hw = snd_cmipci_capture_spdif;
1729 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
1730 return 0;
1731 }
1732
1733
1734 /*
1735 */
1736
1737 static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1738 {
1739 struct cmipci *cm = snd_pcm_substream_chip(substream);
1740 close_device_check(cm, CM_OPEN_PLAYBACK);
1741 return 0;
1742 }
1743
1744 static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1745 {
1746 struct cmipci *cm = snd_pcm_substream_chip(substream);
1747 close_device_check(cm, CM_OPEN_CAPTURE);
1748 return 0;
1749 }
1750
1751 static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1752 {
1753 struct cmipci *cm = snd_pcm_substream_chip(substream);
1754 close_device_check(cm, CM_OPEN_PLAYBACK2);
1755 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1756 return 0;
1757 }
1758
1759 static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1760 {
1761 struct cmipci *cm = snd_pcm_substream_chip(substream);
1762 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1763 return 0;
1764 }
1765
1766 static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1767 {
1768 struct cmipci *cm = snd_pcm_substream_chip(substream);
1769 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1770 return 0;
1771 }
1772
1773
1774 /*
1775 */
1776
1777 static struct snd_pcm_ops snd_cmipci_playback_ops = {
1778 .open = snd_cmipci_playback_open,
1779 .close = snd_cmipci_playback_close,
1780 .ioctl = snd_pcm_lib_ioctl,
1781 .hw_params = snd_cmipci_hw_params,
1782 .hw_free = snd_cmipci_playback_hw_free,
1783 .prepare = snd_cmipci_playback_prepare,
1784 .trigger = snd_cmipci_playback_trigger,
1785 .pointer = snd_cmipci_playback_pointer,
1786 };
1787
1788 static struct snd_pcm_ops snd_cmipci_capture_ops = {
1789 .open = snd_cmipci_capture_open,
1790 .close = snd_cmipci_capture_close,
1791 .ioctl = snd_pcm_lib_ioctl,
1792 .hw_params = snd_cmipci_hw_params,
1793 .hw_free = snd_cmipci_hw_free,
1794 .prepare = snd_cmipci_capture_prepare,
1795 .trigger = snd_cmipci_capture_trigger,
1796 .pointer = snd_cmipci_capture_pointer,
1797 };
1798
1799 static struct snd_pcm_ops snd_cmipci_playback2_ops = {
1800 .open = snd_cmipci_playback2_open,
1801 .close = snd_cmipci_playback2_close,
1802 .ioctl = snd_pcm_lib_ioctl,
1803 .hw_params = snd_cmipci_playback2_hw_params,
1804 .hw_free = snd_cmipci_playback2_hw_free,
1805 .prepare = snd_cmipci_capture_prepare, /* channel B */
1806 .trigger = snd_cmipci_capture_trigger, /* channel B */
1807 .pointer = snd_cmipci_capture_pointer, /* channel B */
1808 };
1809
1810 static struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1811 .open = snd_cmipci_playback_spdif_open,
1812 .close = snd_cmipci_playback_spdif_close,
1813 .ioctl = snd_pcm_lib_ioctl,
1814 .hw_params = snd_cmipci_hw_params,
1815 .hw_free = snd_cmipci_playback_hw_free,
1816 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1817 .trigger = snd_cmipci_playback_trigger,
1818 .pointer = snd_cmipci_playback_pointer,
1819 };
1820
1821 static struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1822 .open = snd_cmipci_capture_spdif_open,
1823 .close = snd_cmipci_capture_spdif_close,
1824 .ioctl = snd_pcm_lib_ioctl,
1825 .hw_params = snd_cmipci_hw_params,
1826 .hw_free = snd_cmipci_capture_spdif_hw_free,
1827 .prepare = snd_cmipci_capture_spdif_prepare,
1828 .trigger = snd_cmipci_capture_trigger,
1829 .pointer = snd_cmipci_capture_pointer,
1830 };
1831
1832
1833 /*
1834 */
1835
1836 static int __devinit snd_cmipci_pcm_new(struct cmipci *cm, int device)
1837 {
1838 struct snd_pcm *pcm;
1839 int err;
1840
1841 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1842 if (err < 0)
1843 return err;
1844
1845 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
1846 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
1847
1848 pcm->private_data = cm;
1849 pcm->info_flags = 0;
1850 strcpy(pcm->name, "C-Media PCI DAC/ADC");
1851 cm->pcm = pcm;
1852
1853 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1854 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1855
1856 return 0;
1857 }
1858
1859 static int __devinit snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1860 {
1861 struct snd_pcm *pcm;
1862 int err;
1863
1864 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
1865 if (err < 0)
1866 return err;
1867
1868 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
1869
1870 pcm->private_data = cm;
1871 pcm->info_flags = 0;
1872 strcpy(pcm->name, "C-Media PCI 2nd DAC");
1873 cm->pcm2 = pcm;
1874
1875 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1876 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1877
1878 return 0;
1879 }
1880
1881 static int __devinit snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1882 {
1883 struct snd_pcm *pcm;
1884 int err;
1885
1886 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
1887 if (err < 0)
1888 return err;
1889
1890 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
1891 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
1892
1893 pcm->private_data = cm;
1894 pcm->info_flags = 0;
1895 strcpy(pcm->name, "C-Media PCI IEC958");
1896 cm->pcm_spdif = pcm;
1897
1898 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1899 snd_dma_pci_data(cm->pci), 64*1024, 128*1024);
1900
1901 return 0;
1902 }
1903
1904 /*
1905 * mixer interface:
1906 * - CM8338/8738 has a compatible mixer interface with SB16, but
1907 * lack of some elements like tone control, i/o gain and AGC.
1908 * - Access to native registers:
1909 * - A 3D switch
1910 * - Output mute switches
1911 */
1912
1913 static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1914 {
1915 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1916 outb(data, s->iobase + CM_REG_SB16_DATA);
1917 }
1918
1919 static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1920 {
1921 unsigned char v;
1922
1923 outb(idx, s->iobase + CM_REG_SB16_ADDR);
1924 v = inb(s->iobase + CM_REG_SB16_DATA);
1925 return v;
1926 }
1927
1928 /*
1929 * general mixer element
1930 */
1931 struct cmipci_sb_reg {
1932 unsigned int left_reg, right_reg;
1933 unsigned int left_shift, right_shift;
1934 unsigned int mask;
1935 unsigned int invert: 1;
1936 unsigned int stereo: 1;
1937 };
1938
1939 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1940 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1941
1942 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1943 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1944 .info = snd_cmipci_info_volume, \
1945 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1946 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1947 }
1948
1949 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1950 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1951 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1952 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1953
1954 static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1955 {
1956 r->left_reg = val & 0xff;
1957 r->right_reg = (val >> 8) & 0xff;
1958 r->left_shift = (val >> 16) & 0x07;
1959 r->right_shift = (val >> 19) & 0x07;
1960 r->invert = (val >> 22) & 1;
1961 r->stereo = (val >> 23) & 1;
1962 r->mask = (val >> 24) & 0xff;
1963 }
1964
1965 static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1966 struct snd_ctl_elem_info *uinfo)
1967 {
1968 struct cmipci_sb_reg reg;
1969
1970 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1971 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1972 uinfo->count = reg.stereo + 1;
1973 uinfo->value.integer.min = 0;
1974 uinfo->value.integer.max = reg.mask;
1975 return 0;
1976 }
1977
1978 static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1979 struct snd_ctl_elem_value *ucontrol)
1980 {
1981 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1982 struct cmipci_sb_reg reg;
1983 int val;
1984
1985 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
1986 spin_lock_irq(&cm->reg_lock);
1987 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
1988 if (reg.invert)
1989 val = reg.mask - val;
1990 ucontrol->value.integer.value[0] = val;
1991 if (reg.stereo) {
1992 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
1993 if (reg.invert)
1994 val = reg.mask - val;
1995 ucontrol->value.integer.value[1] = val;
1996 }
1997 spin_unlock_irq(&cm->reg_lock);
1998 return 0;
1999 }
2000
2001 static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2002 struct snd_ctl_elem_value *ucontrol)
2003 {
2004 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2005 struct cmipci_sb_reg reg;
2006 int change;
2007 int left, right, oleft, oright;
2008
2009 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2010 left = ucontrol->value.integer.value[0] & reg.mask;
2011 if (reg.invert)
2012 left = reg.mask - left;
2013 left <<= reg.left_shift;
2014 if (reg.stereo) {
2015 right = ucontrol->value.integer.value[1] & reg.mask;
2016 if (reg.invert)
2017 right = reg.mask - right;
2018 right <<= reg.right_shift;
2019 } else
2020 right = 0;
2021 spin_lock_irq(&cm->reg_lock);
2022 oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
2023 left |= oleft & ~(reg.mask << reg.left_shift);
2024 change = left != oleft;
2025 if (reg.stereo) {
2026 if (reg.left_reg != reg.right_reg) {
2027 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2028 oright = snd_cmipci_mixer_read(cm, reg.right_reg);
2029 } else
2030 oright = left;
2031 right |= oright & ~(reg.mask << reg.right_shift);
2032 change |= right != oright;
2033 snd_cmipci_mixer_write(cm, reg.right_reg, right);
2034 } else
2035 snd_cmipci_mixer_write(cm, reg.left_reg, left);
2036 spin_unlock_irq(&cm->reg_lock);
2037 return change;
2038 }
2039
2040 /*
2041 * input route (left,right) -> (left,right)
2042 */
2043 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2044 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2045 .info = snd_cmipci_info_input_sw, \
2046 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2047 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2048 }
2049
2050 static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2051 struct snd_ctl_elem_info *uinfo)
2052 {
2053 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2054 uinfo->count = 4;
2055 uinfo->value.integer.min = 0;
2056 uinfo->value.integer.max = 1;
2057 return 0;
2058 }
2059
2060 static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2061 struct snd_ctl_elem_value *ucontrol)
2062 {
2063 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2064 struct cmipci_sb_reg reg;
2065 int val1, val2;
2066
2067 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2068 spin_lock_irq(&cm->reg_lock);
2069 val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2070 val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2071 spin_unlock_irq(&cm->reg_lock);
2072 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2073 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2074 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2075 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2076 return 0;
2077 }
2078
2079 static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2080 struct snd_ctl_elem_value *ucontrol)
2081 {
2082 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2083 struct cmipci_sb_reg reg;
2084 int change;
2085 int val1, val2, oval1, oval2;
2086
2087 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2088 spin_lock_irq(&cm->reg_lock);
2089 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
2090 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
2091 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2092 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2093 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2094 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2095 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2096 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2097 change = val1 != oval1 || val2 != oval2;
2098 snd_cmipci_mixer_write(cm, reg.left_reg, val1);
2099 snd_cmipci_mixer_write(cm, reg.right_reg, val2);
2100 spin_unlock_irq(&cm->reg_lock);
2101 return change;
2102 }
2103
2104 /*
2105 * native mixer switches/volumes
2106 */
2107
2108 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2109 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2110 .info = snd_cmipci_info_native_mixer, \
2111 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2112 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2113 }
2114
2115 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2116 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2117 .info = snd_cmipci_info_native_mixer, \
2118 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2119 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2120 }
2121
2122 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2123 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2124 .info = snd_cmipci_info_native_mixer, \
2125 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2126 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2127 }
2128
2129 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2130 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2131 .info = snd_cmipci_info_native_mixer, \
2132 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2133 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2134 }
2135
2136 static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2137 struct snd_ctl_elem_info *uinfo)
2138 {
2139 struct cmipci_sb_reg reg;
2140
2141 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2142 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2143 uinfo->count = reg.stereo + 1;
2144 uinfo->value.integer.min = 0;
2145 uinfo->value.integer.max = reg.mask;
2146 return 0;
2147
2148 }
2149
2150 static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2151 struct snd_ctl_elem_value *ucontrol)
2152 {
2153 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2154 struct cmipci_sb_reg reg;
2155 unsigned char oreg, val;
2156
2157 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2158 spin_lock_irq(&cm->reg_lock);
2159 oreg = inb(cm->iobase + reg.left_reg);
2160 val = (oreg >> reg.left_shift) & reg.mask;
2161 if (reg.invert)
2162 val = reg.mask - val;
2163 ucontrol->value.integer.value[0] = val;
2164 if (reg.stereo) {
2165 val = (oreg >> reg.right_shift) & reg.mask;
2166 if (reg.invert)
2167 val = reg.mask - val;
2168 ucontrol->value.integer.value[1] = val;
2169 }
2170 spin_unlock_irq(&cm->reg_lock);
2171 return 0;
2172 }
2173
2174 static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2175 struct snd_ctl_elem_value *ucontrol)
2176 {
2177 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2178 struct cmipci_sb_reg reg;
2179 unsigned char oreg, nreg, val;
2180
2181 cmipci_sb_reg_decode(&reg, kcontrol->private_value);
2182 spin_lock_irq(&cm->reg_lock);
2183 oreg = inb(cm->iobase + reg.left_reg);
2184 val = ucontrol->value.integer.value[0] & reg.mask;
2185 if (reg.invert)
2186 val = reg.mask - val;
2187 nreg = oreg & ~(reg.mask << reg.left_shift);
2188 nreg |= (val << reg.left_shift);
2189 if (reg.stereo) {
2190 val = ucontrol->value.integer.value[1] & reg.mask;
2191 if (reg.invert)
2192 val = reg.mask - val;
2193 nreg &= ~(reg.mask << reg.right_shift);
2194 nreg |= (val << reg.right_shift);
2195 }
2196 outb(nreg, cm->iobase + reg.left_reg);
2197 spin_unlock_irq(&cm->reg_lock);
2198 return (nreg != oreg);
2199 }
2200
2201 /*
2202 * special case - check mixer sensitivity
2203 */
2204 static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2205 struct snd_ctl_elem_value *ucontrol)
2206 {
2207 //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2208 return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2209 }
2210
2211 static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2212 struct snd_ctl_elem_value *ucontrol)
2213 {
2214 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2215 if (cm->mixer_insensitive) {
2216 /* ignored */
2217 return 0;
2218 }
2219 return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2220 }
2221
2222
2223 static struct snd_kcontrol_new snd_cmipci_mixers[] __devinitdata = {
2224 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2225 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2226 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2227 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2228 { /* switch with sensitivity */
2229 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2230 .name = "PCM Playback Switch",
2231 .info = snd_cmipci_info_native_mixer,
2232 .get = snd_cmipci_get_native_mixer_sensitive,
2233 .put = snd_cmipci_put_native_mixer_sensitive,
2234 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2235 },
2236 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2237 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2238 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2239 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2240 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2241 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2242 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2243 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2244 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2245 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2246 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2247 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2248 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2249 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2250 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2251 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2252 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2253 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2254 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2255 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2256 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2257 CMIPCI_DOUBLE("PC Speaker Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2258 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2259 };
2260
2261 /*
2262 * other switches
2263 */
2264
2265 struct cmipci_switch_args {
2266 int reg; /* register index */
2267 unsigned int mask; /* mask bits */
2268 unsigned int mask_on; /* mask bits to turn on */
2269 unsigned int is_byte: 1; /* byte access? */
2270 unsigned int ac3_sensitive: 1; /* access forbidden during
2271 * non-audio operation?
2272 */
2273 };
2274
2275 #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2276
2277 static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2278 struct snd_ctl_elem_value *ucontrol,
2279 struct cmipci_switch_args *args)
2280 {
2281 unsigned int val;
2282 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2283
2284 spin_lock_irq(&cm->reg_lock);
2285 if (args->ac3_sensitive && cm->mixer_insensitive) {
2286 ucontrol->value.integer.value[0] = 0;
2287 spin_unlock_irq(&cm->reg_lock);
2288 return 0;
2289 }
2290 if (args->is_byte)
2291 val = inb(cm->iobase + args->reg);
2292 else
2293 val = snd_cmipci_read(cm, args->reg);
2294 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2295 spin_unlock_irq(&cm->reg_lock);
2296 return 0;
2297 }
2298
2299 static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2300 struct snd_ctl_elem_value *ucontrol)
2301 {
2302 struct cmipci_switch_args *args;
2303 args = (struct cmipci_switch_args *)kcontrol->private_value;
2304 snd_assert(args != NULL, return -EINVAL);
2305 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2306 }
2307
2308 static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2309 struct snd_ctl_elem_value *ucontrol,
2310 struct cmipci_switch_args *args)
2311 {
2312 unsigned int val;
2313 int change;
2314 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2315
2316 spin_lock_irq(&cm->reg_lock);
2317 if (args->ac3_sensitive && cm->mixer_insensitive) {
2318 /* ignored */
2319 spin_unlock_irq(&cm->reg_lock);
2320 return 0;
2321 }
2322 if (args->is_byte)
2323 val = inb(cm->iobase + args->reg);
2324 else
2325 val = snd_cmipci_read(cm, args->reg);
2326 change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2327 args->mask_on : (args->mask & ~args->mask_on));
2328 if (change) {
2329 val &= ~args->mask;
2330 if (ucontrol->value.integer.value[0])
2331 val |= args->mask_on;
2332 else
2333 val |= (args->mask & ~args->mask_on);
2334 if (args->is_byte)
2335 outb((unsigned char)val, cm->iobase + args->reg);
2336 else
2337 snd_cmipci_write(cm, args->reg, val);
2338 }
2339 spin_unlock_irq(&cm->reg_lock);
2340 return change;
2341 }
2342
2343 static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2344 struct snd_ctl_elem_value *ucontrol)
2345 {
2346 struct cmipci_switch_args *args;
2347 args = (struct cmipci_switch_args *)kcontrol->private_value;
2348 snd_assert(args != NULL, return -EINVAL);
2349 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2350 }
2351
2352 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2353 static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2354 .reg = xreg, \
2355 .mask = xmask, \
2356 .mask_on = xmask_on, \
2357 .is_byte = xis_byte, \
2358 .ac3_sensitive = xac3, \
2359 }
2360
2361 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2362 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2363
2364 #if 0 /* these will be controlled in pcm device */
2365 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2366 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2367 #endif
2368 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2369 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2370 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2371 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2372 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2373 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2374 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2375 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2376 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2377 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2378 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2379 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2380 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2381 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2382 #if CM_CH_PLAY == 1
2383 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2384 #else
2385 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2386 #endif
2387 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2388 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2389 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2390 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2391 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2392
2393 #define DEFINE_SWITCH(sname, stype, sarg) \
2394 { .name = sname, \
2395 .iface = stype, \
2396 .info = snd_cmipci_uswitch_info, \
2397 .get = snd_cmipci_uswitch_get, \
2398 .put = snd_cmipci_uswitch_put, \
2399 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2400 }
2401
2402 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2403 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2404
2405
2406 /*
2407 * callbacks for spdif output switch
2408 * needs toggle two registers..
2409 */
2410 static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2411 struct snd_ctl_elem_value *ucontrol)
2412 {
2413 int changed;
2414 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2415 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2416 return changed;
2417 }
2418
2419 static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2420 struct snd_ctl_elem_value *ucontrol)
2421 {
2422 struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2423 int changed;
2424 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
2425 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
2426 if (changed) {
2427 if (ucontrol->value.integer.value[0]) {
2428 if (chip->spdif_playback_avail)
2429 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2430 } else {
2431 if (chip->spdif_playback_avail)
2432 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2433 }
2434 }
2435 chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2436 return changed;
2437 }
2438
2439
2440 static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2441 struct snd_ctl_elem_info *uinfo)
2442 {
2443 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2444 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" };
2445 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2446 uinfo->count = 1;
2447 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2;
2448 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2449 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2450 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2451 return 0;
2452 }
2453
2454 static inline unsigned int get_line_in_mode(struct cmipci *cm)
2455 {
2456 unsigned int val;
2457 if (cm->chip_version >= 39) {
2458 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2459 if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2460 return 2;
2461 }
2462 val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2463 if (val & CM_REAR2LIN)
2464 return 1;
2465 return 0;
2466 }
2467
2468 static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2469 struct snd_ctl_elem_value *ucontrol)
2470 {
2471 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2472
2473 spin_lock_irq(&cm->reg_lock);
2474 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2475 spin_unlock_irq(&cm->reg_lock);
2476 return 0;
2477 }
2478
2479 static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2480 struct snd_ctl_elem_value *ucontrol)
2481 {
2482 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2483 int change;
2484
2485 spin_lock_irq(&cm->reg_lock);
2486 if (ucontrol->value.enumerated.item[0] == 2)
2487 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2488 else
2489 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2490 if (ucontrol->value.enumerated.item[0] == 1)
2491 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2492 else
2493 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2494 spin_unlock_irq(&cm->reg_lock);
2495 return change;
2496 }
2497
2498 static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2499 struct snd_ctl_elem_info *uinfo)
2500 {
2501 static char *texts[2] = { "Mic-In", "Center/LFE Output" };
2502 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2503 uinfo->count = 1;
2504 uinfo->value.enumerated.items = 2;
2505 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2506 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2507 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2508 return 0;
2509 }
2510
2511 static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2512 struct snd_ctl_elem_value *ucontrol)
2513 {
2514 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2515 /* same bit as spdi_phase */
2516 spin_lock_irq(&cm->reg_lock);
2517 ucontrol->value.enumerated.item[0] =
2518 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2519 spin_unlock_irq(&cm->reg_lock);
2520 return 0;
2521 }
2522
2523 static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2524 struct snd_ctl_elem_value *ucontrol)
2525 {
2526 struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2527 int change;
2528
2529 spin_lock_irq(&cm->reg_lock);
2530 if (ucontrol->value.enumerated.item[0])
2531 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2532 else
2533 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2534 spin_unlock_irq(&cm->reg_lock);
2535 return change;
2536 }
2537
2538 /* both for CM8338/8738 */
2539 static struct snd_kcontrol_new snd_cmipci_mixer_switches[] __devinitdata = {
2540 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2541 {
2542 .name = "Line-In Mode",
2543 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2544 .info = snd_cmipci_line_in_mode_info,
2545 .get = snd_cmipci_line_in_mode_get,
2546 .put = snd_cmipci_line_in_mode_put,
2547 },
2548 };
2549
2550 /* for non-multichannel chips */
2551 static struct snd_kcontrol_new snd_cmipci_nomulti_switch __devinitdata =
2552 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2553
2554 /* only for CM8738 */
2555 static struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] __devinitdata = {
2556 #if 0 /* controlled in pcm device */
2557 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2558 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2559 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2560 #endif
2561 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2562 { .name = "IEC958 Output Switch",
2563 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2564 .info = snd_cmipci_uswitch_info,
2565 .get = snd_cmipci_spdout_enable_get,
2566 .put = snd_cmipci_spdout_enable_put,
2567 },
2568 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2569 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2570 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2571 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2572 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2573 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2574 };
2575
2576 /* only for model 033/037 */
2577 static struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] __devinitdata = {
2578 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2579 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2580 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2581 };
2582
2583 /* only for model 039 or later */
2584 static struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] __devinitdata = {
2585 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2586 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2587 {
2588 .name = "Mic-In Mode",
2589 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2590 .info = snd_cmipci_mic_in_mode_info,
2591 .get = snd_cmipci_mic_in_mode_get,
2592 .put = snd_cmipci_mic_in_mode_put,
2593 }
2594 };
2595
2596 /* card control switches */
2597 static struct snd_kcontrol_new snd_cmipci_control_switches[] __devinitdata = {
2598 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2599 DEFINE_CARD_SWITCH("Modem", modem),
2600 };
2601
2602
2603 static int __devinit snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2604 {
2605 struct snd_card *card;
2606 struct snd_kcontrol_new *sw;
2607 struct snd_kcontrol *kctl;
2608 unsigned int idx;
2609 int err;
2610
2611 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL);
2612
2613 card = cm->card;
2614
2615 strcpy(card->mixername, "CMedia PCI");
2616
2617 spin_lock_irq(&cm->reg_lock);
2618 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
2619 spin_unlock_irq(&cm->reg_lock);
2620
2621 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2622 if (cm->chip_version == 68) { // 8768 has no PCM volume
2623 if (!strcmp(snd_cmipci_mixers[idx].name,
2624 "PCM Playback Volume"))
2625 continue;
2626 }
2627 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
2628 return err;
2629 }
2630
2631 /* mixer switches */
2632 sw = snd_cmipci_mixer_switches;
2633 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2634 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2635 if (err < 0)
2636 return err;
2637 }
2638 if (! cm->can_multi_ch) {
2639 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
2640 if (err < 0)
2641 return err;
2642 }
2643 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2644 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2645 sw = snd_cmipci_8738_mixer_switches;
2646 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2647 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2648 if (err < 0)
2649 return err;
2650 }
2651 if (cm->can_ac3_hw) {
2652 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
2653 return err;
2654 kctl->id.device = pcm_spdif_device;
2655 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
2656 return err;
2657 kctl->id.device = pcm_spdif_device;
2658 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
2659 return err;
2660 kctl->id.device = pcm_spdif_device;
2661 }
2662 if (cm->chip_version <= 37) {
2663 sw = snd_cmipci_old_mixer_switches;
2664 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2665 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2666 if (err < 0)
2667 return err;
2668 }
2669 }
2670 }
2671 if (cm->chip_version >= 39) {
2672 sw = snd_cmipci_extra_mixer_switches;
2673 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2674 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2675 if (err < 0)
2676 return err;
2677 }
2678 }
2679
2680 /* card switches */
2681 sw = snd_cmipci_control_switches;
2682 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) {
2683 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
2684 if (err < 0)
2685 return err;
2686 }
2687
2688 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2689 struct snd_ctl_elem_id id;
2690 struct snd_kcontrol *ctl;
2691 memset(&id, 0, sizeof(id));
2692 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2693 strcpy(id.name, cm_saved_mixer[idx].name);
2694 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL)
2695 cm->mixer_res_ctl[idx] = ctl;
2696 }
2697
2698 return 0;
2699 }
2700
2701
2702 /*
2703 * proc interface
2704 */
2705
2706 #ifdef CONFIG_PROC_FS
2707 static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2708 struct snd_info_buffer *buffer)
2709 {
2710 struct cmipci *cm = entry->private_data;
2711 int i, v;
2712
2713 snd_iprintf(buffer, "%s\n", cm->card->longname);
2714 for (i = 0; i < 0x94; i++) {
2715 if (i == 0x28)
2716 i = 0x90;
2717 v = inb(cm->iobase + i);
2718 if (i % 4 == 0)
2719 snd_iprintf(buffer, "\n%02x:", i);
2720 snd_iprintf(buffer, " %02x", v);
2721 }
2722 snd_iprintf(buffer, "\n");
2723 }
2724
2725 static void __devinit snd_cmipci_proc_init(struct cmipci *cm)
2726 {
2727 struct snd_info_entry *entry;
2728
2729 if (! snd_card_proc_new(cm->card, "cmipci", &entry))
2730 snd_info_set_text_ops(entry, cm, snd_cmipci_proc_read);
2731 }
2732 #else /* !CONFIG_PROC_FS */
2733 static inline void snd_cmipci_proc_init(struct cmipci *cm) {}
2734 #endif
2735
2736
2737 static struct pci_device_id snd_cmipci_ids[] = {
2738 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2739 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2740 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2741 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2742 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2743 {0,},
2744 };
2745
2746
2747 /*
2748 * check chip version and capabilities
2749 * driver name is modified according to the chip model
2750 */
2751 static void __devinit query_chip(struct cmipci *cm)
2752 {
2753 unsigned int detect;
2754
2755 /* check reg 0Ch, bit 24-31 */
2756 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2757 if (! detect) {
2758 /* check reg 08h, bit 24-28 */
2759 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2760 switch (detect) {
2761 case 0:
2762 cm->chip_version = 33;
2763 if (cm->do_soft_ac3)
2764 cm->can_ac3_sw = 1;
2765 else
2766 cm->can_ac3_hw = 1;
2767 break;
2768 case CM_CHIP_037:
2769 cm->chip_version = 37;
2770 cm->can_ac3_hw = 1;
2771 break;
2772 default:
2773 cm->chip_version = 39;
2774 cm->can_ac3_hw = 1;
2775 break;
2776 }
2777 cm->max_channels = 2;
2778 } else {
2779 if (detect & CM_CHIP_039) {
2780 cm->chip_version = 39;
2781 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2782 cm->max_channels = 6;
2783 else
2784 cm->max_channels = 4;
2785 } else if (detect & CM_CHIP_8768) {
2786 cm->chip_version = 68;
2787 cm->max_channels = 8;
2788 } else {
2789 cm->chip_version = 55;
2790 cm->max_channels = 6;
2791 }
2792 cm->can_ac3_hw = 1;
2793 cm->can_multi_ch = 1;
2794 }
2795 }
2796
2797 #ifdef SUPPORT_JOYSTICK
2798 static int __devinit snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2799 {
2800 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2801 struct gameport *gp;
2802 struct resource *r = NULL;
2803 int i, io_port = 0;
2804
2805 if (joystick_port[dev] == 0)
2806 return -ENODEV;
2807
2808 if (joystick_port[dev] == 1) { /* auto-detect */
2809 for (i = 0; ports[i]; i++) {
2810 io_port = ports[i];
2811 r = request_region(io_port, 1, "CMIPCI gameport");
2812 if (r)
2813 break;
2814 }
2815 } else {
2816 io_port = joystick_port[dev];
2817 r = request_region(io_port, 1, "CMIPCI gameport");
2818 }
2819
2820 if (!r) {
2821 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n");
2822 return -EBUSY;
2823 }
2824
2825 cm->gameport = gp = gameport_allocate_port();
2826 if (!gp) {
2827 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n");
2828 release_and_free_resource(r);
2829 return -ENOMEM;
2830 }
2831 gameport_set_name(gp, "C-Media Gameport");
2832 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
2833 gameport_set_dev_parent(gp, &cm->pci->dev);
2834 gp->io = io_port;
2835 gameport_set_port_data(gp, r);
2836
2837 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2838
2839 gameport_register_port(cm->gameport);
2840
2841 return 0;
2842 }
2843
2844 static void snd_cmipci_free_gameport(struct cmipci *cm)
2845 {
2846 if (cm->gameport) {
2847 struct resource *r = gameport_get_port_data(cm->gameport);
2848
2849 gameport_unregister_port(cm->gameport);
2850 cm->gameport = NULL;
2851
2852 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2853 release_and_free_resource(r);
2854 }
2855 }
2856 #else
2857 static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2858 static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2859 #endif
2860
2861 static int snd_cmipci_free(struct cmipci *cm)
2862 {
2863 if (cm->irq >= 0) {
2864 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2865 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2866 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
2867 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2868 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2869 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
2870 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
2871
2872 /* reset mixer */
2873 snd_cmipci_mixer_write(cm, 0, 0);
2874
2875 synchronize_irq(cm->irq);
2876
2877 free_irq(cm->irq, cm);
2878 }
2879
2880 snd_cmipci_free_gameport(cm);
2881 pci_release_regions(cm->pci);
2882 pci_disable_device(cm->pci);
2883 kfree(cm);
2884 return 0;
2885 }
2886
2887 static int snd_cmipci_dev_free(struct snd_device *device)
2888 {
2889 struct cmipci *cm = device->device_data;
2890 return snd_cmipci_free(cm);
2891 }
2892
2893 static int __devinit snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2894 {
2895 long iosynth;
2896 unsigned int val;
2897 struct snd_opl3 *opl3;
2898 int err;
2899
2900 if (!fm_port)
2901 goto disable_fm;
2902
2903 if (cm->chip_version >= 39) {
2904 /* first try FM regs in PCI port range */
2905 iosynth = cm->iobase + CM_REG_FM_PCI;
2906 err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
2907 OPL3_HW_OPL3, 1, &opl3);
2908 } else {
2909 err = -EIO;
2910 }
2911 if (err < 0) {
2912 /* then try legacy ports */
2913 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2914 iosynth = fm_port;
2915 switch (iosynth) {
2916 case 0x3E8: val |= CM_FMSEL_3E8; break;
2917 case 0x3E0: val |= CM_FMSEL_3E0; break;
2918 case 0x3C8: val |= CM_FMSEL_3C8; break;
2919 case 0x388: val |= CM_FMSEL_388; break;
2920 default:
2921 goto disable_fm;
2922 }
2923 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
2924 /* enable FM */
2925 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2926
2927 if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
2928 OPL3_HW_OPL3, 0, &opl3) < 0) {
2929 printk(KERN_ERR "cmipci: no OPL device at %#lx, "
2930 "skipping...\n", iosynth);
2931 goto disable_fm;
2932 }
2933 }
2934 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
2935 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n");
2936 return err;
2937 }
2938 return 0;
2939
2940 disable_fm:
2941 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2942 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2943 return 0;
2944 }
2945
2946 static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2947 int dev, struct cmipci **rcmipci)
2948 {
2949 struct cmipci *cm;
2950 int err;
2951 static struct snd_device_ops ops = {
2952 .dev_free = snd_cmipci_dev_free,
2953 };
2954 unsigned int val;
2955 long iomidi;
2956 int integrated_midi = 0;
2957 char modelstr[16];
2958 int pcm_index, pcm_spdif_index;
2959 static struct pci_device_id intel_82437vx[] = {
2960 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2961 { },
2962 };
2963
2964 *rcmipci = NULL;
2965
2966 if ((err = pci_enable_device(pci)) < 0)
2967 return err;
2968
2969 cm = kzalloc(sizeof(*cm), GFP_KERNEL);
2970 if (cm == NULL) {
2971 pci_disable_device(pci);
2972 return -ENOMEM;
2973 }
2974
2975 spin_lock_init(&cm->reg_lock);
2976 mutex_init(&cm->open_mutex);
2977 cm->device = pci->device;
2978 cm->card = card;
2979 cm->pci = pci;
2980 cm->irq = -1;
2981 cm->channel[0].ch = 0;
2982 cm->channel[1].ch = 1;
2983 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2984
2985 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2986 kfree(cm);
2987 pci_disable_device(pci);
2988 return err;
2989 }
2990 cm->iobase = pci_resource_start(pci, 0);
2991
2992 if (request_irq(pci->irq, snd_cmipci_interrupt,
2993 IRQF_SHARED, card->driver, cm)) {
2994 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2995 snd_cmipci_free(cm);
2996 return -EBUSY;
2997 }
2998 cm->irq = pci->irq;
2999
3000 pci_set_master(cm->pci);
3001
3002 /*
3003 * check chip version, max channels and capabilities
3004 */
3005
3006 cm->chip_version = 0;
3007 cm->max_channels = 2;
3008 cm->do_soft_ac3 = soft_ac3[dev];
3009
3010 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
3011 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
3012 query_chip(cm);
3013 /* added -MCx suffix for chip supporting multi-channels */
3014 if (cm->can_multi_ch)
3015 sprintf(cm->card->driver + strlen(cm->card->driver),
3016 "-MC%d", cm->max_channels);
3017 else if (cm->can_ac3_sw)
3018 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
3019
3020 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3021 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
3022
3023 #if CM_CH_PLAY == 1
3024 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3025 #else
3026 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
3027 #endif
3028
3029 /* initialize codec registers */
3030 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3031 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
3032 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
3033 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3034 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3035 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
3036 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
3037
3038 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
3039 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3040 #if CM_CH_PLAY == 1
3041 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3042 #else
3043 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3044 #endif
3045 if (cm->chip_version) {
3046 snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
3047 snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
3048 }
3049 /* Set Bus Master Request */
3050 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3051
3052 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3053 switch (pci->device) {
3054 case PCI_DEVICE_ID_CMEDIA_CM8738:
3055 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3056 if (!pci_dev_present(intel_82437vx))
3057 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3058 break;
3059 default:
3060 break;
3061 }
3062
3063 if (cm->chip_version < 68) {
3064 val = pci->device < 0x110 ? 8338 : 8738;
3065 } else {
3066 switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3067 case 0:
3068 val = 8769;
3069 break;
3070 case 2:
3071 val = 8762;
3072 break;
3073 default:
3074 switch ((pci->subsystem_vendor << 16) |
3075 pci->subsystem_device) {
3076 case 0x13f69761:
3077 case 0x584d3741:
3078 case 0x584d3751:
3079 case 0x584d3761:
3080 case 0x584d3771:
3081 case 0x72848384:
3082 val = 8770;
3083 break;
3084 default:
3085 val = 8768;
3086 break;
3087 }
3088 }
3089 }
3090 sprintf(card->shortname, "C-Media CMI%d", val);
3091 if (cm->chip_version < 68)
3092 sprintf(modelstr, " (model %d)", cm->chip_version);
3093 else
3094 modelstr[0] = '\0';
3095 sprintf(card->longname, "%s%s at %#lx, irq %i",
3096 card->shortname, modelstr, cm->iobase, cm->irq);
3097
3098 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
3099 snd_cmipci_free(cm);
3100 return err;
3101 }
3102
3103 if (cm->chip_version >= 39) {
3104 val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3105 if (val != 0x00 && val != 0xff) {
3106 iomidi = cm->iobase + CM_REG_MPU_PCI;
3107 integrated_midi = 1;
3108 }
3109 }
3110 if (!integrated_midi) {
3111 val = 0;
3112 iomidi = mpu_port[dev];
3113 switch (iomidi) {
3114 case 0x320: val = CM_VMPU_320; break;
3115 case 0x310: val = CM_VMPU_310; break;
3116 case 0x300: val = CM_VMPU_300; break;
3117 case 0x330: val = CM_VMPU_330; break;
3118 default:
3119 iomidi = 0; break;
3120 }
3121 if (iomidi > 0) {
3122 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
3123 /* enable UART */
3124 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3125 if (inb(iomidi + 1) == 0xff) {
3126 snd_printk(KERN_ERR "cannot enable MPU-401 port"
3127 " at %#lx\n", iomidi);
3128 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3129 CM_UART_EN);
3130 iomidi = 0;
3131 }
3132 }
3133 }
3134
3135 if (cm->chip_version < 68) {
3136 err = snd_cmipci_create_fm(cm, fm_port[dev]);
3137 if (err < 0)
3138 return err;
3139 }
3140
3141 /* reset mixer */
3142 snd_cmipci_mixer_write(cm, 0, 0);
3143
3144 snd_cmipci_proc_init(cm);
3145
3146 /* create pcm devices */
3147 pcm_index = pcm_spdif_index = 0;
3148 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
3149 return err;
3150 pcm_index++;
3151 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
3152 return err;
3153 pcm_index++;
3154 if (cm->can_ac3_hw || cm->can_ac3_sw) {
3155 pcm_spdif_index = pcm_index;
3156 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
3157 return err;
3158 }
3159
3160 /* create mixer interface & switches */
3161 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
3162 return err;
3163
3164 if (iomidi > 0) {
3165 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
3166 iomidi,
3167 (integrated_midi ?
3168 MPU401_INFO_INTEGRATED : 0),
3169 cm->irq, 0, &cm->rmidi)) < 0) {
3170 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi);
3171 }
3172 }
3173
3174 #ifdef USE_VAR48KRATE
3175 for (val = 0; val < ARRAY_SIZE(rates); val++)
3176 snd_cmipci_set_pll(cm, rates[val], val);
3177
3178 /*
3179 * (Re-)Enable external switch spdo_48k
3180 */
3181 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3182 #endif /* USE_VAR48KRATE */
3183
3184 if (snd_cmipci_create_gameport(cm, dev) < 0)
3185 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3186
3187 snd_card_set_dev(card, &pci->dev);
3188
3189 *rcmipci = cm;
3190 return 0;
3191 }
3192
3193 /*
3194 */
3195
3196 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3197
3198 static int __devinit snd_cmipci_probe(struct pci_dev *pci,
3199 const struct pci_device_id *pci_id)
3200 {
3201 static int dev;
3202 struct snd_card *card;
3203 struct cmipci *cm;
3204 int err;
3205
3206 if (dev >= SNDRV_CARDS)
3207 return -ENODEV;
3208 if (! enable[dev]) {
3209 dev++;
3210 return -ENOENT;
3211 }
3212
3213 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
3214 if (card == NULL)
3215 return -ENOMEM;
3216
3217 switch (pci->device) {
3218 case PCI_DEVICE_ID_CMEDIA_CM8738:
3219 case PCI_DEVICE_ID_CMEDIA_CM8738B:
3220 strcpy(card->driver, "CMI8738");
3221 break;
3222 case PCI_DEVICE_ID_CMEDIA_CM8338A:
3223 case PCI_DEVICE_ID_CMEDIA_CM8338B:
3224 strcpy(card->driver, "CMI8338");
3225 break;
3226 default:
3227 strcpy(card->driver, "CMIPCI");
3228 break;
3229 }
3230
3231 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) {
3232 snd_card_free(card);
3233 return err;
3234 }
3235 card->private_data = cm;
3236
3237 if ((err = snd_card_register(card)) < 0) {
3238 snd_card_free(card);
3239 return err;
3240 }
3241 pci_set_drvdata(pci, card);
3242 dev++;
3243 return 0;
3244
3245 }
3246
3247 static void __devexit snd_cmipci_remove(struct pci_dev *pci)
3248 {
3249 snd_card_free(pci_get_drvdata(pci));
3250 pci_set_drvdata(pci, NULL);
3251 }
3252
3253
3254 #ifdef CONFIG_PM
3255 /*
3256 * power management
3257 */
3258 static unsigned char saved_regs[] = {
3259 CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3260 CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_MIXER3, CM_REG_PLL,
3261 CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3262 CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3263 CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3264 };
3265
3266 static unsigned char saved_mixers[] = {
3267 SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3268 SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3269 SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3270 SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3271 SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3272 SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3273 CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3274 SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3275 };
3276
3277 static int snd_cmipci_suspend(struct pci_dev *pci, pm_message_t state)
3278 {
3279 struct snd_card *card = pci_get_drvdata(pci);
3280 struct cmipci *cm = card->private_data;
3281 int i;
3282
3283 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3284
3285 snd_pcm_suspend_all(cm->pcm);
3286 snd_pcm_suspend_all(cm->pcm2);
3287 snd_pcm_suspend_all(cm->pcm_spdif);
3288
3289 /* save registers */
3290 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3291 cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
3292 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3293 cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
3294
3295 /* disable ints */
3296 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3297
3298 pci_disable_device(pci);
3299 pci_save_state(pci);
3300 pci_set_power_state(pci, pci_choose_state(pci, state));
3301 return 0;
3302 }
3303
3304 static int snd_cmipci_resume(struct pci_dev *pci)
3305 {
3306 struct snd_card *card = pci_get_drvdata(pci);
3307 struct cmipci *cm = card->private_data;
3308 int i;
3309
3310 pci_set_power_state(pci, PCI_D0);
3311 pci_restore_state(pci);
3312 if (pci_enable_device(pci) < 0) {
3313 printk(KERN_ERR "cmipci: pci_enable_device failed, "
3314 "disabling device\n");
3315 snd_card_disconnect(card);
3316 return -EIO;
3317 }
3318 pci_set_master(pci);
3319
3320 /* reset / initialize to a sane state */
3321 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
3322 snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3323 snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3324 snd_cmipci_mixer_write(cm, 0, 0);
3325
3326 /* restore registers */
3327 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3328 snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
3329 for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3330 snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
3331
3332 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3333 return 0;
3334 }
3335 #endif /* CONFIG_PM */
3336
3337 static struct pci_driver driver = {
3338 .name = "C-Media PCI",
3339 .id_table = snd_cmipci_ids,
3340 .probe = snd_cmipci_probe,
3341 .remove = __devexit_p(snd_cmipci_remove),
3342 #ifdef CONFIG_PM
3343 .suspend = snd_cmipci_suspend,
3344 .resume = snd_cmipci_resume,
3345 #endif
3346 };
3347
3348 static int __init alsa_card_cmipci_init(void)
3349 {
3350 return pci_register_driver(&driver);
3351 }
3352
3353 static void __exit alsa_card_cmipci_exit(void)
3354 {
3355 pci_unregister_driver(&driver);
3356 }
3357
3358 module_init(alsa_card_cmipci_init)
3359 module_exit(alsa_card_cmipci_exit)
WRT350N Kernel Patches